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-rw-r--r--libmaple/fsmc.c138
-rw-r--r--libmaple/fsmc.h1
-rw-r--r--libmaple/gpio.c8
-rw-r--r--libmaple/libmaple.h94
-rw-r--r--libmaple/usb/usb_callbacks.c18
5 files changed, 145 insertions, 114 deletions
diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c
index db77ff1..49526f4 100644
--- a/libmaple/fsmc.c
+++ b/libmaple/fsmc.c
@@ -31,58 +31,10 @@
#include "gpio.h"
#include "fsmc.h"
-void fsmc_init_gpios(void) {
- /* Data lines... */
- gpio_set_mode(GPIOD_BASE, 0, MODE_AF_OUTPUT_PP); /* D2 */
- gpio_set_mode(GPIOD_BASE, 1, MODE_AF_OUTPUT_PP); /* D3 */
- gpio_set_mode(GPIOD_BASE, 8, MODE_AF_OUTPUT_PP); /* D13 */
- gpio_set_mode(GPIOD_BASE, 9, MODE_AF_OUTPUT_PP); /* D14 */
- gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP); /* D15 */
- gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP); /* D0 */
- gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP); /* D1 */
- gpio_set_mode(GPIOE_BASE, 7, MODE_AF_OUTPUT_PP); /* D4 */
- gpio_set_mode(GPIOE_BASE, 8, MODE_AF_OUTPUT_PP); /* D5 */
- gpio_set_mode(GPIOE_BASE, 9, MODE_AF_OUTPUT_PP); /* D6 */
- gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP); /* D7 */
- gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP); /* D8 */
- gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP); /* D9 */
- gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP); /* D10 */
- gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP); /* D11 */
- gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP); /* D12 */
-
- /* Address lines... */
- gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP); /* A16 */
- gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP); /* A17 */
- gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP); /* A18 */
- gpio_set_mode(GPIOF_BASE, 0, MODE_AF_OUTPUT_PP); /* A0 */
- gpio_set_mode(GPIOF_BASE, 1, MODE_AF_OUTPUT_PP); /* A1 */
- gpio_set_mode(GPIOF_BASE, 2, MODE_AF_OUTPUT_PP); /* A2 */
- gpio_set_mode(GPIOF_BASE, 3, MODE_AF_OUTPUT_PP); /* A3 */
- gpio_set_mode(GPIOF_BASE, 4, MODE_AF_OUTPUT_PP); /* A4 */
- gpio_set_mode(GPIOF_BASE, 5, MODE_AF_OUTPUT_PP); /* A5 */
- gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP); /* A6 */
- gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP); /* A7 */
- gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP); /* A8 */
- gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP); /* A9 */
- gpio_set_mode(GPIOG_BASE, 0, MODE_AF_OUTPUT_PP); /* A10 */
- gpio_set_mode(GPIOG_BASE, 1, MODE_AF_OUTPUT_PP); /* A11 */
- gpio_set_mode(GPIOG_BASE, 2, MODE_AF_OUTPUT_PP); /* A12 */
- gpio_set_mode(GPIOG_BASE, 3, MODE_AF_OUTPUT_PP); /* A13 */
- gpio_set_mode(GPIOG_BASE, 4, MODE_AF_OUTPUT_PP); /* A14 */
- gpio_set_mode(GPIOG_BASE, 5, MODE_AF_OUTPUT_PP); /* A15 */
-
- /* And control lines... */
- gpio_set_mode(GPIOD_BASE, 4, MODE_AF_OUTPUT_PP); /* NOE */
- gpio_set_mode(GPIOD_BASE, 5, MODE_AF_OUTPUT_PP); /* NWE */
-
- gpio_set_mode(GPIOD_BASE, 7, MODE_AF_OUTPUT_PP); /* NE1 */
- gpio_set_mode(GPIOG_BASE, 9, MODE_AF_OUTPUT_PP); /* NE2 */
- gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP); /* NE3 */
- gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP); /* NE4 */
-
- gpio_set_mode(GPIOE_BASE, 0, MODE_AF_OUTPUT_PP); /* NBL0 */
- gpio_set_mode(GPIOE_BASE, 1, MODE_AF_OUTPUT_PP); /* NBL1 */
-}
+/* These values determined for a particular SRAM chip by following the
+ * calculations in the ST FSMC application note. */
+#define FSMC_ADDSET 0x0
+#define FSMC_DATAST 0x3
/* Sets up the FSMC peripheral to use the SRAM chip on the maple
* native as an external segment of system memory space. This
@@ -91,8 +43,57 @@ void fsmc_init_gpios(void) {
void fsmc_native_sram_init(void) {
FSMC_Bank *bank;
- /* First set up the GPIO pins */
- fsmc_init_gpios();
+ /* First we setup all the GPIO pins. */
+ /* Data lines... */
+ gpio_set_mode(GPIOD_BASE, 0, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 1, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 8, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 9, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 7, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 8, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 9, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP);
+
+ /* Address lines... */
+ gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 0, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 1, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 2, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 3, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 4, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 5, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 0, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 1, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 2, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 3, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 4, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 5, MODE_AF_OUTPUT_PP);
+
+ /* And control lines... */
+ gpio_set_mode(GPIOD_BASE, 4, MODE_AF_OUTPUT_PP); // NOE
+ gpio_set_mode(GPIOD_BASE, 5, MODE_AF_OUTPUT_PP); // NWE
+
+ gpio_set_mode(GPIOD_BASE, 7, MODE_AF_OUTPUT_PP); // NE1
+ gpio_set_mode(GPIOG_BASE, 9, MODE_AF_OUTPUT_PP); // NE2
+ gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP); // NE3
+ gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP); // NE4
+
+ gpio_set_mode(GPIOE_BASE, 0, MODE_AF_OUTPUT_PP); // NBL0
+ gpio_set_mode(GPIOE_BASE, 1, MODE_AF_OUTPUT_PP); // NBL1
/* Next enable the clock */
rcc_clk_enable(RCC_FSMC);
@@ -101,9 +102,32 @@ void fsmc_native_sram_init(void) {
* channels are in "Bank 1" of the FSMC) */
bank = (FSMC_Bank*)(FSMC1_BASE);
- /* FIXME replace with macros from fsmc.h */
- bank->BCR = (1 << 12) | (1 << 4) | 1;
- bank->BTR = (3 << 8);
+ /* Everything else is cleared (BCR1) */
+ bank->BCR = 0x0000;
+
+ /* Memory type is SRAM */
+ bank->BCR &= ~(FSMC_BCR_MTYP); // '00'
+
+ /* Databus width is 16bits */
+ bank->BCR &= ~(FSMC_BCR_MWID);
+ bank->BCR |= 0x1 << 4; // '01'
+
+ /* Memory is nonmultiplexed */
+ bank->BCR &= ~(FSMC_BCR_MUXEN); // '0'
+
+ /* Need write enable to write to the chip */
+ bank->BCR |= FSMC_BCR_WREN;
+
+ /* Set ADDSET */
+ bank->BTR &= ~(FSMC_BTR_ADDSET);
+ bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET);
+
+ /* Set DATAST */
+ bank->BTR &= ~(FSMC_BTR_DATAST);
+ bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8));
+
+ /* Enable channel 1 */
+ bank->BCR |= FSMC_BCR_MBKEN; // '1'
/* (FSMC_BWTR3 not used for this simple configuration.) */
}
diff --git a/libmaple/fsmc.h b/libmaple/fsmc.h
index 7be1968..e83b529 100644
--- a/libmaple/fsmc.h
+++ b/libmaple/fsmc.h
@@ -80,7 +80,6 @@ typedef struct {
#define FSMC_BWTR_DATLAT 0b00001111000000000000000000000000
#define FSMC_BWTR_ACCMOD 0b00110000000000000000000000000000
-void fsmc_init_gpios(void);
void fsmc_native_sram_init(void);
#ifdef __cplusplus
diff --git a/libmaple/gpio.c b/libmaple/gpio.c
index 0ebc130..71e5230 100644
--- a/libmaple/gpio.c
+++ b/libmaple/gpio.c
@@ -34,13 +34,9 @@ void gpio_init(void) {
rcc_clk_enable(RCC_GPIOA);
rcc_clk_enable(RCC_GPIOB);
rcc_clk_enable(RCC_GPIOC);
-#if NR_GPIO_PORTS >= 4
- /* Maple, but not Maple Mini (D0 and D1 are used for OSC on Mini,
- and those are the only Port D pins). */
+#if NR_GPIO_PORTS >= 4 /* Maple, but not Maple Mini */
rcc_clk_enable(RCC_GPIOD);
-#endif
-#if NR_GPIO_PORTS >= 7
- /* Maple Native (high density only) */
+#elif NR_GPIO_PORTS >= 7 /* Maple Native (high density only) */
rcc_clk_enable(RCC_GPIOE);
rcc_clk_enable(RCC_GPIOF);
rcc_clk_enable(RCC_GPIOG);
diff --git a/libmaple/libmaple.h b/libmaple/libmaple.h
index f893cff..02e27d3 100644
--- a/libmaple/libmaple.h
+++ b/libmaple/libmaple.h
@@ -42,20 +42,6 @@
#define DEBUG_LEVEL DEBUG_ALL
#endif
-/* Bitbanded Memory sections */
-#define BITBAND_SRAM_REF 0x20000000
-#define BITBAND_SRAM_BASE 0x22000000
-#define BITBAND_PERI_REF 0x40000000
-#define BITBAND_PERI_BASE 0x42000000
-
-#define USB_CONFIG_MAX_POWER (100 >> 1)
-#define RESET_DELAY (100)
-
-#define ERROR_USART_NUM USART2
-#define ERROR_USART_BAUD 9600
-#define ERROR_TX_PORT GPIOA_BASE
-#define ERROR_TX_PIN 2
-
/* MCU-specific configuration */
#if defined(MCU_STM32F103RB)
/* e.g., LeafLabs Maple */
@@ -88,21 +74,39 @@
#define VCOM_ID_PRODUCT 0x0004
#define USB_DISC_BANK GPIOC_BASE
#define USB_DISC_PIN 12
+ #define USB_CONFIG_MAX_POWER (100 >> 1)
+ #define RESET_DELAY (100)
/* Where to put usercode (based on space reserved for bootloader) */
#define USER_ADDR_ROM 0x08005000
#define USER_ADDR_RAM 0x20000C00
- #define STACK_TOP 0x20000800 /* FIXME can this possibly be correct? */
+ #define STACK_TOP 0x20000800
+ /* Debug port settings (from ASSERT) */
#define ERROR_LED_PORT GPIOB_BASE
#define ERROR_LED_PIN 12
+ #define ERROR_USART_NUM USART2
+ #define ERROR_USART_BAUD 9600
+ #define ERROR_TX_PORT GPIOA_BASE
+ #define ERROR_TX_PIN 2
+
+ /* Just in case, most boards have at least some memory */
+ #ifndef RAMSIZE
+ # define RAMSIZE (caddr_t)0x50000
+ #endif
+
+ /* Bitbanded Memory sections */
+ #define BITBAND_SRAM_REF 0x20000000
+ #define BITBAND_SRAM_BASE 0x22000000
+ #define BITBAND_PERI_REF 0x40000000
+ #define BITBAND_PERI_BASE 0x42000000
#elif defined(MCU_STM32F103ZE)
/* e.g., LeafLabs Maple Native */
#define NR_GPIO_PORTS 7
#define NR_GPIO_PINS 100
- #define NR_BKP_REGS 42
+ #define NR_BKP_REGS 42 /* TODO test on Native */
#define NR_TIMERS 8
#define NR_USART 5 /* NB: 4 and 5 are UART only */
#define NR_FSMC 1
@@ -112,6 +116,8 @@
#define VCOM_ID_PRODUCT 0x0004
#define USB_DISC_BANK GPIOB_BASE
#define USB_DISC_PIN 8
+ #define USB_CONFIG_MAX_POWER (100 >> 1)
+ #define RESET_DELAY (100)
#define USER_ADDR_ROM 0x08005000
#define USER_ADDR_RAM 0x20000C00
@@ -119,13 +125,26 @@
#define ERROR_LED_PORT GPIOC_BASE
#define ERROR_LED_PIN 15
+ #define ERROR_USART_NUM USART1
+ #define ERROR_USART_BAUD 9600
+ #define ERROR_TX_PORT GPIOA_BASE
+ #define ERROR_TX_PIN 10
+
+ #ifndef RAMSIZE
+ # define RAMSIZE (caddr_t)0x50000
+ #endif
+
+ #define BITBAND_SRAM_REF 0x20000000
+ #define BITBAND_SRAM_BASE 0x22000000
+ #define BITBAND_PERI_REF 0x40000000
+ #define BITBAND_PERI_BASE 0x42000000
#elif defined(MCU_STM32F103CB)
/* e.g., LeafLabs Maple Mini */
#define NR_GPIO_PORTS 3
#define NR_GPIO_PINS 34
- #define NR_BKP_REGS 10
+ #define NR_BKP_REGS 10 /* TODO test on Mini */
#define NR_TIMERS 4
#define NR_USART 3
#define NR_FSMC 0
@@ -135,36 +154,29 @@
#define VCOM_ID_PRODUCT 0x0005
#define USB_DISC_BANK GPIOB_BASE
#define USB_DISC_PIN 9
+ #define USB_CONFIG_MAX_POWER (100 >> 1)
+ #define RESET_DELAY 100
#define USER_ADDR_ROM 0x08005000
#define USER_ADDR_RAM 0x20000C00
#define STACK_TOP 0x20000800
#define ERROR_LED_PORT GPIOB_BASE
- #define ERROR_LED_PIN 1
-
-#elif defined(MCU_STM32F103RE)
- /* e.g., LeafLabs Maple RET6 Edition */
-
- #define NR_GPIO_PORTS 4
- #define NR_GPIO_PINS 39
- #define NR_BKP_REGS 42
- #define NR_TIMERS 8
- #define NR_USART 5 /* NB: 4 and 5 are UART only */
- #define NR_FSMC 0
- #define NR_DAC_PINS 0 /* HACK: LED hooked up to DAC2 */
-
- #define VCOM_ID_VENDOR 0x1EAF
- #define VCOM_ID_PRODUCT 0x0004
- #define USB_DISC_BANK GPIOC_BASE
- #define USB_DISC_PIN 12
-
- #define USER_ADDR_ROM 0x08005000
- #define USER_ADDR_RAM 0x20000C00
- #define STACK_TOP 0x20000800
-
- #define ERROR_LED_PORT GPIOA_BASE
- #define ERROR_LED_PIN 5
+ #define ERROR_LED_PIN 12
+ #define ERROR_USART_NUM USART2
+ #define ERROR_USART_BAUD 9600
+ #define ERROR_TX_PORT GPIOA_BASE
+ #define ERROR_TX_PIN 2
+
+ #ifndef RAMSIZE
+ # define RAMSIZE (caddr_t)0x50000
+ #endif
+
+ /* Bitbanded Memory sections */
+ #define BITBAND_SRAM_REF 0x20000000
+ #define BITBAND_SRAM_BASE 0x22000000
+ #define BITBAND_PERI_REF 0x40000000
+ #define BITBAND_PERI_BASE 0x42000000
#else
diff --git a/libmaple/usb/usb_callbacks.c b/libmaple/usb/usb_callbacks.c
index 375d204..ccb0fdd 100644
--- a/libmaple/usb/usb_callbacks.c
+++ b/libmaple/usb/usb_callbacks.c
@@ -88,19 +88,19 @@ void vcomDataRxCb(void) {
}
if (cmpMatch) {
- asm volatile("mov r0, %[stack_top] \n\t" // Reset the stack
+ asm volatile("mov r0, %[stack_top] \n\t" // Reset the stack
"mov sp, r0 \n\t"
"mov r0, #1 \n\t"
"mov r1, %[target_addr] \n\t"
"mov r2, %[cpsr] \n\t"
- "push {r2} \n\t" // Fake xPSR
- "push {r1} \n\t" // Target address for PC
- "push {r0} \n\t" // Fake LR
- "push {r0} \n\t" // Fake R12
- "push {r0} \n\t" // Fake R3
- "push {r0} \n\t" // Fake R2
- "push {r0} \n\t" // Fake R1
- "push {r0} \n\t" // Fake R0
+ "push {r2} \n\t" // Fake xPSR
+ "push {r1} \n\t" // Target address for PC
+ "push {r0} \n\t" // Fake LR
+ "push {r0} \n\t" // Fake R12
+ "push {r0} \n\t" // Fake R3
+ "push {r0} \n\t" // Fake R2
+ "push {r0} \n\t" // Fake R1
+ "push {r0} \n\t" // Fake R0
"mov lr, %[exc_return] \n\t"
"bx lr"
:
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