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-rw-r--r--libmaple/exc.c1
-rw-r--r--libmaple/fsmc.c120
-rw-r--r--libmaple/fsmc.h86
-rw-r--r--libmaple/gpio.c3
-rw-r--r--libmaple/gpio.h3
-rw-r--r--libmaple/rcc.h34
-rw-r--r--libmaple/rules.mk1
-rw-r--r--libmaple/util.c11
-rw-r--r--libmaple/util.h1
9 files changed, 246 insertions, 14 deletions
diff --git a/libmaple/exc.c b/libmaple/exc.c
index dd02476..3d01492 100644
--- a/libmaple/exc.c
+++ b/libmaple/exc.c
@@ -38,6 +38,7 @@ void NMIException(void) {
}
void HardFaultException(void) {
+ return;
ASSERT(0);
while(1)
;
diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c
new file mode 100644
index 0000000..17431f5
--- /dev/null
+++ b/libmaple/fsmc.c
@@ -0,0 +1,120 @@
+
+/* *****************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ * ****************************************************************************/
+
+#include "libmaple.h"
+#include "rcc.h"
+#include "gpio.h"
+#include "fsmc.h"
+
+#define FSMC_ADDSET 0x5
+#define FSMC_DATAST 0x5
+
+// Setup the FSMC peripheral to use the SRAM chip on the maple native
+// as an external segment of memory space.
+// This is for the IS62WV51216BLL 8meg 55ns chip
+void fsmc_native_sram_init(void) {
+ FSMC_Bank *bank;
+
+ // First we setup all the GPIO pins.
+ // Data lines...
+ gpio_set_mode(GPIOD_BASE, 0, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 1, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 8, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 9, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 7, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 8, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 9, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP);
+ // Address lines...
+ gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 0, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 1, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 2, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 3, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 4, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 5, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 0, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 1, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 2, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 3, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 4, MODE_AF_OUTPUT_PP);
+ gpio_set_mode(GPIOG_BASE, 5, MODE_AF_OUTPUT_PP);
+ // And control lines...
+ gpio_set_mode(GPIOD_BASE, 4, MODE_AF_OUTPUT_PP); // NOE
+ gpio_set_mode(GPIOD_BASE, 5, MODE_AF_OUTPUT_PP); // NWE
+
+ gpio_set_mode(GPIOD_BASE, 7, MODE_AF_OUTPUT_PP); // NE1
+ gpio_set_mode(GPIOG_BASE, 9, MODE_AF_OUTPUT_PP); // NE2
+ gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP); // NE3
+ gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP); // NE4
+
+ gpio_set_mode(GPIOE_BASE, 0, MODE_AF_OUTPUT_PP); // NBL0
+ gpio_set_mode(GPIOE_BASE, 1, MODE_AF_OUTPUT_PP); // NBL1
+
+ // Then we configure the FSMC SRAM channel 1 peripheral
+ // (the SRAM part of the FSMC is "bank 1")
+ bank = (FSMC_Bank*)(FSMC1_BASE);
+
+ // Everything else is cleared (BCR1)
+ bank->BCR = 0x0000;
+
+ // Memory type is SRAM
+ bank->BCR &= ~(FSMC_BCR_MTYP); // '00'
+
+ // Databus width is 16bits
+ bank->BCR &= ~(FSMC_BCR_MWID);
+ bank->BCR |= 0x1 << 4; // '01'
+
+ // Memory is nonmultiplexed
+ bank->BCR &= ~(FSMC_BCR_MUXEN); // '0'
+
+ // Set ADDSET
+ bank->BTR &= ~(FSMC_BTR_ADDSET);
+ bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET);
+
+ // Set DATAST
+ bank->BTR &= ~(FSMC_BTR_DATAST);
+ bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8));
+
+ // Enable bank1
+ bank->BCR |= FSMC_BCR_MBKEN; // '1'
+
+ // FSMC_BWTR3 not used
+}
+
diff --git a/libmaple/fsmc.h b/libmaple/fsmc.h
new file mode 100644
index 0000000..0ac4084
--- /dev/null
+++ b/libmaple/fsmc.h
@@ -0,0 +1,86 @@
+/* *****************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ * ****************************************************************************/
+
+/*
+ * See ../notes/fsmc.txt for more info
+ */
+
+#ifndef _FSMC_H_
+#define _FSMC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+// There are 4 FSMC chip-select devices; here are the SRAM-specific registers
+// for each
+
+#define FSMC1_BASE 0xA0000000
+#define FSMC2_BASE 0xA0000008
+#define FSMC3_BASE 0xA0000010
+#define FSMC4_BASE 0xA0000018
+
+typedef struct {
+ volatile uint32 BCR;
+ volatile uint32 BTR;
+ //uint32 pad[62]; // double check this?
+ //__io uint32 BWTR;
+} FSMC_Bank;
+
+// And here are the register bit ranges
+#define FSMC_BCR_MBKEN 0b00000000000000000000000000000001
+#define FSMC_BCR_MUXEN 0b00000000000000000000000000000010
+#define FSMC_BCR_MTYP 0b00000000000000000000000000001100
+#define FSMC_BCR_MWID 0b00000000000000000000000000110000
+#define FSMC_BCR_FACCEN 0b00000000000000000000000001000000
+#define FSMC_BCR_BURSTEN 0b00000000000000000000000100000000
+#define FSMC_BCR_WAITPOL 0b00000000000000000000001000000000
+#define FSMC_BCR_WRAPMOD 0b00000000000000000000010000000000
+#define FSMC_BCR_WAITCFG 0b00000000000000000000100000000000
+#define FSMC_BCR_WREN 0b00000000000000000001000000000000
+#define FSMC_BCR_WAITEN 0b00000000000000000010000000000000
+#define FSMC_BCR_EXTMOD 0b00000000000000000100000000000000
+#define FSMC_BCR_CBURSTRW 0b00000000000010000000000000000000
+#define FSMC_BTR_ADDSET 0b00000000000000000000000000001111
+#define FSMC_BTR_ADDHOLD 0b00000000000000000000000011110000
+#define FSMC_BTR_DATAST 0b00000000000000001111111100000000
+#define FSMC_BTR_BUSTURN 0b00000000000011110000000000000000
+#define FSMC_BTR_CLKDIV 0b00000000111100000000000000000000
+#define FSMC_BTR_DATALAT 0b00001111000000000000000000000000
+#define FSMC_BTR_ACCMOD 0b00110000000000000000000000000000
+#define FSMC_BWTR_ADDSET 0b00000000000000000000000000001111
+#define FSMC_BWTR_ADDHLD 0b00000000000000000000000011110000
+#define FSMC_BWTR_DATAST 0b00000000000000001111111100000000
+#define FSMC_BWTR_CLKDIV 0b00000000111100000000000000000000
+#define FSMC_BWTR_DATLAT 0b00001111000000000000000000000000
+#define FSMC_BWTR_ACCMOD 0b00110000000000000000000000000000
+
+void fsmc_native_sram_init(void);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+
+#endif
diff --git a/libmaple/gpio.c b/libmaple/gpio.c
index 9334c1e..a47e623 100644
--- a/libmaple/gpio.c
+++ b/libmaple/gpio.c
@@ -37,6 +37,9 @@ void gpio_init(void) {
rcc_enable_clk_gpiob();
rcc_enable_clk_gpioc();
rcc_enable_clk_gpiod();
+ rcc_enable_clk_gpioe();
+ rcc_enable_clk_gpiof();
+ rcc_enable_clk_gpiog();
rcc_enable_clk_afio();
}
diff --git a/libmaple/gpio.h b/libmaple/gpio.h
index 74320e6..edbd4f0 100644
--- a/libmaple/gpio.h
+++ b/libmaple/gpio.h
@@ -48,6 +48,9 @@
#define GPIOB_BASE (GPIO_Port*)0x40010C00
#define GPIOC_BASE (GPIO_Port*)0x40011000
#define GPIOD_BASE (GPIO_Port*)0x40011400
+#define GPIOE_BASE (GPIO_Port*)0x40011800
+#define GPIOF_BASE (GPIO_Port*)0x40011C00
+#define GPIOG_BASE (GPIO_Port*)0x40012000
#define GPIO_SPEED_50MHZ (0x3)
diff --git a/libmaple/rcc.h b/libmaple/rcc.h
index 8e12032..8ad70e5 100644
--- a/libmaple/rcc.h
+++ b/libmaple/rcc.h
@@ -122,11 +122,13 @@ struct rcc_device {
#define RCC_APB2ENR_TIM1EN BIT(11)
#define RCC_APB2ENR_ADC2EN BIT(10)
#define RCC_APB2ENR_ADC1EN BIT(9)
-#define RCC_APB2ENR_IOEEN BIT(6)
-#define RCC_APB2ENR_IODEN BIT(5)
-#define RCC_APB2ENR_IOCEN BIT(4)
-#define RCC_APB2ENR_IOBEN BIT(3)
-#define RCC_APB2ENR_IOAEN BIT(2)
+#define RCC_APB2ENR_IOPGEN BIT(8)
+#define RCC_APB2ENR_IOPFEN BIT(7)
+#define RCC_APB2ENR_IOPEEN BIT(6)
+#define RCC_APB2ENR_IOPDEN BIT(5)
+#define RCC_APB2ENR_IOPCEN BIT(4)
+#define RCC_APB2ENR_IOPBEN BIT(3)
+#define RCC_APB2ENR_IOPAEN BIT(2)
#define RCC_APB2ENR_AFIOEN BIT(0)
/* APB1 peripheral clock enable bits */
@@ -138,6 +140,17 @@ struct rcc_device {
#define RCC_APB1ENR_SPI2EN BIT(14)
#define RCC_APB1ENR_USB BIT(23)
+/* AHB peripheral clock enable bits */
+#define RCC_AHBENR_DMA1EN BIT(0)
+#define RCC_AHBENR_DMA2EN BIT(1)
+#define RCC_AHBENR_SRAMEN BIT(2)
+#define RCC_AHBENR_FLITFEN BIT(4)
+#define RCC_AHBENR_CRCEN BIT(6)
+#define RCC_AHBENR_FSMCEN BIT(8)
+#define RCC_AHBENR_SDIOEN BIT(10)
+
+#define rcc_enable_clk_fsmc() __set_bits(RCC_AHBENR, RCC_AHBENR_FSMCEN)
+
#define rcc_enable_clk_spi1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_SPI1EN)
#define rcc_enable_clk_spi2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_SPI2EN)
@@ -146,10 +159,13 @@ struct rcc_device {
#define rcc_enable_clk_timer3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM3EN)
#define rcc_enable_clk_timer4() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM4EN)
-#define rcc_enable_clk_gpioa() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOAEN)
-#define rcc_enable_clk_gpiob() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOBEN)
-#define rcc_enable_clk_gpioc() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOCEN)
-#define rcc_enable_clk_gpiod() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IODEN)
+#define rcc_enable_clk_gpioa() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPAEN)
+#define rcc_enable_clk_gpiob() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPBEN)
+#define rcc_enable_clk_gpioc() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPCEN)
+#define rcc_enable_clk_gpiod() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPDEN)
+#define rcc_enable_clk_gpioe() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPEEN)
+#define rcc_enable_clk_gpiof() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPFEN)
+#define rcc_enable_clk_gpiog() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOPGEN)
#define rcc_enable_clk_afio() __set_bits(RCC_APB2ENR, RCC_APB2ENR_AFIOEN)
#define rcc_enable_clk_usart1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_USART1EN)
diff --git a/libmaple/rules.mk b/libmaple/rules.mk
index 60673fe..db9540a 100644
--- a/libmaple/rules.mk
+++ b/libmaple/rules.mk
@@ -25,6 +25,7 @@ cSRCS_$(d) := systick.c \
rcc.c \
flash.c \
spi.c \
+ fsmc.c \
usb/usb.c \
usb/usb_callbacks.c \
usb/usb_hardware.c \
diff --git a/libmaple/util.c b/libmaple/util.c
index 36173ee..8c25257 100644
--- a/libmaple/util.c
+++ b/libmaple/util.c
@@ -36,11 +36,11 @@
#include "adc.h"
#include "timers.h"
-#define ERROR_LED_PORT GPIOA_BASE
-#define ERROR_LED_PIN 5
-#define ERROR_USART_NUM 2
+#define ERROR_LED_PORT GPIOC_BASE
+#define ERROR_LED_PIN 15
+#define ERROR_USART_NUM 1
#define ERROR_USART_BAUD 9600
-#define ERROR_TX_PIN 2
+#define ERROR_TX_PIN 10
#define ERROR_TX_PORT GPIOA_BASE
/* Error assert + fade */
@@ -76,7 +76,8 @@ void _fail(const char* file, int line, const char* exp) {
usart_putstr(ERROR_USART_NUM, ": ");
usart_putudec(ERROR_USART_NUM, line);
usart_putc(ERROR_USART_NUM, '\n');
-
+ usart_putc(ERROR_USART_NUM, '\r');
+
/* Turn on the error LED */
gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_MODE_OUTPUT_PP);
diff --git a/libmaple/util.h b/libmaple/util.h
index a18fa84..1aae7bd 100644
--- a/libmaple/util.h
+++ b/libmaple/util.h
@@ -48,6 +48,7 @@
#define BITBAND_PERI_BASE 0x42000000
#define BITBAND_PERI(a,b) ((BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4))) // Convert PERI address
+
#define COUNTFLAG *((volatile unsigned char*) (BITBAND_PERI(SYSTICK_CSR,2)))
#define REG_SET(reg, val) (*(volatile uint32*)(reg) = (val))