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-rw-r--r--libmaple/spi.c154
1 files changed, 78 insertions, 76 deletions
diff --git a/libmaple/spi.c b/libmaple/spi.c
index 68855a5..8bba0d6 100644
--- a/libmaple/spi.c
+++ b/libmaple/spi.c
@@ -1,4 +1,4 @@
-/* *****************************************************************************
+/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
@@ -20,7 +20,7 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
- * ****************************************************************************/
+ *****************************************************************************/
/**
* @brief libmaple serial peripheral interface (SPI) definitions
@@ -42,27 +42,27 @@
#include "spi.h"
typedef struct spi_dev {
- SPI *base;
- GPIO_Port *port;
- uint8 sck_pin;
- uint8 miso_pin;
- uint8 mosi_pin;
+ SPI *base;
+ GPIO_Port *port;
+ uint8 sck_pin;
+ uint8 miso_pin;
+ uint8 mosi_pin;
} spi_dev;
static const spi_dev spi_dev1 = {
- .base = (SPI*)SPI1_BASE,
- .port = GPIOA_BASE,
- .sck_pin = 5,
- .miso_pin = 6,
- .mosi_pin = 7
+ .base = (SPI*)SPI1_BASE,
+ .port = GPIOA_BASE,
+ .sck_pin = 5,
+ .miso_pin = 6,
+ .mosi_pin = 7
};
static const spi_dev spi_dev2 = {
- .base = (SPI*)SPI2_BASE,
- .port = GPIOB_BASE,
- .sck_pin = 13,
- .miso_pin = 14,
- .mosi_pin = 15
+ .base = (SPI*)SPI2_BASE,
+ .port = GPIOB_BASE,
+ .sck_pin = 13,
+ .miso_pin = 14,
+ .mosi_pin = 15
};
static void spi_gpio_cfg(const spi_dev *dev);
@@ -78,82 +78,84 @@ void spi_init(uint32 spi_num,
uint32 prescale,
uint32 endian,
uint32 mode) {
- ASSERT(spi_num == 1 || spi_num == 2);
- ASSERT(mode < 4);
-
- SPI *spi;
- uint32 cr1 = 0;
-
- switch (spi_num) {
- case 1:
- /* limit to 18 mhz max speed */
- ASSERT(prescale != CR1_BR_PRESCALE_2);
- spi = (SPI*)SPI1_BASE;
- rcc_clk_enable(RCC_SPI1);
- spi_gpio_cfg(&spi_dev1);
- break;
- case 2:
- spi = (SPI*)SPI2_BASE;
- rcc_clk_enable(RCC_SPI2);
- spi_gpio_cfg(&spi_dev2);
- break;
- }
-
- cr1 = prescale | endian | mode | CR1_MSTR | CR1_SSI | CR1_SSM;
- spi->CR1 = cr1;
-
- /* Peripheral enable */
- spi->CR1 |= CR1_SPE;
+ ASSERT(spi_num == 1 || spi_num == 2);
+ ASSERT(mode < 4);
+
+ SPI *spi;
+ uint32 cr1 = 0;
+
+ switch (spi_num) {
+ case 1:
+ /* limit to 18 mhz max speed */
+ ASSERT(prescale != CR1_BR_PRESCALE_2);
+ spi = (SPI*)SPI1_BASE;
+ rcc_clk_enable(RCC_SPI1);
+ spi_gpio_cfg(&spi_dev1);
+ break;
+ case 2:
+ spi = (SPI*)SPI2_BASE;
+ rcc_clk_enable(RCC_SPI2);
+ spi_gpio_cfg(&spi_dev2);
+ break;
+ }
+
+ cr1 = prescale | endian | mode | CR1_MSTR | CR1_SSI | CR1_SSM;
+ spi->CR1 = cr1;
+
+ /* Peripheral enable */
+ spi->CR1 |= CR1_SPE;
}
-
/**
* @brief SPI synchronous 8-bit write, blocking.
* @param spi_num which spi to send on
* @return data shifted back from the slave
*/
uint8 spi_tx_byte(uint32 spi_num, uint8 data) {
- SPI *spi;
+ SPI *spi;
- ASSERT(spi_num == 1 || spi_num == 2);
+ spi = (spi_num == 1) ? (SPI*)SPI1_BASE : (SPI*)SPI2_BASE;
- spi = (spi_num == 1) ? (SPI*)SPI1_BASE : (SPI*)SPI2_BASE;
+ while (!(spi->SR & SR_TXE))
+ ;
- spi->DR = data;
+ spi->DR = data;
- while (!(spi->SR & SR_TXE) ||
- (spi->SR & SR_BSY))
- ;
+ while (!(spi->SR & SR_RXNE))
+ ;
- return spi->DR;
+ return spi->DR;
}
uint8 spi_tx(uint32 spi_num, uint8 *buf, uint32 len) {
- SPI *spi;
- uint32 i = 0;
- uint8 rc;
-
- ASSERT(spi_num == 1 || spi_num == 2);
- spi = (spi_num == 1) ? (SPI*)SPI1_BASE : (SPI*)SPI2_BASE;
-
- if (!len) {
- return 0;
- }
-
- while (i < len) {
- spi->DR = buf[i];
- while (!(spi->SR & SR_TXE) ||
- (spi->SR & SR_BSY) ||
- !(spi->SR & SR_RXNE))
- ;
- rc = spi->DR;
- i++;
- }
- return rc;
+ SPI *spi;
+ uint32 i = 0;
+ uint8 rc;
+
+ ASSERT(spi_num == 1 || spi_num == 2);
+ spi = (spi_num == 1) ? (SPI*)SPI1_BASE : (SPI*)SPI2_BASE;
+
+ if (!len) {
+ return 0;
+ }
+
+ while (i < len) {
+ while (!(spi->SR & SR_TXE))
+ ;
+
+ spi->DR = buf[i];
+
+ while (!(spi->SR & SR_RXNE))
+ ;
+
+ rc = spi->DR;
+ i++;
+ }
+ return rc;
}
static void spi_gpio_cfg(const spi_dev *dev) {
- gpio_set_mode(dev->port, dev->sck_pin, GPIO_MODE_AF_OUTPUT_PP);
- gpio_set_mode(dev->port, dev->miso_pin, GPIO_MODE_AF_OUTPUT_PP);
- gpio_set_mode(dev->port, dev->mosi_pin, GPIO_MODE_AF_OUTPUT_PP);
+ gpio_set_mode(dev->port, dev->sck_pin, GPIO_MODE_AF_OUTPUT_PP);
+ gpio_set_mode(dev->port, dev->miso_pin, GPIO_MODE_AF_OUTPUT_PP);
+ gpio_set_mode(dev->port, dev->mosi_pin, GPIO_MODE_AF_OUTPUT_PP);
}