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Diffstat (limited to 'libmaple/scb.h')
| -rw-r--r-- | libmaple/scb.h | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/libmaple/scb.h b/libmaple/scb.h new file mode 100644 index 0000000..f851a08 --- /dev/null +++ b/libmaple/scb.h @@ -0,0 +1,58 @@ +/* ***************************************************************************** + * The MIT License + * + * Copyright (c) 2010 Perry Hung. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * ****************************************************************************/ + +/** + * @brief System control block header + */ + +#ifndef _SCB_H_ +#define _SCB_H_ + +typedef struct scb_reg_map { + __io uint32 CPUID; // CPU ID Base Register + __io uint32 ICSR; // Interrupt Control State Register + __io uint32 VTOR; // Vector Table Offset Register + __io uint32 AIRCR; // Application Interrupt / Reset Control Register + __io uint32 SCR; // System Control Register + __io uint32 CCR; // Configuration Control Register + __io uint8 SHP[12]; // System Handlers Priority Registers (4-7, 8-11, 12-15) + __io uint32 SHCSR; // System Handler Control and State Register + __io uint32 CFSR; // Configurable Fault Status Register + __io uint32 HFSR; // Hard Fault Status Register + __io uint32 DFSR; // Debug Fault Status Register + __io uint32 MMFAR; // Mem Manage Address Register + __io uint32 BFAR; // Bus Fault Address Register + __io uint32 AFSR; // Auxiliary Fault Status Register + __io uint32 PFR[2]; // Processor Feature Register + __io uint32 DFR; // Debug Feature Register + __io uint32 ADR; // Auxiliary Feature Register + __io uint32 MMFR[4]; // Memory Model Feature Register + __io uint32 ISAR[5]; // ISA Feature Register +} scb_reg_map; + +#define SCB_BASE 0xE000ED00 +#define SCB ((scb_reg_map*)(SCB_BASE)) + +#endif + |