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-rw-r--r--libmaple/stm32f1/bkp.c4
-rw-r--r--libmaple/stm32f1/dma.c1
-rw-r--r--libmaple/stm32f1/include/series/dma.h10
3 files changed, 13 insertions, 2 deletions
diff --git a/libmaple/stm32f1/bkp.c b/libmaple/stm32f1/bkp.c
index f435ff1..01ad419 100644
--- a/libmaple/stm32f1/bkp.c
+++ b/libmaple/stm32f1/bkp.c
@@ -62,14 +62,14 @@ void bkp_init(void) {
* @see bkp_init()
*/
void bkp_enable_writes(void) {
- *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 1;
+ *bb_perip(&PWR_BASE->CR, PWR_CR_DBP_BIT) = 1;
}
/**
* Disable write access to the backup registers.
*/
void bkp_disable_writes(void) {
- *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 0;
+ *bb_perip(&PWR_BASE->CR, PWR_CR_DBP_BIT) = 0;
}
/**
diff --git a/libmaple/stm32f1/dma.c b/libmaple/stm32f1/dma.c
index 5364a04..6400d15 100644
--- a/libmaple/stm32f1/dma.c
+++ b/libmaple/stm32f1/dma.c
@@ -145,6 +145,7 @@ static int config_to_per(dma_tube_reg_map *chregs, dma_tube_config *cfg) {
cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC,
cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC,
(cfg_ccr_flags(cfg->tube_flags) | DMA_CCR_DIR_FROM_MEM));
+ chregs->CNDTR = cfg->tube_nr_xfers;
chregs->CMAR = (uint32)cfg->tube_src;
chregs->CPAR = (uint32)cfg->tube_dst;
return DMA_TUBE_CFG_SUCCESS;
diff --git a/libmaple/stm32f1/include/series/dma.h b/libmaple/stm32f1/include/series/dma.h
index 3b19e2b..bedb602 100644
--- a/libmaple/stm32f1/include/series/dma.h
+++ b/libmaple/stm32f1/include/series/dma.h
@@ -145,6 +145,16 @@ typedef struct dma_tube_reg_map {
/* Interrupt status register */
+#define DMA_ISR_TEIF_BIT 3
+#define DMA_ISR_HTIF_BIT 2
+#define DMA_ISR_TCIF_BIT 1
+#define DMA_ISR_GIF_BIT 0
+
+#define DMA_ISR_TEIF (1 << DMA_ISR_TEIF_BIT)
+#define DMA_ISR_HTIF (1 << DMA_ISR_HTIF_BIT)
+#define DMA_ISR_TCID (1 << DMA_ISR_TCIF_BIT)
+#define DMA_ISR_GIF (1 << DMA_ISR_GIF_BIT)
+
#define DMA_ISR_TEIF7_BIT 27
#define DMA_ISR_HTIF7_BIT 26
#define DMA_ISR_TCIF7_BIT 25