libmaple: Refactor ADC routines

ADC routines rewritten, support for ADC2, 3, added.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

3 files changed, 157 insertions, 159 deletions

diff --git a/wirish/boards.h b/wirish/boards.h
index f8505ab..ac3a74d 100644
--- a/wirish/boards.h
+++ b/wirish/boards.h
@@ -51,18 +51,13 @@ enum {
     D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105,
     D106, D107, D108, D109, D110, D111, };
 
-/* Set of all possible analog pin names; not all boards have all these */
-enum {
-    ADC0, ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, ADC10, ADC11,
-    ADC12, ADC13, ADC14, ADC15, ADC16, ADC17, ADC18, ADC19, ADC20, };
-
 #define ADC_INVALID       0xFFFFFFFF
 
 /* Types used for the tables below */
 typedef struct PinMapping {
     GPIO_Port *port;
     uint32 pin;
-    uint32 adc;
+    uint32 adc_channel;
     TimerCCR timer_ccr;
     uint32 exti_port;
     timer_dev_num timer_num;
@@ -80,89 +75,89 @@ typedef struct PinMapping {
 
     static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
         /* D0/PA3 */
-        {GPIOA_BASE,  3,        ADC3, TIMER2_CH4_CCR,  EXTI_CONFIG_PORTA, TIMER2, 4},
+        {GPIOA_BASE,  3,           3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2, 4},
         /* D1/PA2 */
-        {GPIOA_BASE,  2,        ADC2, TIMER2_CH3_CCR,  EXTI_CONFIG_PORTA, TIMER2, 3},
+        {GPIOA_BASE,  2,           2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2, 3},
         /* D2/PA0 */
-        {GPIOA_BASE,  0,        ADC0, TIMER2_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER2, 1},
+        {GPIOA_BASE,  0,           0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2, 1},
         /* D3/PA1 */
-        {GPIOA_BASE,  1,        ADC1, TIMER2_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER2, 2},
+        {GPIOA_BASE,  1,           1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2, 2},
         /* D4/PB5 */
-        {GPIOB_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D5/PB6 */
-        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR,  EXTI_CONFIG_PORTB, TIMER4, 1},
+        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB, TIMER4, 1},
         /* D6/PA8 */
-        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER1, 1},
+        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA, TIMER1, 1},
         /* D7/PA9 */
-        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER1, 2},
+        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA, TIMER1, 2},
         /* D8/PA10 */
-        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR,  EXTI_CONFIG_PORTA, TIMER1, 3},
+        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA, TIMER1, 3},
         /* D9/PB7 */
-        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR,  EXTI_CONFIG_PORTB, TIMER4, 2},
+        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB, TIMER4, 2},
         /* D10/PA4 */
-        {GPIOA_BASE,  4,        ADC4,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  4,           4,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D11/PA7 */
-        {GPIOA_BASE,  7,        ADC7, TIMER3_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER3, 2},
+        {GPIOA_BASE,  7,           7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3, 2},
         /* D12/PA6 */
-        {GPIOA_BASE,  6,        ADC6, TIMER3_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER3, 1},
+        {GPIOA_BASE,  6,           6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3, 1},
         /* D13/PA5 */
-        {GPIOA_BASE,  5,        ADC5,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  5,           5,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D14/PB8 */
-        {GPIOB_BASE,  8, ADC_INVALID, TIMER4_CH3_CCR,  EXTI_CONFIG_PORTB, TIMER4, 3},
+        {GPIOB_BASE,  8, ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB, TIMER4, 3},
 
         /* Little header */
 
         /* D15/PC0 */
-        {GPIOC_BASE,  0,       ADC10,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  0,          10,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D16/PC1 */
-        {GPIOC_BASE,  1,       ADC11,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  1,          11,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D17/PC2 */
-        {GPIOC_BASE,  2,       ADC12,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  2,          12,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D18/PC3 */
-        {GPIOC_BASE,  3,       ADC13,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  3,          13,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D19/PC4 */
-        {GPIOC_BASE,  4,       ADC14,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  4,          14,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D20/PC5 */
-        {GPIOC_BASE,  5,       ADC15,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  5,          15,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
 
         /* External header */
 
         /* D21/PC13 */
-        {GPIOC_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D22/PC14 */
-        {GPIOC_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D23/PC15 */
-        {GPIOC_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D24/PB9 */
-        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D25/PD2 */
-        {GPIOD_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D26/PC10 */
-        {GPIOC_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D27/PB0 */
-        {GPIOB_BASE,  0,        ADC8, TIMER3_CH3_CCR,  EXTI_CONFIG_PORTB, TIMER3, 3},
+        {GPIOB_BASE,  0,           8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3, 3},
         /* D28/PB1 */
-        {GPIOB_BASE,  1,        ADC9, TIMER3_CH4_CCR,  EXTI_CONFIG_PORTB, TIMER3, 4},
+        {GPIOB_BASE,  1,           9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3, 4},
         /* D29/PB10 */
-        {GPIOB_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D30/PB11 */
-        {GPIOB_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D31/PB12 */
-        {GPIOB_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D32/PB13 */
-        {GPIOB_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D33/PB14 */
-        {GPIOB_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D34/PB15 */
-        {GPIOB_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D35/PC6 */
-        {GPIOC_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D36/PC7 */
-        {GPIOC_BASE,  7, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  7, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D37/PC8 */
-        {GPIOC_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D38/PC9 (BUT) */
-        {GPIOC_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID}
+        {GPIOC_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID}
     };
 
     #define BOARD_INIT do {                           \
@@ -182,212 +177,212 @@ typedef struct PinMapping {
         /* Top header */
 
         /* D0/PB10 */
-        {GPIOB_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D1/PB2 */
-        {GPIOB_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D2/PB12 */
-        {GPIOB_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D3/PB13 */
-        {GPIOB_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D4/PB14 */
-        {GPIOB_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D5/PB15 */
-        {GPIOB_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D6/PC0 */
-        {GPIOC_BASE,  0,       ADC10,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  0,          10,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D7/PC1 */
-        {GPIOC_BASE,  1,       ADC11,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  1,          11,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D8/PC2 */
-        {GPIOC_BASE,  2,       ADC12,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  2,          12,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D9/PC3 */
-        {GPIOC_BASE,  3,       ADC13,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  3,          13,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D10/PC4 */
-        {GPIOC_BASE,  4,       ADC14,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  4,          14,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D11/PC5 */
-        {GPIOC_BASE,  5,       ADC15,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  5,          15,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D12/PC6 */
-        {GPIOC_BASE,  6, ADC_INVALID, TIMER8_CH1_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 1},
+        {GPIOC_BASE,  6, ADC_INVALID, TIMER8_CH1_CCR, EXTI_CONFIG_PORTC,        TIMER8, 1},
         /* D13/PC7 */
-        {GPIOC_BASE,  7, ADC_INVALID, TIMER8_CH2_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 2},
+        {GPIOC_BASE,  7, ADC_INVALID, TIMER8_CH2_CCR, EXTI_CONFIG_PORTC,        TIMER8, 2},
         /* D14/PC8 */
-        {GPIOC_BASE,  8, ADC_INVALID, TIMER8_CH3_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 3},
+        {GPIOC_BASE,  8, ADC_INVALID, TIMER8_CH3_CCR, EXTI_CONFIG_PORTC,        TIMER8, 3},
         /* D15/PC9 */
-        {GPIOC_BASE,  9, ADC_INVALID, TIMER8_CH4_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 4},
+        {GPIOC_BASE,  9, ADC_INVALID, TIMER8_CH4_CCR, EXTI_CONFIG_PORTC,        TIMER8, 4},
         /* D16/PC10 */
-        {GPIOC_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D17/PC11 */
-        {GPIOC_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D18/PC12 */
-        {GPIOC_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D19/PC13 */
-        {GPIOC_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D20/PC14 */
-        {GPIOC_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D21/PC15 */
-        {GPIOC_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D22/PA8 */
-        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR,  EXTI_CONFIG_PORTA,        TIMER1, 1},
+        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA,        TIMER1, 1},
         /* D23/PA9 */
-        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR,  EXTI_CONFIG_PORTA,        TIMER1, 2},
+        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA,        TIMER1, 2},
         /* D24/PA10 */
-        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR,  EXTI_CONFIG_PORTA,        TIMER1, 3},
+        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA,        TIMER1, 3},
         /* D25/PB9 */
-        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR,  EXTI_CONFIG_PORTB,        TIMER4, 4},
+        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB,        TIMER4, 4},
 
         /* Bottom header */
 
         /* D26/PD2 */
-        {GPIOD_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D27/PD3 */
-        {GPIOD_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D28/PD6 */
-        {GPIOD_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D29/PG11 */
-        {GPIOG_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D30/PG12 */
-        {GPIOG_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D31/PG13 */
-        {GPIOG_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D32/PG14 */
-        {GPIOG_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D33/PG8 */
-        {GPIOG_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D34/PG7 */
-        {GPIOG_BASE,  7, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  7, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D35/PG6 */
-        {GPIOG_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D36/PB5 */
-        {GPIOB_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D37/PB6 */
-        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR,  EXTI_CONFIG_PORTB,        TIMER4, 1},
+        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB,        TIMER4, 1},
         /* D38/PB7 */
-        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR,  EXTI_CONFIG_PORTB,        TIMER4, 2},
+        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB,        TIMER4, 2},
         /* D39/PF6 */
-        {GPIOF_BASE,  6,        ADC4,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  6,           4,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D40/PF7 */
-        {GPIOF_BASE,  7,        ADC5,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  7,           5,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D41/PF8 */
-        {GPIOF_BASE,  8,        ADC6,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  8,           6,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D42/PF9 */
-        {GPIOF_BASE,  9,        ADC7,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  9,           7,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D43/PF10 */
-        {GPIOF_BASE, 10,        ADC8,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 10,           8,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D44/PF11 */
-        {GPIOF_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D45/PB1 */
-        {GPIOB_BASE,  1,        ADC9, TIMER3_CH4_CCR,  EXTI_CONFIG_PORTB,        TIMER3, 4},
+        {GPIOB_BASE,  1,           9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB,        TIMER3, 4},
         /* D46/PB0 */
-        {GPIOB_BASE,  0,        ADC8, TIMER3_CH3_CCR,  EXTI_CONFIG_PORTB,        TIMER3, 3},
+        {GPIOB_BASE,  0,           8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB,        TIMER3, 3},
         /* D47/PA0 */
-        {GPIOA_BASE,  0,        ADC0, TIMER5_CH1_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 1},
+        {GPIOA_BASE,  0,           0, TIMER5_CH1_CCR, EXTI_CONFIG_PORTA,        TIMER5, 1},
         /* D48/PA1 */
-        {GPIOA_BASE,  1,        ADC1, TIMER5_CH2_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 2}, /* FIXME (?) what to do about D48--D50
-                                                                                                also being TIMER2_CH[2,3,4]? */
+        {GPIOA_BASE,  1,           1, TIMER5_CH2_CCR, EXTI_CONFIG_PORTA,        TIMER5, 2}, /* FIXME (?) what to do about D48--D50
+                                                                                               also being TIMER2_CH[2,3,4]? */
         /* D49/PA2 */
-        {GPIOA_BASE,  2,        ADC2, TIMER5_CH3_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 3},
+        {GPIOA_BASE,  2,           2, TIMER5_CH3_CCR, EXTI_CONFIG_PORTA,        TIMER5, 3},
         /* D50/PA3 */
-        {GPIOA_BASE,  3,        ADC3, TIMER5_CH4_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 4},
+        {GPIOA_BASE,  3,           3, TIMER5_CH4_CCR, EXTI_CONFIG_PORTA,        TIMER5, 4},
         /* D51/PA4 */
-        {GPIOA_BASE,  4,        ADC4,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  4,           4,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D52/PA5 */
-        {GPIOA_BASE,  5,        ADC5,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  5,           5,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D53/PA6 */
-        {GPIOA_BASE,  6,        ADC6, TIMER3_CH1_CCR,  EXTI_CONFIG_PORTA,        TIMER3, 1},
+        {GPIOA_BASE,  6,           6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA,        TIMER3, 1},
         /* D54/PA7 */
-        {GPIOA_BASE,  7,        ADC7, TIMER3_CH2_CCR,  EXTI_CONFIG_PORTA,        TIMER3, 2},
+        {GPIOA_BASE,  7,           7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA,        TIMER3, 2},
 
         /* Right (triple) header */
 
         /* D55/PF0 */
-        {GPIOF_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D56/PD11 */
-        {GPIOD_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D57/PD14 */
-        {GPIOD_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D58/PF1 */
-        {GPIOF_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D59/PD12 */
-        {GPIOD_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D60/PD15 */
-        {GPIOD_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D61/PF2 */
-        {GPIOF_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D62/PD13 */
-        {GPIOD_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D63/PD0 */
-        {GPIOD_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D64/PF3 */
-        {GPIOF_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D65/PE3 */
-        {GPIOE_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D66/PD1 */
-        {GPIOD_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D67/PF4 */
-        {GPIOF_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D68/PE4 */
-        {GPIOE_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D69/PE7 */
-        {GPIOE_BASE,  7, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  7, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D70/PF5 */
-        {GPIOF_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D71/PE5 */
-        {GPIOE_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D72/PE8 */
-        {GPIOE_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D73/PF12 */
-        {GPIOF_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D74/PE6 */
-        {GPIOE_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D75/PE9 */
-        {GPIOE_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D76/PF13 */
-        {GPIOF_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D77/PE10 */
-        {GPIOE_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D78/PF14 */
-        {GPIOF_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D79/PG9 */
-        {GPIOG_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D80/PE11 */
-        {GPIOE_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D81/PF15 */
-        {GPIOF_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D82/PG10 */
-        {GPIOG_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D83/PE12 */
-        {GPIOE_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D84/PG0 */
-        {GPIOG_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D85/PD5 */
-        {GPIOD_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D86/PE13 */
-        {GPIOE_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D87/PG1 */
-        {GPIOG_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D88/PD4 */
-        {GPIOD_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D89/PE14 */
-        {GPIOE_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D90/PG2 */
-        {GPIOG_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D91/PE1 */
-        {GPIOE_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D92/PE15 */
-        {GPIOE_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D93/PG3 */
-        {GPIOG_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D94/PE0 */
-        {GPIOE_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D95/PD8 */
-        {GPIOD_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D96/PG4 */
-        {GPIOG_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D97/PD9 */
-        {GPIOD_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D98/PG5 */
-        {GPIOG_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D99/PD10 */
-        {GPIOD_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID}
+        {GPIOD_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID}
     };
 
     #define BOARD_INIT do {                           \
@@ -409,23 +404,23 @@ typedef struct PinMapping {
         /* D2/PB2 */
         {GPIOB_BASE,  2,  ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D3/PB0 */
-        {GPIOB_BASE,  0,  ADC8,        TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3,        3},
+        {GPIOB_BASE,  0,            8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3,        3},
         /* D4/PA7 */
-        {GPIOA_BASE,  7,  ADC7,        TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3,        2},
+        {GPIOA_BASE,  7,            7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3,        2},
         /* D5/PA6 */
-        {GPIOA_BASE,  6,  ADC6,        TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3,        1},
+        {GPIOA_BASE,  6,            6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3,        1},
         /* D6/PA5 */
-        {GPIOA_BASE,  5,  ADC5,                    0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  5,            5,             0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D7/PA4 */
-        {GPIOA_BASE,  4,  ADC4,                    0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  4,            4,             0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D8/PA3 */
-        {GPIOA_BASE,  3,  ADC3,        TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2,        4},
+        {GPIOA_BASE,  3,            3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2,        4},
         /* D9/PA2 */
-        {GPIOA_BASE,  2,  ADC2,        TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2,        3},
+        {GPIOA_BASE,  2,            2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2,        3},
         /* D10/PA1 */
-        {GPIOA_BASE,  1,  ADC1,        TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2,        2},
+        {GPIOA_BASE,  1,            1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2,        2},
         /* D11/PA0 */
-        {GPIOA_BASE,  0,  ADC0,        TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2,        1},
+        {GPIOA_BASE,  0,            0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2,        1},
         /* D12/PC15 */
         {GPIOC_BASE, 15,  ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D13/PC14 */
@@ -469,7 +464,7 @@ typedef struct PinMapping {
         /* D32/PB8 */
         {GPIOB_BASE,  8,  ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB, TIMER4,        3},
         /* D33/PB1 */
-        {GPIOB_BASE,  1,  ADC9,        TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3,        4},
+        {GPIOB_BASE,  1,            9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3,        4},
     };
 
     /* since we want the Serial Wire/JTAG pins as GPIOs, disable both
diff --git a/wirish/wirish.c b/wirish/wirish.c
index aaae9d4..1ea4863 100644
--- a/wirish/wirish.c
+++ b/wirish/wirish.c
@@ -64,9 +64,12 @@ void init(void) {
     nvic_init();
     systick_init(SYSTICK_RELOAD_VAL);
     gpio_init();
+
     /* Initialize the ADC for slow conversions, to allow for high
        impedance inputs. */
-    adc_init(ADC_SMPR_55_5);
+    adc_init(ADC1, 0);
+    adc_set_sample_rate(ADC1->regs, ADC_SMPR_55_5);
+
     timer_init(TIMER1, 1);
     timer_init(TIMER2, 1);
     timer_init(TIMER3, 1);
diff --git a/wirish/wirish_analog.c b/wirish/wirish_analog.c
index 3c63342..ba1290d 100644
--- a/wirish/wirish_analog.c
+++ b/wirish/wirish_analog.c
@@ -33,9 +33,9 @@
 /* Assumes that the ADC has been initialized and that the pin is set
  * to ANALOG_INPUT */
 uint32 analogRead(uint8 pin) {
-    if(PIN_MAP[pin].adc == ADC_INVALID) {
+    if(PIN_MAP[pin].adc_channel == ADC_INVALID) {
         return 0;
     }
 
-    return adc_read(PIN_MAP[pin].adc);
+    return adc_read(ADC1->regs, PIN_MAP[pin].adc_channel);
 }