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| author | Marti Bolivar <mbolivar@leaflabs.com> | 2012-06-03 06:19:00 -0400 |
|---|---|---|
| committer | Marti Bolivar <mbolivar@leaflabs.com> | 2012-06-03 22:40:39 -0400 |
| commit | 9cb33ac2d3829715e352e4550493f414b2b4c003 (patch) | |
| tree | c1accb854c0920adc49c5a69a2f967e49147c5fc /wirish/boards/st_stm3220g_eval | |
| parent | 378c3a70f81ddfbbddf3656977f81b7dfd8f96cd (diff) | |
| download | librambutan-9cb33ac2d3829715e352e4550493f414b2b4c003.tar.gz librambutan-9cb33ac2d3829715e352e4550493f414b2b4c003.zip | |
Add ISRs and vector table for F1 value line.
Now libmaple/stm32f1/rules.mk tries to pull in ISRs and a vector table
on a per-line basis. Move isrs_performance.S and
vector_table_performance.S to (new) libmaple/stm32f1/performance, and
rename them.
Add corresponding files for value line under (new)
libmaple/stm32f1/value. This helps clean up some
performance-line-isms, and allows implementing e.g. the CEC interrupt,
which is used by something else on performance line.
Untested (I don't have access to a value line MCU); hopefully this
works.
Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
Diffstat (limited to 'wirish/boards/st_stm3220g_eval')
0 files changed, 0 insertions, 0 deletions