Final stm32_pin_info design candidate; ADC3 support on Native.

Added an adc_dev to struct stm32_pin_info.  This was necessary to add
support for the channels on the Native which are only connected to
ADC3, but it does add a bunch of NULLs to the PIN_MAPs.

I don't think any other peripherals need representation on a per-pin
basis.  Each peripheral library will be responsible for keeping track
of related GPIO ports and bits, and we can throw #defines in to
boards/*.h for other things (e.g. BOARD_SPI1_MISO_PIN).

Fleshed out the ADC refactor and brought it more in keeping with the
new design as it evolves.

A couple of other tweaks.  Notably: waitForButtonPress() now takes a
default argument meaning "wait forever".

Removed Maple-specific documentation from core functions in io.h; this
information will need to go into the individual board docs files.

1 files changed, 34 insertions, 34 deletions

diff --git a/wirish/boards/maple_mini.cpp b/wirish/boards/maple_mini.cpp
index 8c005cf..66a0997 100644
--- a/wirish/boards/maple_mini.cpp
+++ b/wirish/boards/maple_mini.cpp
@@ -45,43 +45,43 @@ stm32_pin_info PIN_MAP[NR_GPIO_PINS] = {
 
     /* Top header */
 
-    {GPIOB,   NULL, 11, 0, ADCx}, /* D0/PB11 */
-    {GPIOB,   NULL, 10, 0, ADCx}, /* D1/PB10 */
-    {GPIOB,   NULL,  2, 0, ADCx}, /* D2/PB2 */
-    {GPIOB, TIMER3,  0, 3,    8}, /* D3/PB0 */
-    {GPIOA, TIMER3,  7, 2,    7}, /* D4/PA7 */
-    {GPIOA, TIMER3,  6, 1,    6}, /* D5/PA6 */
-    {GPIOA,   NULL,  5, 0,    5}, /* D6/PA5 */
-    {GPIOA,   NULL,  4, 0,    4}, /* D7/PA4 */
-    {GPIOA, TIMER2,  3, 4,    3}, /* D8/PA3 */
-    {GPIOA, TIMER2,  2, 3,    2}, /* D9/PA2 */
-    {GPIOA, TIMER2,  1, 2,    1}, /* D10/PA1 */
-    {GPIOA, TIMER2,  0, 1,    0}, /* D11/PA0 */
-    {GPIOC,   NULL, 15, 0, ADCx}, /* D12/PC15 */
-    {GPIOC,   NULL, 14, 0, ADCx}, /* D13/PC14 */
-    {GPIOC,   NULL, 13, 0, ADCx}, /* D14/PC13 */
+    {GPIOB,   NULL, NULL, 11, 0, ADCx}, /* D0/PB11 */
+    {GPIOB,   NULL, NULL, 10, 0, ADCx}, /* D1/PB10 */
+    {GPIOB,   NULL, NULL,  2, 0, ADCx}, /* D2/PB2 */
+    {GPIOB, TIMER3, ADC1,  0, 3,    8}, /* D3/PB0 */
+    {GPIOA, TIMER3, ADC1,  7, 2,    7}, /* D4/PA7 */
+    {GPIOA, TIMER3, ADC1,  6, 1,    6}, /* D5/PA6 */
+    {GPIOA,   NULL, ADC1,  5, 0,    5}, /* D6/PA5 */
+    {GPIOA,   NULL, ADC1,  4, 0,    4}, /* D7/PA4 */
+    {GPIOA, TIMER2, ADC1,  3, 4,    3}, /* D8/PA3 */
+    {GPIOA, TIMER2, ADC1,  2, 3,    2}, /* D9/PA2 */
+    {GPIOA, TIMER2, ADC1,  1, 2,    1}, /* D10/PA1 */
+    {GPIOA, TIMER2, ADC1,  0, 1,    0}, /* D11/PA0 */
+    {GPIOC,   NULL, NULL, 15, 0, ADCx}, /* D12/PC15 */
+    {GPIOC,   NULL, NULL, 14, 0, ADCx}, /* D13/PC14 */
+    {GPIOC,   NULL, NULL, 13, 0, ADCx}, /* D14/PC13 */
 
     /* Bottom header */
 
-    {GPIOB, TIMER4,  7, 2, ADCx}, /* D15/PB7 */
-    {GPIOB, TIMER4,  6, 1, ADCx}, /* D16/PB6 */
-    {GPIOB,   NULL,  5, 0, ADCx}, /* D17/PB5 */
-    {GPIOB,   NULL,  4, 0, ADCx}, /* D18/PB4 */
-    {GPIOB,   NULL,  3, 0, ADCx}, /* D19/PB3 */
-    {GPIOA,   NULL, 15, 0, ADCx}, /* D20/PA15 */
-    {GPIOA,   NULL, 14, 0, ADCx}, /* D21/PA14 */
-    {GPIOA,   NULL, 13, 0, ADCx}, /* D22/PA13 */
-    {GPIOA,   NULL, 12, 0, ADCx}, /* D23/PA12 */
-    {GPIOA, TIMER1, 11, 4, ADCx}, /* D24/PA11 */
-    {GPIOA, TIMER1, 10, 3, ADCx}, /* D25/PA10 */
-    {GPIOA, TIMER2,  9, 2, ADCx}, /* D26/PA9 */
-    {GPIOA, TIMER1,  8, 1, ADCx}, /* D27/PA8 */
-    {GPIOB,   NULL, 15, 0, ADCx}, /* D28/PB15 */
-    {GPIOB,   NULL, 14, 0, ADCx}, /* D29/PB14 */
-    {GPIOB,   NULL, 13, 0, ADCx}, /* D30/PB13 */
-    {GPIOB,   NULL, 12, 0, ADCx}, /* D31/PB12 */
-    {GPIOB, TIMER4,  8, 3, ADCx}, /* D32/PB8 */
-    {GPIOB, TIMER3,  1, 4,    9}, /* D33/PB1 */
+    {GPIOB, TIMER4, NULL,  7, 2, ADCx}, /* D15/PB7 */
+    {GPIOB, TIMER4, NULL,  6, 1, ADCx}, /* D16/PB6 */
+    {GPIOB,   NULL, NULL,  5, 0, ADCx}, /* D17/PB5 */
+    {GPIOB,   NULL, NULL,  4, 0, ADCx}, /* D18/PB4 */
+    {GPIOB,   NULL, NULL,  3, 0, ADCx}, /* D19/PB3 */
+    {GPIOA,   NULL, NULL, 15, 0, ADCx}, /* D20/PA15 */
+    {GPIOA,   NULL, NULL, 14, 0, ADCx}, /* D21/PA14 */
+    {GPIOA,   NULL, NULL, 13, 0, ADCx}, /* D22/PA13 */
+    {GPIOA,   NULL, NULL, 12, 0, ADCx}, /* D23/PA12 */
+    {GPIOA, TIMER1, NULL, 11, 4, ADCx}, /* D24/PA11 */
+    {GPIOA, TIMER1, NULL, 10, 3, ADCx}, /* D25/PA10 */
+    {GPIOA, TIMER2, NULL,  9, 2, ADCx}, /* D26/PA9 */
+    {GPIOA, TIMER1, NULL,  8, 1, ADCx}, /* D27/PA8 */
+    {GPIOB,   NULL, NULL, 15, 0, ADCx}, /* D28/PB15 */
+    {GPIOB,   NULL, NULL, 14, 0, ADCx}, /* D29/PB14 */
+    {GPIOB,   NULL, NULL, 13, 0, ADCx}, /* D30/PB13 */
+    {GPIOB,   NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */
+    {GPIOB, TIMER4, NULL,  8, 3, ADCx}, /* D32/PB8 */
+    {GPIOB, TIMER3, ADC1,  1, 4,    9}, /* D33/PB1 */
 };
 
 #endif