diff options
| author | iperry <iperry@749a229e-a60e-11de-b98f-4500b42dc123> | 2009-12-17 02:37:07 +0000 |
|---|---|---|
| committer | iperry <iperry@749a229e-a60e-11de-b98f-4500b42dc123> | 2009-12-17 02:37:07 +0000 |
| commit | 32e57dac2e61e79b029593eb4d34d727bcc10678 (patch) | |
| tree | 98d7ff41993576bb150d13d5f63dc744f6812852 /stm32conf | |
| download | librambutan-32e57dac2e61e79b029593eb4d34d727bcc10678.tar.gz librambutan-32e57dac2e61e79b029593eb4d34d727bcc10678.zip | |
Initial commit of library code, moved from leaftest repo
git-svn-id: https://leaflabs.googlecode.com/svn/trunk/library@69 749a229e-a60e-11de-b98f-4500b42dc123
Diffstat (limited to 'stm32conf')
36 files changed, 2178 insertions, 0 deletions
diff --git a/stm32conf/flash.cfg b/stm32conf/flash.cfg new file mode 100644 index 0000000..86020bf --- /dev/null +++ b/stm32conf/flash.cfg @@ -0,0 +1,85 @@ +# script for stm32 + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 26.6.3 + set _CPUTAPID 0x3ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + # High density devices, Rev A + set _BSTAPID4 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID5 0x06418041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 + + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 + +flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME + +proc flash_chip {} { + echo "Halting..." + halt + echo "Erasing 128KB..." + flash erase_address 0x08000000 0x20000 + echo "Flashing image..." + flash write_bank 0 build/main.bin 0 + echo "Verifying image..." + verify_image build/main.bin 0x08000000 bin + echo "Checksum verified, resetting chip" + reset run + echo "Daemon shutdown" + shutdown +} + +init +flash_chip diff --git a/stm32conf/lanchon-stm32.ld b/stm32conf/lanchon-stm32.ld new file mode 100644 index 0000000..504f1d4 --- /dev/null +++ b/stm32conf/lanchon-stm32.ld @@ -0,0 +1,20 @@ +/* Linker script for STM32 (by Lanchon)
+ *
+ * Configure target memory and included script
+ * according to your application requirements. */
+
+/* Define memory spaces. */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+}
+
+/* Include the appropriate script.
+ * Options:
+ * lanchon-stm32-rom.ld
+ * lanchon-stm32-rom-hosted.ld
+ * lanchon-stm32-ram.ld
+ * lanchon-stm32-ram-hosted.ld
+ */
+INCLUDE "lanchon-stm32-rom.ld"
diff --git a/stm32conf/lanchon-stm32/lanchon-stm32-128k-20k-rom.ld b/stm32conf/lanchon-stm32/lanchon-stm32-128k-20k-rom.ld new file mode 100644 index 0000000..133a8b5 --- /dev/null +++ b/stm32conf/lanchon-stm32/lanchon-stm32-128k-20k-rom.ld @@ -0,0 +1,20 @@ +/* Linker script for STM32 (by Lanchon)
+ *
+ * Configure target memory and included script
+ * according to your application requirements. */
+
+/* Define memory spaces. */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+}
+
+/* Include the appropriate script.
+ * Options:
+ * lanchon-stm32-rom.ld
+ * lanchon-stm32-rom-hosted.ld
+ * lanchon-stm32-ram.ld
+ * lanchon-stm32-ram-hosted.ld
+ */
+INCLUDE "lanchon-stm32-rom.ld"
diff --git a/stm32conf/lanchon-stm32/lanchon-stm32-names.inc b/stm32conf/lanchon-stm32/lanchon-stm32-names.inc new file mode 100644 index 0000000..a0e1fb2 --- /dev/null +++ b/stm32conf/lanchon-stm32/lanchon-stm32-names.inc @@ -0,0 +1,61 @@ +/* ISR names for STM32 (by Lanchon) */
+
+EXTERN (__cs3_stack)
+EXTERN (__cs3_reset)
+EXTERN (NMIException)
+EXTERN (HardFaultException)
+EXTERN (MemManageException)
+EXTERN (BusFaultException)
+EXTERN (UsageFaultException)
+EXTERN (__STM32ReservedException7)
+EXTERN (__STM32ReservedException8)
+EXTERN (__STM32ReservedException9)
+EXTERN (__STM32ReservedException10)
+EXTERN (SVCHandler)
+EXTERN (DebugMonitor)
+EXTERN (__STM32ReservedException13)
+EXTERN (PendSVC)
+EXTERN (SysTickHandler)
+EXTERN (WWDG_IRQHandler)
+EXTERN (PVD_IRQHandler)
+EXTERN (TAMPER_IRQHandler)
+EXTERN (RTC_IRQHandler)
+EXTERN (FLASH_IRQHandler)
+EXTERN (RCC_IRQHandler)
+EXTERN (EXTI0_IRQHandler)
+EXTERN (EXTI1_IRQHandler)
+EXTERN (EXTI2_IRQHandler)
+EXTERN (EXTI3_IRQHandler)
+EXTERN (EXTI4_IRQHandler)
+EXTERN (DMAChannel1_IRQHandler)
+EXTERN (DMAChannel2_IRQHandler)
+EXTERN (DMAChannel3_IRQHandler)
+EXTERN (DMAChannel4_IRQHandler)
+EXTERN (DMAChannel5_IRQHandler)
+EXTERN (DMAChannel6_IRQHandler)
+EXTERN (DMAChannel7_IRQHandler)
+EXTERN (ADC_IRQHandler)
+EXTERN (USB_HP_CAN_TX_IRQHandler)
+EXTERN (USB_LP_CAN_RX0_IRQHandler)
+EXTERN (CAN_RX1_IRQHandler)
+EXTERN (CAN_SCE_IRQHandler)
+EXTERN (EXTI9_5_IRQHandler)
+EXTERN (TIM1_BRK_IRQHandler)
+EXTERN (TIM1_UP_IRQHandler)
+EXTERN (TIM1_TRG_COM_IRQHandler)
+EXTERN (TIM1_CC_IRQHandler)
+EXTERN (TIM2_IRQHandler)
+EXTERN (TIM3_IRQHandler)
+EXTERN (TIM4_IRQHandler)
+EXTERN (I2C1_EV_IRQHandler)
+EXTERN (I2C1_ER_IRQHandler)
+EXTERN (I2C2_EV_IRQHandler)
+EXTERN (I2C2_ER_IRQHandler)
+EXTERN (SPI1_IRQHandler)
+EXTERN (SPI2_IRQHandler)
+EXTERN (USART1_IRQHandler)
+EXTERN (USART2_IRQHandler)
+EXTERN (USART3_IRQHandler)
+EXTERN (EXTI15_10_IRQHandler)
+EXTERN (RTCAlarm_IRQHandler)
+EXTERN (USBWakeUp_IRQHandler)
diff --git a/stm32conf/lanchon-stm32/lanchon-stm32-ram-hosted.ld b/stm32conf/lanchon-stm32/lanchon-stm32-ram-hosted.ld new file mode 100644 index 0000000..3ab33ec --- /dev/null +++ b/stm32conf/lanchon-stm32/lanchon-stm32-ram-hosted.ld @@ -0,0 +1,203 @@ +/* Linker script for STM32 (by Lanchon)
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+/* GROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3-lanchon-stm32) */
+GROUP(libgcc.a libc.a libcs3.a libcs3hosted.a libcs3-lanchon-stm32.a)
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_lanchon_stm32)
+INCLUDE lanchon-stm32-names.inc
+EXTERN(__cs3_interrupt_vector_lanchon_stm32)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+/* force exit to be picked up in a hosted or os environment */
+EXTERN(exit atexit)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");
+
+ PROVIDE(__cs3_reset_lanchon_stm32 = _start);
+ __cs3_reset = __cs3_reset_lanchon_stm32;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ } >ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >ram
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >ram
+
+ .cs3.rom :
+ {
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ *(.rom)
+ . = ALIGN (8);
+ } >rom
+ .cs3.rom.bss :
+ {
+ *(.rom.b)
+ . = ALIGN (8);
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_init_rom = LOADADDR (.cs3.rom);
+ __cs3_region_init_size_rom = SIZEOF(.cs3.rom);
+ __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);
+
+ .data :
+ {
+
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.text);
+ __cs3_region_init_size_ram = _edata - ADDR (.text);
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/stm32conf/lanchon-stm32/lanchon-stm32-ram.ld b/stm32conf/lanchon-stm32/lanchon-stm32-ram.ld new file mode 100644 index 0000000..59c321e --- /dev/null +++ b/stm32conf/lanchon-stm32/lanchon-stm32-ram.ld @@ -0,0 +1,201 @@ +/* Linker script for STM32 (by Lanchon)
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */
+GROUP(libgcc.a libc.a libcs3.a libcs3unhosted.a libcs3-lanchon-stm32.a)
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_lanchon_stm32)
+INCLUDE lanchon-stm32-names.inc
+EXTERN(__cs3_interrupt_vector_lanchon_stm32)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");
+
+ PROVIDE(__cs3_reset_lanchon_stm32 = _start);
+ __cs3_reset = __cs3_reset_lanchon_stm32;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ } >ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >ram
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >ram
+
+ .cs3.rom :
+ {
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ *(.rom)
+ . = ALIGN (8);
+ } >rom
+ .cs3.rom.bss :
+ {
+ *(.rom.b)
+ . = ALIGN (8);
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_init_rom = LOADADDR (.cs3.rom);
+ __cs3_region_init_size_rom = SIZEOF(.cs3.rom);
+ __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);
+
+ .data :
+ {
+
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.text);
+ __cs3_region_init_size_ram = _edata - ADDR (.text);
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/stm32conf/lanchon-stm32/lanchon-stm32-rom-hosted.ld b/stm32conf/lanchon-stm32/lanchon-stm32-rom-hosted.ld new file mode 100644 index 0000000..d7de11a --- /dev/null +++ b/stm32conf/lanchon-stm32/lanchon-stm32-rom-hosted.ld @@ -0,0 +1,191 @@ +/* Linker script for STM32 (by Lanchon)
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+/* GROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3-lanchon-stm32) */
+GROUP(libgcc.a libc.a libcs3.a libcs3hosted.a libcs3-lanchon-stm32.a)
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_lanchon_stm32)
+INCLUDE lanchon-stm32-names.inc
+EXTERN(__cs3_interrupt_vector_lanchon_stm32)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+/* force exit to be picked up in a hosted or os environment */
+EXTERN(exit atexit)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ PROVIDE(__cs3_reset_lanchon_stm32 = _start);
+ __cs3_reset = __cs3_reset_lanchon_stm32;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ } >rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - ADDR (.data);
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/stm32conf/lanchon-stm32/lanchon-stm32-rom.ld b/stm32conf/lanchon-stm32/lanchon-stm32-rom.ld new file mode 100644 index 0000000..909557f --- /dev/null +++ b/stm32conf/lanchon-stm32/lanchon-stm32-rom.ld @@ -0,0 +1,189 @@ +/* Linker script for STM32 (by Lanchon)
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */
+GROUP(libgcc.a libc.a libcs3.a libcs3unhosted.a libcs3-lanchon-stm32.a)
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_lanchon_stm32)
+INCLUDE lanchon-stm32-names.inc
+EXTERN(__cs3_interrupt_vector_lanchon_stm32)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ PROVIDE(__cs3_reset_lanchon_stm32 = _start);
+ __cs3_reset = __cs3_reset_lanchon_stm32;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ } >rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - ADDR (.data);
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/stm32conf/lanchon-stm32/src.zip b/stm32conf/lanchon-stm32/src.zip Binary files differnew file mode 100644 index 0000000..58ff908 --- /dev/null +++ b/stm32conf/lanchon-stm32/src.zip diff --git a/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-isrs.S.epilog b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-isrs.S.epilog new file mode 100644 index 0000000..7102d59 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-isrs.S.epilog @@ -0,0 +1,2 @@ +
+#endif /* L_lanchon_stm32_isr_interrupt */
diff --git a/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-isrs.S.prolog b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-isrs.S.prolog new file mode 100644 index 0000000..8e0629b --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-isrs.S.prolog @@ -0,0 +1,14 @@ +/* ISRs for STM32 (by Lanchon) */
+
+ .thumb
+
+#if defined (L_lanchon_stm32_isr_interrupt)
+
+ .globl __STM32DefaultExceptionHandler
+ .type __STM32DefaultExceptionHandler, %function
+
+__STM32DefaultExceptionHandler:
+ b .
+
+ .size __STM32DefaultExceptionHandler, . - __STM32DefaultExceptionHandler
+
diff --git a/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-names.inc.epilog b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-names.inc.epilog new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-names.inc.epilog diff --git a/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-names.inc.prolog b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-names.inc.prolog new file mode 100644 index 0000000..a233a3f --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-names.inc.prolog @@ -0,0 +1,4 @@ +/* ISR names for STM32 (by Lanchon) */
+
+EXTERN (__cs3_stack)
+EXTERN (__cs3_reset)
diff --git a/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-vector.S.epilog b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-vector.S.epilog new file mode 100644 index 0000000..c8f3f4b --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-vector.S.epilog @@ -0,0 +1,2 @@ +
+ .size __cs3_interrupt_vector_lanchon_stm32, . - __cs3_interrupt_vector_lanchon_stm32
diff --git a/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-vector.S.prolog b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-vector.S.prolog new file mode 100644 index 0000000..85fa6f5 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/lanchon-stm32-vector.S.prolog @@ -0,0 +1,10 @@ +/* Vector table for STM32 (by Lanchon) */
+
+ .section ".cs3.interrupt_vector"
+
+ .globl __cs3_interrupt_vector_lanchon_stm32
+ .type __cs3_interrupt_vector_lanchon_stm32, %object
+
+__cs3_interrupt_vector_lanchon_stm32:
+ .long __cs3_stack
+ .long __cs3_reset
diff --git a/stm32conf/lanchon-stm32/src/exceptions/make-clean.cmd b/stm32conf/lanchon-stm32/src/exceptions/make-clean.cmd new file mode 100644 index 0000000..82e4746 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/make-clean.cmd @@ -0,0 +1,10 @@ +@echo off
+setlocal
+
+set DO=del
+
+%DO% lanchon-stm32-vector.S
+%DO% lanchon-stm32-isrs.S
+%DO% lanchon-stm32-names.inc
+%DO% stm32exceptions.h
+%DO% stm32exceptions.c
diff --git a/stm32conf/lanchon-stm32/src/exceptions/make-foreach.cmd b/stm32conf/lanchon-stm32/src/exceptions/make-foreach.cmd new file mode 100644 index 0000000..4c3b00e --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/make-foreach.cmd @@ -0,0 +1,38 @@ +setlocal
+
+set ADR=0x%~1
+set TYPE=%~2
+set NAME=%~3
+set TEXT=%~4
+set HELP=%~5
+
+set /a NUM=%ADR%/4
+if %TYPE%==x set NAME=__STM32ReservedException%NUM%
+if %TYPE%==e set FULLTYPE=Exception
+if %TYPE%==i set FULLTYPE=Interrupt
+set FULLTEXT=%TEXT% %FULLTYPE%
+if not "%HELP%"=="" set FULLHELP= (%HELP%)
+set FULL=[%ADR%] %FULLTEXT%%FULLHELP%
+
+rem echo %NAME%
+
+echo .long %NAME%>>lanchon-stm32-vector.S
+
+echo .weak %NAME%>>lanchon-stm32-isrs.S
+echo .globl %NAME%>>lanchon-stm32-isrs.S
+echo .set %NAME%, __STM32DefaultExceptionHandler>>lanchon-stm32-isrs.S
+
+echo EXTERN (%NAME%)>>lanchon-stm32-names.inc
+
+if %TYPE%==x goto :eof
+
+echo /* %FULL% */>>stm32exceptions.h
+echo void %NAME%(void);>>stm32exceptions.h
+echo.>>stm32exceptions.h
+
+echo /* %FULL% */>>stm32exceptions.c
+echo void %NAME%(void)>>stm32exceptions.c
+echo {>>stm32exceptions.c
+echo DEFAULT_EXCEPTION_HANDLER(%NAME%, "%TEXT%", %NUM%, %ADR%);>>stm32exceptions.c
+echo }>>stm32exceptions.c
+echo.>>stm32exceptions.c
diff --git a/stm32conf/lanchon-stm32/src/exceptions/make.cmd b/stm32conf/lanchon-stm32/src/exceptions/make.cmd new file mode 100644 index 0000000..918ffeb --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/make.cmd @@ -0,0 +1,76 @@ +@echo off
+setlocal
+
+type lanchon-stm32-vector.S.prolog>lanchon-stm32-vector.S
+type lanchon-stm32-isrs.S.prolog>lanchon-stm32-isrs.S
+type lanchon-stm32-names.inc.prolog>lanchon-stm32-names.inc
+type stm32exceptions.h.prolog>stm32exceptions.h
+type stm32exceptions.c.prolog>stm32exceptions.c
+
+set DO=call make-foreach
+
+rem %DO% 00 - __cs3_stack
+rem %DO% 04 - __cs3_reset
+%DO% 08 e NMIException "NMI" "from the RCC Clock Security System"
+%DO% 0C e HardFaultException "Hard Fault"
+%DO% 10 e MemManageException "Memory Management"
+%DO% 14 e BusFaultException "Bus Fault" "prefetch and memory access faults"
+%DO% 18 e UsageFaultException "Usage Fault" "undefined instruction or illegal state faults"
+%DO% 1C x
+%DO% 20 x
+%DO% 24 x
+%DO% 28 x
+%DO% 2C e SVCHandler "SVCall" "system service call via SWI instruction"
+%DO% 30 e DebugMonitor "Debug Monitor"
+%DO% 34 x
+%DO% 38 e PendSVC "PendSVC" "pendable request for system service"
+%DO% 3C e SysTickHandler "SysTick"
+%DO% 40 i WWDG_IRQHandler "WWDG"
+%DO% 44 i PVD_IRQHandler "PVD" "EXTI Line 16"
+%DO% 48 i TAMPER_IRQHandler "Tamper"
+%DO% 4C i RTC_IRQHandler "RTC"
+%DO% 50 i FLASH_IRQHandler "Flash"
+%DO% 54 i RCC_IRQHandler "RCC"
+%DO% 58 i EXTI0_IRQHandler "EXTI Line 0"
+%DO% 5C i EXTI1_IRQHandler "EXTI Line 1"
+%DO% 60 i EXTI2_IRQHandler "EXTI Line 2"
+%DO% 64 i EXTI3_IRQHandler "EXTI Line 3"
+%DO% 68 i EXTI4_IRQHandler "EXTI Line 4"
+%DO% 6C i DMAChannel1_IRQHandler "DMA Channel 1"
+%DO% 70 i DMAChannel2_IRQHandler "DMA Channel 2"
+%DO% 74 i DMAChannel3_IRQHandler "DMA Channel 3"
+%DO% 78 i DMAChannel4_IRQHandler "DMA Channel 4"
+%DO% 7C i DMAChannel5_IRQHandler "DMA Channel 5"
+%DO% 80 i DMAChannel6_IRQHandler "DMA Channel 6"
+%DO% 84 i DMAChannel7_IRQHandler "DMA Channel 7"
+%DO% 88 i ADC_IRQHandler "ADC"
+%DO% 8C i USB_HP_CAN_TX_IRQHandler "USB High Priority/CAN TX"
+%DO% 90 i USB_LP_CAN_RX0_IRQHandler "USB Low Priority/CAN RX0"
+%DO% 94 i CAN_RX1_IRQHandler "CAN RX1"
+%DO% 98 i CAN_SCE_IRQHandler "CAN SCE"
+%DO% 9C i EXTI9_5_IRQHandler "EXTI Lines 5-9"
+%DO% A0 i TIM1_BRK_IRQHandler "TIM1 Break"
+%DO% A4 i TIM1_UP_IRQHandler "TIM1 Update"
+%DO% A8 i TIM1_TRG_COM_IRQHandler "TIM1 Trigger/Commutation"
+%DO% AC i TIM1_CC_IRQHandler "TIM1 Capture/Compare"
+%DO% B0 i TIM2_IRQHandler "TIM2"
+%DO% B4 i TIM3_IRQHandler "TIM3"
+%DO% B8 i TIM4_IRQHandler "TIM4"
+%DO% BC i I2C1_EV_IRQHandler "I2C1 Event"
+%DO% C0 i I2C1_ER_IRQHandler "I2C1 Error"
+%DO% C4 i I2C2_EV_IRQHandler "I2C2 Event"
+%DO% C8 i I2C2_ER_IRQHandler "I2C2 Error"
+%DO% CC i SPI1_IRQHandler "SPI1"
+%DO% D0 i SPI2_IRQHandler "SPI2"
+%DO% D4 i USART1_IRQHandler "USART1"
+%DO% D8 i USART2_IRQHandler "USART2"
+%DO% DC i USART3_IRQHandler "USART3"
+%DO% E0 i EXTI15_10_IRQHandler "EXTI Lines 10-15"
+%DO% E4 i RTCAlarm_IRQHandler "RTC Alarm" "EXTI Line 17"
+%DO% E8 i USBWakeUp_IRQHandler "USB Wake Up" "EXTI Line 18"
+
+type lanchon-stm32-vector.S.epilog>>lanchon-stm32-vector.S
+type lanchon-stm32-isrs.S.epilog>>lanchon-stm32-isrs.S
+type lanchon-stm32-names.inc.epilog>>lanchon-stm32-names.inc
+type stm32exceptions.h.epilog>>stm32exceptions.h
+type stm32exceptions.c.epilog>>stm32exceptions.c
diff --git a/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.c.epilog b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.c.epilog new file mode 100644 index 0000000..7e500a1 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.c.epilog @@ -0,0 +1 @@ +#endif /* COMBINED_DEFAULT_HANDLER */
diff --git a/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.c.prolog b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.c.prolog new file mode 100644 index 0000000..140f151 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.c.prolog @@ -0,0 +1,20 @@ +/* Exception handlers for STM32 (by Lanchon)
+ *
+ * This code is meant to handle exceptions that the application does not expect.
+ * Handlers that are part of the application should be defined elsewhere. */
+
+#include "stm32exceptions.h"
+
+#ifndef CUSTOM_EXCEPTION_HANDLER
+ #ifdef DEBUG
+ /* Use individual infinite loops to ease debugging. */
+ #define DEFAULT_EXCEPTION_HANDLER(handler, name, number, address) while (1);
+ #else
+ /* Avoid individual infinite loops when not debugging. */
+ #define SHARED_EXCEPTION_HANDLER
+ #endif
+#endif
+
+/* Undefined handlers will default to a shared infinite loop (see lanchon-stm32-isrs.S). */
+#ifndef SHARED_EXCEPTION_HANDLER
+
diff --git a/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.h.epilog b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.h.epilog new file mode 100644 index 0000000..6314553 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.h.epilog @@ -0,0 +1,5 @@ +#if __cplusplus
+}
+#endif
+
+#endif /* __STM32EXCEPTIONS_H */
diff --git a/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.h.prolog b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.h.prolog new file mode 100644 index 0000000..dbf6ce9 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/exceptions/stm32exceptions.h.prolog @@ -0,0 +1,24 @@ +/* Exception handlers for STM32 (by Lanchon) */
+
+#ifndef __STM32EXCEPTIONS_H
+#define __STM32EXCEPTIONS_H
+
+#if __cplusplus
+extern "C"
+{
+#endif
+
+/* Use a shared infinite loop for unexpected exceptions. */
+/* #define SHARED_EXCEPTION_HANDLER */
+
+/* Or use an external handler for unexpected exceptions. */
+/* #define CUSTOM_EXCEPTION_HANDLER */
+
+/* Or else use individual infinite loops when debugging,
+ * or a shared infinite loop when not. */
+
+#ifdef CUSTOM_EXCEPTION_HANDLER
+ void unexpected_exception(const char* name, int address);
+ #define DEFAULT_EXCEPTION_HANDLER(handler, name, number, address) unexpected_exception(name, address);
+#endif
+
diff --git a/stm32conf/lanchon-stm32/src/lanchon-stm32-reset.S b/stm32conf/lanchon-stm32/src/lanchon-stm32-reset.S new file mode 100644 index 0000000..518f99f --- /dev/null +++ b/stm32conf/lanchon-stm32/src/lanchon-stm32-reset.S @@ -0,0 +1,39 @@ +/* Reset code for STM32 (by Lanchon)
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+#if defined(__thumb2__) || defined(__ARM_ARCH_6M__)
+#define THUMB 1
+ .thumb
+ .thumb_func
+#else
+ .arm
+#endif
+ .section .cs3.reset,"x",%progbits
+ .globl __cs3_reset_lanchon_stm32
+ .type __cs3_reset_lanchon_stm32, %function
+__cs3_reset_lanchon_stm32:
+ .fnstart
+#if THUMB
+ ldr r0,=_start
+ bx r0
+#else
+ b _start
+#endif
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_lanchon_stm32,.-__cs3_reset_lanchon_stm32
diff --git a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S new file mode 100644 index 0000000..b68af59 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S @@ -0,0 +1,187 @@ +/* ISRs for STM32 (by Lanchon) */
+
+ .thumb
+
+#if defined (L_lanchon_stm32_isr_interrupt)
+
+ .globl __STM32DefaultExceptionHandler
+ .type __STM32DefaultExceptionHandler, %function
+
+__STM32DefaultExceptionHandler:
+ b .
+
+ .size __STM32DefaultExceptionHandler, . - __STM32DefaultExceptionHandler
+
+ .weak NMIException
+ .globl NMIException
+ .set NMIException, __STM32DefaultExceptionHandler
+ .weak HardFaultException
+ .globl HardFaultException
+ .set HardFaultException, __STM32DefaultExceptionHandler
+ .weak MemManageException
+ .globl MemManageException
+ .set MemManageException, __STM32DefaultExceptionHandler
+ .weak BusFaultException
+ .globl BusFaultException
+ .set BusFaultException, __STM32DefaultExceptionHandler
+ .weak UsageFaultException
+ .globl UsageFaultException
+ .set UsageFaultException, __STM32DefaultExceptionHandler
+ .weak __STM32ReservedException7
+ .globl __STM32ReservedException7
+ .set __STM32ReservedException7, __STM32DefaultExceptionHandler
+ .weak __STM32ReservedException8
+ .globl __STM32ReservedException8
+ .set __STM32ReservedException8, __STM32DefaultExceptionHandler
+ .weak __STM32ReservedException9
+ .globl __STM32ReservedException9
+ .set __STM32ReservedException9, __STM32DefaultExceptionHandler
+ .weak __STM32ReservedException10
+ .globl __STM32ReservedException10
+ .set __STM32ReservedException10, __STM32DefaultExceptionHandler
+ .weak SVCHandler
+ .globl SVCHandler
+ .set SVCHandler, __STM32DefaultExceptionHandler
+ .weak DebugMonitor
+ .globl DebugMonitor
+ .set DebugMonitor, __STM32DefaultExceptionHandler
+ .weak __STM32ReservedException13
+ .globl __STM32ReservedException13
+ .set __STM32ReservedException13, __STM32DefaultExceptionHandler
+ .weak PendSVC
+ .globl PendSVC
+ .set PendSVC, __STM32DefaultExceptionHandler
+ .weak SysTickHandler
+ .globl SysTickHandler
+ .set SysTickHandler, __STM32DefaultExceptionHandler
+ .weak WWDG_IRQHandler
+ .globl WWDG_IRQHandler
+ .set WWDG_IRQHandler, __STM32DefaultExceptionHandler
+ .weak PVD_IRQHandler
+ .globl PVD_IRQHandler
+ .set PVD_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TAMPER_IRQHandler
+ .globl TAMPER_IRQHandler
+ .set TAMPER_IRQHandler, __STM32DefaultExceptionHandler
+ .weak RTC_IRQHandler
+ .globl RTC_IRQHandler
+ .set RTC_IRQHandler, __STM32DefaultExceptionHandler
+ .weak FLASH_IRQHandler
+ .globl FLASH_IRQHandler
+ .set FLASH_IRQHandler, __STM32DefaultExceptionHandler
+ .weak RCC_IRQHandler
+ .globl RCC_IRQHandler
+ .set RCC_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI0_IRQHandler
+ .globl EXTI0_IRQHandler
+ .set EXTI0_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI1_IRQHandler
+ .globl EXTI1_IRQHandler
+ .set EXTI1_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI2_IRQHandler
+ .globl EXTI2_IRQHandler
+ .set EXTI2_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI3_IRQHandler
+ .globl EXTI3_IRQHandler
+ .set EXTI3_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI4_IRQHandler
+ .globl EXTI4_IRQHandler
+ .set EXTI4_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel1_IRQHandler
+ .globl DMAChannel1_IRQHandler
+ .set DMAChannel1_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel2_IRQHandler
+ .globl DMAChannel2_IRQHandler
+ .set DMAChannel2_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel3_IRQHandler
+ .globl DMAChannel3_IRQHandler
+ .set DMAChannel3_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel4_IRQHandler
+ .globl DMAChannel4_IRQHandler
+ .set DMAChannel4_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel5_IRQHandler
+ .globl DMAChannel5_IRQHandler
+ .set DMAChannel5_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel6_IRQHandler
+ .globl DMAChannel6_IRQHandler
+ .set DMAChannel6_IRQHandler, __STM32DefaultExceptionHandler
+ .weak DMAChannel7_IRQHandler
+ .globl DMAChannel7_IRQHandler
+ .set DMAChannel7_IRQHandler, __STM32DefaultExceptionHandler
+ .weak ADC_IRQHandler
+ .globl ADC_IRQHandler
+ .set ADC_IRQHandler, __STM32DefaultExceptionHandler
+ .weak USB_HP_CAN_TX_IRQHandler
+ .globl USB_HP_CAN_TX_IRQHandler
+ .set USB_HP_CAN_TX_IRQHandler, __STM32DefaultExceptionHandler
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .globl USB_LP_CAN_RX0_IRQHandler
+ .set USB_LP_CAN_RX0_IRQHandler, __STM32DefaultExceptionHandler
+ .weak CAN_RX1_IRQHandler
+ .globl CAN_RX1_IRQHandler
+ .set CAN_RX1_IRQHandler, __STM32DefaultExceptionHandler
+ .weak CAN_SCE_IRQHandler
+ .globl CAN_SCE_IRQHandler
+ .set CAN_SCE_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI9_5_IRQHandler
+ .globl EXTI9_5_IRQHandler
+ .set EXTI9_5_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM1_BRK_IRQHandler
+ .globl TIM1_BRK_IRQHandler
+ .set TIM1_BRK_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM1_UP_IRQHandler
+ .globl TIM1_UP_IRQHandler
+ .set TIM1_UP_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM1_TRG_COM_IRQHandler
+ .globl TIM1_TRG_COM_IRQHandler
+ .set TIM1_TRG_COM_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM1_CC_IRQHandler
+ .globl TIM1_CC_IRQHandler
+ .set TIM1_CC_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM2_IRQHandler
+ .globl TIM2_IRQHandler
+ .set TIM2_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM3_IRQHandler
+ .globl TIM3_IRQHandler
+ .set TIM3_IRQHandler, __STM32DefaultExceptionHandler
+ .weak TIM4_IRQHandler
+ .globl TIM4_IRQHandler
+ .set TIM4_IRQHandler, __STM32DefaultExceptionHandler
+ .weak I2C1_EV_IRQHandler
+ .globl I2C1_EV_IRQHandler
+ .set I2C1_EV_IRQHandler, __STM32DefaultExceptionHandler
+ .weak I2C1_ER_IRQHandler
+ .globl I2C1_ER_IRQHandler
+ .set I2C1_ER_IRQHandler, __STM32DefaultExceptionHandler
+ .weak I2C2_EV_IRQHandler
+ .globl I2C2_EV_IRQHandler
+ .set I2C2_EV_IRQHandler, __STM32DefaultExceptionHandler
+ .weak I2C2_ER_IRQHandler
+ .globl I2C2_ER_IRQHandler
+ .set I2C2_ER_IRQHandler, __STM32DefaultExceptionHandler
+ .weak SPI1_IRQHandler
+ .globl SPI1_IRQHandler
+ .set SPI1_IRQHandler, __STM32DefaultExceptionHandler
+ .weak SPI2_IRQHandler
+ .globl SPI2_IRQHandler
+ .set SPI2_IRQHandler, __STM32DefaultExceptionHandler
+ .weak USART1_IRQHandler
+ .globl USART1_IRQHandler
+ .set USART1_IRQHandler, __STM32DefaultExceptionHandler
+ .weak USART2_IRQHandler
+ .globl USART2_IRQHandler
+ .set USART2_IRQHandler, __STM32DefaultExceptionHandler
+ .weak USART3_IRQHandler
+ .globl USART3_IRQHandler
+ .set USART3_IRQHandler, __STM32DefaultExceptionHandler
+ .weak EXTI15_10_IRQHandler
+ .globl EXTI15_10_IRQHandler
+ .set EXTI15_10_IRQHandler, __STM32DefaultExceptionHandler
+ .weak RTCAlarm_IRQHandler
+ .globl RTCAlarm_IRQHandler
+ .set RTCAlarm_IRQHandler, __STM32DefaultExceptionHandler
+ .weak USBWakeUp_IRQHandler
+ .globl USBWakeUp_IRQHandler
+ .set USBWakeUp_IRQHandler, __STM32DefaultExceptionHandler
+
+#endif /* L_lanchon_stm32_isr_interrupt */
diff --git a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S new file mode 100644 index 0000000..17a9c01 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S @@ -0,0 +1,69 @@ +/* Vector table for STM32 (by Lanchon) */
+
+ .section ".cs3.interrupt_vector"
+
+ .globl __cs3_interrupt_vector_lanchon_stm32
+ .type __cs3_interrupt_vector_lanchon_stm32, %object
+
+__cs3_interrupt_vector_lanchon_stm32:
+ .long __cs3_stack
+ .long __cs3_reset
+ .long NMIException
+ .long HardFaultException
+ .long MemManageException
+ .long BusFaultException
+ .long UsageFaultException
+ .long __STM32ReservedException7
+ .long __STM32ReservedException8
+ .long __STM32ReservedException9
+ .long __STM32ReservedException10
+ .long SVCHandler
+ .long DebugMonitor
+ .long __STM32ReservedException13
+ .long PendSVC
+ .long SysTickHandler
+ .long WWDG_IRQHandler
+ .long PVD_IRQHandler
+ .long TAMPER_IRQHandler
+ .long RTC_IRQHandler
+ .long FLASH_IRQHandler
+ .long RCC_IRQHandler
+ .long EXTI0_IRQHandler
+ .long EXTI1_IRQHandler
+ .long EXTI2_IRQHandler
+ .long EXTI3_IRQHandler
+ .long EXTI4_IRQHandler
+ .long DMAChannel1_IRQHandler
+ .long DMAChannel2_IRQHandler
+ .long DMAChannel3_IRQHandler
+ .long DMAChannel4_IRQHandler
+ .long DMAChannel5_IRQHandler
+ .long DMAChannel6_IRQHandler
+ .long DMAChannel7_IRQHandler
+ .long ADC_IRQHandler
+ .long USB_HP_CAN_TX_IRQHandler
+ .long USB_LP_CAN_RX0_IRQHandler
+ .long CAN_RX1_IRQHandler
+ .long CAN_SCE_IRQHandler
+ .long EXTI9_5_IRQHandler
+ .long TIM1_BRK_IRQHandler
+ .long TIM1_UP_IRQHandler
+ .long TIM1_TRG_COM_IRQHandler
+ .long TIM1_CC_IRQHandler
+ .long TIM2_IRQHandler
+ .long TIM3_IRQHandler
+ .long TIM4_IRQHandler
+ .long I2C1_EV_IRQHandler
+ .long I2C1_ER_IRQHandler
+ .long I2C2_EV_IRQHandler
+ .long I2C2_ER_IRQHandler
+ .long SPI1_IRQHandler
+ .long SPI2_IRQHandler
+ .long USART1_IRQHandler
+ .long USART2_IRQHandler
+ .long USART3_IRQHandler
+ .long EXTI15_10_IRQHandler
+ .long RTCAlarm_IRQHandler
+ .long USBWakeUp_IRQHandler
+
+ .size __cs3_interrupt_vector_lanchon_stm32, . - __cs3_interrupt_vector_lanchon_stm32
diff --git a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon_stm32_isr_interrupt.S b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon_stm32_isr_interrupt.S new file mode 100644 index 0000000..1f6c54a --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon_stm32_isr_interrupt.S @@ -0,0 +1,4 @@ +/* ISRs for STM32 (by Lanchon) */
+
+#define L_lanchon_stm32_isr_interrupt 1
+#include "lanchon-stm32-isrs.S"
diff --git a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/makefile b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/makefile new file mode 100644 index 0000000..1c5eac1 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/makefile @@ -0,0 +1,36 @@ +# setup environment
+
+TARGET_ARCH = -mcpu=cortex-m3 -mthumb
+
+CC = arm-none-eabi-gcc
+CFLAGS =
+
+AS = $(CC) -x assembler-with-cpp -c $(TARGET_ARCH)
+ASFLAGS =
+
+AR = arm-none-eabi-ar
+ARFLAGS = cr
+
+
+LIB_OUT = libcs3-lanchon-stm32.a
+
+LIB_OBJS = lanchon-stm32-vector.o lanchon_stm32_isr_interrupt.o
+
+
+# all
+
+.PHONY: all
+all: $(LIB_OUT)
+
+
+# lib
+
+$(LIB_OUT): $(LIB_OBJS)
+ $(AR) $(ARFLAGS) $@ $(LIB_OBJS)
+
+
+# clean
+
+.PHONY: clean
+clean:
+ -rm -f $(LIB_OBJS) $(LIB_OUT)
diff --git a/stm32conf/lanchon-stm32/src/libcs3/generic-m-reset.S b/stm32conf/lanchon-stm32/src/libcs3/generic-m-reset.S new file mode 100644 index 0000000..95dbdbe --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3/generic-m-reset.S @@ -0,0 +1,87 @@ +/* Reset code for generic-m
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+#if defined(__thumb2__) || defined(__ARM_ARCH_6M__)
+#define THUMB 1
+ .thumb
+ .thumb_func
+#else
+ .arm
+#endif
+ .section .cs3.reset,"x",%progbits
+ .globl __cs3_reset_generic_m
+ .type __cs3_reset_generic_m, %function
+__cs3_reset_generic_m:
+ .fnstart
+#include <rdi-io.h>
+
+ adr r1, __cs3_heap_start_ptr
+ mov r0,#AngelSWI_Reason_HeapInfo
+#if THUMB
+ bkpt 0xAB
+#else
+ swi 0x123456
+#endif
+ cmp r0,#0
+ blt 2f
+/* __cs3_heap_start contains
+ [0] ?
+ [4] zero or heap limit
+ [8] zero or top of stack
+ [12] ? */
+ ldr r2, __cs3_heap_start_ptr
+
+#if THUMB
+ ldr r1,=__cs3_stack
+ mov sp,r1
+#else
+ ldr sp,=__cs3_stack
+#endif
+ ldr r0,[r2,#8] /* top of stack */
+ cmp r0, #0
+#if THUMB
+ beq 1f
+ mov sp,r0
+1:
+#else
+ movne sp,r0
+#endif
+ ldr r1,=__cs3_heap_limit
+ ldr r0,[r2,#4] /* heap limit */
+ cmp r0,#0
+#if THUMB
+ beq 1f
+ str r0,[r1]
+1:
+#else
+ strne r0,[r1]
+#endif
+ .word __cs3_heap_start
+2:
+#if THUMB
+ ldr r0,=__cs3_start_c
+ bx r0
+#else
+ b __cs3_start_c
+#endif
+ .pool
+ .cantunwind
+ .fnend
+ .align 2
+__cs3_heap_start_ptr:
+ .word __cs3_heap_start
+ .size __cs3_reset_generic_m,.-__cs3_reset_generic_m
diff --git a/stm32conf/lanchon-stm32/src/libcs3/generic-reset.S b/stm32conf/lanchon-stm32/src/libcs3/generic-reset.S new file mode 100644 index 0000000..d5b54ab --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3/generic-reset.S @@ -0,0 +1,87 @@ +/* Reset code for generic
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+#if defined(__thumb2__) || defined(__ARM_ARCH_6M__)
+#define THUMB 1
+ .thumb
+ .thumb_func
+#else
+ .arm
+#endif
+ .section .cs3.reset,"x",%progbits
+ .globl __cs3_reset_generic
+ .type __cs3_reset_generic, %function
+__cs3_reset_generic:
+ .fnstart
+#include <rdi-io.h>
+
+ adr r1, __cs3_heap_start_ptr
+ mov r0,#AngelSWI_Reason_HeapInfo
+#if THUMB
+ bkpt 0xAB
+#else
+ swi 0x123456
+#endif
+ cmp r0,#0
+ blt 2f
+/* __cs3_heap_start contains
+ [0] ?
+ [4] zero or heap limit
+ [8] zero or top of stack
+ [12] ? */
+ ldr r2, __cs3_heap_start_ptr
+
+#if THUMB
+ ldr r1,=__cs3_stack
+ mov sp,r1
+#else
+ ldr sp,=__cs3_stack
+#endif
+ ldr r0,[r2,#8] /* top of stack */
+ cmp r0, #0
+#if THUMB
+ beq 1f
+ mov sp,r0
+1:
+#else
+ movne sp,r0
+#endif
+ ldr r1,=__cs3_heap_limit
+ ldr r0,[r2,#4] /* heap limit */
+ cmp r0,#0
+#if THUMB
+ beq 1f
+ str r0,[r1]
+1:
+#else
+ strne r0,[r1]
+#endif
+ .word __cs3_heap_start
+2:
+#if THUMB
+ ldr r0,=__cs3_start_c
+ bx r0
+#else
+ b __cs3_start_c
+#endif
+ .pool
+ .cantunwind
+ .fnend
+ .align 2
+__cs3_heap_start_ptr:
+ .word __cs3_heap_start
+ .size __cs3_reset_generic,.-__cs3_reset_generic
diff --git a/stm32conf/lanchon-stm32/src/libcs3/start_c.c b/stm32conf/lanchon-stm32/src/libcs3/start_c.c new file mode 100644 index 0000000..dff9fa3 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3/start_c.c @@ -0,0 +1,58 @@ +/* CS3 start_c routine.
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include "cs3.h"
+
+extern void __libc_init_array (void);
+
+extern int main (int, char **, char **);
+
+extern void exit (int) __attribute__ ((noreturn, weak));
+
+void __attribute ((noreturn))
+__cs3_start_c (void)
+{
+ unsigned regions = __cs3_region_num;
+ const struct __cs3_region *rptr = __cs3_regions;
+ int exit_code;
+
+ /* Initialize memory */
+ for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++)
+ {
+ long long *src = (long long *)rptr->init;
+ long long *dst = (long long *)rptr->data;
+ unsigned limit = rptr->init_size;
+ unsigned count;
+
+ if (src != dst)
+ for (count = 0; count != limit; count += sizeof (long long))
+ *dst++ = *src++;
+ else
+ dst = (long long *)((char *)dst + limit);
+ limit = rptr->zero_size;
+ for (count = 0; count != limit; count += sizeof (long long))
+ *dst++ = 0;
+ }
+
+ /* Run initializers. */
+ __libc_init_array ();
+
+ exit_code = main (0, NULL, NULL);
+ if (exit)
+ exit (exit_code);
+ /* If exit is NULL, make sure we don't return. */
+ for (;;)
+ continue;
+}
diff --git a/stm32conf/lanchon-stm32/src/libcs3arm/arm-isrs.S b/stm32conf/lanchon-stm32/src/libcs3arm/arm-isrs.S new file mode 100644 index 0000000..3688573 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3arm/arm-isrs.S @@ -0,0 +1,49 @@ +/* ISRs for arm
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+ .arch armv4t
+ .arm
+
+#if defined (L_arm_isr_interrupt)
+ .globl __cs3_isr_interrupt
+ .type __cs3_isr_interrupt, %function
+__cs3_isr_interrupt:
+ b .
+ .size __cs3_isr_interrupt, . - __cs3_isr_interrupt
+
+ .weak __cs3_isr_undef
+ .globl __cs3_isr_undef
+ .set __cs3_isr_undef, __cs3_isr_interrupt
+ .weak __cs3_isr_swi
+ .globl __cs3_isr_swi
+ .set __cs3_isr_swi, __cs3_isr_interrupt
+ .weak __cs3_isr_pabort
+ .globl __cs3_isr_pabort
+ .set __cs3_isr_pabort, __cs3_isr_interrupt
+ .weak __cs3_isr_dabort
+ .globl __cs3_isr_dabort
+ .set __cs3_isr_dabort, __cs3_isr_interrupt
+ .weak __cs3_isr_reserved
+ .globl __cs3_isr_reserved
+ .set __cs3_isr_reserved, __cs3_isr_interrupt
+ .weak __cs3_isr_irq
+ .globl __cs3_isr_irq
+ .set __cs3_isr_irq, __cs3_isr_interrupt
+ .weak __cs3_isr_fiq
+ .globl __cs3_isr_fiq
+ .set __cs3_isr_fiq, __cs3_isr_interrupt
+#endif /* interrupt */
diff --git a/stm32conf/lanchon-stm32/src/libcs3arm/arm-vector.S b/stm32conf/lanchon-stm32/src/libcs3arm/arm-vector.S new file mode 100644 index 0000000..1c5b632 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3arm/arm-vector.S @@ -0,0 +1,40 @@ +/* Vector table for arm
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_arm
+ .type __cs3_interrupt_vector_arm, %object
+__cs3_interrupt_vector_arm:
+ .arch armv4
+ .arm
+ ldr pc, [pc, #24] @ reset
+ ldr pc, [pc, #24] @ undef
+ ldr pc, [pc, #24] @ swi
+ ldr pc, [pc, #24] @ pabort
+ ldr pc, [pc, #24] @ dabort
+ ldr pc, [pc, #24] @ reserved
+ ldr pc, [pc, #24] @ irq
+ ldr pc, [pc, #24] @ fiq
+ .long __cs3_reset
+ .long __cs3_isr_undef
+ .long __cs3_isr_swi
+ .long __cs3_isr_pabort
+ .long __cs3_isr_dabort
+ .long __cs3_isr_reserved
+ .long __cs3_isr_irq
+ .long __cs3_isr_fiq
+ .size __cs3_interrupt_vector_arm, . - __cs3_interrupt_vector_arm
diff --git a/stm32conf/lanchon-stm32/src/libcs3micro/micro-isrs.S b/stm32conf/lanchon-stm32/src/libcs3micro/micro-isrs.S new file mode 100644 index 0000000..19787e4 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3micro/micro-isrs.S @@ -0,0 +1,165 @@ +/* ISRs for micro
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+ .thumb
+
+#if defined (L_micro_isr_interrupt)
+ .globl __cs3_isr_interrupt
+ .type __cs3_isr_interrupt, %function
+__cs3_isr_interrupt:
+ b .
+ .size __cs3_isr_interrupt, . - __cs3_isr_interrupt
+
+ .weak __cs3_isr_nmi
+ .globl __cs3_isr_nmi
+ .set __cs3_isr_nmi, __cs3_isr_interrupt
+ .weak __cs3_isr_hard_fault
+ .globl __cs3_isr_hard_fault
+ .set __cs3_isr_hard_fault, __cs3_isr_interrupt
+ .weak __cs3_isr_mpu_fault
+ .globl __cs3_isr_mpu_fault
+ .set __cs3_isr_mpu_fault, __cs3_isr_interrupt
+ .weak __cs3_isr_bus_fault
+ .globl __cs3_isr_bus_fault
+ .set __cs3_isr_bus_fault, __cs3_isr_interrupt
+ .weak __cs3_isr_usage_fault
+ .globl __cs3_isr_usage_fault
+ .set __cs3_isr_usage_fault, __cs3_isr_interrupt
+ .weak __cs3_isr_reserved_7
+ .globl __cs3_isr_reserved_7
+ .set __cs3_isr_reserved_7, __cs3_isr_interrupt
+ .weak __cs3_isr_reserved_8
+ .globl __cs3_isr_reserved_8
+ .set __cs3_isr_reserved_8, __cs3_isr_interrupt
+ .weak __cs3_isr_reserved_9
+ .globl __cs3_isr_reserved_9
+ .set __cs3_isr_reserved_9, __cs3_isr_interrupt
+ .weak __cs3_isr_reserved_10
+ .globl __cs3_isr_reserved_10
+ .set __cs3_isr_reserved_10, __cs3_isr_interrupt
+ .weak __cs3_isr_svcall
+ .globl __cs3_isr_svcall
+ .set __cs3_isr_svcall, __cs3_isr_interrupt
+ .weak __cs3_isr_debug
+ .globl __cs3_isr_debug
+ .set __cs3_isr_debug, __cs3_isr_interrupt
+ .weak __cs3_isr_reserved_13
+ .globl __cs3_isr_reserved_13
+ .set __cs3_isr_reserved_13, __cs3_isr_interrupt
+ .weak __cs3_isr_pendsv
+ .globl __cs3_isr_pendsv
+ .set __cs3_isr_pendsv, __cs3_isr_interrupt
+ .weak __cs3_isr_systick
+ .globl __cs3_isr_systick
+ .set __cs3_isr_systick, __cs3_isr_interrupt
+ .weak __cs3_isr_external_0
+ .globl __cs3_isr_external_0
+ .set __cs3_isr_external_0, __cs3_isr_interrupt
+ .weak __cs3_isr_external_1
+ .globl __cs3_isr_external_1
+ .set __cs3_isr_external_1, __cs3_isr_interrupt
+ .weak __cs3_isr_external_2
+ .globl __cs3_isr_external_2
+ .set __cs3_isr_external_2, __cs3_isr_interrupt
+ .weak __cs3_isr_external_3
+ .globl __cs3_isr_external_3
+ .set __cs3_isr_external_3, __cs3_isr_interrupt
+ .weak __cs3_isr_external_4
+ .globl __cs3_isr_external_4
+ .set __cs3_isr_external_4, __cs3_isr_interrupt
+ .weak __cs3_isr_external_5
+ .globl __cs3_isr_external_5
+ .set __cs3_isr_external_5, __cs3_isr_interrupt
+ .weak __cs3_isr_external_6
+ .globl __cs3_isr_external_6
+ .set __cs3_isr_external_6, __cs3_isr_interrupt
+ .weak __cs3_isr_external_7
+ .globl __cs3_isr_external_7
+ .set __cs3_isr_external_7, __cs3_isr_interrupt
+ .weak __cs3_isr_external_8
+ .globl __cs3_isr_external_8
+ .set __cs3_isr_external_8, __cs3_isr_interrupt
+ .weak __cs3_isr_external_9
+ .globl __cs3_isr_external_9
+ .set __cs3_isr_external_9, __cs3_isr_interrupt
+ .weak __cs3_isr_external_10
+ .globl __cs3_isr_external_10
+ .set __cs3_isr_external_10, __cs3_isr_interrupt
+ .weak __cs3_isr_external_11
+ .globl __cs3_isr_external_11
+ .set __cs3_isr_external_11, __cs3_isr_interrupt
+ .weak __cs3_isr_external_12
+ .globl __cs3_isr_external_12
+ .set __cs3_isr_external_12, __cs3_isr_interrupt
+ .weak __cs3_isr_external_13
+ .globl __cs3_isr_external_13
+ .set __cs3_isr_external_13, __cs3_isr_interrupt
+ .weak __cs3_isr_external_14
+ .globl __cs3_isr_external_14
+ .set __cs3_isr_external_14, __cs3_isr_interrupt
+ .weak __cs3_isr_external_15
+ .globl __cs3_isr_external_15
+ .set __cs3_isr_external_15, __cs3_isr_interrupt
+ .weak __cs3_isr_external_16
+ .globl __cs3_isr_external_16
+ .set __cs3_isr_external_16, __cs3_isr_interrupt
+ .weak __cs3_isr_external_17
+ .globl __cs3_isr_external_17
+ .set __cs3_isr_external_17, __cs3_isr_interrupt
+ .weak __cs3_isr_external_18
+ .globl __cs3_isr_external_18
+ .set __cs3_isr_external_18, __cs3_isr_interrupt
+ .weak __cs3_isr_external_19
+ .globl __cs3_isr_external_19
+ .set __cs3_isr_external_19, __cs3_isr_interrupt
+ .weak __cs3_isr_external_20
+ .globl __cs3_isr_external_20
+ .set __cs3_isr_external_20, __cs3_isr_interrupt
+ .weak __cs3_isr_external_21
+ .globl __cs3_isr_external_21
+ .set __cs3_isr_external_21, __cs3_isr_interrupt
+ .weak __cs3_isr_external_22
+ .globl __cs3_isr_external_22
+ .set __cs3_isr_external_22, __cs3_isr_interrupt
+ .weak __cs3_isr_external_23
+ .globl __cs3_isr_external_23
+ .set __cs3_isr_external_23, __cs3_isr_interrupt
+ .weak __cs3_isr_external_24
+ .globl __cs3_isr_external_24
+ .set __cs3_isr_external_24, __cs3_isr_interrupt
+ .weak __cs3_isr_external_25
+ .globl __cs3_isr_external_25
+ .set __cs3_isr_external_25, __cs3_isr_interrupt
+ .weak __cs3_isr_external_26
+ .globl __cs3_isr_external_26
+ .set __cs3_isr_external_26, __cs3_isr_interrupt
+ .weak __cs3_isr_external_27
+ .globl __cs3_isr_external_27
+ .set __cs3_isr_external_27, __cs3_isr_interrupt
+ .weak __cs3_isr_external_28
+ .globl __cs3_isr_external_28
+ .set __cs3_isr_external_28, __cs3_isr_interrupt
+ .weak __cs3_isr_external_29
+ .globl __cs3_isr_external_29
+ .set __cs3_isr_external_29, __cs3_isr_interrupt
+ .weak __cs3_isr_external_30
+ .globl __cs3_isr_external_30
+ .set __cs3_isr_external_30, __cs3_isr_interrupt
+ .weak __cs3_isr_external_31
+ .globl __cs3_isr_external_31
+ .set __cs3_isr_external_31, __cs3_isr_interrupt
+#endif /* interrupt */
diff --git a/stm32conf/lanchon-stm32/src/libcs3micro/micro-vector.S b/stm32conf/lanchon-stm32/src/libcs3micro/micro-vector.S new file mode 100644 index 0000000..d00ee17 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/libcs3micro/micro-vector.S @@ -0,0 +1,70 @@ +/* Vector table for micro
+ *
+ * Version:Sourcery G++ 4.2-84
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_micro
+ .type __cs3_interrupt_vector_micro, %object
+__cs3_interrupt_vector_micro:
+ .long __cs3_stack
+ .long __cs3_reset
+ .long __cs3_isr_nmi
+ .long __cs3_isr_hard_fault
+ .long __cs3_isr_mpu_fault
+ .long __cs3_isr_bus_fault
+ .long __cs3_isr_usage_fault
+ .long __cs3_isr_reserved_7
+ .long __cs3_isr_reserved_8
+ .long __cs3_isr_reserved_9
+ .long __cs3_isr_reserved_10
+ .long __cs3_isr_svcall
+ .long __cs3_isr_debug
+ .long __cs3_isr_reserved_13
+ .long __cs3_isr_pendsv
+ .long __cs3_isr_systick
+ .long __cs3_isr_external_0
+ .long __cs3_isr_external_1
+ .long __cs3_isr_external_2
+ .long __cs3_isr_external_3
+ .long __cs3_isr_external_4
+ .long __cs3_isr_external_5
+ .long __cs3_isr_external_6
+ .long __cs3_isr_external_7
+ .long __cs3_isr_external_8
+ .long __cs3_isr_external_9
+ .long __cs3_isr_external_10
+ .long __cs3_isr_external_11
+ .long __cs3_isr_external_12
+ .long __cs3_isr_external_13
+ .long __cs3_isr_external_14
+ .long __cs3_isr_external_15
+ .long __cs3_isr_external_16
+ .long __cs3_isr_external_17
+ .long __cs3_isr_external_18
+ .long __cs3_isr_external_19
+ .long __cs3_isr_external_20
+ .long __cs3_isr_external_21
+ .long __cs3_isr_external_22
+ .long __cs3_isr_external_23
+ .long __cs3_isr_external_24
+ .long __cs3_isr_external_25
+ .long __cs3_isr_external_26
+ .long __cs3_isr_external_27
+ .long __cs3_isr_external_28
+ .long __cs3_isr_external_29
+ .long __cs3_isr_external_30
+ .long __cs3_isr_external_31
+ .size __cs3_interrupt_vector_micro, . - __cs3_interrupt_vector_micro
diff --git a/stm32conf/lanchon-stm32/src/start.S b/stm32conf/lanchon-stm32/src/start.S new file mode 100644 index 0000000..595af07 --- /dev/null +++ b/stm32conf/lanchon-stm32/src/start.S @@ -0,0 +1,36 @@ +/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+ .text
+#if defined(__thumb2__) || defined(__ARM_ARCH_6M__)
+#define THUMB 1
+ .code 16
+ .thumb_func
+#else
+ .code 32
+#endif
+ .globl _start
+ .type _start, %function
+_start:
+ .fnstart
+#if THUMB
+ ldr r1,=__cs3_stack
+ mov sp,r1
+ ldr r1,=__cs3_start_c
+ bx r1
+#else
+ ldr sp,=__cs3_stack
+ b __cs3_start_c
+#endif
+ .pool
+ .cantunwind
+ .fnend
diff --git a/stm32conf/run.cfg b/stm32conf/run.cfg new file mode 100644 index 0000000..234a3c8 --- /dev/null +++ b/stm32conf/run.cfg @@ -0,0 +1,75 @@ +# script for stm32 + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG" +ft2232_layout olimex-jtag +ft2232_vid_pid 0x15ba 0x0003 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 26.6.3 + set _CPUTAPID 0x3ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + # High density devices, Rev A + set _BSTAPID4 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID5 0x06418041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 + + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0 + +flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME + +proc nopforever {} { + puts "Resetting the chip..." + reset run +} + +init +nopforever |