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author | Perry Hung <iperry@alum.mit.edu> | 2010-03-26 00:58:23 -0400 |
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committer | Perry Hung <iperry@alum.mit.edu> | 2010-03-26 00:58:23 -0400 |
commit | 35811da8ab196dea7b4590c56a91195eccd2f834 (patch) | |
tree | 63ec487046566066ef7bb37d62d8e6b62f1a4acb /src/wiring | |
parent | ca8033c92a382be789d9bb325b03165004cd0bb2 (diff) | |
download | librambutan-35811da8ab196dea7b4590c56a91195eccd2f834.tar.gz librambutan-35811da8ab196dea7b4590c56a91195eccd2f834.zip |
Removed stm32 rcc code. Briefly tested the basic set up procedure,
brings up the board to 72MHz, clocked by external crystal PLL boosted to
72MHz.
Diffstat (limited to 'src/wiring')
-rw-r--r-- | src/wiring/wiring.c | 56 |
1 files changed, 2 insertions, 54 deletions
diff --git a/src/wiring/wiring.c b/src/wiring/wiring.c index dc6796f..6ef1968 100644 --- a/src/wiring/wiring.c +++ b/src/wiring/wiring.c @@ -27,6 +27,7 @@ #include "stm32f10x_flash.h" #include "stm32f10x_map.h" #include "stm32f10x_nvic.h" +#include "rcc.h" #include "systick.h" #include "gpio.h" @@ -34,12 +35,7 @@ void RCC_Configuration(void); void NVIC_Configuration(void); void init(void) { -// RCC_Configuration(); -// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | -// RCC_APB2Periph_GPIOB | -// RCC_APB2Periph_GPIOC | -// RCC_APB2Periph_AFIO -// , ENABLE); + rcc_init(); NVIC_Configuration(); systick_init(); @@ -67,51 +63,3 @@ void NVIC_Configuration(void) { #endif } - -#if 0 -void RCC_Configuration(void) { - ErrorStatus HSEStartUpStatus; - /* RCC system reset(for debug purpose) */ - RCC_DeInit(); - - /* Enable HSE */ - RCC_HSEConfig(RCC_HSE_ON); - - /* Wait till HSE is ready */ - HSEStartUpStatus = RCC_WaitForHSEStartUp(); - - if(HSEStartUpStatus == SUCCESS) { - /* Enable Prefetch Buffer */ - FLASH_PrefetchBufferCmd( (u32)FLASH_PrefetchBuffer_Enable); - - /* Flash 2 wait state */ - FLASH_SetLatency(FLASH_Latency_2); - - /* HCLK = SYSCLK */ - RCC_HCLKConfig(RCC_SYSCLK_Div1); - - /* PCLK2 = HCLK APB2 Periphs, no prescaler 72MHz */ - RCC_PCLK2Config(RCC_HCLK_Div1); - - /* PCLK1 = HCLK/2 APB1 periphs = 36MHZ*/ - RCC_PCLK1Config(RCC_HCLK_Div2); - - /* PLLCLK = 8MHz * 9 = 72 MHz */ - RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); - - /* Enable PLL */ - RCC_PLLCmd(ENABLE); - - /* Wait till PLL is ready */ - while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) - ; - - /* Select PLL as system clock source */ - RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); - - /* Wait till PLL is used as system clock source */ - while(RCC_GetSYSCLKSource() != 0x08) - ; - } -} -#endif |