diff options
| author | iperry <iperry@749a229e-a60e-11de-b98f-4500b42dc123> | 2009-12-17 02:37:07 +0000 |
|---|---|---|
| committer | iperry <iperry@749a229e-a60e-11de-b98f-4500b42dc123> | 2009-12-17 02:37:07 +0000 |
| commit | 32e57dac2e61e79b029593eb4d34d727bcc10678 (patch) | |
| tree | 98d7ff41993576bb150d13d5f63dc744f6812852 /src/stm32lib/inc | |
| download | librambutan-32e57dac2e61e79b029593eb4d34d727bcc10678.tar.gz librambutan-32e57dac2e61e79b029593eb4d34d727bcc10678.zip | |
Initial commit of library code, moved from leaftest repo
git-svn-id: https://leaflabs.googlecode.com/svn/trunk/library@69 749a229e-a60e-11de-b98f-4500b42dc123
Diffstat (limited to 'src/stm32lib/inc')
27 files changed, 6612 insertions, 0 deletions
diff --git a/src/stm32lib/inc/cortexm3_macro.h b/src/stm32lib/inc/cortexm3_macro.h new file mode 100644 index 0000000..26b04ef --- /dev/null +++ b/src/stm32lib/inc/cortexm3_macro.h @@ -0,0 +1,176 @@ +#if 0
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : cortexm3_macro.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : Header file for cortexm3_macro.s.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void __WFI(void);
+void __WFE(void);
+void __SEV(void);
+void __ISB(void);
+void __DSB(void);
+void __DMB(void);
+void __SVC(void);
+u32 __MRS_CONTROL(void);
+void __MSR_CONTROL(u32 Control);
+u32 __MRS_PSP(void);
+void __MSR_PSP(u32 TopOfProcessStack);
+u32 __MRS_MSP(void);
+void __MSR_MSP(u32 TopOfMainStack);
+void __RESETPRIMASK(void);
+void __SETPRIMASK(void);
+u32 __READ_PRIMASK(void);
+void __RESETFAULTMASK(void);
+void __SETFAULTMASK(void);
+u32 __READ_FAULTMASK(void);
+void __BASEPRICONFIG(u32 NewPriority);
+u32 __GetBASEPRI(void);
+u16 __REV_HalfWord(u16 Data);
+u32 __REV_Word(u32 Data);
+
+#endif /* __CORTEXM3_MACRO_H */
+#endif
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+
+/******************** (C) COPYRIGHT 2008 Andreas Fritiofson ********************
+* File Name : cortexm3_macro.h
+* Author : Andreas Fritiofson
+* Version : V1.0
+* Date : 30/04/2008
+* Description : Instruction wrappers for special Cortex-M3 instructions.
+********************************************************************************
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+static inline void __WFI(void) {
+ asm volatile ( "WFI \n" );
+}
+static inline void __WFE(void) {
+ asm volatile ( "WFE \n" );
+}
+static inline void __SEV(void) {
+ asm volatile ( "SEV \n" );
+}
+static inline void __ISB(void) {
+ asm volatile ( "ISB \n" );
+}
+static inline void __DSB(void) {
+ asm volatile ( "DSB \n" );
+}
+static inline void __DMB(void) {
+ asm volatile ( "DMB \n" );
+}
+static inline void __SVC(void) {
+ asm volatile ( "SVC 0x01 \n" );
+}
+static inline u32 __MRS_CONTROL(void) {
+ u32 x;
+ asm volatile ( "MRS %0, control \n" : "=r" (x));
+ return x;
+}
+static inline void __MSR_CONTROL(u32 Control) {
+ asm volatile (
+ "MSR control, %0 \n"
+ "ISB \n"
+ : : "r" (Control));
+}
+static inline u32 __MRS_PSP(void) {
+ u32 x;
+ asm volatile ( "MRS %0, psp \n" : "=r" (x));
+ return x;
+}
+static inline void __MSR_PSP(u32 TopOfProcessStack) {
+ asm volatile ( "MSR psp, %0 \n" : : "r" (TopOfProcessStack));
+}
+static inline u32 __MRS_MSP(void) {
+ u32 x;
+ asm volatile ( "MRS %0, msp \n" : "=r" (x));
+ return x;
+}
+static inline void __MSR_MSP(u32 TopOfMainStack) {
+ asm volatile ( "MSR msp, %0 \n" : : "r" (TopOfMainStack));
+}
+static inline void __SETPRIMASK(void) {
+ asm volatile ( "CPSID i \n" );
+}
+static inline void __RESETPRIMASK(void) {
+ asm volatile ( "CPSIE i \n" );
+}
+static inline void __SETFAULTMASK(void) {
+ asm volatile ( "CPSID f \n" );
+}
+static inline void __RESETFAULTMASK(void) {
+ asm volatile ( "CPSIE f \n" );
+}
+static inline void __BASEPRICONFIG(u32 NewPriority) {
+ asm volatile ( "MSR basepri, %0 \n" : : "r" (NewPriority));
+}
+static inline u32 __GetBASEPRI(void) {
+ u32 x;
+ asm volatile ( "MRS %0, basepri_max \n" : "=r" (x));
+ return x;
+}
+static inline u16 __REV_HalfWord(u16 Data) {
+ u16 x;
+ asm volatile ( "REV16 %0, %1 \n" : "=r" (x) : "r" (Data));
+ return x;
+}
+static inline u32 __REV_Word(u32 Data) {
+ u32 x;
+ asm volatile ( "REV %0, %1 \n" : "=r" (x) : "r" (Data));
+ return x;
+}
+
+#endif /* __CORTEXM3_MACRO_H */
+
+/******************* (C) COPYRIGHT 2008 Andreas Fritiofson *****END OF FILE****/
+
diff --git a/src/stm32lib/inc/stm32f10x_adc.h b/src/stm32lib/inc/stm32f10x_adc.h new file mode 100644 index 0000000..8fc9098 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_adc.h @@ -0,0 +1,300 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_adc.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* ADC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* ADC Init structure definition */
+typedef struct
+{
+ u32 ADC_Mode;
+ FunctionalState ADC_ScanConvMode;
+ FunctionalState ADC_ContinuousConvMode;
+ u32 ADC_ExternalTrigConv;
+ u32 ADC_DataAlign;
+ u8 ADC_NbrOfChannel;
+}ADC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
+ ((*(u32*)&(PERIPH)) == ADC2_BASE) || \
+ ((*(u32*)&(PERIPH)) == ADC3_BASE))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
+ ((*(u32*)&(PERIPH)) == ADC3_BASE))
+
+/* ADC dual mode -------------------------------------------------------------*/
+#define ADC_Mode_Independent ((u32)0x00000000)
+#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
+#define ADC_Mode_InjecSimult ((u32)0x00050000)
+#define ADC_Mode_RegSimult ((u32)0x00060000)
+#define ADC_Mode_FastInterl ((u32)0x00070000)
+#define ADC_Mode_SlowInterl ((u32)0x00080000)
+#define ADC_Mode_AlterTrig ((u32)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+ ((MODE) == ADC_Mode_RegInjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult) || \
+ ((MODE) == ADC_Mode_FastInterl) || \
+ ((MODE) == ADC_Mode_SlowInterl) || \
+ ((MODE) == ADC_Mode_AlterTrig))
+
+/* ADC extrenal trigger sources for regular channels conversion --------------*/
+/* for ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
+#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)
+/* for ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
+#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
+/* for ADC3 */
+#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)
+#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)
+#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)
+#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)
+#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)
+#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+
+/* ADC data align ------------------------------------------------------------*/
+#define ADC_DataAlign_Right ((u32)0x00000000)
+#define ADC_DataAlign_Left ((u32)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+
+/* ADC channels --------------------------------------------------------------*/
+#define ADC_Channel_0 ((u8)0x00)
+#define ADC_Channel_1 ((u8)0x01)
+#define ADC_Channel_2 ((u8)0x02)
+#define ADC_Channel_3 ((u8)0x03)
+#define ADC_Channel_4 ((u8)0x04)
+#define ADC_Channel_5 ((u8)0x05)
+#define ADC_Channel_6 ((u8)0x06)
+#define ADC_Channel_7 ((u8)0x07)
+#define ADC_Channel_8 ((u8)0x08)
+#define ADC_Channel_9 ((u8)0x09)
+#define ADC_Channel_10 ((u8)0x0A)
+#define ADC_Channel_11 ((u8)0x0B)
+#define ADC_Channel_12 ((u8)0x0C)
+#define ADC_Channel_13 ((u8)0x0D)
+#define ADC_Channel_14 ((u8)0x0E)
+#define ADC_Channel_15 ((u8)0x0F)
+#define ADC_Channel_16 ((u8)0x10)
+#define ADC_Channel_17 ((u8)0x11)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+
+/* ADC sampling times --------------------------------------------------------*/
+#define ADC_SampleTime_1Cycles5 ((u8)0x00)
+#define ADC_SampleTime_7Cycles5 ((u8)0x01)
+#define ADC_SampleTime_13Cycles5 ((u8)0x02)
+#define ADC_SampleTime_28Cycles5 ((u8)0x03)
+#define ADC_SampleTime_41Cycles5 ((u8)0x04)
+#define ADC_SampleTime_55Cycles5 ((u8)0x05)
+#define ADC_SampleTime_71Cycles5 ((u8)0x06)
+#define ADC_SampleTime_239Cycles5 ((u8)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+ ((TIME) == ADC_SampleTime_7Cycles5) || \
+ ((TIME) == ADC_SampleTime_13Cycles5) || \
+ ((TIME) == ADC_SampleTime_28Cycles5) || \
+ ((TIME) == ADC_SampleTime_41Cycles5) || \
+ ((TIME) == ADC_SampleTime_55Cycles5) || \
+ ((TIME) == ADC_SampleTime_71Cycles5) || \
+ ((TIME) == ADC_SampleTime_239Cycles5))
+
+/* ADC extrenal trigger sources for injected channels conversion -------------*/
+/* For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)
+/* For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
+#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
+/* For ADC3 */
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+
+/* ADC injected channel selection --------------------------------------------*/
+#define ADC_InjectedChannel_1 ((u8)0x14)
+#define ADC_InjectedChannel_2 ((u8)0x18)
+#define ADC_InjectedChannel_3 ((u8)0x1C)
+#define ADC_InjectedChannel_4 ((u8)0x20)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4))
+
+/* ADC analog watchdog selection ---------------------------------------------*/
+#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
+#define ADC_AnalogWatchdog_None ((u32)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+
+/* ADC interrupts definition -------------------------------------------------*/
+#define ADC_IT_EOC ((u16)0x0220)
+#define ADC_IT_AWD ((u16)0x0140)
+#define ADC_IT_JEOC ((u16)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+ ((IT) == ADC_IT_JEOC))
+
+/* ADC flags definition ------------------------------------------------------*/
+#define ADC_FLAG_AWD ((u8)0x01)
+#define ADC_FLAG_EOC ((u8)0x02)
+#define ADC_FLAG_JEOC ((u8)0x04)
+#define ADC_FLAG_JSTRT ((u8)0x08)
+#define ADC_FLAG_STRT ((u8)0x10)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+ ((FLAG) == ADC_FLAG_STRT))
+
+/* ADC thresholds ------------------------------------------------------------*/
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/* ADC injected offset -------------------------------------------------------*/
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/* ADC injected length -------------------------------------------------------*/
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/* ADC injected rank ---------------------------------------------------------*/
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/* ADC regular length --------------------------------------------------------*/
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+
+/* ADC regular rank ----------------------------------------------------------*/
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/* ADC regular discontinuous mode number -------------------------------------*/
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
+u32 ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
+
+#endif /*__STM32F10x_ADC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_bkp.h b/src/stm32lib/inc/stm32f10x_bkp.h new file mode 100644 index 0000000..39ea7ae --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_bkp.h @@ -0,0 +1,122 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_bkp.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* BKP firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Tamper Pin active level */
+#define BKP_TamperPinLevel_High ((u16)0x0000)
+#define BKP_TamperPinLevel_Low ((u16)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+ ((LEVEL) == BKP_TamperPinLevel_Low))
+
+/* RTC output source to output on the Tamper pin */
+#define BKP_RTCOutputSource_None ((u16)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
+#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
+#define BKP_RTCOutputSource_Second ((u16)0x0300)
+
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+ ((SOURCE) == BKP_RTCOutputSource_Second))
+
+/* Data Backup Register */
+#define BKP_DR1 ((u16)0x0004)
+#define BKP_DR2 ((u16)0x0008)
+#define BKP_DR3 ((u16)0x000C)
+#define BKP_DR4 ((u16)0x0010)
+#define BKP_DR5 ((u16)0x0014)
+#define BKP_DR6 ((u16)0x0018)
+#define BKP_DR7 ((u16)0x001C)
+#define BKP_DR8 ((u16)0x0020)
+#define BKP_DR9 ((u16)0x0024)
+#define BKP_DR10 ((u16)0x0028)
+#define BKP_DR11 ((u16)0x0040)
+#define BKP_DR12 ((u16)0x0044)
+#define BKP_DR13 ((u16)0x0048)
+#define BKP_DR14 ((u16)0x004C)
+#define BKP_DR15 ((u16)0x0050)
+#define BKP_DR16 ((u16)0x0054)
+#define BKP_DR17 ((u16)0x0058)
+#define BKP_DR18 ((u16)0x005C)
+#define BKP_DR19 ((u16)0x0060)
+#define BKP_DR20 ((u16)0x0064)
+#define BKP_DR21 ((u16)0x0068)
+#define BKP_DR22 ((u16)0x006C)
+#define BKP_DR23 ((u16)0x0070)
+#define BKP_DR24 ((u16)0x0074)
+#define BKP_DR25 ((u16)0x0078)
+#define BKP_DR26 ((u16)0x007C)
+#define BKP_DR27 ((u16)0x0080)
+#define BKP_DR28 ((u16)0x0084)
+#define BKP_DR29 ((u16)0x0088)
+#define BKP_DR30 ((u16)0x008C)
+#define BKP_DR31 ((u16)0x0090)
+#define BKP_DR32 ((u16)0x0094)
+#define BKP_DR33 ((u16)0x0098)
+#define BKP_DR34 ((u16)0x009C)
+#define BKP_DR35 ((u16)0x00A0)
+#define BKP_DR36 ((u16)0x00A4)
+#define BKP_DR37 ((u16)0x00A8)
+#define BKP_DR38 ((u16)0x00AC)
+#define BKP_DR39 ((u16)0x00B0)
+#define BKP_DR40 ((u16)0x00B4)
+#define BKP_DR41 ((u16)0x00B8)
+#define BKP_DR42 ((u16)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
+u16 BKP_ReadBackupRegister(u16 BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#endif /* __STM32F10x_BKP_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_can.h b/src/stm32lib/inc/stm32f10x_can.h new file mode 100644 index 0000000..85dd07b --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_can.h @@ -0,0 +1,263 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_can.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* CAN firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* CAN init structure definition */
+typedef struct
+{
+ FunctionalState CAN_TTCM;
+ FunctionalState CAN_ABOM;
+ FunctionalState CAN_AWUM;
+ FunctionalState CAN_NART;
+ FunctionalState CAN_RFLM;
+ FunctionalState CAN_TXFP;
+ u8 CAN_Mode;
+ u8 CAN_SJW;
+ u8 CAN_BS1;
+ u8 CAN_BS2;
+ u16 CAN_Prescaler;
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+ u8 CAN_FilterNumber;
+ u8 CAN_FilterMode;
+ u8 CAN_FilterScale;
+ u16 CAN_FilterIdHigh;
+ u16 CAN_FilterIdLow;
+ u16 CAN_FilterMaskIdHigh;
+ u16 CAN_FilterMaskIdLow;
+ u16 CAN_FilterFIFOAssignment;
+ FunctionalState CAN_FilterActivation;
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+ u32 StdId;
+ u32 ExtId;
+ u8 IDE;
+ u8 RTR;
+ u8 DLC;
+ u8 Data[8];
+} CanTxMsg;
+
+/* CAN Rx message structure definition */
+typedef struct
+{
+ u32 StdId;
+ u32 ExtId;
+ u8 IDE;
+ u8 RTR;
+ u8 DLC;
+ u8 Data[8];
+ u8 FMI;
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/* CAN sleep constants */
+#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */
+#define CANINITOK ((u8)0x01) /* CAN initialization failed */
+
+/* CAN operating mode */
+#define CAN_Mode_Normal ((u8)0x00) /* normal mode */
+#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */
+#define CAN_Mode_Silent ((u8)0x02) /* silent mode */
+#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
+
+/* CAN synchronisation jump width */
+#define CAN_SJW_1tq ((u8)0x00) /* 1 time quantum */
+#define CAN_SJW_2tq ((u8)0x01) /* 2 time quantum */
+#define CAN_SJW_3tq ((u8)0x02) /* 3 time quantum */
+#define CAN_SJW_4tq ((u8)0x03) /* 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+
+/* time quantum in bit segment 1 */
+#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */
+#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */
+#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */
+#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */
+#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */
+#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */
+#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */
+#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */
+#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */
+#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */
+#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */
+#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */
+#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */
+#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */
+#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */
+#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+
+/* time quantum in bit segment 2 */
+#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */
+#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */
+#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */
+#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */
+#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */
+#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */
+#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */
+#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
+/* CAN clock prescaler */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/* CAN filter number */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+
+/* CAN filter mode */
+#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */
+#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+ ((MODE) == CAN_FilterMode_IdList))
+
+/* CAN filter scale */
+#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */
+#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+ ((SCALE) == CAN_FilterScale_32bit))
+
+/* CAN filter FIFO assignation */
+#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */
+#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+ ((FIFO) == CAN_FilterFIFO1))
+
+/* CAN Tx */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((u8)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((u32)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((u32)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((u8)0x08))
+
+/* CAN identifier type */
+#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */
+#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
+
+/* CAN remote transmission request */
+#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */
+#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */
+
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+/* CAN transmit constants */
+#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */
+#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */
+#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */
+#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN receive FIFO number constants */
+#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */
+#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/* CAN sleep constants */
+#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */
+#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */
+
+/* CAN wake up constants */
+#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */
+#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */
+
+/* CAN flags */
+#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */
+#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */
+#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */
+
+#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\
+ ((FLAG) == CAN_FLAG_BOF))
+
+/* CAN interrupts */
+#define CAN_IT_RQCP0 ((u32)0x00000005) /* Request completed mailbox 0 */
+#define CAN_IT_RQCP1 ((u32)0x00000006) /* Request completed mailbox 1 */
+#define CAN_IT_RQCP2 ((u32)0x00000007) /* Request completed mailbox 2 */
+#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */
+#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */
+#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */
+#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */
+#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */
+#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */
+#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */
+#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */
+#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */
+#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */
+#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */
+#define CAN_IT_ERR ((u32)0x00008000) /* Error */
+#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */
+#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */
+
+#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\
+ ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported function protypes ----------------------------------------------- */
+void CAN_DeInit(void);
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);
+u8 CAN_Transmit(CanTxMsg* TxMessage);
+u8 CAN_TransmitStatus(u8 TransmitMailbox);
+void CAN_CancelTransmit(u8 Mailbox);
+void CAN_FIFORelease(u8 FIFONumber);
+u8 CAN_MessagePending(u8 FIFONumber);
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);
+u8 CAN_Sleep(void);
+u8 CAN_WakeUp(void);
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);
+void CAN_ClearFlag(u32 CAN_FLAG);
+ITStatus CAN_GetITStatus(u32 CAN_IT);
+void CAN_ClearITPendingBit(u32 CAN_IT);
+
+#endif /* __STM32F10x_CAN_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_crc.h b/src/stm32lib/inc/stm32f10x_crc.h new file mode 100644 index 0000000..0c3dab4 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_crc.h @@ -0,0 +1,37 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_crc.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* CRC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void CRC_ResetDR(void);
+u32 CRC_CalcCRC(u32 Data);
+u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength);
+u32 CRC_GetCRC(void);
+void CRC_SetIDRegister(u8 IDValue);
+u8 CRC_GetIDRegister(void);
+
+#endif /* __STM32F10x_CRC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_dac.h b/src/stm32lib/inc/stm32f10x_dac.h new file mode 100644 index 0000000..cd7b5ad --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_dac.h @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_dac.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* DAC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* DAC Init structure definition */
+typedef struct
+{
+ u32 DAC_Trigger;
+ u32 DAC_WaveGeneration;
+ u32 DAC_LFSRUnmask_TriangleAmplitude;
+ u32 DAC_OutputBuffer;
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* DAC trigger selection */
+#define DAC_Trigger_None ((u32)0x00000000)
+#define DAC_Trigger_T6_TRGO ((u32)0x00000004)
+#define DAC_Trigger_T8_TRGO ((u32)0x0000000C)
+#define DAC_Trigger_T7_TRGO ((u32)0x00000014)
+#define DAC_Trigger_T5_TRGO ((u32)0x0000001C)
+#define DAC_Trigger_T2_TRGO ((u32)0x00000024)
+#define DAC_Trigger_T4_TRGO ((u32)0x0000002C)
+#define DAC_Trigger_Ext_IT9 ((u32)0x00000034)
+#define DAC_Trigger_Software ((u32)0x0000003C)
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/* DAC wave generation */
+#define DAC_WaveGeneration_None ((u32)0x00000000)
+#define DAC_WaveGeneration_Noise ((u32)0x00000040)
+#define DAC_WaveGeneration_Triangle ((u32)0x00000080)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+
+/* DAC noise wave generation mask / triangle wave generation max amplitude */
+#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000)
+#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100)
+#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200)
+#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300)
+#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400)
+#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500)
+#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600)
+#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700)
+#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800)
+#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900)
+#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00)
+#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00)
+
+#define DAC_TriangleAmplitude_1 ((u32)0x00000000)
+#define DAC_TriangleAmplitude_3 ((u32)0x00000100)
+#define DAC_TriangleAmplitude_7 ((u32)0x00000200)
+#define DAC_TriangleAmplitude_15 ((u32)0x00000300)
+#define DAC_TriangleAmplitude_31 ((u32)0x00000400)
+#define DAC_TriangleAmplitude_63 ((u32)0x00000500)
+#define DAC_TriangleAmplitude_127 ((u32)0x00000600)
+#define DAC_TriangleAmplitude_255 ((u32)0x00000700)
+#define DAC_TriangleAmplitude_511 ((u32)0x00000800)
+#define DAC_TriangleAmplitude_1023 ((u32)0x00000900)
+#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00)
+#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00)
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+
+/* DAC output buffer */
+#define DAC_OutputBuffer_Enable ((u32)0x00000000)
+#define DAC_OutputBuffer_Disable ((u32)0x00000002)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+ ((STATE) == DAC_OutputBuffer_Disable))
+
+/* DAC Channel selection */
+#define DAC_Channel_1 ((u32)0x00000000)
+#define DAC_Channel_2 ((u32)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+
+/* DAC data alignement */
+#define DAC_Align_12b_R ((u32)0x00000000)
+#define DAC_Align_12b_L ((u32)0x00000004)
+#define DAC_Align_8b_R ((u32)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+
+/* DAC wave generation */
+#define DAC_Wave_Noise ((u32)0x00000040)
+#define DAC_Wave_Triangle ((u32)0x00000080)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+
+/* DAC data ------------------------------------------------------------------*/
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+void DAC_DeInit(void);
+void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(u32 DAC_Align, u16 Data);
+void DAC_SetChannel2Data(u32 DAC_Align, u16 Data);
+void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1);
+u16 DAC_GetDataOutputValue(u32 DAC_Channel);
+
+#endif /*__STM32F10x_DAC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_dbgmcu.h b/src/stm32lib/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..212f646 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,55 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_dbgmcu.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* DBGMCU firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DBGMCU_H
+#define __STM32F10x_DBGMCU_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define DBGMCU_SLEEP ((u32)0x00000001)
+#define DBGMCU_STOP ((u32)0x00000002)
+#define DBGMCU_STANDBY ((u32)0x00000004)
+#define DBGMCU_IWDG_STOP ((u32)0x00000100)
+#define DBGMCU_WWDG_STOP ((u32)0x00000200)
+#define DBGMCU_TIM1_STOP ((u32)0x00000400)
+#define DBGMCU_TIM2_STOP ((u32)0x00000800)
+#define DBGMCU_TIM3_STOP ((u32)0x00001000)
+#define DBGMCU_TIM4_STOP ((u32)0x00002000)
+#define DBGMCU_CAN_STOP ((u32)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((u32)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((u32)0x00010000)
+#define DBGMCU_TIM5_STOP ((u32)0x00020000)
+#define DBGMCU_TIM6_STOP ((u32)0x00040000)
+#define DBGMCU_TIM7_STOP ((u32)0x00080000)
+#define DBGMCU_TIM8_STOP ((u32)0x00100000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+u32 DBGMCU_GetREVID(void);
+u32 DBGMCU_GetDEVID(void);
+void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState);
+
+#endif /* __STM32F10x_DBGMCU_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+
+
diff --git a/src/stm32lib/inc/stm32f10x_dma.h b/src/stm32lib/inc/stm32f10x_dma.h new file mode 100644 index 0000000..4803a69 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_dma.h @@ -0,0 +1,297 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_dma.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* DMA firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* DMA Init structure definition */
+typedef struct
+{
+ u32 DMA_PeripheralBaseAddr;
+ u32 DMA_MemoryBaseAddr;
+ u32 DMA_DIR;
+ u32 DMA_BufferSize;
+ u32 DMA_PeripheralInc;
+ u32 DMA_MemoryInc;
+ u32 DMA_PeripheralDataSize;
+ u32 DMA_MemoryDataSize;
+ u32 DMA_Mode;
+ u32 DMA_Priority;
+ u32 DMA_M2M;
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \
+ ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))
+
+/* DMA data transfer direction -----------------------------------------------*/
+#define DMA_DIR_PeripheralDST ((u32)0x00000010)
+#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+ ((DIR) == DMA_DIR_PeripheralSRC))
+
+/* DMA peripheral incremented mode -------------------------------------------*/
+#define DMA_PeripheralInc_Enable ((u32)0x00000040)
+#define DMA_PeripheralInc_Disable ((u32)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+
+/* DMA memory incremented mode -----------------------------------------------*/
+#define DMA_MemoryInc_Enable ((u32)0x00000080)
+#define DMA_MemoryInc_Disable ((u32)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+
+/* DMA peripheral data size --------------------------------------------------*/
+#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
+#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+
+/* DMA memory data size ------------------------------------------------------*/
+#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
+#define DMA_MemoryDataSize_Word ((u32)0x00000800)
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+
+/* DMA circular/normal mode --------------------------------------------------*/
+#define DMA_Mode_Circular ((u32)0x00000020)
+#define DMA_Mode_Normal ((u32)0x00000000)
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+
+/* DMA priority level --------------------------------------------------------*/
+#define DMA_Priority_VeryHigh ((u32)0x00003000)
+#define DMA_Priority_High ((u32)0x00002000)
+#define DMA_Priority_Medium ((u32)0x00001000)
+#define DMA_Priority_Low ((u32)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+
+/* DMA memory to memory ------------------------------------------------------*/
+#define DMA_M2M_Enable ((u32)0x00004000)
+#define DMA_M2M_Disable ((u32)0x00000000)
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/* DMA interrupts definition -------------------------------------------------*/
+#define DMA_IT_TC ((u32)0x00000002)
+#define DMA_IT_HT ((u32)0x00000004)
+#define DMA_IT_TE ((u32)0x00000008)
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+/* For DMA1 */
+#define DMA1_IT_GL1 ((u32)0x00000001)
+#define DMA1_IT_TC1 ((u32)0x00000002)
+#define DMA1_IT_HT1 ((u32)0x00000004)
+#define DMA1_IT_TE1 ((u32)0x00000008)
+#define DMA1_IT_GL2 ((u32)0x00000010)
+#define DMA1_IT_TC2 ((u32)0x00000020)
+#define DMA1_IT_HT2 ((u32)0x00000040)
+#define DMA1_IT_TE2 ((u32)0x00000080)
+#define DMA1_IT_GL3 ((u32)0x00000100)
+#define DMA1_IT_TC3 ((u32)0x00000200)
+#define DMA1_IT_HT3 ((u32)0x00000400)
+#define DMA1_IT_TE3 ((u32)0x00000800)
+#define DMA1_IT_GL4 ((u32)0x00001000)
+#define DMA1_IT_TC4 ((u32)0x00002000)
+#define DMA1_IT_HT4 ((u32)0x00004000)
+#define DMA1_IT_TE4 ((u32)0x00008000)
+#define DMA1_IT_GL5 ((u32)0x00010000)
+#define DMA1_IT_TC5 ((u32)0x00020000)
+#define DMA1_IT_HT5 ((u32)0x00040000)
+#define DMA1_IT_TE5 ((u32)0x00080000)
+#define DMA1_IT_GL6 ((u32)0x00100000)
+#define DMA1_IT_TC6 ((u32)0x00200000)
+#define DMA1_IT_HT6 ((u32)0x00400000)
+#define DMA1_IT_TE6 ((u32)0x00800000)
+#define DMA1_IT_GL7 ((u32)0x01000000)
+#define DMA1_IT_TC7 ((u32)0x02000000)
+#define DMA1_IT_HT7 ((u32)0x04000000)
+#define DMA1_IT_TE7 ((u32)0x08000000)
+/* For DMA2 */
+#define DMA2_IT_GL1 ((u32)0x10000001)
+#define DMA2_IT_TC1 ((u32)0x10000002)
+#define DMA2_IT_HT1 ((u32)0x10000004)
+#define DMA2_IT_TE1 ((u32)0x10000008)
+#define DMA2_IT_GL2 ((u32)0x10000010)
+#define DMA2_IT_TC2 ((u32)0x10000020)
+#define DMA2_IT_HT2 ((u32)0x10000040)
+#define DMA2_IT_TE2 ((u32)0x10000080)
+#define DMA2_IT_GL3 ((u32)0x10000100)
+#define DMA2_IT_TC3 ((u32)0x10000200)
+#define DMA2_IT_HT3 ((u32)0x10000400)
+#define DMA2_IT_TE3 ((u32)0x10000800)
+#define DMA2_IT_GL4 ((u32)0x10001000)
+#define DMA2_IT_TC4 ((u32)0x10002000)
+#define DMA2_IT_HT4 ((u32)0x10004000)
+#define DMA2_IT_TE4 ((u32)0x10008000)
+#define DMA2_IT_GL5 ((u32)0x10010000)
+#define DMA2_IT_TC5 ((u32)0x10020000)
+#define DMA2_IT_HT5 ((u32)0x10040000)
+#define DMA2_IT_TE5 ((u32)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/* DMA flags definition ------------------------------------------------------*/
+/* For DMA1 */
+#define DMA1_FLAG_GL1 ((u32)0x00000001)
+#define DMA1_FLAG_TC1 ((u32)0x00000002)
+#define DMA1_FLAG_HT1 ((u32)0x00000004)
+#define DMA1_FLAG_TE1 ((u32)0x00000008)
+#define DMA1_FLAG_GL2 ((u32)0x00000010)
+#define DMA1_FLAG_TC2 ((u32)0x00000020)
+#define DMA1_FLAG_HT2 ((u32)0x00000040)
+#define DMA1_FLAG_TE2 ((u32)0x00000080)
+#define DMA1_FLAG_GL3 ((u32)0x00000100)
+#define DMA1_FLAG_TC3 ((u32)0x00000200)
+#define DMA1_FLAG_HT3 ((u32)0x00000400)
+#define DMA1_FLAG_TE3 ((u32)0x00000800)
+#define DMA1_FLAG_GL4 ((u32)0x00001000)
+#define DMA1_FLAG_TC4 ((u32)0x00002000)
+#define DMA1_FLAG_HT4 ((u32)0x00004000)
+#define DMA1_FLAG_TE4 ((u32)0x00008000)
+#define DMA1_FLAG_GL5 ((u32)0x00010000)
+#define DMA1_FLAG_TC5 ((u32)0x00020000)
+#define DMA1_FLAG_HT5 ((u32)0x00040000)
+#define DMA1_FLAG_TE5 ((u32)0x00080000)
+#define DMA1_FLAG_GL6 ((u32)0x00100000)
+#define DMA1_FLAG_TC6 ((u32)0x00200000)
+#define DMA1_FLAG_HT6 ((u32)0x00400000)
+#define DMA1_FLAG_TE6 ((u32)0x00800000)
+#define DMA1_FLAG_GL7 ((u32)0x01000000)
+#define DMA1_FLAG_TC7 ((u32)0x02000000)
+#define DMA1_FLAG_HT7 ((u32)0x04000000)
+#define DMA1_FLAG_TE7 ((u32)0x08000000)
+/* For DMA2 */
+#define DMA2_FLAG_GL1 ((u32)0x10000001)
+#define DMA2_FLAG_TC1 ((u32)0x10000002)
+#define DMA2_FLAG_HT1 ((u32)0x10000004)
+#define DMA2_FLAG_TE1 ((u32)0x10000008)
+#define DMA2_FLAG_GL2 ((u32)0x10000010)
+#define DMA2_FLAG_TC2 ((u32)0x10000020)
+#define DMA2_FLAG_HT2 ((u32)0x10000040)
+#define DMA2_FLAG_TE2 ((u32)0x10000080)
+#define DMA2_FLAG_GL3 ((u32)0x10000100)
+#define DMA2_FLAG_TC3 ((u32)0x10000200)
+#define DMA2_FLAG_HT3 ((u32)0x10000400)
+#define DMA2_FLAG_TE3 ((u32)0x10000800)
+#define DMA2_FLAG_GL4 ((u32)0x10001000)
+#define DMA2_FLAG_TC4 ((u32)0x10002000)
+#define DMA2_FLAG_HT4 ((u32)0x10004000)
+#define DMA2_FLAG_TE4 ((u32)0x10008000)
+#define DMA2_FLAG_GL5 ((u32)0x10010000)
+#define DMA2_FLAG_TC5 ((u32)0x10020000)
+#define DMA2_FLAG_HT5 ((u32)0x10040000)
+#define DMA2_FLAG_TE5 ((u32)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+
+/* DMA Buffer Size -----------------------------------------------------------*/
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
+void DMA_ClearFlag(u32 DMA_FLAG);
+ITStatus DMA_GetITStatus(u32 DMA_IT);
+void DMA_ClearITPendingBit(u32 DMA_IT);
+
+#endif /*__STM32F10x_DMA_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_exti.h b/src/stm32lib/inc/stm32f10x_exti.h new file mode 100644 index 0000000..46ac68d --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_exti.h @@ -0,0 +1,113 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_exti.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* EXTI firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* EXTI mode enumeration -----------------------------------------------------*/
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/* EXTI Trigger enumeration --------------------------------------------------*/
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+
+/* EXTI Init Structure definition --------------------------------------------*/
+typedef struct
+{
+ u32 EXTI_Line;
+ EXTIMode_TypeDef EXTI_Mode;
+ EXTITrigger_TypeDef EXTI_Trigger;
+ FunctionalState EXTI_LineCmd;
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* EXTI Lines ----------------------------------------------------------------*/
+#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */
+#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */
+#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */
+#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */
+#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */
+#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */
+#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */
+#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */
+#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */
+#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */
+#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */
+#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */
+#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */
+#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */
+#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */
+#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */
+#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16
+ Connected to the PVD Output */
+#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17
+ Connected to the RTC Alarm event */
+#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18
+ Connected to the USB Wakeup from
+ suspend event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (u32)0xFFF80000) == 0x00) && ((LINE) != (u16)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);
+void EXTI_ClearFlag(u32 EXTI_Line);
+ITStatus EXTI_GetITStatus(u32 EXTI_Line);
+void EXTI_ClearITPendingBit(u32 EXTI_Line);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_flash.h b/src/stm32lib/inc/stm32f10x_flash.h new file mode 100644 index 0000000..459a044 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_flash.h @@ -0,0 +1,215 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_flash.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* FLASH firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+
+/* Exported types ------------------------------------------------------------*/
+#ifdef _FLASH_PROG
+/* FLASH Status */
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_PG,
+ FLASH_ERROR_WRP,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+#endif
+
+/* Flash Latency -------------------------------------------------------------*/
+#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */
+#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1) || \
+ ((LATENCY) == FLASH_Latency_2))
+
+/* Half Cycle Enable/Disable -------------------------------------------------*/
+#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */
+
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+ ((STATE) == FLASH_HalfCycleAccess_Disable))
+
+
+/* Prefetch Buffer Enable/Disable --------------------------------------------*/
+#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */
+
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+ ((STATE) == FLASH_PrefetchBuffer_Disable))
+
+#ifdef _FLASH_PROG
+/* Option Bytes Write Protection ---------------------------------------------*/
+/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density
+ ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
+#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */
+#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */
+/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density
+ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
+#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */
+#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/* Option Bytes IWatchdog ----------------------------------------------------*/
+#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */
+#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/* Option Bytes nRST_STOP ----------------------------------------------------*/
+#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/* Option Bytes nRST_STDBY ---------------------------------------------------*/
+#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/* FLASH Interrupts ----------------------------------------------------------*/
+#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */
+#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */
+
+#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/* FLASH Flags ---------------------------------------------------------------*/
+#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */
+#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_OPTERR))
+#endif
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+void FLASH_SetLatency(u32 FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer);
+#ifdef __cplusplus
+};
+#endif
+
+#ifdef _FLASH_PROG
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(u32 Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data);
+FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data);
+FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data);
+FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY);
+u32 FLASH_GetUserOptionByte(void);
+u32 FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG);
+void FLASH_ClearFlag(u16 FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(u32 Timeout);
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_fsmc.h b/src/stm32lib/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..d508299 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_fsmc.h @@ -0,0 +1,355 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_fsmc.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* FSMC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FSMC_H
+#define __STM32F10x_FSMC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Timing parameters For NOR/SRAM Banks */
+typedef struct
+{
+ u32 FSMC_AddressSetupTime;
+ u32 FSMC_AddressHoldTime;
+ u32 FSMC_DataSetupTime;
+ u32 FSMC_BusTurnAroundDuration;
+ u32 FSMC_CLKDivision;
+ u32 FSMC_DataLatency;
+ u32 FSMC_AccessMode;
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/* FSMC NOR/SRAM Init structure definition */
+typedef struct
+{
+ u32 FSMC_Bank;
+ u32 FSMC_DataAddressMux;
+ u32 FSMC_MemoryType;
+ u32 FSMC_MemoryDataWidth;
+ u32 FSMC_BurstAccessMode;
+ u32 FSMC_WaitSignalPolarity;
+ u32 FSMC_WrapMode;
+ u32 FSMC_WaitSignalActive;
+ u32 FSMC_WriteOperation;
+ u32 FSMC_WaitSignal;
+ u32 FSMC_ExtendedMode;
+ u32 FSMC_AsyncWait;
+ u32 FSMC_WriteBurst;
+ /* Timing Parameters for write and read access if the ExtendedMode is not used*/
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
+ /* Timing Parameters for write access if the ExtendedMode is used*/
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
+}FSMC_NORSRAMInitTypeDef;
+
+/* Timing parameters For FSMC NAND and PCCARD Banks */
+typedef struct
+{
+ u32 FSMC_SetupTime;
+ u32 FSMC_WaitSetupTime;
+ u32 FSMC_HoldSetupTime;
+ u32 FSMC_HiZSetupTime;
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/* FSMC NAND Init structure definition */
+typedef struct
+{
+ u32 FSMC_Bank;
+ u32 FSMC_Waitfeature;
+ u32 FSMC_MemoryDataWidth;
+ u32 FSMC_ECC;
+ u32 FSMC_ECCPageSize;
+ u32 FSMC_AddressLowMapping;
+ u32 FSMC_TCLRSetupTime;
+ u32 FSMC_TARSetupTime;
+ /* FSMC Common Space Timing */
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
+ /* FSMC Attribute Space Timing */
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
+}FSMC_NANDInitTypeDef;
+
+/* FSMC PCCARD Init structure definition */
+typedef struct
+{
+ u32 FSMC_Waitfeature;
+ u32 FSMC_AddressLowMapping;
+ u32 FSMC_TCLRSetupTime;
+ u32 FSMC_TARSetupTime;
+ /* FSMC Common Space Timing */
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
+ /* FSMC Attribute Space Timing */
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
+ /* FSMC IO Space Timing */
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
+}FSMC_PCCARDInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/*-------------------------------FSMC Banks definitions ----------------------*/
+#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)
+#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)
+#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)
+#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)
+#define FSMC_Bank2_NAND ((u32)0x00000010)
+#define FSMC_Bank3_NAND ((u32)0x00000100)
+#define FSMC_Bank4_PCCARD ((u32)0x00001000)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \
+ ((BANK) == FSMC_Bank1_NORSRAM4))
+
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+
+/*------------------------------- NOR/SRAM Banks -----------------------------*/
+/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/
+#define FSMC_DataAddressMux_Disable ((u32)0x00000000)
+#define FSMC_DataAddressMux_Enable ((u32)0x00000002)
+
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+ ((MUX) == FSMC_DataAddressMux_Enable))
+
+/* FSMC Memory Type ----------------------------------------------------------*/
+#define FSMC_MemoryType_SRAM ((u32)0x00000000)
+#define FSMC_MemoryType_CRAM ((u32)0x00000004)
+#define FSMC_MemoryType_NOR ((u32)0x00000008)
+#define FSMC_MemoryType_COSMORAM ((u32)0x0000000C)
+
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+ ((MEMORY) == FSMC_MemoryType_CRAM)|| \
+ ((MEMORY) == FSMC_MemoryType_NOR)|| \
+ ((MEMORY) == FSMC_MemoryType_COSMORAM))
+
+/* FSMC Data Width ----------------------------------------------------------*/
+#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
+
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+
+/* FSMC Burst Access Mode ----------------------------------------------------*/
+#define FSMC_BurstAccessMode_Disable ((u32)0x00000000)
+#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)
+
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+ ((STATE) == FSMC_BurstAccessMode_Enable))
+
+/* FSMC Wait Signal Polarity -------------------------------------------------*/
+#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)
+#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)
+
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+ ((POLARITY) == FSMC_WaitSignalPolarity_High))
+
+/* FSMC Wrap Mode ------------------------------------------------------------*/
+#define FSMC_WrapMode_Disable ((u32)0x00000000)
+#define FSMC_WrapMode_Enable ((u32)0x00000400)
+
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+ ((MODE) == FSMC_WrapMode_Enable))
+
+/* FSMC Wait Timing ----------------------------------------------------------*/
+#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800)
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/* FSMC Write Operation ------------------------------------------------------*/
+#define FSMC_WriteOperation_Disable ((u32)0x00000000)
+#define FSMC_WriteOperation_Enable ((u32)0x00001000)
+
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+ ((OPERATION) == FSMC_WriteOperation_Enable))
+
+/* FSMC Wait Signal ----------------------------------------------------------*/
+#define FSMC_WaitSignal_Disable ((u32)0x00000000)
+#define FSMC_WaitSignal_Enable ((u32)0x00002000)
+
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+ ((SIGNAL) == FSMC_WaitSignal_Enable))
+
+/* FSMC Extended Mode --------------------------------------------------------*/
+#define FSMC_ExtendedMode_Disable ((u32)0x00000000)
+#define FSMC_ExtendedMode_Enable ((u32)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+ ((MODE) == FSMC_ExtendedMode_Enable))
+
+/* FSMC Asynchronous Wait ----------------------------------------------------*/
+#define FSMC_AsyncWait_Disable ((u32)0x00000000)
+#define FSMC_AsyncWait_Enable ((u32)0x00008000)
+
+#define IS_FSMC_ASYNC_WAIT(WAIT) (((WAIT) == FSMC_AsyncWait_Disable) || \
+ ((WAIT) == FSMC_AsyncWait_Enable))
+
+/* FSMC Write Burst ----------------------------------------------------------*/
+#define FSMC_WriteBurst_Disable ((u32)0x00000000)
+#define FSMC_WriteBurst_Enable ((u32)0x00080000)
+
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+ ((BURST) == FSMC_WriteBurst_Enable))
+
+/* FSMC Address Setup Time ---------------------------------------------------*/
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/* FSMC Address Hold Time ----------------------------------------------------*/
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/* FSMC Data Setup Time ------------------------------------------------------*/
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/* FSMC Bus Turn around Duration ---------------------------------------------*/
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/* FSMC CLK Division ---------------------------------------------------------*/
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/* FSMC Data Latency ---------------------------------------------------------*/
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/* FSMC Access Mode ----------------------------------------------------------*/
+#define FSMC_AccessMode_A ((u32)0x00000000)
+#define FSMC_AccessMode_B ((u32)0x10000000)
+#define FSMC_AccessMode_C ((u32)0x20000000)
+#define FSMC_AccessMode_D ((u32)0x30000000)
+
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+ ((MODE) == FSMC_AccessMode_B) || \
+ ((MODE) == FSMC_AccessMode_C) || \
+ ((MODE) == FSMC_AccessMode_D))
+
+/*----------------------------- NAND and PCCARD Banks ------------------------*/
+/* FSMC Wait feature ---------------------------------------------------------*/
+#define FSMC_Waitfeature_Disable ((u32)0x00000000)
+#define FSMC_Waitfeature_Enable ((u32)0x00000002)
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+ ((FEATURE) == FSMC_Waitfeature_Enable))
+
+/* FSMC Memory Data Width ----------------------------------------------------*/
+#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
+
+#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/* FSMC ECC ------------------------------------------------------------------*/
+#define FSMC_ECC_Disable ((u32)0x00000000)
+#define FSMC_ECC_Enable ((u32)0x00000040)
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+ ((STATE) == FSMC_ECC_Enable))
+
+/* FSMC ECC Page Size --------------------------------------------------------*/
+#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)
+#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+/* FSMC Address Low Mapping --------------------------------------------------*/
+#define FSMC_AddressLowMapping_Direct ((u32)0x00000000)
+#define FSMC_AddressLowMapping_InDirect ((u32)0x00000100)
+
+#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) || \
+ ((MAPPING) == FSMC_AddressLowMapping_InDirect))
+/* FSMC TCLR Setup Time ------------------------------------------------------*/
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
+/* FSMC TAR Setup Time -------------------------------------------------------*/
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
+/* FSMC Setup Time ----------------------------------------------------*/
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
+/* FSMC Wait Setup Time -----------------------------------------------*/
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
+/* FSMC Hold Setup Time -----------------------------------------------*/
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
+/* FSMC HiZ Setup Time ------------------------------------------------*/
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
+/* FSMC Interrupt sources ----------------------------------------------------*/
+#define FSMC_IT_RisingEdge ((u32)0x00000008)
+#define FSMC_IT_Level ((u32)0x00000010)
+#define FSMC_IT_FallingEdge ((u32)0x00000020)
+
+#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+ ((IT) == FSMC_IT_Level) || \
+ ((IT) == FSMC_IT_FallingEdge))
+
+/* FSMC Flags ----------------------------------------------------------------*/
+#define FSMC_FLAG_RisingEdge ((u32)0x00000001)
+#define FSMC_FLAG_Level ((u32)0x00000002)
+#define FSMC_FLAG_FallingEdge ((u32)0x00000004)
+#define FSMC_FLAG_FEMPT ((u32)0x00000040)
+
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+ ((FLAG) == FSMC_FLAG_Level) || \
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \
+ ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void FSMC_NORSRAMDeInit(u32 FSMC_Bank);
+void FSMC_NANDDeInit(u32 FSMC_Bank);
+void FSMC_PCCARDDeInit(void);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);
+u32 FSMC_GetECC(u32 FSMC_Bank);
+void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);
+void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);
+ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);
+void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);
+
+#endif /*__STM32F10x_FSMC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_gpio.h b/src/stm32lib/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..ae7f0c2 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_gpio.h @@ -0,0 +1,243 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_gpio.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* GPIO firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \
+ ((*(u32*)&(PERIPH)) == GPIOB_BASE) || \
+ ((*(u32*)&(PERIPH)) == GPIOC_BASE) || \
+ ((*(u32*)&(PERIPH)) == GPIOD_BASE) || \
+ ((*(u32*)&(PERIPH)) == GPIOE_BASE) || \
+ ((*(u32*)&(PERIPH)) == GPIOF_BASE) || \
+ ((*(u32*)&(PERIPH)) == GPIOG_BASE))
+
+/* Output Maximum frequency selection ----------------------------------------*/
+typedef enum
+{
+ GPIO_Speed_10MHz = 1,
+ GPIO_Speed_2MHz,
+ GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+ ((SPEED) == GPIO_Speed_50MHz))
+
+/* Configuration Mode enumeration --------------------------------------------*/
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/* GPIO Init structure definition */
+typedef struct
+{
+ u16 GPIO_Pin;
+ GPIOSpeed_TypeDef GPIO_Speed;
+ GPIOMode_TypeDef GPIO_Mode;
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/* Exported constants --------------------------------------------------------*/
+/* GPIO pins define ----------------------------------------------------------*/
+#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */
+#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */
+#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */
+#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */
+#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */
+#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */
+#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */
+#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */
+#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */
+#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */
+#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */
+#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */
+#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */
+#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */
+#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */
+#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */
+#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/* GPIO Remap define ---------------------------------------------------------*/
+#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */
+#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */
+#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+
+
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
+ ((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+ ((REMAP) == GPIO_Remap_SWJ_Disable))
+
+/* GPIO Port Sources ---------------------------------------------------------*/
+#define GPIO_PortSourceGPIOA ((u8)0x00)
+#define GPIO_PortSourceGPIOB ((u8)0x01)
+#define GPIO_PortSourceGPIOC ((u8)0x02)
+#define GPIO_PortSourceGPIOD ((u8)0x03)
+#define GPIO_PortSourceGPIOE ((u8)0x04)
+#define GPIO_PortSourceGPIOF ((u8)0x05)
+#define GPIO_PortSourceGPIOG ((u8)0x06)
+
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/* GPIO Pin sources ----------------------------------------------------------*/
+#define GPIO_PinSource0 ((u8)0x00)
+#define GPIO_PinSource1 ((u8)0x01)
+#define GPIO_PinSource2 ((u8)0x02)
+#define GPIO_PinSource3 ((u8)0x03)
+#define GPIO_PinSource4 ((u8)0x04)
+#define GPIO_PinSource5 ((u8)0x05)
+#define GPIO_PinSource6 ((u8)0x06)
+#define GPIO_PinSource7 ((u8)0x07)
+#define GPIO_PinSource8 ((u8)0x08)
+#define GPIO_PinSource9 ((u8)0x09)
+#define GPIO_PinSource10 ((u8)0x0A)
+#define GPIO_PinSource11 ((u8)0x0B)
+#define GPIO_PinSource12 ((u8)0x0C)
+#define GPIO_PinSource13 ((u8)0x0D)
+#define GPIO_PinSource14 ((u8)0x0E)
+#define GPIO_PinSource15 ((u8)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __STM32F10x_GPIO_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_i2c.h b/src/stm32lib/inc/stm32f10x_i2c.h new file mode 100644 index 0000000..7dd6d7d --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_i2c.h @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_i2c.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* I2C firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* I2C Init structure definition */
+typedef struct
+{
+ u16 I2C_Mode;
+ u16 I2C_DutyCycle;
+ u16 I2C_OwnAddress1;
+ u16 I2C_Ack;
+ u16 I2C_AcknowledgedAddress;
+ u32 I2C_ClockSpeed;
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+#define IS_I2C_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == I2C1_BASE) || \
+ ((*(u32*)&(PERIPH)) == I2C2_BASE))
+
+/* I2C modes */
+#define I2C_Mode_I2C ((u16)0x0000)
+#define I2C_Mode_SMBusDevice ((u16)0x0002)
+#define I2C_Mode_SMBusHost ((u16)0x000A)
+
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/* I2C duty cycle in fast mode */
+#define I2C_DutyCycle_16_9 ((u16)0x4000)
+#define I2C_DutyCycle_2 ((u16)0xBFFF)
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+ ((CYCLE) == I2C_DutyCycle_2))
+
+/* I2C cknowledgementy */
+#define I2C_Ack_Enable ((u16)0x0400)
+#define I2C_Ack_Disable ((u16)0x0000)
+
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+ ((STATE) == I2C_Ack_Disable))
+
+/* I2C transfer direction */
+#define I2C_Direction_Transmitter ((u8)0x00)
+#define I2C_Direction_Receiver ((u8)0x01)
+
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+
+/* I2C acknowledged address defines */
+#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+
+/* I2C registers */
+#define I2C_Register_CR1 ((u8)0x00)
+#define I2C_Register_CR2 ((u8)0x04)
+#define I2C_Register_OAR1 ((u8)0x08)
+#define I2C_Register_OAR2 ((u8)0x0C)
+#define I2C_Register_DR ((u8)0x10)
+#define I2C_Register_SR1 ((u8)0x14)
+#define I2C_Register_SR2 ((u8)0x18)
+#define I2C_Register_CCR ((u8)0x1C)
+#define I2C_Register_TRISE ((u8)0x20)
+
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_DR) || \
+ ((REGISTER) == I2C_Register_SR1) || \
+ ((REGISTER) == I2C_Register_SR2) || \
+ ((REGISTER) == I2C_Register_CCR) || \
+ ((REGISTER) == I2C_Register_TRISE))
+
+/* I2C SMBus alert pin level */
+#define I2C_SMBusAlert_Low ((u16)0x2000)
+#define I2C_SMBusAlert_High ((u16)0xDFFF)
+
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+ ((ALERT) == I2C_SMBusAlert_High))
+
+/* I2C PEC position */
+#define I2C_PECPosition_Next ((u16)0x0800)
+#define I2C_PECPosition_Current ((u16)0xF7FF)
+
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+ ((POSITION) == I2C_PECPosition_Current))
+
+/* I2C interrupts definition */
+#define I2C_IT_BUF ((u16)0x0400)
+#define I2C_IT_EVT ((u16)0x0200)
+#define I2C_IT_ERR ((u16)0x0100)
+
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (u16)0xF8FF) == 0x00) && ((IT) != 0x00))
+
+/* I2C interrupts definition */
+#define I2C_IT_SMBALERT ((u32)0x01008000)
+#define I2C_IT_TIMEOUT ((u32)0x01004000)
+#define I2C_IT_PECERR ((u32)0x01001000)
+#define I2C_IT_OVR ((u32)0x01000800)
+#define I2C_IT_AF ((u32)0x01000400)
+#define I2C_IT_ARLO ((u32)0x01000200)
+#define I2C_IT_BERR ((u32)0x01000100)
+#define I2C_IT_TXE ((u32)0x06000080)
+#define I2C_IT_RXNE ((u32)0x06000040)
+#define I2C_IT_STOPF ((u32)0x02000010)
+#define I2C_IT_ADD10 ((u32)0x02000008)
+#define I2C_IT_BTF ((u32)0x02000004)
+#define I2C_IT_ADDR ((u32)0x02000002)
+#define I2C_IT_SB ((u32)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (u16)0x20FF) == 0x00) && ((IT) != (u16)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+
+/* I2C flags definition */
+/* SR2 register flags */
+#define I2C_FLAG_DUALF ((u32)0x00800000)
+#define I2C_FLAG_SMBHOST ((u32)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)
+#define I2C_FLAG_GENCALL ((u32)0x00100000)
+#define I2C_FLAG_TRA ((u32)0x00040000)
+#define I2C_FLAG_BUSY ((u32)0x00020000)
+#define I2C_FLAG_MSL ((u32)0x00010000)
+/* SR1 register flags */
+#define I2C_FLAG_SMBALERT ((u32)0x10008000)
+#define I2C_FLAG_TIMEOUT ((u32)0x10004000)
+#define I2C_FLAG_PECERR ((u32)0x10001000)
+#define I2C_FLAG_OVR ((u32)0x10000800)
+#define I2C_FLAG_AF ((u32)0x10000400)
+#define I2C_FLAG_ARLO ((u32)0x10000200)
+#define I2C_FLAG_BERR ((u32)0x10000100)
+#define I2C_FLAG_TXE ((u32)0x10000080)
+#define I2C_FLAG_RXNE ((u32)0x10000040)
+#define I2C_FLAG_STOPF ((u32)0x10000010)
+#define I2C_FLAG_ADD10 ((u32)0x10000008)
+#define I2C_FLAG_BTF ((u32)0x10000004)
+#define I2C_FLAG_ADDR ((u32)0x10000002)
+#define I2C_FLAG_SB ((u32)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0x20FF) == 0x00) && ((FLAG) != (u16)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_SB))
+
+/* I2C Events */
+/* EV1 */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */
+
+/* EV2 */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */
+
+/* EV3 */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+
+/* EV4 */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */
+
+/* EV5 */
+#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */
+
+/* EV6 */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */
+
+/* EV7 */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/* EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/* EV9 */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/* EV3_2 */
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+
+/* I2C own address1 -----------------------------------------------------------*/
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/* I2C clock speed ------------------------------------------------------------*/
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);
+
+#endif /*__STM32F10x_I2C_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_iwdg.h b/src/stm32lib/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000..287950f --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_iwdg.h @@ -0,0 +1,69 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_iwdg.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* IWDG firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Write access to IWDG_PR and IWDG_RLR registers */
+#define IWDG_WriteAccess_Enable ((u16)0x5555)
+#define IWDG_WriteAccess_Disable ((u16)0x0000)
+
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+
+/* IWDG prescaler */
+#define IWDG_Prescaler_4 ((u8)0x00)
+#define IWDG_Prescaler_8 ((u8)0x01)
+#define IWDG_Prescaler_16 ((u8)0x02)
+#define IWDG_Prescaler_32 ((u8)0x03)
+#define IWDG_Prescaler_64 ((u8)0x04)
+#define IWDG_Prescaler_128 ((u8)0x05)
+#define IWDG_Prescaler_256 ((u8)0x06)
+
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+
+/* IWDG Flag */
+#define IWDG_FLAG_PVU ((u16)0x0001)
+#define IWDG_FLAG_RVU ((u16)0x0002)
+
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);
+void IWDG_SetPrescaler(u8 IWDG_Prescaler);
+void IWDG_SetReload(u16 Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);
+
+#endif /* __STM32F10x_IWDG_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_lib.h b/src/stm32lib/inc/stm32f10x_lib.h new file mode 100644 index 0000000..beff887 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_lib.h @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_lib.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file includes the peripherals header files in the
+* user application.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_LIB_H
+#define __STM32F10x_LIB_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+#ifdef _ADC
+ #include "stm32f10x_adc.h"
+#endif /*_ADC */
+
+#ifdef _BKP
+ #include "stm32f10x_bkp.h"
+#endif /*_BKP */
+
+#ifdef _CAN
+ #include "stm32f10x_can.h"
+#endif /*_CAN */
+
+#ifdef _CRC
+ #include "stm32f10x_crc.h"
+#endif /*_CRC */
+
+#ifdef _DAC
+ #include "stm32f10x_dac.h"
+#endif /*_DAC */
+
+#ifdef _DBGMCU
+ #include "stm32f10x_dbgmcu.h"
+#endif /*_DBGMCU */
+
+#ifdef _DMA
+ #include "stm32f10x_dma.h"
+#endif /*_DMA */
+
+#ifdef _EXTI
+ #include "stm32f10x_exti.h"
+#endif /*_EXTI */
+
+#ifdef _FLASH
+ #include "stm32f10x_flash.h"
+#endif /*_FLASH */
+
+#ifdef _FSMC
+ #include "stm32f10x_fsmc.h"
+#endif /*_FSMC */
+
+#ifdef _GPIO
+ #include "stm32f10x_gpio.h"
+#endif /*_GPIO */
+
+#ifdef _I2C
+ #include "stm32f10x_i2c.h"
+#endif /*_I2C */
+
+#ifdef _IWDG
+ #include "stm32f10x_iwdg.h"
+#endif /*_IWDG */
+
+#ifdef _NVIC
+ #include "stm32f10x_nvic.h"
+#endif /*_NVIC */
+
+#ifdef _PWR
+ #include "stm32f10x_pwr.h"
+#endif /*_PWR */
+
+#ifdef _RCC
+ #include "stm32f10x_rcc.h"
+#endif /*_RCC */
+
+#ifdef _RTC
+ #include "stm32f10x_rtc.h"
+#endif /*_RTC */
+
+#ifdef _SDIO
+ #include "stm32f10x_sdio.h"
+#endif /*_SDIO */
+
+#ifdef _SPI
+ #include "stm32f10x_spi.h"
+#endif /*_SPI */
+
+#ifdef _SysTick
+ #include "stm32f10x_systick.h"
+#endif /*_SysTick */
+
+#ifdef _TIM
+ #include "stm32f10x_tim.h"
+#endif /*_TIM */
+
+#ifdef _USART
+ #include "stm32f10x_usart.h"
+#endif /*_USART */
+
+#ifdef _WWDG
+ #include "stm32f10x_wwdg.h"
+#endif /*_WWDG */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void debug(void);
+
+#endif /* __STM32F10x_LIB_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_map.h b/src/stm32lib/inc/stm32f10x_map.h new file mode 100644 index 0000000..33829fc --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_map.h @@ -0,0 +1,1187 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_map.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the peripheral register's definitions
+* and memory mapping.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_MAP_H
+#define __STM32F10x_MAP_H
+
+#ifndef EXT
+ #define EXT extern
+#endif /* EXT */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_conf.h"
+#include "stm32f10x_type.h"
+#include "cortexm3_macro.h"
+
+/* Exported types ------------------------------------------------------------*/
+/******************************************************************************/
+/* Peripheral registers structures */
+/******************************************************************************/
+
+/*------------------------ Analog to Digital Converter -----------------------*/
+typedef struct
+{
+ vu32 SR;
+ vu32 CR1;
+ vu32 CR2;
+ vu32 SMPR1;
+ vu32 SMPR2;
+ vu32 JOFR1;
+ vu32 JOFR2;
+ vu32 JOFR3;
+ vu32 JOFR4;
+ vu32 HTR;
+ vu32 LTR;
+ vu32 SQR1;
+ vu32 SQR2;
+ vu32 SQR3;
+ vu32 JSQR;
+ vu32 JDR1;
+ vu32 JDR2;
+ vu32 JDR3;
+ vu32 JDR4;
+ vu32 DR;
+} ADC_TypeDef;
+
+/*------------------------ Backup Registers ----------------------------------*/
+typedef struct
+{
+ u32 RESERVED0;
+ vu16 DR1;
+ u16 RESERVED1;
+ vu16 DR2;
+ u16 RESERVED2;
+ vu16 DR3;
+ u16 RESERVED3;
+ vu16 DR4;
+ u16 RESERVED4;
+ vu16 DR5;
+ u16 RESERVED5;
+ vu16 DR6;
+ u16 RESERVED6;
+ vu16 DR7;
+ u16 RESERVED7;
+ vu16 DR8;
+ u16 RESERVED8;
+ vu16 DR9;
+ u16 RESERVED9;
+ vu16 DR10;
+ u16 RESERVED10;
+ vu16 RTCCR;
+ u16 RESERVED11;
+ vu16 CR;
+ u16 RESERVED12;
+ vu16 CSR;
+ u16 RESERVED13[5];
+ vu16 DR11;
+ u16 RESERVED14;
+ vu16 DR12;
+ u16 RESERVED15;
+ vu16 DR13;
+ u16 RESERVED16;
+ vu16 DR14;
+ u16 RESERVED17;
+ vu16 DR15;
+ u16 RESERVED18;
+ vu16 DR16;
+ u16 RESERVED19;
+ vu16 DR17;
+ u16 RESERVED20;
+ vu16 DR18;
+ u16 RESERVED21;
+ vu16 DR19;
+ u16 RESERVED22;
+ vu16 DR20;
+ u16 RESERVED23;
+ vu16 DR21;
+ u16 RESERVED24;
+ vu16 DR22;
+ u16 RESERVED25;
+ vu16 DR23;
+ u16 RESERVED26;
+ vu16 DR24;
+ u16 RESERVED27;
+ vu16 DR25;
+ u16 RESERVED28;
+ vu16 DR26;
+ u16 RESERVED29;
+ vu16 DR27;
+ u16 RESERVED30;
+ vu16 DR28;
+ u16 RESERVED31;
+ vu16 DR29;
+ u16 RESERVED32;
+ vu16 DR30;
+ u16 RESERVED33;
+ vu16 DR31;
+ u16 RESERVED34;
+ vu16 DR32;
+ u16 RESERVED35;
+ vu16 DR33;
+ u16 RESERVED36;
+ vu16 DR34;
+ u16 RESERVED37;
+ vu16 DR35;
+ u16 RESERVED38;
+ vu16 DR36;
+ u16 RESERVED39;
+ vu16 DR37;
+ u16 RESERVED40;
+ vu16 DR38;
+ u16 RESERVED41;
+ vu16 DR39;
+ u16 RESERVED42;
+ vu16 DR40;
+ u16 RESERVED43;
+ vu16 DR41;
+ u16 RESERVED44;
+ vu16 DR42;
+ u16 RESERVED45;
+} BKP_TypeDef;
+
+/*------------------------ Controller Area Network ---------------------------*/
+typedef struct
+{
+ vu32 TIR;
+ vu32 TDTR;
+ vu32 TDLR;
+ vu32 TDHR;
+} CAN_TxMailBox_TypeDef;
+
+typedef struct
+{
+ vu32 RIR;
+ vu32 RDTR;
+ vu32 RDLR;
+ vu32 RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+typedef struct
+{
+ vu32 FR1;
+ vu32 FR2;
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ vu32 MCR;
+ vu32 MSR;
+ vu32 TSR;
+ vu32 RF0R;
+ vu32 RF1R;
+ vu32 IER;
+ vu32 ESR;
+ vu32 BTR;
+ u32 RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ u32 RESERVED1[12];
+ vu32 FMR;
+ vu32 FM1R;
+ u32 RESERVED2;
+ vu32 FS1R;
+ u32 RESERVED3;
+ vu32 FFA1R;
+ u32 RESERVED4;
+ vu32 FA1R;
+ u32 RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/*------------------------ CRC calculation unit ------------------------------*/
+typedef struct
+{
+ vu32 DR;
+ vu8 IDR;
+ u8 RESERVED0;
+ u16 RESERVED1;
+ vu32 CR;
+} CRC_TypeDef;
+
+
+/*------------------------ Digital to Analog Converter -----------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 SWTRIGR;
+ vu32 DHR12R1;
+ vu32 DHR12L1;
+ vu32 DHR8R1;
+ vu32 DHR12R2;
+ vu32 DHR12L2;
+ vu32 DHR8R2;
+ vu32 DHR12RD;
+ vu32 DHR12LD;
+ vu32 DHR8RD;
+ vu32 DOR1;
+ vu32 DOR2;
+} DAC_TypeDef;
+
+/*------------------------ Debug MCU -----------------------------------------*/
+typedef struct
+{
+ vu32 IDCODE;
+ vu32 CR;
+}DBGMCU_TypeDef;
+
+/*------------------------ DMA Controller ------------------------------------*/
+typedef struct
+{
+ vu32 CCR;
+ vu32 CNDTR;
+ vu32 CPAR;
+ vu32 CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ vu32 ISR;
+ vu32 IFCR;
+} DMA_TypeDef;
+
+/*------------------------ External Interrupt/Event Controller ---------------*/
+typedef struct
+{
+ vu32 IMR;
+ vu32 EMR;
+ vu32 RTSR;
+ vu32 FTSR;
+ vu32 SWIER;
+ vu32 PR;
+} EXTI_TypeDef;
+
+/*------------------------ FLASH and Option Bytes Registers ------------------*/
+typedef struct
+{
+ vu32 ACR;
+ vu32 KEYR;
+ vu32 OPTKEYR;
+ vu32 SR;
+ vu32 CR;
+ vu32 AR;
+ vu32 RESERVED;
+ vu32 OBR;
+ vu32 WRPR;
+} FLASH_TypeDef;
+
+typedef struct
+{
+ vu16 RDP;
+ vu16 USER;
+ vu16 Data0;
+ vu16 Data1;
+ vu16 WRP0;
+ vu16 WRP1;
+ vu16 WRP2;
+ vu16 WRP3;
+} OB_TypeDef;
+
+/*------------------------ Flexible Static Memory Controller -----------------*/
+typedef struct
+{
+ vu32 BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+typedef struct
+{
+ vu32 BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+typedef struct
+{
+ vu32 PCR2;
+ vu32 SR2;
+ vu32 PMEM2;
+ vu32 PATT2;
+ u32 RESERVED0;
+ vu32 ECCR2;
+} FSMC_Bank2_TypeDef;
+
+typedef struct
+{
+ vu32 PCR3;
+ vu32 SR3;
+ vu32 PMEM3;
+ vu32 PATT3;
+ u32 RESERVED0;
+ vu32 ECCR3;
+} FSMC_Bank3_TypeDef;
+
+typedef struct
+{
+ vu32 PCR4;
+ vu32 SR4;
+ vu32 PMEM4;
+ vu32 PATT4;
+ vu32 PIO4;
+} FSMC_Bank4_TypeDef;
+
+/*------------------------ General Purpose and Alternate Function IO ---------*/
+typedef struct
+{
+ vu32 CRL;
+ vu32 CRH;
+ vu32 IDR;
+ vu32 ODR;
+ vu32 BSRR;
+ vu32 BRR;
+ vu32 LCKR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+ vu32 EVCR;
+ vu32 MAPR;
+ vu32 EXTICR[4];
+} AFIO_TypeDef;
+
+/*------------------------ Inter-integrated Circuit Interface ----------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 OAR1;
+ u16 RESERVED2;
+ vu16 OAR2;
+ u16 RESERVED3;
+ vu16 DR;
+ u16 RESERVED4;
+ vu16 SR1;
+ u16 RESERVED5;
+ vu16 SR2;
+ u16 RESERVED6;
+ vu16 CCR;
+ u16 RESERVED7;
+ vu16 TRISE;
+ u16 RESERVED8;
+} I2C_TypeDef;
+
+/*------------------------ Independent WATCHDOG ------------------------------*/
+typedef struct
+{
+ vu32 KR;
+ vu32 PR;
+ vu32 RLR;
+ vu32 SR;
+} IWDG_TypeDef;
+
+/*------------------------ Nested Vectored Interrupt Controller --------------*/
+typedef struct
+{
+ vu32 ISER[2];
+ u32 RESERVED0[30];
+ vu32 ICER[2];
+ u32 RSERVED1[30];
+ vu32 ISPR[2];
+ u32 RESERVED2[30];
+ vu32 ICPR[2];
+ u32 RESERVED3[30];
+ vu32 IABR[2];
+ u32 RESERVED4[62];
+ vu32 IPR[15];
+} NVIC_TypeDef;
+
+typedef struct
+{
+ vuc32 CPUID;
+ vu32 ICSR;
+ vu32 VTOR;
+ vu32 AIRCR;
+ vu32 SCR;
+ vu32 CCR;
+ vu32 SHPR[3];
+ vu32 SHCSR;
+ vu32 CFSR;
+ vu32 HFSR;
+ vu32 DFSR;
+ vu32 MMFAR;
+ vu32 BFAR;
+ vu32 AFSR;
+} SCB_TypeDef;
+
+/*------------------------ Power Control -------------------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CSR;
+} PWR_TypeDef;
+
+/*------------------------ Reset and Clock Control ---------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CFGR;
+ vu32 CIR;
+ vu32 APB2RSTR;
+ vu32 APB1RSTR;
+ vu32 AHBENR;
+ vu32 APB2ENR;
+ vu32 APB1ENR;
+ vu32 BDCR;
+ vu32 CSR;
+} RCC_TypeDef;
+
+/*------------------------ Real-Time Clock -----------------------------------*/
+typedef struct
+{
+ vu16 CRH;
+ u16 RESERVED0;
+ vu16 CRL;
+ u16 RESERVED1;
+ vu16 PRLH;
+ u16 RESERVED2;
+ vu16 PRLL;
+ u16 RESERVED3;
+ vu16 DIVH;
+ u16 RESERVED4;
+ vu16 DIVL;
+ u16 RESERVED5;
+ vu16 CNTH;
+ u16 RESERVED6;
+ vu16 CNTL;
+ u16 RESERVED7;
+ vu16 ALRH;
+ u16 RESERVED8;
+ vu16 ALRL;
+ u16 RESERVED9;
+} RTC_TypeDef;
+
+/*------------------------ SD host Interface ---------------------------------*/
+typedef struct
+{
+ vu32 POWER;
+ vu32 CLKCR;
+ vu32 ARG;
+ vu32 CMD;
+ vuc32 RESPCMD;
+ vuc32 RESP1;
+ vuc32 RESP2;
+ vuc32 RESP3;
+ vuc32 RESP4;
+ vu32 DTIMER;
+ vu32 DLEN;
+ vu32 DCTRL;
+ vuc32 DCOUNT;
+ vuc32 STA;
+ vu32 ICR;
+ vu32 MASK;
+ u32 RESERVED0[2];
+ vuc32 FIFOCNT;
+ u32 RESERVED1[13];
+ vu32 FIFO;
+} SDIO_TypeDef;
+
+/*------------------------ Serial Peripheral Interface -----------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SR;
+ u16 RESERVED2;
+ vu16 DR;
+ u16 RESERVED3;
+ vu16 CRCPR;
+ u16 RESERVED4;
+ vu16 RXCRCR;
+ u16 RESERVED5;
+ vu16 TXCRCR;
+ u16 RESERVED6;
+ vu16 I2SCFGR;
+ u16 RESERVED7;
+ vu16 I2SPR;
+ u16 RESERVED8;
+} SPI_TypeDef;
+
+/*------------------------ SystemTick ----------------------------------------*/
+typedef struct
+{
+ vu32 CTRL;
+ vu32 LOAD;
+ vu32 VAL;
+ vuc32 CALIB;
+} SysTick_TypeDef;
+
+/*------------------------ TIM -----------------------------------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SMCR;
+ u16 RESERVED2;
+ vu16 DIER;
+ u16 RESERVED3;
+ vu16 SR;
+ u16 RESERVED4;
+ vu16 EGR;
+ u16 RESERVED5;
+ vu16 CCMR1;
+ u16 RESERVED6;
+ vu16 CCMR2;
+ u16 RESERVED7;
+ vu16 CCER;
+ u16 RESERVED8;
+ vu16 CNT;
+ u16 RESERVED9;
+ vu16 PSC;
+ u16 RESERVED10;
+ vu16 ARR;
+ u16 RESERVED11;
+ vu16 RCR;
+ u16 RESERVED12;
+ vu16 CCR1;
+ u16 RESERVED13;
+ vu16 CCR2;
+ u16 RESERVED14;
+ vu16 CCR3;
+ u16 RESERVED15;
+ vu16 CCR4;
+ u16 RESERVED16;
+ vu16 BDTR;
+ u16 RESERVED17;
+ vu16 DCR;
+ u16 RESERVED18;
+ vu16 DMAR;
+ u16 RESERVED19;
+} TIM_TypeDef;
+
+/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
+typedef struct
+{
+ vu16 SR;
+ u16 RESERVED0;
+ vu16 DR;
+ u16 RESERVED1;
+ vu16 BRR;
+ u16 RESERVED2;
+ vu16 CR1;
+ u16 RESERVED3;
+ vu16 CR2;
+ u16 RESERVED4;
+ vu16 CR3;
+ u16 RESERVED5;
+ vu16 GTPR;
+ u16 RESERVED6;
+} USART_TypeDef;
+
+/*------------------------ Window WATCHDOG -----------------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CFR;
+ vu32 SR;
+} WWDG_TypeDef;
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Peripheral and SRAM base address in the alias region */
+#define PERIPH_BB_BASE ((u32)0x42000000)
+#define SRAM_BB_BASE ((u32)0x22000000)
+
+/* Peripheral and SRAM base address in the bit-band region */
+#define SRAM_BASE ((u32)0x20000000)
+#define PERIPH_BASE ((u32)0x40000000)
+
+/* FSMC registers base address */
+#define FSMC_R_BASE ((u32)0xA0000000)
+
+/* Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+/* Flash registers base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
+/* Flash Option Bytes base address */
+#define OB_BASE ((u32)0x1FFFF800)
+
+/* FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((u32)0xE0042000)
+
+/* System Control Space memory map */
+#define SCS_BASE ((u32)0xE000E000)
+
+#define SysTick_BASE (SCS_BASE + 0x0010)
+#define NVIC_BASE (SCS_BASE + 0x0100)
+#define SCB_BASE (SCS_BASE + 0x0D00)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+/*------------------------ Non Debug Mode ------------------------------------*/
+#ifndef DEBUG
+#ifdef _TIM2
+ #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#endif /*_TIM4 */
+
+#ifdef _TIM5
+ #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#endif /*_TIM5 */
+
+#ifdef _TIM6
+ #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#endif /*_TIM6 */
+
+#ifdef _TIM7
+ #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#endif /*_TIM7 */
+
+#ifdef _RTC
+ #define RTC ((RTC_TypeDef *) RTC_BASE)
+#endif /*_RTC */
+
+#ifdef _WWDG
+ #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#endif /*_WWDG */
+
+#ifdef _IWDG
+ #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#endif /*_IWDG */
+
+#ifdef _SPI2
+ #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#endif /*_SPI2 */
+
+#ifdef _SPI3
+ #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#endif /*_SPI3 */
+
+#ifdef _USART2
+ #define USART2 ((USART_TypeDef *) USART2_BASE)
+#endif /*_USART2 */
+
+#ifdef _USART3
+ #define USART3 ((USART_TypeDef *) USART3_BASE)
+#endif /*_USART3 */
+
+#ifdef _UART4
+ #define UART4 ((USART_TypeDef *) UART4_BASE)
+#endif /*_UART4 */
+
+#ifdef _UART5
+ #define UART5 ((USART_TypeDef *) UART5_BASE)
+#endif /*_USART5 */
+
+#ifdef _I2C1
+ #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#endif /*_I2C2 */
+
+#ifdef _CAN
+ #define CAN ((CAN_TypeDef *) CAN_BASE)
+#endif /*_CAN */
+
+#ifdef _BKP
+ #define BKP ((BKP_TypeDef *) BKP_BASE)
+#endif /*_BKP */
+
+#ifdef _PWR
+ #define PWR ((PWR_TypeDef *) PWR_BASE)
+#endif /*_PWR */
+
+#ifdef _DAC
+ #define DAC ((DAC_TypeDef *) DAC_BASE)
+#endif /*_DAC */
+
+#ifdef _AFIO
+ #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#endif /*_AFIO */
+
+#ifdef _EXTI
+ #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#endif /*_GPIOE */
+
+#ifdef _GPIOF
+ #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#endif /*_GPIOF */
+
+#ifdef _GPIOG
+ #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#endif /*_GPIOG */
+
+#ifdef _ADC1
+ #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+ #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+ #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#endif /*_SPI1 */
+
+#ifdef _TIM8
+ #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#endif /*_TIM8 */
+
+#ifdef _USART1
+ #define USART1 ((USART_TypeDef *) USART1_BASE)
+#endif /*_USART1 */
+
+#ifdef _ADC3
+ #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#endif /*_ADC3 */
+
+#ifdef _SDIO
+ #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#endif /*_SDIO */
+
+#ifdef _DMA
+ #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+ #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#endif /*_DMA */
+
+#ifdef _DMA1_Channel1
+ #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#endif /*_DMA1_Channel1 */
+
+#ifdef _DMA1_Channel2
+ #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#endif /*_DMA1_Channel2 */
+
+#ifdef _DMA1_Channel3
+ #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#endif /*_DMA1_Channel3 */
+
+#ifdef _DMA1_Channel4
+ #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#endif /*_DMA1_Channel4 */
+
+#ifdef _DMA1_Channel5
+ #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#endif /*_DMA1_Channel5 */
+
+#ifdef _DMA1_Channel6
+ #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#endif /*_DMA1_Channel6 */
+
+#ifdef _DMA1_Channel7
+ #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#endif /*_DMA1_Channel7 */
+
+#ifdef _DMA2_Channel1
+ #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#endif /*_DMA2_Channel1 */
+
+#ifdef _DMA2_Channel2
+ #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#endif /*_DMA2_Channel2 */
+
+#ifdef _DMA2_Channel3
+ #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#endif /*_DMA2_Channel3 */
+
+#ifdef _DMA2_Channel4
+ #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#endif /*_DMA2_Channel4 */
+
+#ifdef _DMA2_Channel5
+ #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#endif /*_DMA2_Channel5 */
+
+#ifdef _RCC
+ #define RCC ((RCC_TypeDef *) RCC_BASE)
+#endif /*_RCC */
+
+#ifdef _CRC
+ #define CRC ((CRC_TypeDef *) CRC_BASE)
+#endif /*_CRC */
+
+#ifdef _FLASH
+ #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+ #define OB ((OB_TypeDef *) OB_BASE)
+#endif /*_FLASH */
+
+#ifdef _FSMC
+ #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+ #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+ #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+ #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+ #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#endif /*_FSMC */
+
+#ifdef _DBGMCU
+ #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#endif /*_DBGMCU */
+
+#ifdef _SysTick
+ #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
+#endif /*_SysTick */
+
+#ifdef _NVIC
+ #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
+ #define SCB ((SCB_TypeDef *) SCB_BASE)
+#endif /*_NVIC */
+
+/*------------------------ Debug Mode ----------------------------------------*/
+#else /* DEBUG */
+#ifdef _TIM2
+ EXT TIM_TypeDef *TIM2;
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ EXT TIM_TypeDef *TIM3;
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ EXT TIM_TypeDef *TIM4;
+#endif /*_TIM4 */
+
+#ifdef _TIM5
+ EXT TIM_TypeDef *TIM5;
+#endif /*_TIM5 */
+
+#ifdef _TIM6
+ EXT TIM_TypeDef *TIM6;
+#endif /*_TIM6 */
+
+#ifdef _TIM7
+ EXT TIM_TypeDef *TIM7;
+#endif /*_TIM7 */
+
+#ifdef _RTC
+ EXT RTC_TypeDef *RTC;
+#endif /*_RTC */
+
+#ifdef _WWDG
+ EXT WWDG_TypeDef *WWDG;
+#endif /*_WWDG */
+
+#ifdef _IWDG
+ EXT IWDG_TypeDef *IWDG;
+#endif /*_IWDG */
+
+#ifdef _SPI2
+ EXT SPI_TypeDef *SPI2;
+#endif /*_SPI2 */
+
+#ifdef _SPI3
+ EXT SPI_TypeDef *SPI3;
+#endif /*_SPI3 */
+
+#ifdef _USART2
+ EXT USART_TypeDef *USART2;
+#endif /*_USART2 */
+
+#ifdef _USART3
+ EXT USART_TypeDef *USART3;
+#endif /*_USART3 */
+
+#ifdef _UART4
+ EXT USART_TypeDef *UART4;
+#endif /*_UART4 */
+
+#ifdef _UART5
+ EXT USART_TypeDef *UART5;
+#endif /*_UART5 */
+
+#ifdef _I2C1
+ EXT I2C_TypeDef *I2C1;
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ EXT I2C_TypeDef *I2C2;
+#endif /*_I2C2 */
+
+#ifdef _CAN
+ EXT CAN_TypeDef *CAN;
+#endif /*_CAN */
+
+#ifdef _BKP
+ EXT BKP_TypeDef *BKP;
+#endif /*_BKP */
+
+#ifdef _PWR
+ EXT PWR_TypeDef *PWR;
+#endif /*_PWR */
+
+#ifdef _DAC
+ EXT DAC_TypeDef *DAC;
+#endif /*_DAC */
+
+#ifdef _AFIO
+ EXT AFIO_TypeDef *AFIO;
+#endif /*_AFIO */
+
+#ifdef _EXTI
+ EXT EXTI_TypeDef *EXTI;
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+ EXT GPIO_TypeDef *GPIOA;
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ EXT GPIO_TypeDef *GPIOB;
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ EXT GPIO_TypeDef *GPIOC;
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ EXT GPIO_TypeDef *GPIOD;
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ EXT GPIO_TypeDef *GPIOE;
+#endif /*_GPIOE */
+
+#ifdef _GPIOF
+ EXT GPIO_TypeDef *GPIOF;
+#endif /*_GPIOF */
+
+#ifdef _GPIOG
+ EXT GPIO_TypeDef *GPIOG;
+#endif /*_GPIOG */
+
+#ifdef _ADC1
+ EXT ADC_TypeDef *ADC1;
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ EXT ADC_TypeDef *ADC2;
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+ EXT TIM_TypeDef *TIM1;
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+ EXT SPI_TypeDef *SPI1;
+#endif /*_SPI1 */
+
+#ifdef _TIM8
+ EXT TIM_TypeDef *TIM8;
+#endif /*_TIM8 */
+
+#ifdef _USART1
+ EXT USART_TypeDef *USART1;
+#endif /*_USART1 */
+
+#ifdef _ADC3
+ EXT ADC_TypeDef *ADC3;
+#endif /*_ADC3 */
+
+#ifdef _SDIO
+ EXT SDIO_TypeDef *SDIO;
+#endif /*_SDIO */
+
+#ifdef _DMA
+ EXT DMA_TypeDef *DMA1;
+ EXT DMA_TypeDef *DMA2;
+#endif /*_DMA */
+
+#ifdef _DMA1_Channel1
+ EXT DMA_Channel_TypeDef *DMA1_Channel1;
+#endif /*_DMA1_Channel1 */
+
+#ifdef _DMA1_Channel2
+ EXT DMA_Channel_TypeDef *DMA1_Channel2;
+#endif /*_DMA1_Channel2 */
+
+#ifdef _DMA1_Channel3
+ EXT DMA_Channel_TypeDef *DMA1_Channel3;
+#endif /*_DMA1_Channel3 */
+
+#ifdef _DMA1_Channel4
+ EXT DMA_Channel_TypeDef *DMA1_Channel4;
+#endif /*_DMA1_Channel4 */
+
+#ifdef _DMA1_Channel5
+ EXT DMA_Channel_TypeDef *DMA1_Channel5;
+#endif /*_DMA1_Channel5 */
+
+#ifdef _DMA1_Channel6
+ EXT DMA_Channel_TypeDef *DMA1_Channel6;
+#endif /*_DMA1_Channel6 */
+
+#ifdef _DMA1_Channel7
+ EXT DMA_Channel_TypeDef *DMA1_Channel7;
+#endif /*_DMA1_Channel7 */
+
+#ifdef _DMA2_Channel1
+ EXT DMA_Channel_TypeDef *DMA2_Channel1;
+#endif /*_DMA2_Channel1 */
+
+#ifdef _DMA2_Channel2
+ EXT DMA_Channel_TypeDef *DMA2_Channel2;
+#endif /*_DMA2_Channel2 */
+
+#ifdef _DMA2_Channel3
+ EXT DMA_Channel_TypeDef *DMA2_Channel3;
+#endif /*_DMA2_Channel3 */
+
+#ifdef _DMA2_Channel4
+ EXT DMA_Channel_TypeDef *DMA2_Channel4;
+#endif /*_DMA2_Channel4 */
+
+#ifdef _DMA2_Channel5
+ EXT DMA_Channel_TypeDef *DMA2_Channel5;
+#endif /*_DMA2_Channel5 */
+
+#ifdef _RCC
+ EXT RCC_TypeDef *RCC;
+#endif /*_RCC */
+
+#ifdef _CRC
+ EXT CRC_TypeDef *CRC;
+#endif /*_CRC */
+
+#ifdef _FLASH
+ EXT FLASH_TypeDef *FLASH;
+ EXT OB_TypeDef *OB;
+#endif /*_FLASH */
+
+#ifdef _FSMC
+ EXT FSMC_Bank1_TypeDef *FSMC_Bank1;
+ EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E;
+ EXT FSMC_Bank2_TypeDef *FSMC_Bank2;
+ EXT FSMC_Bank3_TypeDef *FSMC_Bank3;
+ EXT FSMC_Bank4_TypeDef *FSMC_Bank4;
+#endif /*_FSMC */
+
+#ifdef _DBGMCU
+ EXT DBGMCU_TypeDef *DBGMCU;
+#endif /*_DBGMCU */
+
+#ifdef _SysTick
+ EXT SysTick_TypeDef *SysTick;
+#endif /*_SysTick */
+
+#ifdef _NVIC
+ EXT NVIC_TypeDef *NVIC;
+ EXT SCB_TypeDef *SCB;
+#endif /*_NVIC */
+
+#endif /* DEBUG */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_MAP_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_nvic.h b/src/stm32lib/inc/stm32f10x_nvic.h new file mode 100644 index 0000000..6a9815b --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_nvic.h @@ -0,0 +1,293 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_nvic.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* NVIC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_NVIC_H
+#define __STM32F10x_NVIC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* NVIC Init Structure definition */
+typedef struct
+{
+ u8 NVIC_IRQChannel;
+ u8 NVIC_IRQChannelPreemptionPriority;
+ u8 NVIC_IRQChannelSubPriority;
+ FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* IRQ Channels --------------------------------------------------------------*/
+#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
+#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
+#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
+#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
+#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
+#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
+#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
+#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
+#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
+#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
+#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
+#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
+#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
+#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
+#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
+#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
+#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
+#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
+#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
+#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
+#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
+#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
+#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
+#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
+#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
+#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
+#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
+#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
+#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
+#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
+#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
+#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
+#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
+#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
+#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
+#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
+#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
+#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
+#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
+#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
+#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
+#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
+#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
+#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
+#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
+#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
+#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
+#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
+#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
+#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
+#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
+#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
+#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
+#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
+#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
+#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
+#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
+#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
+#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
+#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
+
+
+#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
+ ((CHANNEL) == PVD_IRQChannel) || \
+ ((CHANNEL) == TAMPER_IRQChannel) || \
+ ((CHANNEL) == RTC_IRQChannel) || \
+ ((CHANNEL) == FLASH_IRQChannel) || \
+ ((CHANNEL) == RCC_IRQChannel) || \
+ ((CHANNEL) == EXTI0_IRQChannel) || \
+ ((CHANNEL) == EXTI1_IRQChannel) || \
+ ((CHANNEL) == EXTI2_IRQChannel) || \
+ ((CHANNEL) == EXTI3_IRQChannel) || \
+ ((CHANNEL) == EXTI4_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel1_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel2_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel3_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel4_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel5_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel6_IRQChannel) || \
+ ((CHANNEL) == DMA1_Channel7_IRQChannel) || \
+ ((CHANNEL) == ADC1_2_IRQChannel) || \
+ ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
+ ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
+ ((CHANNEL) == CAN_RX1_IRQChannel) || \
+ ((CHANNEL) == CAN_SCE_IRQChannel) || \
+ ((CHANNEL) == EXTI9_5_IRQChannel) || \
+ ((CHANNEL) == TIM1_BRK_IRQChannel) || \
+ ((CHANNEL) == TIM1_UP_IRQChannel) || \
+ ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
+ ((CHANNEL) == TIM1_CC_IRQChannel) || \
+ ((CHANNEL) == TIM2_IRQChannel) || \
+ ((CHANNEL) == TIM3_IRQChannel) || \
+ ((CHANNEL) == TIM4_IRQChannel) || \
+ ((CHANNEL) == I2C1_EV_IRQChannel) || \
+ ((CHANNEL) == I2C1_ER_IRQChannel) || \
+ ((CHANNEL) == I2C2_EV_IRQChannel) || \
+ ((CHANNEL) == I2C2_ER_IRQChannel) || \
+ ((CHANNEL) == SPI1_IRQChannel) || \
+ ((CHANNEL) == SPI2_IRQChannel) || \
+ ((CHANNEL) == USART1_IRQChannel) || \
+ ((CHANNEL) == USART2_IRQChannel) || \
+ ((CHANNEL) == USART3_IRQChannel) || \
+ ((CHANNEL) == EXTI15_10_IRQChannel) || \
+ ((CHANNEL) == RTCAlarm_IRQChannel) || \
+ ((CHANNEL) == USBWakeUp_IRQChannel) || \
+ ((CHANNEL) == TIM8_BRK_IRQChannel) || \
+ ((CHANNEL) == TIM8_UP_IRQChannel) || \
+ ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
+ ((CHANNEL) == TIM8_CC_IRQChannel) || \
+ ((CHANNEL) == ADC3_IRQChannel) || \
+ ((CHANNEL) == FSMC_IRQChannel) || \
+ ((CHANNEL) == SDIO_IRQChannel) || \
+ ((CHANNEL) == TIM5_IRQChannel) || \
+ ((CHANNEL) == SPI3_IRQChannel) || \
+ ((CHANNEL) == UART4_IRQChannel) || \
+ ((CHANNEL) == UART5_IRQChannel) || \
+ ((CHANNEL) == TIM6_IRQChannel) || \
+ ((CHANNEL) == TIM7_IRQChannel) || \
+ ((CHANNEL) == DMA2_Channel1_IRQChannel) || \
+ ((CHANNEL) == DMA2_Channel2_IRQChannel) || \
+ ((CHANNEL) == DMA2_Channel3_IRQChannel) || \
+ ((CHANNEL) == DMA2_Channel4_5_IRQChannel))
+
+
+/* System Handlers -----------------------------------------------------------*/
+#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
+#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
+#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
+#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
+#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
+#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
+#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
+#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
+#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
+
+#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
+ ((HANDLER) == SystemHandler_BusFault) || \
+ ((HANDLER) == SystemHandler_UsageFault))
+
+#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
+ ((HANDLER) == SystemHandler_BusFault) || \
+ ((HANDLER) == SystemHandler_UsageFault) || \
+ ((HANDLER) == SystemHandler_SVCall) || \
+ ((HANDLER) == SystemHandler_DebugMonitor) || \
+ ((HANDLER) == SystemHandler_PSV) || \
+ ((HANDLER) == SystemHandler_SysTick))
+
+#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
+ ((HANDLER) == SystemHandler_BusFault) || \
+ ((HANDLER) == SystemHandler_SVCall))
+
+#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
+ ((HANDLER) == SystemHandler_PSV) || \
+ ((HANDLER) == SystemHandler_SysTick))
+
+#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
+ ((HANDLER) == SystemHandler_SysTick))
+
+#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
+ ((HANDLER) == SystemHandler_BusFault) || \
+ ((HANDLER) == SystemHandler_UsageFault) || \
+ ((HANDLER) == SystemHandler_SVCall) || \
+ ((HANDLER) == SystemHandler_DebugMonitor) || \
+ ((HANDLER) == SystemHandler_PSV) || \
+ ((HANDLER) == SystemHandler_SysTick))
+
+#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
+ ((HANDLER) == SystemHandler_MemoryManage) || \
+ ((HANDLER) == SystemHandler_BusFault) || \
+ ((HANDLER) == SystemHandler_UsageFault) || \
+ ((HANDLER) == SystemHandler_DebugMonitor))
+
+#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
+ ((HANDLER) == SystemHandler_BusFault))
+
+
+/* Vector Table Base ---------------------------------------------------------*/
+#define NVIC_VectTab_RAM ((u32)0x20000000)
+#define NVIC_VectTab_FLASH ((u32)0x08000000)
+
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+
+/* System Low Power ----------------------------------------------------------*/
+#define NVIC_LP_SEVONPEND ((u8)0x10)
+#define NVIC_LP_SLEEPDEEP ((u8)0x04)
+#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
+
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+
+/* Preemption Priority Group -------------------------------------------------*/
+#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
+#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+void NVIC_DeInit(void);
+void NVIC_SCBDeInit(void);
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SETPRIMASK(void);
+void NVIC_RESETPRIMASK(void);
+void NVIC_SETFAULTMASK(void);
+void NVIC_RESETFAULTMASK(void);
+void NVIC_BASEPRICONFIG(u32 NewPriority);
+u32 NVIC_GetBASEPRI(void);
+u16 NVIC_GetCurrentPendingIRQChannel(void);
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
+u16 NVIC_GetCurrentActiveHandler(void);
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
+u32 NVIC_GetCPUID(void);
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
+void NVIC_GenerateSystemReset(void);
+void NVIC_GenerateCoreReset(void);
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
+ u8 SystemHandlerSubPriority);
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
+u32 NVIC_GetFaultAddress(u32 SystemHandler);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_NVIC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_pwr.h b/src/stm32lib/inc/stm32f10x_pwr.h new file mode 100644 index 0000000..ffcc438 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_pwr.h @@ -0,0 +1,77 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_pwr.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* PWR firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* PVD detection level */
+#define PWR_PVDLevel_2V2 ((u32)0x00000000)
+#define PWR_PVDLevel_2V3 ((u32)0x00000020)
+#define PWR_PVDLevel_2V4 ((u32)0x00000040)
+#define PWR_PVDLevel_2V5 ((u32)0x00000060)
+#define PWR_PVDLevel_2V6 ((u32)0x00000080)
+#define PWR_PVDLevel_2V7 ((u32)0x000000A0)
+#define PWR_PVDLevel_2V8 ((u32)0x000000C0)
+#define PWR_PVDLevel_2V9 ((u32)0x000000E0)
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+
+/* Regulator state is STOP mode */
+#define PWR_Regulator_ON ((u32)0x00000000)
+#define PWR_Regulator_LowPower ((u32)0x00000001)
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+
+/* STOP mode entry */
+#define PWR_STOPEntry_WFI ((u8)0x01)
+#define PWR_STOPEntry_WFE ((u8)0x02)
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/* PWR Flag */
+#define PWR_FLAG_WU ((u32)0x00000001)
+#define PWR_FLAG_SB ((u32)0x00000002)
+#define PWR_FLAG_PVDO ((u32)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO))
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);
+void PWR_ClearFlag(u32 PWR_FLAG);
+
+#endif /* __STM32F10x_PWR_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_rcc.h b/src/stm32lib/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..f0c39d7 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_rcc.h @@ -0,0 +1,295 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_rcc.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* RCC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+ u32 SYSCLK_Frequency;
+ u32 HCLK_Frequency;
+ u32 PCLK1_Frequency;
+ u32 PCLK2_Frequency;
+ u32 ADCCLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* HSE configuration */
+#define RCC_HSE_OFF ((u32)0x00000000)
+#define RCC_HSE_ON ((u32)0x00010000)
+#define RCC_HSE_Bypass ((u32)0x00040000)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/* PLL entry clock source */
+#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
+#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
+#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
+
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))
+
+/* PLL multiplication factor */
+#define RCC_PLLMul_2 ((u32)0x00000000)
+#define RCC_PLLMul_3 ((u32)0x00040000)
+#define RCC_PLLMul_4 ((u32)0x00080000)
+#define RCC_PLLMul_5 ((u32)0x000C0000)
+#define RCC_PLLMul_6 ((u32)0x00100000)
+#define RCC_PLLMul_7 ((u32)0x00140000)
+#define RCC_PLLMul_8 ((u32)0x00180000)
+#define RCC_PLLMul_9 ((u32)0x001C0000)
+#define RCC_PLLMul_10 ((u32)0x00200000)
+#define RCC_PLLMul_11 ((u32)0x00240000)
+#define RCC_PLLMul_12 ((u32)0x00280000)
+#define RCC_PLLMul_13 ((u32)0x002C0000)
+#define RCC_PLLMul_14 ((u32)0x00300000)
+#define RCC_PLLMul_15 ((u32)0x00340000)
+#define RCC_PLLMul_16 ((u32)0x00380000)
+
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+
+/* System clock source */
+#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
+#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
+
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+
+/* AHB clock source */
+#define RCC_SYSCLK_Div1 ((u32)0x00000000)
+#define RCC_SYSCLK_Div2 ((u32)0x00000080)
+#define RCC_SYSCLK_Div4 ((u32)0x00000090)
+#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
+#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
+#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
+#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
+#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
+#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+
+/* APB1/APB2 clock source */
+#define RCC_HCLK_Div1 ((u32)0x00000000)
+#define RCC_HCLK_Div2 ((u32)0x00000400)
+#define RCC_HCLK_Div4 ((u32)0x00000500)
+#define RCC_HCLK_Div8 ((u32)0x00000600)
+#define RCC_HCLK_Div16 ((u32)0x00000700)
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+
+/* RCC Interrupt source */
+#define RCC_IT_LSIRDY ((u8)0x01)
+#define RCC_IT_LSERDY ((u8)0x02)
+#define RCC_IT_HSIRDY ((u8)0x04)
+#define RCC_IT_HSERDY ((u8)0x08)
+#define RCC_IT_PLLRDY ((u8)0x10)
+#define RCC_IT_CSS ((u8)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))
+
+/* USB clock source */
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
+
+#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+
+/* ADC clock source */
+#define RCC_PCLK2_Div2 ((u32)0x00000000)
+#define RCC_PCLK2_Div4 ((u32)0x00004000)
+#define RCC_PCLK2_Div6 ((u32)0x00008000)
+#define RCC_PCLK2_Div8 ((u32)0x0000C000)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+
+/* LSE configuration */
+#define RCC_LSE_OFF ((u8)0x00)
+#define RCC_LSE_ON ((u8)0x01)
+#define RCC_LSE_Bypass ((u8)0x04)
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+
+/* RTC clock source */
+#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
+#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+
+/* AHB peripheral */
+#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)
+#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
+#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
+#define RCC_AHBPeriph_CRC ((u32)0x00000040)
+#define RCC_AHBPeriph_FSMC ((u32)0x00000100)
+#define RCC_AHBPeriph_SDIO ((u32)0x00000400)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+
+/* APB2 peripheral */
+#define RCC_APB2Periph_AFIO ((u32)0x00000001)
+#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
+#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
+#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
+#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
+#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
+#define RCC_APB2Periph_GPIOF ((u32)0x00000080)
+#define RCC_APB2Periph_GPIOG ((u32)0x00000100)
+#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
+#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
+#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
+#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
+#define RCC_APB2Periph_TIM8 ((u32)0x00002000)
+#define RCC_APB2Periph_USART1 ((u32)0x00004000)
+#define RCC_APB2Periph_ADC3 ((u32)0x00008000)
+#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
+
+/* APB1 peripheral */
+#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
+#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
+#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
+#define RCC_APB1Periph_TIM5 ((u32)0x00000008)
+#define RCC_APB1Periph_TIM6 ((u32)0x00000010)
+#define RCC_APB1Periph_TIM7 ((u32)0x00000020)
+#define RCC_APB1Periph_WWDG ((u32)0x00000800)
+#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
+#define RCC_APB1Periph_SPI3 ((u32)0x00008000)
+#define RCC_APB1Periph_USART2 ((u32)0x00020000)
+#define RCC_APB1Periph_USART3 ((u32)0x00040000)
+#define RCC_APB1Periph_UART4 ((u32)0x00080000)
+#define RCC_APB1Periph_UART5 ((u32)0x00100000)
+#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
+#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
+#define RCC_APB1Periph_USB ((u32)0x00800000)
+#define RCC_APB1Periph_CAN ((u32)0x02000000)
+#define RCC_APB1Periph_BKP ((u32)0x08000000)
+#define RCC_APB1Periph_PWR ((u32)0x10000000)
+#define RCC_APB1Periph_DAC ((u32)0x20000000)
+#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
+
+/* Clock source to output on MCO pin */
+#define RCC_MCO_NoClock ((u8)0x00)
+#define RCC_MCO_SYSCLK ((u8)0x04)
+#define RCC_MCO_HSI ((u8)0x05)
+#define RCC_MCO_HSE ((u8)0x06)
+#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
+
+#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2))
+
+/* RCC Flag */
+#define RCC_FLAG_HSIRDY ((u8)0x20)
+#define RCC_FLAG_HSERDY ((u8)0x31)
+#define RCC_FLAG_PLLRDY ((u8)0x39)
+#define RCC_FLAG_LSERDY ((u8)0x41)
+#define RCC_FLAG_LSIRDY ((u8)0x61)
+#define RCC_FLAG_PINRST ((u8)0x7A)
+#define RCC_FLAG_PORRST ((u8)0x7B)
+#define RCC_FLAG_SFTRST ((u8)0x7C)
+#define RCC_FLAG_IWDGRST ((u8)0x7D)
+#define RCC_FLAG_WWDGRST ((u8)0x7E)
+#define RCC_FLAG_LPWRRST ((u8)0x7F)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(u32 RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
+u8 RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(u32 RCC_SYSCLK);
+void RCC_PCLK1Config(u32 RCC_HCLK);
+void RCC_PCLK2Config(u32 RCC_HCLK);
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
+void RCC_ADCCLKConfig(u32 RCC_PCLK2);
+void RCC_LSEConfig(u8 RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(u8 RCC_MCO);
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(u8 RCC_IT);
+void RCC_ClearITPendingBit(u8 RCC_IT);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RCC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_rtc.h b/src/stm32lib/inc/stm32f10x_rtc.h new file mode 100644 index 0000000..6ea7b78 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_rtc.h @@ -0,0 +1,70 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_rtc.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* RTC firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* RTC interrupts define -----------------------------------------------------*/
+#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */
+#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */
+#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */
+
+#define IS_RTC_IT(IT) ((((IT) & (u16)0xFFF8) == 0x00) && ((IT) != 0x00))
+
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+ ((IT) == RTC_IT_SEC))
+
+/* RTC interrupts flags ------------------------------------------------------*/
+#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */
+#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */
+#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */
+#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */
+
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+ ((FLAG) == RTC_FLAG_SEC))
+
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+u32 RTC_GetCounter(void);
+void RTC_SetCounter(u32 CounterValue);
+void RTC_SetPrescaler(u32 PrescalerValue);
+void RTC_SetAlarm(u32 AlarmValue);
+u32 RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);
+void RTC_ClearFlag(u16 RTC_FLAG);
+ITStatus RTC_GetITStatus(u16 RTC_IT);
+void RTC_ClearITPendingBit(u16 RTC_IT);
+
+#endif /* __STM32F10x_RTC_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_sdio.h b/src/stm32lib/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..27f74f7 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_sdio.h @@ -0,0 +1,337 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_sdio.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* SDIO firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+ u8 SDIO_ClockDiv;
+ u32 SDIO_ClockEdge;
+ u32 SDIO_ClockBypass;
+ u32 SDIO_ClockPowerSave;
+ u32 SDIO_BusWide;
+ u32 SDIO_HardwareFlowControl;
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+ u32 SDIO_Argument;
+ u32 SDIO_CmdIndex;
+ u32 SDIO_Response;
+ u32 SDIO_Wait;
+ u32 SDIO_CPSM;
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+ u32 SDIO_DataTimeOut;
+ u32 SDIO_DataLength;
+ u32 SDIO_DataBlockSize;
+ u32 SDIO_TransferDir;
+ u32 SDIO_TransferMode;
+ u32 SDIO_DPSM;
+} SDIO_DataInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* SDIO Clock Edge -----------------------------------------------------------*/
+#define SDIO_ClockEdge_Rising ((u32)0x00000000)
+#define SDIO_ClockEdge_Falling ((u32)0x00002000)
+
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+ ((EDGE) == SDIO_ClockEdge_Falling))
+/* SDIO Clock Bypass ----------------------------------------------------------*/
+#define SDIO_ClockBypass_Disable ((u32)0x00000000)
+#define SDIO_ClockBypass_Enable ((u32)0x00000400)
+
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+ ((BYPASS) == SDIO_ClockBypass_Enable))
+
+/* SDIO Clock Power Save ----------------------------------------------------*/
+#define SDIO_ClockPowerSave_Disable ((u32)0x00000000)
+#define SDIO_ClockPowerSave_Enable ((u32)0x00000200)
+
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+ ((SAVE) == SDIO_ClockPowerSave_Enable))
+
+/* SDIO Bus Wide -------------------------------------------------------------*/
+#define SDIO_BusWide_1b ((u32)0x00000000)
+#define SDIO_BusWide_4b ((u32)0x00000800)
+#define SDIO_BusWide_8b ((u32)0x00001000)
+
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+ ((WIDE) == SDIO_BusWide_8b))
+
+/* SDIO Hardware Flow Control -----------------------------------------------*/
+#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000)
+#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000)
+
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+
+/* SDIO Power State ----------------------------------------------------------*/
+#define SDIO_PowerState_OFF ((u32)0x00000000)
+#define SDIO_PowerState_ON ((u32)0x00000003)
+
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+
+/* SDIO Interrupt soucres ----------------------------------------------------*/
+#define SDIO_IT_CCRCFAIL ((u32)0x00000001)
+#define SDIO_IT_DCRCFAIL ((u32)0x00000002)
+#define SDIO_IT_CTIMEOUT ((u32)0x00000004)
+#define SDIO_IT_DTIMEOUT ((u32)0x00000008)
+#define SDIO_IT_TXUNDERR ((u32)0x00000010)
+#define SDIO_IT_RXOVERR ((u32)0x00000020)
+#define SDIO_IT_CMDREND ((u32)0x00000040)
+#define SDIO_IT_CMDSENT ((u32)0x00000080)
+#define SDIO_IT_DATAEND ((u32)0x00000100)
+#define SDIO_IT_STBITERR ((u32)0x00000200)
+#define SDIO_IT_DBCKEND ((u32)0x00000400)
+#define SDIO_IT_CMDACT ((u32)0x00000800)
+#define SDIO_IT_TXACT ((u32)0x00001000)
+#define SDIO_IT_RXACT ((u32)0x00002000)
+#define SDIO_IT_TXFIFOHE ((u32)0x00004000)
+#define SDIO_IT_RXFIFOHF ((u32)0x00008000)
+#define SDIO_IT_TXFIFOF ((u32)0x00010000)
+#define SDIO_IT_RXFIFOF ((u32)0x00020000)
+#define SDIO_IT_TXFIFOE ((u32)0x00040000)
+#define SDIO_IT_RXFIFOE ((u32)0x00080000)
+#define SDIO_IT_TXDAVL ((u32)0x00100000)
+#define SDIO_IT_RXDAVL ((u32)0x00200000)
+#define SDIO_IT_SDIOIT ((u32)0x00400000)
+#define SDIO_IT_CEATAEND ((u32)0x00800000)
+
+#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00))
+
+/* SDIO Command Index -------------------------------------------------------*/
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+
+/* SDIO Response Type --------------------------------------------------------*/
+#define SDIO_Response_No ((u32)0x00000000)
+#define SDIO_Response_Short ((u32)0x00000040)
+#define SDIO_Response_Long ((u32)0x000000C0)
+
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+ ((RESPONSE) == SDIO_Response_Short) || \
+ ((RESPONSE) == SDIO_Response_Long))
+
+/* SDIO Wait Interrupt State -------------------------------------------------*/
+#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */
+
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+ ((WAIT) == SDIO_Wait_Pend))
+
+/* SDIO CPSM State -----------------------------------------------------------*/
+#define SDIO_CPSM_Disable ((u32)0x00000000)
+#define SDIO_CPSM_Enable ((u32)0x00000400)
+
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+
+/* SDIO Response Registers ---------------------------------------------------*/
+#define SDIO_RESP1 ((u32)0x00000000)
+#define SDIO_RESP2 ((u32)0x00000004)
+#define SDIO_RESP3 ((u32)0x00000008)
+#define SDIO_RESP4 ((u32)0x0000000C)
+
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+
+/* SDIO Data Length ----------------------------------------------------------*/
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+
+/* SDIO Data Block Size ------------------------------------------------------*/
+#define SDIO_DataBlockSize_1b ((u32)0x00000000)
+#define SDIO_DataBlockSize_2b ((u32)0x00000010)
+#define SDIO_DataBlockSize_4b ((u32)0x00000020)
+#define SDIO_DataBlockSize_8b ((u32)0x00000030)
+#define SDIO_DataBlockSize_16b ((u32)0x00000040)
+#define SDIO_DataBlockSize_32b ((u32)0x00000050)
+#define SDIO_DataBlockSize_64b ((u32)0x00000060)
+#define SDIO_DataBlockSize_128b ((u32)0x00000070)
+#define SDIO_DataBlockSize_256b ((u32)0x00000080)
+#define SDIO_DataBlockSize_512b ((u32)0x00000090)
+#define SDIO_DataBlockSize_1024b ((u32)0x000000A0)
+#define SDIO_DataBlockSize_2048b ((u32)0x000000B0)
+#define SDIO_DataBlockSize_4096b ((u32)0x000000C0)
+#define SDIO_DataBlockSize_8192b ((u32)0x000000D0)
+#define SDIO_DataBlockSize_16384b ((u32)0x000000E0)
+
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+ ((SIZE) == SDIO_DataBlockSize_2b) || \
+ ((SIZE) == SDIO_DataBlockSize_4b) || \
+ ((SIZE) == SDIO_DataBlockSize_8b) || \
+ ((SIZE) == SDIO_DataBlockSize_16b) || \
+ ((SIZE) == SDIO_DataBlockSize_32b) || \
+ ((SIZE) == SDIO_DataBlockSize_64b) || \
+ ((SIZE) == SDIO_DataBlockSize_128b) || \
+ ((SIZE) == SDIO_DataBlockSize_256b) || \
+ ((SIZE) == SDIO_DataBlockSize_512b) || \
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \
+ ((SIZE) == SDIO_DataBlockSize_16384b))
+
+/* SDIO Transfer Direction ---------------------------------------------------*/
+#define SDIO_TransferDir_ToCard ((u32)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
+
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+ ((DIR) == SDIO_TransferDir_ToSDIO))
+
+/* SDIO Transfer Type --------------------------------------------------------*/
+#define SDIO_TransferMode_Block ((u32)0x00000000)
+#define SDIO_TransferMode_Stream ((u32)0x00000004)
+
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+ ((MODE) == SDIO_TransferMode_Block))
+
+/* SDIO DPSM State -----------------------------------------------------------*/
+#define SDIO_DPSM_Disable ((u32)0x00000000)
+#define SDIO_DPSM_Enable ((u32)0x00000001)
+
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+
+/* SDIO Flags ----------------------------------------------------------------*/
+#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
+#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
+#define SDIO_FLAG_CMDREND ((u32)0x00000040)
+#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
+#define SDIO_FLAG_DATAEND ((u32)0x00000100)
+#define SDIO_FLAG_STBITERR ((u32)0x00000200)
+#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
+#define SDIO_FLAG_CMDACT ((u32)0x00000800)
+#define SDIO_FLAG_TXACT ((u32)0x00001000)
+#define SDIO_FLAG_RXACT ((u32)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
+#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
+#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
+#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
+#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
+
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00))
+
+/* SDIO Read Wait Mode -------------------------------------------------------*/
+#define SDIO_ReadWaitMode_CLK ((u32)0x00000000)
+#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001)
+
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+ ((MODE) == SDIO_ReadWaitMode_DATA2))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(u32 SDIO_PowerState);
+u32 SDIO_GetPowerState(void);
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+u8 SDIO_GetCommandResponse(void);
+u32 SDIO_GetResponse(u32 SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+u32 SDIO_GetDataCounter(void);
+u32 SDIO_ReadData(void);
+void SDIO_WriteData(u32 Data);
+u32 SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
+void SDIO_ClearFlag(u32 SDIO_FLAG);
+ITStatus SDIO_GetITStatus(u32 SDIO_IT);
+void SDIO_ClearITPendingBit(u32 SDIO_IT);
+
+#endif /* __STM32F10x_SDIO_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_spi.h b/src/stm32lib/inc/stm32f10x_spi.h new file mode 100644 index 0000000..b39817c --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_spi.h @@ -0,0 +1,289 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_spi.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* SPI firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* SPI Init structure definition */
+typedef struct
+{
+ u16 SPI_Direction;
+ u16 SPI_Mode;
+ u16 SPI_DataSize;
+ u16 SPI_CPOL;
+ u16 SPI_CPHA;
+ u16 SPI_NSS;
+ u16 SPI_BaudRatePrescaler;
+ u16 SPI_FirstBit;
+ u16 SPI_CRCPolynomial;
+}SPI_InitTypeDef;
+
+/* I2S Init structure definition */
+typedef struct
+{
+ u16 I2S_Mode;
+ u16 I2S_Standard;
+ u16 I2S_DataFormat;
+ u16 I2S_MCLKOutput;
+ u16 I2S_AudioFreq;
+ u16 I2S_CPOL;
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \
+ ((*(u32*)&(PERIPH)) == SPI2_BASE) || \
+ ((*(u32*)&(PERIPH)) == SPI3_BASE))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \
+ ((*(u32*)&(PERIPH)) == SPI3_BASE))
+
+/* SPI data direction mode */
+#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)
+#define SPI_Direction_1Line_Rx ((u16)0x8000)
+#define SPI_Direction_1Line_Tx ((u16)0xC000)
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+
+/* SPI master/slave mode */
+#define SPI_Mode_Master ((u16)0x0104)
+#define SPI_Mode_Slave ((u16)0x0000)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+
+/* SPI data size */
+#define SPI_DataSize_16b ((u16)0x0800)
+#define SPI_DataSize_8b ((u16)0x0000)
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+ ((DATASIZE) == SPI_DataSize_8b))
+
+/* SPI Clock Polarity */
+#define SPI_CPOL_Low ((u16)0x0000)
+#define SPI_CPOL_High ((u16)0x0002)
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+
+/* SPI Clock Phase */
+#define SPI_CPHA_1Edge ((u16)0x0000)
+#define SPI_CPHA_2Edge ((u16)0x0001)
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+
+/* SPI Slave Select management */
+#define SPI_NSS_Soft ((u16)0x0200)
+#define SPI_NSS_Hard ((u16)0x0000)
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+
+/* SPI BaudRate Prescaler */
+#define SPI_BaudRatePrescaler_2 ((u16)0x0000)
+#define SPI_BaudRatePrescaler_4 ((u16)0x0008)
+#define SPI_BaudRatePrescaler_8 ((u16)0x0010)
+#define SPI_BaudRatePrescaler_16 ((u16)0x0018)
+#define SPI_BaudRatePrescaler_32 ((u16)0x0020)
+#define SPI_BaudRatePrescaler_64 ((u16)0x0028)
+#define SPI_BaudRatePrescaler_128 ((u16)0x0030)
+#define SPI_BaudRatePrescaler_256 ((u16)0x0038)
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+
+/* SPI MSB/LSB transmission */
+#define SPI_FirstBit_MSB ((u16)0x0000)
+#define SPI_FirstBit_LSB ((u16)0x0080)
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+
+/* I2S Mode */
+#define I2S_Mode_SlaveTx ((u16)0x0000)
+#define I2S_Mode_SlaveRx ((u16)0x0100)
+#define I2S_Mode_MasterTx ((u16)0x0200)
+#define I2S_Mode_MasterRx ((u16)0x0300)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx) || \
+ ((MODE) == I2S_Mode_MasterRx) )
+
+/* I2S Standard */
+#define I2S_Standard_Phillips ((u16)0x0000)
+#define I2S_Standard_MSB ((u16)0x0010)
+#define I2S_Standard_LSB ((u16)0x0020)
+#define I2S_Standard_PCMShort ((u16)0x0030)
+#define I2S_Standard_PCMLong ((u16)0x00B0)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+
+/* I2S Data Format */
+#define I2S_DataFormat_16b ((u16)0x0000)
+#define I2S_DataFormat_16bextended ((u16)0x0001)
+#define I2S_DataFormat_24b ((u16)0x0003)
+#define I2S_DataFormat_32b ((u16)0x0005)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+
+/* I2S MCLK Output */
+#define I2S_MCLKOutput_Enable ((u16)0x0200)
+#define I2S_MCLKOutput_Disable ((u16)0x0000)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+
+/* I2S Audio Frequency */
+#define I2S_AudioFreq_48k ((u16)48000)
+#define I2S_AudioFreq_44k ((u16)44100)
+#define I2S_AudioFreq_22k ((u16)22050)
+#define I2S_AudioFreq_16k ((u16)16000)
+#define I2S_AudioFreq_8k ((u16)8000)
+#define I2S_AudioFreq_Default ((u16)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
+ ((FREQ) == I2S_AudioFreq_44k) || \
+ ((FREQ) == I2S_AudioFreq_22k) || \
+ ((FREQ) == I2S_AudioFreq_16k) || \
+ ((FREQ) == I2S_AudioFreq_8k) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+
+/* I2S Clock Polarity */
+#define I2S_CPOL_Low ((u16)0x0000)
+#define I2S_CPOL_High ((u16)0x0008)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+
+/* SPI_I2S DMA transfer requests */
+#define SPI_I2S_DMAReq_Tx ((u16)0x0002)
+#define SPI_I2S_DMAReq_Rx ((u16)0x0001)
+
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+
+/* SPI NSS internal software mangement */
+#define SPI_NSSInternalSoft_Set ((u16)0x0100)
+#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)
+
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+
+/* SPI CRC Transmit/Receive */
+#define SPI_CRC_Tx ((u8)0x00)
+#define SPI_CRC_Rx ((u8)0x01)
+
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+
+/* SPI direction transmit/receive */
+#define SPI_Direction_Rx ((u16)0xBFFF)
+#define SPI_Direction_Tx ((u16)0x4000)
+
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+
+/* SPI_I2S interrupts definition */
+#define SPI_I2S_IT_TXE ((u8)0x71)
+#define SPI_I2S_IT_RXNE ((u8)0x60)
+#define SPI_I2S_IT_ERR ((u8)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+
+#define SPI_I2S_IT_OVR ((u8)0x56)
+#define SPI_IT_MODF ((u8)0x55)
+#define SPI_IT_CRCERR ((u8)0x54)
+#define I2S_IT_UDR ((u8)0x53)
+
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+
+/* SPI_I2S flags definition */
+#define SPI_I2S_FLAG_RXNE ((u16)0x0001)
+#define SPI_I2S_FLAG_TXE ((u16)0x0002)
+#define I2S_FLAG_CHSIDE ((u16)0x0004)
+#define I2S_FLAG_UDR ((u16)0x0008)
+#define SPI_FLAG_CRCERR ((u16)0x0010)
+#define SPI_FLAG_MODF ((u16)0x0020)
+#define SPI_I2S_FLAG_OVR ((u16)0x0040)
+#define SPI_I2S_FLAG_BSY ((u16)0x0080)
+
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+
+/* SPI CRC polynomial --------------------------------------------------------*/
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data);
+u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);
+
+#endif /*__STM32F10x_SPI_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_systick.h b/src/stm32lib/inc/stm32f10x_systick.h new file mode 100644 index 0000000..3dfb036 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_systick.h @@ -0,0 +1,70 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_systick.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* SysTick firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SYSTICK_H
+#define __STM32F10x_SYSTICK_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* SysTick clock source */
+#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((u32)0x00000004)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+
+/* SysTick counter state */
+#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)
+#define SysTick_Counter_Enable ((u32)0x00000001)
+#define SysTick_Counter_Clear ((u32)0x00000000)
+
+#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \
+ ((COUNTER) == SysTick_Counter_Enable) || \
+ ((COUNTER) == SysTick_Counter_Clear))
+
+/* SysTick Flag */
+#define SysTick_FLAG_COUNT ((u32)0x00000010)
+#define SysTick_FLAG_SKEW ((u32)0x0000001E)
+#define SysTick_FLAG_NOREF ((u32)0x0000001F)
+
+#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \
+ ((FLAG) == SysTick_FLAG_SKEW) || \
+ ((FLAG) == SysTick_FLAG_NOREF))
+
+#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);
+void SysTick_SetReload(u32 Reload);
+void SysTick_CounterCmd(u32 SysTick_Counter);
+void SysTick_ITConfig(FunctionalState NewState);
+u32 SysTick_GetCounter(void);
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_SYSTICK_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_tim.h b/src/stm32lib/inc/stm32f10x_tim.h new file mode 100644 index 0000000..423516c --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_tim.h @@ -0,0 +1,784 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_tim.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* TIM firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* TIM Time Base Init structure definition */
+typedef struct
+{
+ u16 TIM_Prescaler;
+ u16 TIM_CounterMode;
+ u16 TIM_Period;
+ u16 TIM_ClockDivision;
+ u8 TIM_RepetitionCounter;
+} TIM_TimeBaseInitTypeDef;
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+ u16 TIM_OCMode;
+ u16 TIM_OutputState;
+ u16 TIM_OutputNState;
+ u16 TIM_Pulse;
+ u16 TIM_OCPolarity;
+ u16 TIM_OCNPolarity;
+ u16 TIM_OCIdleState;
+ u16 TIM_OCNIdleState;
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+ u16 TIM_Channel;
+ u16 TIM_ICPolarity;
+ u16 TIM_ICSelection;
+ u16 TIM_ICPrescaler;
+ u16 TIM_ICFilter;
+} TIM_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+ u16 TIM_OSSRState;
+ u16 TIM_OSSIState;
+ u16 TIM_LOCKLevel;
+ u16 TIM_DeadTime;
+ u16 TIM_Break;
+ u16 TIM_BreakPolarity;
+ u16 TIM_AutomaticOutput;
+} TIM_BDTRInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM2_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM5_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM6_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM7_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM8_BASE))
+
+#define IS_TIM_18_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM8_BASE))
+
+#define IS_TIM_123458_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM2_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM5_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM8_BASE))
+
+/* TIM Output Compare and PWM modes -----------------------------------------*/
+#define TIM_OCMode_Timing ((u16)0x0000)
+#define TIM_OCMode_Active ((u16)0x0010)
+#define TIM_OCMode_Inactive ((u16)0x0020)
+#define TIM_OCMode_Toggle ((u16)0x0030)
+#define TIM_OCMode_PWM1 ((u16)0x0060)
+#define TIM_OCMode_PWM2 ((u16)0x0070)
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2))
+
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive))
+/* TIM One Pulse Mode -------------------------------------------------------*/
+#define TIM_OPMode_Single ((u16)0x0008)
+#define TIM_OPMode_Repetitive ((u16)0x0000)
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+
+/* TIM Channel -------------------------------------------------------------*/
+#define TIM_Channel_1 ((u16)0x0000)
+#define TIM_Channel_2 ((u16)0x0004)
+#define TIM_Channel_3 ((u16)0x0008)
+#define TIM_Channel_4 ((u16)0x000C)
+
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3))
+/* TIM Clock Division CKD --------------------------------------------------*/
+#define TIM_CKD_DIV1 ((u16)0x0000)
+#define TIM_CKD_DIV2 ((u16)0x0100)
+#define TIM_CKD_DIV4 ((u16)0x0200)
+
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+
+/* TIM Counter Mode --------------------------------------------------------*/
+#define TIM_CounterMode_Up ((u16)0x0000)
+#define TIM_CounterMode_Down ((u16)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+
+/* TIM Output Compare Polarity ---------------------------------------------*/
+#define TIM_OCPolarity_High ((u16)0x0000)
+#define TIM_OCPolarity_Low ((u16)0x0002)
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+
+/* TIM Output Compare N Polarity -------------------------------------------*/
+#define TIM_OCNPolarity_High ((u16)0x0000)
+#define TIM_OCNPolarity_Low ((u16)0x0008)
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+ ((POLARITY) == TIM_OCNPolarity_Low))
+
+/* TIM Output Compare states -----------------------------------------------*/
+#define TIM_OutputState_Disable ((u16)0x0000)
+#define TIM_OutputState_Enable ((u16)0x0001)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+
+/* TIM Output Compare N States ---------------------------------------------*/
+#define TIM_OutputNState_Disable ((u16)0x0000)
+#define TIM_OutputNState_Enable ((u16)0x0004)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+ ((STATE) == TIM_OutputNState_Enable))
+
+/* TIM Capture Compare States -----------------------------------------------*/
+#define TIM_CCx_Enable ((u16)0x0001)
+#define TIM_CCx_Disable ((u16)0x0000)
+
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+
+/* TIM Capture Compare N States --------------------------------------------*/
+#define TIM_CCxN_Enable ((u16)0x0004)
+#define TIM_CCxN_Disable ((u16)0x0000)
+
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+ ((CCXN) == TIM_CCxN_Disable))
+
+/* Break Input enable/disable -----------------------------------------------*/
+#define TIM_Break_Enable ((u16)0x1000)
+#define TIM_Break_Disable ((u16)0x0000)
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+ ((STATE) == TIM_Break_Disable))
+
+/* Break Polarity -----------------------------------------------------------*/
+#define TIM_BreakPolarity_Low ((u16)0x0000)
+#define TIM_BreakPolarity_High ((u16)0x2000)
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+ ((POLARITY) == TIM_BreakPolarity_High))
+
+/* TIM AOE Bit Set/Reset ---------------------------------------------------*/
+#define TIM_AutomaticOutput_Enable ((u16)0x4000)
+#define TIM_AutomaticOutput_Disable ((u16)0x0000)
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+ ((STATE) == TIM_AutomaticOutput_Disable))
+/* Lock levels --------------------------------------------------------------*/
+#define TIM_LOCKLevel_OFF ((u16)0x0000)
+#define TIM_LOCKLevel_1 ((u16)0x0100)
+#define TIM_LOCKLevel_2 ((u16)0x0200)
+#define TIM_LOCKLevel_3 ((u16)0x0300)
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+ ((LEVEL) == TIM_LOCKLevel_1) || \
+ ((LEVEL) == TIM_LOCKLevel_2) || \
+ ((LEVEL) == TIM_LOCKLevel_3))
+
+/* OSSI: Off-State Selection for Idle mode states ---------------------------*/
+#define TIM_OSSIState_Enable ((u16)0x0400)
+#define TIM_OSSIState_Disable ((u16)0x0000)
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+ ((STATE) == TIM_OSSIState_Disable))
+
+/* OSSR: Off-State Selection for Run mode states ----------------------------*/
+#define TIM_OSSRState_Enable ((u16)0x0800)
+#define TIM_OSSRState_Disable ((u16)0x0000)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+ ((STATE) == TIM_OSSRState_Disable))
+
+/* TIM Output Compare Idle State -------------------------------------------*/
+#define TIM_OCIdleState_Set ((u16)0x0100)
+#define TIM_OCIdleState_Reset ((u16)0x0000)
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+ ((STATE) == TIM_OCIdleState_Reset))
+
+/* TIM Output Compare N Idle State -----------------------------------------*/
+#define TIM_OCNIdleState_Set ((u16)0x0200)
+#define TIM_OCNIdleState_Reset ((u16)0x0000)
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+ ((STATE) == TIM_OCNIdleState_Reset))
+
+/* TIM Input Capture Polarity ----------------------------------------------*/
+#define TIM_ICPolarity_Rising ((u16)0x0000)
+#define TIM_ICPolarity_Falling ((u16)0x0002)
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling))
+
+/* TIM Input Capture Selection ---------------------------------------------*/
+#define TIM_ICSelection_DirectTI ((u16)0x0001)
+#define TIM_ICSelection_IndirectTI ((u16)0x0002)
+#define TIM_ICSelection_TRC ((u16)0x0003)
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+
+/* TIM Input Capture Prescaler ---------------------------------------------*/
+#define TIM_ICPSC_DIV1 ((u16)0x0000)
+#define TIM_ICPSC_DIV2 ((u16)0x0004)
+#define TIM_ICPSC_DIV4 ((u16)0x0008)
+#define TIM_ICPSC_DIV8 ((u16)0x000C)
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+/* TIM interrupt sources ---------------------------------------------------*/
+#define TIM_IT_Update ((u16)0x0001)
+#define TIM_IT_CC1 ((u16)0x0002)
+#define TIM_IT_CC2 ((u16)0x0004)
+#define TIM_IT_CC3 ((u16)0x0008)
+#define TIM_IT_CC4 ((u16)0x0010)
+#define TIM_IT_COM ((u16)0x0020)
+#define TIM_IT_Trigger ((u16)0x0040)
+#define TIM_IT_Break ((u16)0x0080)
+
+#define IS_TIM_IT(IT) ((((IT) & (u16)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
+ (((TIM_IT) & (u16)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
+ (((TIM_IT) & (u16)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
+ (((TIM_IT) & (u16)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_Trigger) || \
+ ((IT) == TIM_IT_Break))
+
+/* TIM DMA Base address ----------------------------------------------------*/
+#define TIM_DMABase_CR1 ((u16)0x0000)
+#define TIM_DMABase_CR2 ((u16)0x0001)
+#define TIM_DMABase_SMCR ((u16)0x0002)
+#define TIM_DMABase_DIER ((u16)0x0003)
+#define TIM_DMABase_SR ((u16)0x0004)
+#define TIM_DMABase_EGR ((u16)0x0005)
+#define TIM_DMABase_CCMR1 ((u16)0x0006)
+#define TIM_DMABase_CCMR2 ((u16)0x0007)
+#define TIM_DMABase_CCER ((u16)0x0008)
+#define TIM_DMABase_CNT ((u16)0x0009)
+#define TIM_DMABase_PSC ((u16)0x000A)
+#define TIM_DMABase_ARR ((u16)0x000B)
+#define TIM_DMABase_RCR ((u16)0x000C)
+#define TIM_DMABase_CCR1 ((u16)0x000D)
+#define TIM_DMABase_CCR2 ((u16)0x000E)
+#define TIM_DMABase_CCR3 ((u16)0x000F)
+#define TIM_DMABase_CCR4 ((u16)0x0010)
+#define TIM_DMABase_BDTR ((u16)0x0011)
+#define TIM_DMABase_DCR ((u16)0x0012)
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR))
+
+/* TIM DMA Burst Length ----------------------------------------------------*/
+#define TIM_DMABurstLength_1Byte ((u16)0x0000)
+#define TIM_DMABurstLength_2Bytes ((u16)0x0100)
+#define TIM_DMABurstLength_3Bytes ((u16)0x0200)
+#define TIM_DMABurstLength_4Bytes ((u16)0x0300)
+#define TIM_DMABurstLength_5Bytes ((u16)0x0400)
+#define TIM_DMABurstLength_6Bytes ((u16)0x0500)
+#define TIM_DMABurstLength_7Bytes ((u16)0x0600)
+#define TIM_DMABurstLength_8Bytes ((u16)0x0700)
+#define TIM_DMABurstLength_9Bytes ((u16)0x0800)
+#define TIM_DMABurstLength_10Bytes ((u16)0x0900)
+#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)
+#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)
+#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)
+#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)
+#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)
+#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)
+#define TIM_DMABurstLength_17Bytes ((u16)0x1000)
+#define TIM_DMABurstLength_18Bytes ((u16)0x1100)
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))
+
+/* TIM DMA sources ---------------------------------------------------------*/
+#define TIM_DMA_Update ((u16)0x0100)
+#define TIM_DMA_CC1 ((u16)0x0200)
+#define TIM_DMA_CC2 ((u16)0x0400)
+#define TIM_DMA_CC3 ((u16)0x0800)
+#define TIM_DMA_CC4 ((u16)0x1000)
+#define TIM_DMA_COM ((u16)0x2000)
+#define TIM_DMA_Trigger ((u16)0x4000)
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
+ (((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
+ (((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
+ (((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
+
+/* TIM External Trigger Prescaler ------------------------------------------*/
+#define TIM_ExtTRGPSC_OFF ((u16)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)
+
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+
+/* TIM Internal Trigger Selection ------------------------------------------*/
+#define TIM_TS_ITR0 ((u16)0x0000)
+#define TIM_TS_ITR1 ((u16)0x0010)
+#define TIM_TS_ITR2 ((u16)0x0020)
+#define TIM_TS_ITR3 ((u16)0x0030)
+#define TIM_TS_TI1F_ED ((u16)0x0040)
+#define TIM_TS_TI1FP1 ((u16)0x0050)
+#define TIM_TS_TI2FP2 ((u16)0x0060)
+#define TIM_TS_ETRF ((u16)0x0070)
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+/* TIM TIx External Clock Source -------------------------------------------*/
+#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)
+
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+
+/* TIM External Trigger Polarity -------------------------------------------*/
+#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)
+
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+
+/* TIM Prescaler Reload Mode -----------------------------------------------*/
+#define TIM_PSCReloadMode_Update ((u16)0x0000)
+#define TIM_PSCReloadMode_Immediate ((u16)0x0001)
+
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+
+/* TIM Forced Action -------------------------------------------------------*/
+#define TIM_ForcedAction_Active ((u16)0x0050)
+#define TIM_ForcedAction_InActive ((u16)0x0040)
+
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+
+/* TIM Encoder Mode --------------------------------------------------------*/
+#define TIM_EncoderMode_TI1 ((u16)0x0001)
+#define TIM_EncoderMode_TI2 ((u16)0x0002)
+#define TIM_EncoderMode_TI12 ((u16)0x0003)
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+
+/* TIM Event Source --------------------------------------------------------*/
+#define TIM_EventSource_Update ((u16)0x0001)
+#define TIM_EventSource_CC1 ((u16)0x0002)
+#define TIM_EventSource_CC2 ((u16)0x0004)
+#define TIM_EventSource_CC3 ((u16)0x0008)
+#define TIM_EventSource_CC4 ((u16)0x0010)
+#define TIM_EventSource_COM ((u16)0x0020)
+#define TIM_EventSource_Trigger ((u16)0x0040)
+#define TIM_EventSource_Break ((u16)0x0080)
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
+ (((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
+ (((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
+ (((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
+
+/* TIM Update Source --------------------------------------------------------*/
+#define TIM_UpdateSource_Global ((u16)0x0000)
+#define TIM_UpdateSource_Regular ((u16)0x0001)
+
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+
+/* TIM Ouput Compare Preload State ------------------------------------------*/
+#define TIM_OCPreload_Enable ((u16)0x0008)
+#define TIM_OCPreload_Disable ((u16)0x0000)
+
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+
+/* TIM Ouput Compare Fast State ---------------------------------------------*/
+#define TIM_OCFast_Enable ((u16)0x0004)
+#define TIM_OCFast_Disable ((u16)0x0000)
+
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/* TIM Ouput Compare Clear State --------------------------------------------*/
+#define TIM_OCClear_Enable ((u16)0x0080)
+#define TIM_OCClear_Disable ((u16)0x0000)
+
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+
+/* TIM Trigger Output Source ------------------------------------------------*/
+#define TIM_TRGOSource_Reset ((u16)0x0000)
+#define TIM_TRGOSource_Enable ((u16)0x0010)
+#define TIM_TRGOSource_Update ((u16)0x0020)
+#define TIM_TRGOSource_OC1 ((u16)0x0030)
+#define TIM_TRGOSource_OC1Ref ((u16)0x0040)
+#define TIM_TRGOSource_OC2Ref ((u16)0x0050)
+#define TIM_TRGOSource_OC3Ref ((u16)0x0060)
+#define TIM_TRGOSource_OC4Ref ((u16)0x0070)
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+
+#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_Reset)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_Enable)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_Update)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_OC1)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \
+ ((TRGO) == TIM_TRGOSource_OC4Ref)))
+
+/* TIM Slave Mode ----------------------------------------------------------*/
+#define TIM_SlaveMode_Reset ((u16)0x0004)
+#define TIM_SlaveMode_Gated ((u16)0x0005)
+#define TIM_SlaveMode_Trigger ((u16)0x0006)
+#define TIM_SlaveMode_External1 ((u16)0x0007)
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1))
+
+/* TIM Master Slave Mode ---------------------------------------------------*/
+#define TIM_MasterSlaveMode_Enable ((u16)0x0080)
+#define TIM_MasterSlaveMode_Disable ((u16)0x0000)
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+
+/* TIM Flags ---------------------------------------------------------------*/
+#define TIM_FLAG_Update ((u16)0x0001)
+#define TIM_FLAG_CC1 ((u16)0x0002)
+#define TIM_FLAG_CC2 ((u16)0x0004)
+#define TIM_FLAG_CC3 ((u16)0x0008)
+#define TIM_FLAG_CC4 ((u16)0x0010)
+#define TIM_FLAG_COM ((u16)0x0020)
+#define TIM_FLAG_Trigger ((u16)0x0040)
+#define TIM_FLAG_Break ((u16)0x0080)
+#define TIM_FLAG_CC1OF ((u16)0x0200)
+#define TIM_FLAG_CC2OF ((u16)0x0400)
+#define TIM_FLAG_CC3OF ((u16)0x0800)
+#define TIM_FLAG_CC4OF ((u16)0x1000)
+
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_Break) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+
+#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \
+ (((TIM_FLAG) & (u16)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \
+ (((TIM_FLAG) & (u16)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \
+ (((TIM_FLAG) & (u16)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
+
+#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) ||\
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
+ ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
+ (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\
+ ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \
+ ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\
+ ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) ||\
+ ((*(u32*)&(PERIPH))==TIM1_BASE)|| ((*(u32*)&(PERIPH))==TIM8_BASE) || \
+ ((*(u32*)&(PERIPH))==TIM7_BASE) || ((*(u32*)&(PERIPH))==TIM6_BASE)) && \
+ (((TIM_FLAG) == TIM_FLAG_Update))) ||\
+ ((((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) &&\
+ (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\
+ ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \
+ ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\
+ (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\
+ ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
+
+/* TIM Input Capture Filer Value ---------------------------------------------*/
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+/* TIM External Trigger Filter -----------------------------------------------*/
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,
+ u16 TIM_ICPolarity, u16 ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+ u16 ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
+ u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
+ u16 ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
+ u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx);
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx);
+u16 TIM_GetCounter(TIM_TypeDef* TIMx);
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_TIM_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
+
+
diff --git a/src/stm32lib/inc/stm32f10x_type.h b/src/stm32lib/inc/stm32f10x_type.h new file mode 100644 index 0000000..895cbb2 --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_type.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the common data types used for the
+* STM32F10x firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TYPE_H
+#define __STM32F10x_TYPE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef signed long s32;
+typedef signed short s16;
+typedef signed char s8;
+
+typedef signed long const sc32; /* Read Only */
+typedef signed short const sc16; /* Read Only */
+typedef signed char const sc8; /* Read Only */
+
+typedef volatile signed long vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char vs8;
+
+typedef volatile signed long const vsc32; /* Read Only */
+typedef volatile signed short const vsc16; /* Read Only */
+typedef volatile signed char const vsc8; /* Read Only */
+
+typedef unsigned long u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+typedef unsigned long const uc32; /* Read Only */
+typedef unsigned short const uc16; /* Read Only */
+typedef unsigned char const uc8; /* Read Only */
+
+typedef volatile unsigned long vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char vu8;
+
+typedef volatile unsigned long const vuc32; /* Read Only */
+typedef volatile unsigned short const vuc16; /* Read Only */
+typedef volatile unsigned char const vuc8; /* Read Only */
+
+//typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#define U8_MAX ((u8)255)
+#define S8_MAX ((s8)127)
+#define S8_MIN ((s8)-128)
+#define U16_MAX ((u16)65535u)
+#define S16_MAX ((s16)32767)
+#define S16_MIN ((s16)-32768)
+#define U32_MAX ((u32)4294967295uL)
+#define S32_MAX ((s32)2147483647)
+#define S32_MIN ((s32)-2147483648)
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_TYPE_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_usart.h b/src/stm32lib/inc/stm32f10x_usart.h new file mode 100644 index 0000000..0731b7b --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_usart.h @@ -0,0 +1,259 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_usart.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* USART firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* USART Init Structure definition */
+typedef struct
+{
+ u32 USART_BaudRate;
+ u16 USART_WordLength;
+ u16 USART_StopBits;
+ u16 USART_Parity;
+ u16 USART_Mode;
+ u16 USART_HardwareFlowControl;
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */
+typedef struct
+{
+ u16 USART_Clock;
+ u16 USART_CPOL;
+ u16 USART_CPHA;
+ u16 USART_LastBit;
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
+ ((*(u32*)&(PERIPH)) == USART2_BASE) || \
+ ((*(u32*)&(PERIPH)) == USART3_BASE) || \
+ ((*(u32*)&(PERIPH)) == UART4_BASE) || \
+ ((*(u32*)&(PERIPH)) == UART5_BASE))
+
+#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
+ ((*(u32*)&(PERIPH)) == USART2_BASE) || \
+ ((*(u32*)&(PERIPH)) == USART3_BASE))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \
+ ((*(u32*)&(PERIPH)) == USART2_BASE) || \
+ ((*(u32*)&(PERIPH)) == USART3_BASE) || \
+ ((*(u32*)&(PERIPH)) == UART4_BASE))
+
+/* USART Word Length ---------------------------------------------------------*/
+#define USART_WordLength_8b ((u16)0x0000)
+#define USART_WordLength_9b ((u16)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b))
+
+/* USART Stop Bits -----------------------------------------------------------*/
+#define USART_StopBits_1 ((u16)0x0000)
+#define USART_StopBits_0_5 ((u16)0x1000)
+#define USART_StopBits_2 ((u16)0x2000)
+#define USART_StopBits_1_5 ((u16)0x3000)
+
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_0_5) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/* USART Parity --------------------------------------------------------------*/
+#define USART_Parity_No ((u16)0x0000)
+#define USART_Parity_Even ((u16)0x0400)
+#define USART_Parity_Odd ((u16)0x0600)
+
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+
+/* USART Mode ----------------------------------------------------------------*/
+#define USART_Mode_Rx ((u16)0x0004)
+#define USART_Mode_Tx ((u16)0x0008)
+
+#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00))
+
+/* USART Hardware Flow Control -----------------------------------------------*/
+#define USART_HardwareFlowControl_None ((u16)0x0000)
+#define USART_HardwareFlowControl_RTS ((u16)0x0100)
+#define USART_HardwareFlowControl_CTS ((u16)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)
+
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+
+#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
+ ((*(u32*)&(PERIPH)) != UART5_BASE)) \
+ || ((HFC) == USART_HardwareFlowControl_None))
+
+/* USART Clock ---------------------------------------------------------------*/
+#define USART_Clock_Disable ((u16)0x0000)
+#define USART_Clock_Enable ((u16)0x0800)
+
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+
+/* USART Clock Polarity ------------------------------------------------------*/
+#define USART_CPOL_Low ((u16)0x0000)
+#define USART_CPOL_High ((u16)0x0400)
+
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/* USART Clock Phase ---------------------------------------------------------*/
+#define USART_CPHA_1Edge ((u16)0x0000)
+#define USART_CPHA_2Edge ((u16)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/* USART Last Bit ------------------------------------------------------------*/
+#define USART_LastBit_Disable ((u16)0x0000)
+#define USART_LastBit_Enable ((u16)0x0100)
+
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+
+/* USART Interrupt definition ------------------------------------------------*/
+#define USART_IT_PE ((u16)0x0028)
+#define USART_IT_TXE ((u16)0x0727)
+#define USART_IT_TC ((u16)0x0626)
+#define USART_IT_RXNE ((u16)0x0525)
+#define USART_IT_IDLE ((u16)0x0424)
+#define USART_IT_LBD ((u16)0x0846)
+#define USART_IT_CTS ((u16)0x096A)
+#define USART_IT_ERR ((u16)0x0060)
+#define USART_IT_ORE ((u16)0x0360)
+#define USART_IT_NE ((u16)0x0260)
+#define USART_IT_FE ((u16)0x0160)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+
+#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \
+ ((*(u32*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_IT) != USART_IT_CTS))
+
+/* USART DMA Requests --------------------------------------------------------*/
+#define USART_DMAReq_Tx ((u16)0x0080)
+#define USART_DMAReq_Rx ((u16)0x0040)
+
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00))
+
+/* USART WakeUp methods ------------------------------------------------------*/
+#define USART_WakeUp_IdleLine ((u16)0x0000)
+#define USART_WakeUp_AddressMark ((u16)0x0800)
+
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+
+/* USART LIN Break Detection Length ------------------------------------------*/
+#define USART_LINBreakDetectLength_10b ((u16)0x0000)
+#define USART_LINBreakDetectLength_11b ((u16)0x0020)
+
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+
+/* USART IrDA Low Power ------------------------------------------------------*/
+#define USART_IrDAMode_LowPower ((u16)0x0004)
+#define USART_IrDAMode_Normal ((u16)0x0000)
+
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+
+/* USART Flags ---------------------------------------------------------------*/
+#define USART_FLAG_CTS ((u16)0x0200)
+#define USART_FLAG_LBD ((u16)0x0100)
+#define USART_FLAG_TXE ((u16)0x0080)
+#define USART_FLAG_TC ((u16)0x0040)
+#define USART_FLAG_RXNE ((u16)0x0020)
+#define USART_FLAG_IDLE ((u16)0x0010)
+#define USART_FLAG_ORE ((u16)0x0008)
+#define USART_FLAG_NE ((u16)0x0004)
+#define USART_FLAG_FE ((u16)0x0002)
+#define USART_FLAG_PE ((u16)0x0001)
+
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00))
+
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\
+ ((*(u32*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTS))
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef __cplusplus
+extern "C" {
+#endif
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, u16 Data);
+u16 USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __STM32F10x_USART_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/inc/stm32f10x_wwdg.h b/src/stm32lib/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000..3c5339e --- /dev/null +++ b/src/stm32lib/inc/stm32f10x_wwdg.h @@ -0,0 +1,54 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_wwdg.h
+* Author : MCD Application Team
+* Version : V2.0.2
+* Date : 07/11/2008
+* Description : This file contains all the functions prototypes for the
+* WWDG firmware library.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* WWDG Prescaler */
+#define WWDG_Prescaler_1 ((u32)0x00000000)
+#define WWDG_Prescaler_2 ((u32)0x00000080)
+#define WWDG_Prescaler_4 ((u32)0x00000100)
+#define WWDG_Prescaler_8 ((u32)0x00000180)
+
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(u32 WWDG_Prescaler);
+void WWDG_SetWindowValue(u8 WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(u8 Counter);
+void WWDG_Enable(u8 Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#endif /* __STM32F10x_WWDG_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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