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author | Michael Hope <michael.hope@linaro.org> | 2010-09-29 20:45:57 +1300 |
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committer | Michael Hope <michael.hope@linaro.org> | 2010-09-29 20:45:57 +1300 |
commit | 6fcd4cd306dbecf56f5b0b506a3c23762d1219fa (patch) | |
tree | 467125eca5a2e6706001cad8e09bc475e58a12d9 /notes/fsmc.txt | |
parent | 368e4fc1662c2594b2a0908900713a2555a3ed8e (diff) | |
parent | adde11b099ff5dad176e410279d21feac39d2c7e (diff) | |
download | librambutan-6fcd4cd306dbecf56f5b0b506a3c23762d1219fa.tar.gz librambutan-6fcd4cd306dbecf56f5b0b506a3c23762d1219fa.zip |
Merge remote branch 'upstream/master'
Diffstat (limited to 'notes/fsmc.txt')
-rw-r--r-- | notes/fsmc.txt | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/notes/fsmc.txt b/notes/fsmc.txt index b41de60..1f70760 100644 --- a/notes/fsmc.txt +++ b/notes/fsmc.txt @@ -15,14 +15,15 @@ SRAM chip details t_aa (address access) = 55ns -The FSMC nomenclature is very confusing. There are three seperate "banks" -(which I will call "peripheral banks") each of specialized for different types -of external memory (NOR flash, NAND flash, SRAM, etc). We use the one for -"PSRAM" with our SRAM chip; it's bank #1. The SRAM peripheral bank is further -split into 4 "banks" (which I will call "channels") to support multiple -external devices with chip select pins. I think what's going on is that there -are 4 hardware peripherals and many sections of RAM; the docs are confusing -about what's a "block of memeory" and what's an "FSMC block". +The FSMC nomenclature is very confusing. There are three separate +"banks" (which I will call "peripheral banks") each specialized for +different types of external memory (NOR flash, NAND flash, SRAM, +etc). We use the one for "PSRAM" with our SRAM chip; it's bank #1. The +SRAM peripheral bank is further split into 4 "banks" (which I will +call "channels") to support multiple external devices with chip select +pins. I think what's going on is that there are 4 hardware peripherals +and many sections of RAM; the docs are confusing about what's a "block +of memeory" and what's an "FSMC block". Anyways, this all takes place on the AHB memory bus. |