Merge pull request #54 from ginge/master

Added i2c slave support

3 files changed, 344 insertions, 3 deletions

diff --git a/libmaple/i2c.c b/libmaple/i2c.c
index 9c93d3f..bbbf123 100644
--- a/libmaple/i2c.c
+++ b/libmaple/i2c.c
@@ -28,9 +28,11 @@
 /**
  * @file libmaple/i2c.c
  * @author Perry Hung <perry@leaflabs.com>
+ * @author Barry Carter <barry.carter@gmail.com>
  * @brief Inter-Integrated Circuit (I2C) support.
  *
- * Currently, only master mode is supported.
+ * Master and Slave supported
+ * Slave code added Barry Carter 2012
  */
 
 #include "i2c_private.h"
@@ -154,6 +156,7 @@ void i2c_bus_reset(const i2c_dev *dev) {
 void i2c_init(i2c_dev *dev) {
     rcc_reset_dev(dev->clk_id);
     rcc_clk_enable(dev->clk_id);
+    _i2c_irq_priority_fixup(dev);
 }
 
 /* Hack for deprecated bit of STM32F1 functionality */
@@ -198,13 +201,51 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
     nvic_irq_enable(dev->er_nvic_line);
     i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
 
+    /* Configure the slave unit */
+    if (flags & I2C_SLAVE_DUAL_ADDRESS) {
+        i2c_slave_dual_address_enable(dev);
+    }
+
+    if (flags & I2C_SLAVE_GENERAL_CALL) {
+        i2c_slave_general_call_enable(dev);
+    }
+
+    /* store all of the flags */
+    dev->config_flags = flags;
+
     /* Make it go! */
     i2c_peripheral_enable(dev);
+    i2c_enable_ack(dev);
 
     dev->state = I2C_STATE_IDLE;
 }
 
 /**
+ * @brief Initialize an I2C device as slave (and master)
+ * @param dev Device to enable
+ * @param flags Bitwise or of the following I2C options:
+ *              I2C_FAST_MODE: 400 khz operation,
+ *              I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
+ *                             fast mode),
+ *              I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
+ *                             initialization,
+ *              I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
+ *              I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
+ *                         SDA/PB9.
+ *              I2C_SLAVE_DUAL_ADDRESS: Slave can respond on 2 i2C addresses
+ *              I2C_SLAVE_GENERAL_CALL: SLA+W broadcast to all general call
+ *                                      listeners on bus. Addr 0x00
+ *              I2C_SLAVE_USE_RX_BUFFER: Use a buffer to receive the incoming
+ *                                       data. Callback at end of recv
+ *              I2C_SLAVE_USE_TX_BUFFER: Use a buffer to transmit data.
+ *                                       Callback will be called before tx
+ */
+void i2c_slave_enable(i2c_dev *dev, uint32 flags) {
+    i2c_disable(dev);
+    i2c_master_enable(dev, dev->config_flags | flags);
+}
+
+/**
  * @brief Process an i2c transaction.
  *
  * Transactions are composed of one or more i2c_msg's, and may be read
@@ -304,6 +345,164 @@ void _i2c_irq_handler(i2c_dev *dev) {
     dev->timestamp = systick_uptime();
 
     /*
+     * Add Slave support
+     */
+
+    /* Check to see if MSL master slave bit is set */
+    if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
+
+        /* Check for address match */
+        if (sr1 & I2C_SR1_ADDR) {
+            /* Find out which address was matched */
+            /* Check the general call address first */
+            if (sr2 & I2C_SR2_GENCALL) {
+                dev->i2c_slave_msg->addr = 0;
+            }
+            /* We matched the secondary address */
+            else if (sr2 & I2C_SR2_DUALF) {
+                dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE;
+            }
+            /* We matched the primary address */
+            else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) {
+                dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE;
+            }
+            /* Shouldn't get here */
+            else {
+                dev->i2c_slave_msg->addr = -1; /* uh oh */
+            }
+
+            /* if we have buffered io */
+            if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
+                (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
+
+                /* if receiving then this would be a repeated start
+                 *
+                 *if we have some bytes already
+                 */
+                if ((dev->state == I2C_STATE_SL_RX) &&
+                    (dev->i2c_slave_msg->xferred > 0)  &&
+                    (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
+                    /* Call the callback with the contents of the data */
+                    if (dev->i2c_slave_recv_callback != NULL) {
+                        (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+                    }
+                }
+
+                /* Reset the message back to defaults.
+                 * We are starting a new message
+                 */
+                dev->i2c_slave_msg->flags = 0;
+                dev->i2c_slave_msg->length = 0;
+                dev->i2c_slave_msg->xferred = 0;
+                dev->msgs_left = 0;
+                dev->timestamp = systick_uptime();
+
+                /* We have been addressed with SLA+R so
+                 * the master wants us to transmit
+                 */
+                if ((sr1 & I2C_SR1_TXE) &&
+                    (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
+                    /* Call the transmit callback so it can populate the msg
+                     * data with the bytes to go
+                     */
+                    if (dev->i2c_slave_transmit_callback != NULL) {
+                        (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
+                    }
+                }
+                dev->state = I2C_STATE_BUSY;
+            }
+
+            sr1 = sr2 = 0;
+        }
+        
+         /* EV3: Master requesting data from slave. Transmit a byte*/
+        if (sr1 & I2C_SR1_TXE) {
+            if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) {
+                if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) {
+                    /* End of the transmit buffer? If so we NACK */
+                    i2c_disable_ack(dev);
+                    /* We have to either issue a STOP or write something here.
+                     * STOP here seems to screw up some masters,
+                     * For now padding with 0
+                     */
+                    i2c_write(dev, 0);
+                    /*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/
+                }
+                else
+                {
+                    /* NACk the last byte */
+                    if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) {
+                        i2c_disable_ack(dev);
+                    }
+                    else {
+                        i2c_enable_ack(dev);
+                    }
+                    i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]);
+                }
+            }
+            else
+            {
+                /* Call the callback to get the data we need.
+                 * The callback is expected to write using i2c_write(...)
+                 * If the slave is going to terminate the transfer, this function should
+                 * also do a NACK on the last byte!
+                 */
+                if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
+            }
+
+            dev->state = I2C_STATE_BUSY;
+            sr1 = sr2 = 0;
+        }
+        
+        /* EV2: Slave received data from a master. Get from DR */
+        if (sr1 & I2C_SR1_RXNE) {
+            if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) {
+                /* Fill the buffer with the contents of the data register */
+                /* These is potential for buffer overflow here, so we should
+                 * really store the size of the array. This is expensive in
+                 * the ISR so left out for now. We must trust the implementor!
+                 */
+                dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR;
+                dev->i2c_slave_msg->length++;
+            }
+            else  {
+                /* Call the callback with the contents of the data */
+                dev->i2c_slave_msg->data[0] = dev->regs->DR;
+                if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+            }
+            dev->state = I2C_STATE_SL_RX;
+            sr1 = sr2 = 0;
+        }
+
+        /* EV4: Slave has detected a STOP condition on the bus */
+        if (sr1 & I2C_SR1_STOPF) {
+            dev->regs->CR1 |= I2C_CR1_PE;
+
+            if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
+                (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
+
+                /* The callback with the data will happen on a NACK of the last data byte.
+                 * This is handled in the error IRQ (AF bit)
+                 */
+                /* Handle the case where the master misbehaves by sending no NACK */
+                if (dev->state != I2C_STATE_IDLE) {
+                    if (dev->state == I2C_STATE_SL_RX) {
+                        if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+                    }
+                    else {
+                        if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
+                    }
+                }
+            }
+
+            sr1 = sr2 = 0;
+            dev->state = I2C_STATE_IDLE;
+        }
+
+        return;
+    }
+    
+    /*
      * EV5: Start condition sent
      */
     if (sr1 & I2C_SR1_SB) {
@@ -447,6 +646,7 @@ void _i2c_irq_handler(i2c_dev *dev) {
             }
         }
     }
+
 }
 
 /*
@@ -456,10 +656,49 @@ void _i2c_irq_handler(i2c_dev *dev) {
 void _i2c_irq_error_handler(i2c_dev *dev) {
     I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2);
 
-    dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR |
+    dev->error_flags = dev->regs->SR1 & (I2C_SR1_BERR |
                                          I2C_SR1_ARLO |
                                          I2C_SR1_AF |
                                          I2C_SR1_OVR);
+
+    /* Are we in slave mode? */
+    if ((dev->regs->SR2 & I2C_SR2_MSL) != I2C_SR2_MSL) {
+        /* Check to see if the master device did a NAK on the last bit
+         * This is perfectly valid for a master to do this on the bus.
+         * We ignore this. Any further error processing takes us into dead
+         * loop waiting for the stop condition that will never arrive
+         */
+        if (dev->regs->SR1 & I2C_SR1_AF) {
+            /* Clear flags */
+            dev->regs->SR1 = 0;
+            dev->regs->SR2 = 0;
+            /* We need to write something to CR1 to clear the flag.
+             * This isn't really mentioned but seems important */
+            i2c_enable_ack(dev);
+
+            if (dev->state == I2C_STATE_SL_RX &&
+                dev->config_flags & I2C_SLAVE_USE_RX_BUFFER &&
+                dev->i2c_slave_msg->xferred > 0) {
+                /* Call the callback with the contents of the data */
+                if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+            }
+
+            dev->state = I2C_STATE_IDLE;
+            return;
+        }
+        /* Catch any other strange errors while in slave mode.
+         * I have seen BERR caused by an over fast master device
+         * as well as several overflows and arbitration failures.
+         * We are going to reset SR flags and carry on at this point which
+         * is not the best thing to do, but stops the bus locking up completely
+         * If we carry on below and send the stop bit, the code spins forever */
+        /* Clear flags */
+        dev->regs->SR1 = 0;
+        dev->regs->SR2 = 0;
+        dev->state = I2C_STATE_IDLE;
+        return;
+    }
+
     /* Clear flags */
     dev->regs->SR1 = 0;
     dev->regs->SR2 = 0;
@@ -507,3 +746,31 @@ static void set_ccr_trise(i2c_dev *dev, uint32 flags) {
     i2c_set_clk_control(dev, ccr);
     i2c_set_trise(dev, trise);
 }
+
+
+/**
+ * @brief callback for when the device acts as a slave. If using an rx buffer, this is triggered
+ * after the last byte, otherwise it is called for every incoming packet.
+ * @param dev I2C device
+ * @param msg The dev_msg to pass to the slave init code
+ * @param func The function pointer to call
+ */
+void i2c_slave_attach_recv_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_recv_callback_func func) {
+    dev->i2c_slave_recv_callback = func;
+    dev->i2c_slave_msg = msg;
+    msg->xferred = 0;
+}
+
+
+/**
+ * @brief callback for when the device acts as a slave. If using a tx buffer, this is triggered
+ * after the device is successsfully addressed with SLA+R.
+ * @param dev I2C device
+ * @param msg The dev_msg to pass to the slave init code
+ * @param func The function pointer to call
+ */
+void i2c_slave_attach_transmit_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_transmit_callback_func func) {
+    dev->i2c_slave_transmit_callback = func;
+    dev->i2c_slave_msg = msg;
+    msg->xferred = 0;
+}
diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h
index ff1c313..fbb4c09 100644
--- a/libmaple/include/libmaple/i2c.h
+++ b/libmaple/include/libmaple/i2c.h
@@ -29,12 +29,19 @@
  * @file libmaple/include/libmaple/i2c.h
  * @brief Inter-Integrated Circuit (I2C) peripheral support
  *
- * Currently master-only. Usage notes:
+ * Supports Master and Slave.
+ *  Master Usage notes:
  *
  * - Enable an I2C device with i2c_master_enable().
  * - Initialize an array of struct i2c_msg to suit the bus
  *   transactions (reads/writes) you wish to perform.
  * - Call i2c_master_xfer() to do the work.
+ *
+ * Slave Usage notes:
+ * - Enable I2C slave by calling i2c_slave_enable().
+ *   Check flags for usage. Enabling master also enabled slave.
+ * - initialise the i2c_msg struct and the data buffer
+ * - initialise the callback functions
  */
 
 #ifndef _LIBMAPLE_I2C_H_
@@ -93,6 +100,7 @@ typedef struct i2c_msg {
 
 #define I2C_MSG_READ            0x1
 #define I2C_MSG_10BIT_ADDR      0x2
+
     /**
      * Bitwise OR of:
      * - I2C_MSG_READ (write is default)
@@ -197,7 +205,12 @@ typedef struct i2c_msg {
 #define I2C_DUTY_16_9           0x2           // 16/9 duty ratio
 /* Flag 0x4 is reserved; DO NOT USE. */
 #define I2C_BUS_RESET           0x8           // Perform a bus reset
+#define I2C_SLAVE_USE_RX_BUFFER 0x10          // Use a buffered message when doing a slave recv
+#define I2C_SLAVE_USE_TX_BUFFER 0x20          // Use a buffered message when doing a slave transmit
+#define I2C_SLAVE_DUAL_ADDRESS  0x40          // Enable the dual slave address scheme
+#define I2C_SLAVE_GENERAL_CALL  0x80          // Enable the general call on address 0x00
 void i2c_master_enable(i2c_dev *dev, uint32 flags);
+void i2c_slave_enable(i2c_dev *dev, uint32 flags);
 
 #define I2C_ERROR_PROTOCOL      (-1)
 #define I2C_ERROR_TIMEOUT       (-2)
@@ -406,6 +419,53 @@ static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) {
     dev->regs->TRISE = trise;
 }
 
+/*
+ * Slave support
+ */
+
+/**
+ * @brief Enable Dual addressing mode to allow peripheral to have 2 addresses
+ * @param dev I2C device
+  */
+static inline void i2c_slave_dual_address_enable(i2c_dev *dev) {
+    dev->regs->OAR2 |= I2C_OAR2_ENDUAL;
+}
+
+/**
+ * @brief Enable General Call to allow the  unit to respond on addr 0x00
+ * @param dev I2C device
+  */
+static inline void i2c_slave_general_call_enable(i2c_dev *dev) {
+    dev->regs->CR1 |= I2C_CR1_ENGC;
+}
+
+/* callback functions */
+/* Callback handler for data received over the bus */
+void i2c_slave_attach_recv_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_recv_callback_func func);
+
+/* Callback handler for data being requested over the bus
+ * The callback function must call i2c_write to get the data over the bus
+ */
+void i2c_slave_attach_transmit_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_transmit_callback_func func);
+
+/**
+ * @brief Set the primary I2c slave address
+ * @param dev I2C device
+ * @param address the 8 or 10 bit i2c address
+  */
+static inline void i2c_slave_set_own_address(i2c_dev *dev, uint16 address) {
+    dev->regs->OAR1 = address <<1;
+}
+
+/**
+ * @brief Set the secondary I2c slave address
+ * @param dev I2C device
+ * @param address the 8 or 10 bit i2c address
+  */
+static inline void i2c_slave_set_own_address2(i2c_dev *dev, uint16 address) {
+dev->regs->OAR2 = (address <<1 ) | I2C_OAR2_ENDUAL;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/libmaple/include/libmaple/i2c_common.h b/libmaple/include/libmaple/i2c_common.h
index 17cabe3..93e17e2 100644
--- a/libmaple/include/libmaple/i2c_common.h
+++ b/libmaple/include/libmaple/i2c_common.h
@@ -52,9 +52,12 @@ typedef enum i2c_state {
     I2C_STATE_IDLE              = 1, /**< Idle */
     I2C_STATE_XFER_DONE         = 2, /**< Done with transfer */
     I2C_STATE_BUSY              = 3, /**< Busy */
+    I2C_STATE_SL_RX             = 4, /**< Slave receiving */
     I2C_STATE_ERROR             = -1 /**< Error occurred */
 } i2c_state;
 
+typedef void (*i2c_slave_recv_callback_func)(struct i2c_msg *);
+typedef void (*i2c_slave_transmit_callback_func)(struct i2c_msg *);
 /**
  * @brief I2C device type.
  */
@@ -88,6 +91,17 @@ typedef struct i2c_dev {
     nvic_irq_num ev_nvic_line;  /**< Event IRQ number */
     nvic_irq_num er_nvic_line;  /**< Error IRQ number */
     volatile i2c_state state;   /**< Device state */
+    uint32 config_flags;        /**< Configuration flags */
+
+    /*
+     * Slave implementation. Callback functions in this struct allow
+     * for a separate callback function for each I2C unit available onboard
+     */
+    i2c_slave_transmit_callback_func i2c_slave_transmit_callback;
+    i2c_slave_recv_callback_func i2c_slave_recv_callback;
+
+    struct i2c_msg *i2c_slave_msg; /* the message that the i2c slave will use */
+
 } i2c_dev;
 
 #endif