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authorMarti Bolivar <mbolivar@leaflabs.com>2012-06-19 15:25:00 -0400
committerMarti Bolivar <mbolivar@leaflabs.com>2012-06-22 14:06:09 -0400
commit1a4ac9190b22da2477b759a0a402dfed0811ca30 (patch)
tree0f433cde056374308a4f7b177943c095650efa88 /libmaple
parentbd5719db16f05dcc41ca1e148b07ed4837525104 (diff)
downloadlibrambutan-1a4ac9190b22da2477b759a0a402dfed0811ca30.tar.gz
librambutan-1a4ac9190b22da2477b759a0a402dfed0811ca30.zip
libmaple/i2c.h: Don't use BIT().
Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
Diffstat (limited to 'libmaple')
-rw-r--r--libmaple/include/libmaple/i2c.h80
1 files changed, 40 insertions, 40 deletions
diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h
index ffd0cfb..c77bd32 100644
--- a/libmaple/include/libmaple/i2c.h
+++ b/libmaple/include/libmaple/i2c.h
@@ -117,56 +117,56 @@ extern i2c_dev* const I2C2;
/* Control register 1 */
-#define I2C_CR1_SWRST BIT(15) // Software reset
-#define I2C_CR1_ALERT BIT(13) // SMBus alert
-#define I2C_CR1_PEC BIT(12) // Packet error checking
-#define I2C_CR1_POS BIT(11) // Acknowledge/PEC position
-#define I2C_CR1_ACK BIT(10) // Acknowledge enable
-#define I2C_CR1_START BIT(8) // Start generation
-#define I2C_CR1_STOP BIT(9) // Stop generation
-#define I2C_CR1_PE BIT(0) // Peripheral Enable
+#define I2C_CR1_SWRST (1U << 15) // Software reset
+#define I2C_CR1_ALERT (1U << 13) // SMBus alert
+#define I2C_CR1_PEC (1U << 12) // Packet error checking
+#define I2C_CR1_POS (1U << 11) // Acknowledge/PEC position
+#define I2C_CR1_ACK (1U << 10) // Acknowledge enable
+#define I2C_CR1_START (1U << 8) // Start generation
+#define I2C_CR1_STOP (1U << 9) // Stop generation
+#define I2C_CR1_PE (1U << 0) // Peripheral Enable
/* Control register 2 */
-#define I2C_CR2_LAST BIT(12) // DMA last transfer
-#define I2C_CR2_DMAEN BIT(11) // DMA requests enable
-#define I2C_CR2_ITBUFEN BIT(10) // Buffer interrupt enable
-#define I2C_CR2_ITEVTEN BIT(9) // Event interupt enable
-#define I2C_CR2_ITERREN BIT(8) // Error interupt enable
+#define I2C_CR2_LAST (1U << 12) // DMA last transfer
+#define I2C_CR2_DMAEN (1U << 11) // DMA requests enable
+#define I2C_CR2_ITBUFEN (1U << 10) // Buffer interrupt enable
+#define I2C_CR2_ITEVTEN (1U << 9) // Event interupt enable
+#define I2C_CR2_ITERREN (1U << 8) // Error interupt enable
#define I2C_CR2_FREQ 0xFFF // Peripheral input frequency
/* Clock control register */
-#define I2C_CCR_FS BIT(15) // Fast mode selection
-#define I2C_CCR_DUTY BIT(14) // 16/9 duty ratio
+#define I2C_CCR_FS (1U << 15) // Fast mode selection
+#define I2C_CCR_DUTY (1U << 14) // 16/9 duty ratio
#define I2C_CCR_CCR 0xFFF // Clock control bits
/* Status register 1 */
-#define I2C_SR1_SB BIT(0) // Start bit
-#define I2C_SR1_ADDR BIT(1) // Address sent/matched
-#define I2C_SR1_BTF BIT(2) // Byte transfer finished
-#define I2C_SR1_ADD10 BIT(3) // 10-bit header sent
-#define I2C_SR1_STOPF BIT(4) // Stop detection
-#define I2C_SR1_RXNE BIT(6) // Data register not empty
-#define I2C_SR1_TXE BIT(7) // Data register empty
-#define I2C_SR1_BERR BIT(8) // Bus error
-#define I2C_SR1_ARLO BIT(9) // Arbitration lost
-#define I2C_SR1_AF BIT(10) // Acknowledge failure
-#define I2C_SR1_OVR BIT(11) // Overrun/underrun
-#define I2C_SR1_PECERR BIT(12) // PEC Error in reception
-#define I2C_SR1_TIMEOUT BIT(14) // Timeout or Tlow error
-#define I2C_SR1_SMBALERT BIT(15) // SMBus alert
+#define I2C_SR1_SB (1U << 0) // Start bit
+#define I2C_SR1_ADDR (1U << 1) // Address sent/matched
+#define I2C_SR1_BTF (1U << 2) // Byte transfer finished
+#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent
+#define I2C_SR1_STOPF (1U << 4) // Stop detection
+#define I2C_SR1_RXNE (1U << 6) // Data register not empty
+#define I2C_SR1_TXE (1U << 7) // Data register empty
+#define I2C_SR1_BERR (1U << 8) // Bus error
+#define I2C_SR1_ARLO (1U << 9) // Arbitration lost
+#define I2C_SR1_AF (1U << 10) // Acknowledge failure
+#define I2C_SR1_OVR (1U << 11) // Overrun/underrun
+#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception
+#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error
+#define I2C_SR1_SMBALERT (1U << 15) // SMBus alert
/* Status register 2 */
-#define I2C_SR2_MSL BIT(0) // Master/slave
-#define I2C_SR2_BUSY BIT(1) // Bus busy
-#define I2C_SR2_TRA BIT(2) // Transmitter/receiver
-#define I2C_SR2_GENCALL BIT(4) // General call address
-#define I2C_SR2_SMBDEFAULT BIT(5) // SMBus device default address
-#define I2C_SR2_SMBHOST BIT(6) // SMBus host header
-#define I2C_SR2_DUALF BIT(7) // Dual flag
+#define I2C_SR2_MSL (1U << 0) // Master/slave
+#define I2C_SR2_BUSY (1U << 1) // Bus busy
+#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver
+#define I2C_SR2_GENCALL (1U << 4) // General call address
+#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address
+#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header
+#define I2C_SR2_DUALF (1U << 7) // Dual flag
#define I2C_SR2_PEC 0xFF00 // Packet error checking register
/*
@@ -176,10 +176,10 @@ extern i2c_dev* const I2C2;
void i2c_init(i2c_dev *dev);
/* I2C enable options */
-#define I2C_FAST_MODE BIT(0) // 400 khz
-#define I2C_DUTY_16_9 BIT(1) // 16/9 duty ratio
-#define I2C_REMAP BIT(2) // Use alternate pin mapping
-#define I2C_BUS_RESET BIT(3) // Perform a bus reset
+#define I2C_FAST_MODE 0x1 // 400 khz
+#define I2C_DUTY_16_9 0x2 // 16/9 duty ratio
+#define I2C_REMAP 0x4 // Use alternate pin mapping
+#define I2C_BUS_RESET 0x8 // Perform a bus reset
void i2c_master_enable(i2c_dev *dev, uint32 flags);
#define I2C_ERROR_PROTOCOL (-1)