Flash refactor

2 files changed, 107 insertions, 30 deletions

diff --git a/libmaple/flash.c b/libmaple/flash.c
index 1d7bfa6..c921256 100644
--- a/libmaple/flash.c
+++ b/libmaple/flash.c
@@ -28,41 +28,30 @@
 
 #include "libmaple.h"
 #include "flash.h"
-
-/* flash registers  */
-#define FLASH_BASE                      0x40022000
-#define FLASH_ACR                       FLASH_BASE
-
-/* flash prefetcher  */
-#define ACR_PRFTBE                      BIT(4)
-#define ACR_PRFTBE_ENABLE               BIT(4)
-
-/* flash wait states  */
-#define ACR_LATENCY                     (0x7)
-
-#define FLASH_WRITE_ACR(val)            __write(FLASH_ACR, val)
-#define FLASH_READ_ACR()                __read(FLASH_ACR)
+#include "bitband.h"
 
 /**
- * @brief turn on the hardware prefetcher
+ * @brief Turn on the hardware prefetcher.
  */
 void flash_enable_prefetch(void) {
-    uint32 val = FLASH_READ_ACR();
-
-    val |= ACR_PRFTBE_ENABLE;
-
-    FLASH_WRITE_ACR(val);
+    *bb_perip(&FLASH_BASE->ACR, FLASH_ACR_PRFTBE_BIT) = 1;
 }
 
 /**
- * @brief set flash wait states
- * @param number of wait states
+ * @brief Set flash wait states
+ *
+ * See ST PM0042, section 3.1 for restrictions on the acceptable value
+ * of wait_states for a given SYSCLK configuration.
+ *
+ * @param wait_states number of wait states (one of
+ *                    FLASH_WAIT_STATE_0, FLASH_WAIT_STATE_1,
+ *                    FLASH_WAIT_STATE_2).
  */
 void flash_set_latency(uint32 wait_states) {
-    uint32 val = FLASH_READ_ACR();
+    uint32 val = FLASH_BASE->ACR;
 
-    val &= ~ACR_LATENCY;
+    val &= ~FLASH_ACR_LATENCY;
     val |= wait_states;
 
-    FLASH_WRITE_ACR(val);
+    FLASH_BASE->ACR = val;
 }
diff --git a/libmaple/flash.h b/libmaple/flash.h
index 7b74c83..9db5015 100644
--- a/libmaple/flash.h
+++ b/libmaple/flash.h
@@ -25,20 +25,108 @@
 
 /**
  * @file flash.h
- * @brief basic stm32 flash setup routines
+ * @brief STM32 Medium and high density Flash register map and setup
+ * routines
  */
 
 #ifndef _FLASH_H_
 #define _FLASH_H_
 
-#define FLASH_WAIT_STATE_0              0x0
-#define FLASH_WAIT_STATE_1              0x1
-#define FLASH_WAIT_STATE_2              0x2
-
 #ifdef __cplusplus
 extern "C"{
 #endif
 
+/** Flash register map type */
+typedef struct flash_reg_map {
+    __io uint32 ACR;            /**< Access control register */
+    __io uint32 KEYR;           /**< Key register */
+    __io uint32 OPTKEYR;        /**< OPTKEY register */
+    __io uint32 SR;             /**< Status register */
+    __io uint32 CR;             /**< Control register */
+    __io uint32 AR;             /**< Address register */
+    __io uint32 OBR;            /**< Option byte register */
+    __io uint32 WRPR;           /**< Write protection register */
+} flash_reg_map;
+
+/** Flash register map base pointer */
+#define FLASH_BASE                      ((flash_reg_map*)0x40022000)
+
+/*
+ * Register bit definitions
+ */
+
+/* Access control register */
+
+#define FLASH_ACR_PRFTBS_BIT            5
+#define FLASH_ACR_PRFTBE_BIT            4
+#define FLASH_ACR_HLFCYA_BIT            3
+
+#define FLASH_ACR_PRFTBS                BIT(FLASH_ACR_PRFTBS_BIT)
+#define FLASH_ACR_PRFTBE                BIT(FLASH_ACR_PRFTBE_BIT)
+#define FLASH_ACR_HLFCYA                BIT(FLASH_ACR_HLFCYA_BIT)
+#define FLASH_ACR_LATENCY               0x7
+
+/* Status register */
+
+#define FLASH_SR_EOP_BIT                5
+#define FLASH_SR_WRPRTERR_BIT           4
+#define FLASH_SR_PGERR_BIT              2
+#define FLASH_SR_BSY_BIT                0
+
+#define FLASH_SR_EOP                    BIT(FLASH_SR_EOP_BIT)
+#define FLASH_SR_WRPRTERR               BIT(FLASH_SR_WRPRTERR_BIT)
+#define FLASH_SR_PGERR                  BIT(FLASH_SR_PGERR_BIT)
+#define FLASH_SR_BSY                    BIT(FLASH_SR_BSY_BIT)
+
+/* Control register */
+
+#define FLASH_CR_EOPIE_BIT              12
+#define FLASH_CR_ERRIE_BIT              10
+#define FLASH_CR_OPTWRE_BIT             9
+#define FLASH_CR_LOCK_BIT               7
+#define FLASH_CR_STRT_BIT               6
+#define FLASH_CR_OPTER_BIT              5
+#define FLASH_CR_OPTPG_BIT              4
+#define FLASH_CR_MER_BIT                2
+#define FLASH_CR_PER_BIT                1
+#define FLASH_CR_PG_BIT                 0
+
+#define FLASH_CR_EOPIE                  BIT(FLASH_CR_EOPIE_BIT)
+#define FLASH_CR_ERRIE                  BIT(FLASH_CR_ERRIE_BIT)
+#define FLASH_CR_OPTWRE                 BIT(FLASH_CR_OPTWRE_BIT)
+#define FLASH_CR_LOCK                   BIT(FLASH_CR_LOCK_BIT)
+#define FLASH_CR_STRT                   BIT(FLASH_CR_STRT_BIT)
+#define FLASH_CR_OPTER                  BIT(FLASH_CR_OPTER_BIT)
+#define FLASH_CR_OPTPG                  BIT(FLASH_CR_OPTPG_BIT)
+#define FLASH_CR_MER                    BIT(FLASH_CR_MER_BIT)
+#define FLASH_CR_PER                    BIT(FLASH_CR_PER_BIT)
+#define FLASH_CR_PG                     BIT(FLASH_CR_PG_BIT)
+
+/* Option byte register */
+
+#define FLASH_OBR_nRST_STDBY_BIT        4
+#define FLASH_OBR_nRST_STOP_BIT         3
+#define FLASH_OBR_WDG_SW_BIT            2
+#define FLASH_OBR_RDPRT_BIT             1
+#define FLASH_OBR_OPTERR_BIT            0
+
+#define FLASH_OBR_DATA1                 (0xFF << 18)
+#define FLASH_OBR_DATA0                 (0xFF << 10)
+#define FLASH_OBR_USER                  0x3FF
+#define FLASH_OBR_nRST_STDBY            BIT(FLASH_OBR_nRST_STDBY_BIT)
+#define FLASH_OBR_nRST_STOP             BIT(FLASH_OBR_nRST_STOP_BIT)
+#define FLASH_OBR_WDG_SW                BIT(FLASH_OBR_WDG_SW_BIT)
+#define FLASH_OBR_RDPRT                 BIT(FLASH_OBR_RDPRT_BIT)
+#define FLASH_OBR_OPTERR                BIT(FLASH_OBR_OPTERR_BIT)
+
+/*
+ * Setup routines
+ */
+
+#define FLASH_WAIT_STATE_0              0x0
+#define FLASH_WAIT_STATE_1              0x1
+#define FLASH_WAIT_STATE_2              0x2
+
 void flash_enable_prefetch(void);
 void flash_set_latency(uint32 wait_states);