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authorMarti Bolivar <mbolivar@leaflabs.com>2011-07-21 15:22:19 -0400
committerMarti Bolivar <mbolivar@leaflabs.com>2011-07-21 15:22:19 -0400
commit722b31d62740de47b417708a7428673faf3d4cab (patch)
tree0df1d765dcbf9698f56aff5698e3da7bb67e8ca0 /libmaple
parente65a05a9f556b96b9d061dc394c022ba21c1c7b4 (diff)
downloadlibrambutan-722b31d62740de47b417708a7428673faf3d4cab.tar.gz
librambutan-722b31d62740de47b417708a7428673faf3d4cab.zip
timer.c: Minor IRQ dispatch tweaks.
Read TIMx_SR before grabbing a pointer to the user handlers instead of after. This should shave a couple of cycles off of the time between IRQ entry and SR read.
Diffstat (limited to 'libmaple')
-rw-r--r--libmaple/timer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/libmaple/timer.c b/libmaple/timer.c
index 951baf4..83e9ace 100644
--- a/libmaple/timer.c
+++ b/libmaple/timer.c
@@ -350,8 +350,8 @@ static inline void dispatch_adv_up(timer_dev *dev) {
static inline void dispatch_adv_trg_com(timer_dev *dev) {
timer_adv_reg_map *regs = (dev->regs).adv;
- void (**hs)(void) = dev->handlers;
uint32 dsr = regs->DIER & regs->SR;
+ void (**hs)(void) = dev->handlers;
uint32 handled = 0; /* Logical OR of SR interrupt flags we end up
* handling. We clear these. User handlers
* must clear overcapture flags, to avoid
@@ -365,8 +365,8 @@ static inline void dispatch_adv_trg_com(timer_dev *dev) {
static inline void dispatch_adv_cc(timer_dev *dev) {
timer_adv_reg_map *regs = (dev->regs).adv;
- void (**hs)(void) = dev->handlers;
uint32 dsr = regs->DIER & regs->SR;
+ void (**hs)(void) = dev->handlers;
uint32 handled = 0;
handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled);
@@ -379,8 +379,8 @@ static inline void dispatch_adv_cc(timer_dev *dev) {
static inline void dispatch_general(timer_dev *dev) {
timer_gen_reg_map *regs = (dev->regs).gen;
- void (**hs)(void) = dev->handlers;
uint32 dsr = regs->DIER & regs->SR;
+ void (**hs)(void) = dev->handlers;
uint32 handled = 0;
handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled);