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authorbnewbold <bnewbold@robocracy.org>2010-08-05 20:58:51 -0400
committerbnewbold <bnewbold@robocracy.org>2010-08-05 21:47:47 -0400
commit314846bee32479f8fd6aae46c508fdc7ff8e0a95 (patch)
treed3271e5239fb972bcc73803de9c10cf9f4d318e6 /libmaple
parent0f55cc0d89dc018aa1a2e7ad1c926889f98ec26d (diff)
downloadlibrambutan-314846bee32479f8fd6aae46c508fdc7ff8e0a95.tar.gz
librambutan-314846bee32479f8fd6aae46c508fdc7ff8e0a95.zip
Partially working!
Documented; see ./notes/fsmc.txt. Not yet integrated into .ld scripts or fully tested
Diffstat (limited to 'libmaple')
-rw-r--r--libmaple/exc.c1
-rw-r--r--libmaple/fsmc.c25
2 files changed, 15 insertions, 11 deletions
diff --git a/libmaple/exc.c b/libmaple/exc.c
index 3d01492..dd02476 100644
--- a/libmaple/exc.c
+++ b/libmaple/exc.c
@@ -38,7 +38,6 @@ void NMIException(void) {
}
void HardFaultException(void) {
- return;
ASSERT(0);
while(1)
;
diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c
index 17431f5..4e25ef6 100644
--- a/libmaple/fsmc.c
+++ b/libmaple/fsmc.c
@@ -28,12 +28,14 @@
#include "gpio.h"
#include "fsmc.h"
-#define FSMC_ADDSET 0x5
-#define FSMC_DATAST 0x5
-
-// Setup the FSMC peripheral to use the SRAM chip on the maple native
-// as an external segment of memory space.
-// This is for the IS62WV51216BLL 8meg 55ns chip
+// These values determined for a particular SRAM chip by following the
+// calculations in the ST FSMC application note.
+#define FSMC_ADDSET 0x0
+#define FSMC_DATAST 0x3
+
+// Sets up the FSMC peripheral to use the SRAM chip on the maple native as an
+// external segment of system memory space.
+// This implementation is for the IS62WV51216BLL 8mbit chip (55ns timing)
void fsmc_native_sram_init(void) {
FSMC_Bank *bank;
@@ -87,8 +89,8 @@ void fsmc_native_sram_init(void) {
gpio_set_mode(GPIOE_BASE, 0, MODE_AF_OUTPUT_PP); // NBL0
gpio_set_mode(GPIOE_BASE, 1, MODE_AF_OUTPUT_PP); // NBL1
- // Then we configure the FSMC SRAM channel 1 peripheral
- // (the SRAM part of the FSMC is "bank 1")
+ // Then we configure channel 1 the FSMC SRAM peripheral
+ // (all SRAM channels are in "Bank 1" of the FSMC)
bank = (FSMC_Bank*)(FSMC1_BASE);
// Everything else is cleared (BCR1)
@@ -104,6 +106,9 @@ void fsmc_native_sram_init(void) {
// Memory is nonmultiplexed
bank->BCR &= ~(FSMC_BCR_MUXEN); // '0'
+ // Need write enable to write to the chip
+ bank->BCR |= FSMC_BCR_WREN;
+
// Set ADDSET
bank->BTR &= ~(FSMC_BTR_ADDSET);
bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET);
@@ -112,9 +117,9 @@ void fsmc_native_sram_init(void) {
bank->BTR &= ~(FSMC_BTR_DATAST);
bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8));
- // Enable bank1
+ // Enable channel 1
bank->BCR |= FSMC_BCR_MBKEN; // '1'
- // FSMC_BWTR3 not used
+ // FSMC_BWTR3 not used for this simple configuration.
}