RCC: Add new mechanism for configuring the main PLL.

The new style for configuring the PLL is to initialize
a (series-specific) struct rcc_pll_cfg, and pass a pointer to it to
rcc_configure_pll(). After that's done, you can use
rcc_turn_on_clk(RCC_CLK_PLL) to turn on the main PLL, and busy-wait
until rcc_is_clk_ready(RCC_CLK_PLL) is true to make sure the new
configuration took effect.

- libmaple/rcc.h:

  -- Add struct rcc_pll_cfg, which specifies a PLL configuration. This
     specifies a PLL source and a void pointer to series-specific PLL
     configuration data.

  -- Add rcc_configure_pll(), which takes a pointer to struct
     rcc_pll_cfg, and configures the main PLL. It's up to each series
     to define this function.

- stm32f1/rcc.h: Add struct stm32f1_rcc_pll_data, to store F1-specific
  PLL configuration state.

- stm32f1/rcc.c: Add an implementation for rcc_configure_pll().

- stm32f2/rcc.h: Add struct stm32f2_rcc_pll_data, to store F2-specific
  PLL configuration data.

- stm32f2/rcc.c: Add an implementation for rcc_configure_pll().

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

1 files changed, 34 insertions, 0 deletions

diff --git a/libmaple/stm32f2/rcc.c b/libmaple/stm32f2/rcc.c
index 7bc220d..b94f2e6 100644
--- a/libmaple/stm32f2/rcc.c
+++ b/libmaple/stm32f2/rcc.c
@@ -160,3 +160,37 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
     };
     rcc_do_set_prescaler(masks, prescaler, divider);
 }
+
+/**
+ * @brief Configure the main PLL.
+ *
+ * You may only call this function while the PLL is disabled.
+ *
+ * @param pll_cfg Desired PLL configuration. The data field must point
+ *                to a valid struct stm32f2_rcc_pll_data.
+ */
+void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
+    stm32f2_rcc_pll_data *data = pll_cfg->data;
+    uint32 pllcfgr;
+
+    /* Sanity-check all the parameters */
+    ASSERT_FAULT((data->pllq >= 4) && (data->pllq <= 15));
+    ASSERT_FAULT((data->pllp >= 2) && (data->pllp <= 8));
+    ASSERT_FAULT(!(data->pllp & 1));
+    ASSERT_FAULT((data->plln >= 192) && (data->plln <= 432));
+    ASSERT_FAULT((data->pllm >= 2) && (data->pllm <= 63));
+
+    /* Update RCC_PLLCFGR to reflect new values. */
+    pllcfgr = RCC_BASE->PLLCFGR;
+    pllcfgr &= ~(RCC_PLLCFGR_PLLQ |
+                 RCC_PLLCFGR_PLLP |
+                 RCC_PLLCFGR_PLLN |
+                 RCC_PLLCFGR_PLLM |
+                 RCC_PLLCFGR_PLLSRC);
+    pllcfgr |= (pll_cfg->pllsrc |
+                (data->pllq << 24) |
+                (((data->pllp >> 1) - 1) << 16) |
+                (data->plln << 6) |
+                data->pllm);
+    RCC_BASE->PLLCFGR = pllcfgr;
+}