Merge branch 'wip-family-support'

Merge the long-lived (too long; future changes like these will need to
proceed more incrementally) development branch of libmaple, containing
experimental STM32F2 and STM32F1 value line support, into master.

This required many changes to the structure of the library. The most
important structural reorganizations occurred in:

- 954f9e5: moves public headers to include directories
- 3efa313: uses "series" instead of "family"
- c0d60e3: adds board files to the build system, to make it easier to
  add new boards
- 096d86c: adds build logic for targeting different STM32 series
  (e.g. STM32F1, STM32F2)

This last commit in particular (096d86c) is the basis for the
repartitioning of libmaple into portable sections, which work on all
supported MCUs, and nonportable sections, which are segregated into
separate directories and contain all series-specific code. Moving
existing STM32F1-only code into libmaple/stm32f1 and wirish/stm32f1,
along with adding equivalents under .../stm32f2 directories, was the
principal project of this branch.

Important API changes occur in several places. Existing code is still
expected to work on STM32F1 targets, but there have been many
deprecations. A detailed changelog explaining the situation needs to
be prepared.

F2 and F1 value line support is not complete; the merge is proceeding
prematurely in this respect. We've been getting more libmaple patches
from the community lately, and I'm worried that the merge conflicts
with the old tree structure will become painful to manage.

Conflicts:
	Makefile

Resolved Makefile conflicts manually; this required propagating
-Xlinker usage into support/make/target-config.mk.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

1 files changed, 116 insertions, 0 deletions

diff --git a/libmaple/stm32f1/performance/vector_table.S b/libmaple/stm32f1/performance/vector_table.S
new file mode 100644
index 0000000..b489b94
--- /dev/null
+++ b/libmaple/stm32f1/performance/vector_table.S
@@ -0,0 +1,116 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/* STM32F1 performance line vector table */
+
+	.section	".stm32.interrupt_vector"
+
+	.globl	__stm32_vector_table
+	.type	__stm32_vector_table, %object
+
+__stm32_vector_table:
+/* CM3 core interrupts */
+	.long	__msp_init
+	.long	__exc_reset
+	.long	__exc_nmi
+	.long	__exc_hardfault
+	.long	__exc_memmanage
+	.long	__exc_busfault
+	.long	__exc_usagefault
+	.long	__stm32reservedexception7
+	.long	__stm32reservedexception8
+	.long	__stm32reservedexception9
+	.long	__stm32reservedexception10
+	.long	__exc_svc
+	.long	__exc_debug_monitor
+	.long	__stm32reservedexception13
+	.long	__exc_pendsv
+	.long	__exc_systick
+/* Peripheral interrupts */
+	.long	__irq_wwdg
+	.long	__irq_pvd
+	.long	__irq_tamper
+	.long	__irq_rtc
+	.long	__irq_flash
+	.long	__irq_rcc
+	.long	__irq_exti0
+	.long	__irq_exti1
+	.long	__irq_exti2
+	.long	__irq_exti3
+	.long	__irq_exti4
+	.long	__irq_dma1_channel1
+	.long	__irq_dma1_channel2
+	.long	__irq_dma1_channel3
+	.long	__irq_dma1_channel4
+	.long	__irq_dma1_channel5
+	.long	__irq_dma1_channel6
+	.long	__irq_dma1_channel7
+	.long	__irq_adc
+	.long	__irq_usb_hp_can_tx
+	.long	__irq_usb_lp_can_rx0
+	.long	__irq_can_rx1
+	.long	__irq_can_sce
+	.long	__irq_exti9_5
+	.long	__irq_tim1_brk
+	.long	__irq_tim1_up
+	.long	__irq_tim1_trg_com
+	.long	__irq_tim1_cc
+	.long	__irq_tim2
+	.long	__irq_tim3
+	.long	__irq_tim4
+	.long	__irq_i2c1_ev
+	.long	__irq_i2c1_er
+	.long	__irq_i2c2_ev
+	.long	__irq_i2c2_er
+	.long	__irq_spi1
+	.long	__irq_spi2
+	.long	__irq_usart1
+	.long	__irq_usart2
+	.long	__irq_usart3
+	.long	__irq_exti15_10
+	.long	__irq_rtcalarm
+	.long	__irq_usbwakeup
+#if defined (STM32_HIGH_DENSITY)
+	.long	__irq_tim8_brk
+	.long	__irq_tim8_up
+	.long	__irq_tim8_trg_com
+	.long	__irq_tim8_cc
+	.long	__irq_adc3
+	.long	__irq_fsmc
+	.long	__irq_sdio
+	.long	__irq_tim5
+	.long	__irq_spi3
+	.long	__irq_uart4
+	.long	__irq_uart5
+	.long	__irq_tim6
+	.long	__irq_tim7
+	.long	__irq_dma2_channel1
+	.long	__irq_dma2_channel2
+	.long	__irq_dma2_channel3
+	.long	__irq_dma2_channel4_5
+#endif /* STM32_HIGH_DENSITY */
+
+	.size	__stm32_vector_table, . - __stm32_vector_table