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| author | Marti Bolivar <mbolivar@leaflabs.com> | 2012-06-19 17:29:10 -0400 |
|---|---|---|
| committer | Marti Bolivar <mbolivar@leaflabs.com> | 2012-06-22 14:06:09 -0400 |
| commit | e9574e9c9bc91a8213d1292c8fcab8a7a93aeb2b (patch) | |
| tree | 9f6be409b0718cec131d73bbd4b97fcecff6fac9 /libmaple/include | |
| parent | fb683bcc19e48e33c9f9310d2debb8d9e51496db (diff) | |
| download | librambutan-e9574e9c9bc91a8213d1292c8fcab8a7a93aeb2b.tar.gz librambutan-e9574e9c9bc91a8213d1292c8fcab8a7a93aeb2b.zip | |
<libmaple/i2c.h>: Cosmetics.
Reorder register bit definitions by descending bit number, for
consistency with the rest of the library.
Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
Diffstat (limited to 'libmaple/include')
| -rw-r--r-- | libmaple/include/libmaple/i2c.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/libmaple/include/libmaple/i2c.h b/libmaple/include/libmaple/i2c.h index 26a0b65..f27f8eb 100644 --- a/libmaple/include/libmaple/i2c.h +++ b/libmaple/include/libmaple/i2c.h @@ -166,31 +166,31 @@ extern i2c_dev* const I2C2; /* Status register 1 */ -#define I2C_SR1_SB (1U << 0) // Start bit -#define I2C_SR1_ADDR (1U << 1) // Address sent/matched -#define I2C_SR1_BTF (1U << 2) // Byte transfer finished -#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent -#define I2C_SR1_STOPF (1U << 4) // Stop detection -#define I2C_SR1_RXNE (1U << 6) // Data register not empty -#define I2C_SR1_TXE (1U << 7) // Data register empty -#define I2C_SR1_BERR (1U << 8) // Bus error -#define I2C_SR1_ARLO (1U << 9) // Arbitration lost -#define I2C_SR1_AF (1U << 10) // Acknowledge failure -#define I2C_SR1_OVR (1U << 11) // Overrun/underrun -#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception -#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error #define I2C_SR1_SMBALERT (1U << 15) // SMBus alert +#define I2C_SR1_TIMEOUT (1U << 14) // Timeout or Tlow error +#define I2C_SR1_PECERR (1U << 12) // PEC Error in reception +#define I2C_SR1_OVR (1U << 11) // Overrun/underrun +#define I2C_SR1_AF (1U << 10) // Acknowledge failure +#define I2C_SR1_ARLO (1U << 9) // Arbitration lost +#define I2C_SR1_BERR (1U << 8) // Bus error +#define I2C_SR1_TXE (1U << 7) // Data register empty +#define I2C_SR1_RXNE (1U << 6) // Data register not empty +#define I2C_SR1_STOPF (1U << 4) // Stop detection +#define I2C_SR1_ADD10 (1U << 3) // 10-bit header sent +#define I2C_SR1_BTF (1U << 2) // Byte transfer finished +#define I2C_SR1_ADDR (1U << 1) // Address sent/matched +#define I2C_SR1_SB (1U << 0) // Start bit /* Status register 2 */ -#define I2C_SR2_MSL (1U << 0) // Master/slave -#define I2C_SR2_BUSY (1U << 1) // Bus busy -#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver -#define I2C_SR2_GENCALL (1U << 4) // General call address -#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address -#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header -#define I2C_SR2_DUALF (1U << 7) // Dual flag #define I2C_SR2_PEC 0xFF00 // Packet error checking register +#define I2C_SR2_DUALF (1U << 7) // Dual flag +#define I2C_SR2_SMBHOST (1U << 6) // SMBus host header +#define I2C_SR2_SMBDEFAULT (1U << 5) // SMBus device default address +#define I2C_SR2_GENCALL (1U << 4) // General call address +#define I2C_SR2_TRA (1U << 2) // Transmitter/receiver +#define I2C_SR2_BUSY (1U << 1) // Bus busy +#define I2C_SR2_MSL (1U << 0) // Master/slave /* * Convenience routines |