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| author | Marti Bolivar <mbolivar@leaflabs.com> | 2012-03-26 19:27:37 -0400 |
|---|---|---|
| committer | Marti Bolivar <mbolivar@leaflabs.com> | 2012-04-11 16:56:55 -0400 |
| commit | b70544a1fd713db6c9fb2cef773da2029cdc8c70 (patch) | |
| tree | 4f3159d2e4d4c360458cf9210c2c2ab572eaebdb /libmaple/include | |
| parent | 66f75ca74ea11d0c242bd3773a7b31f07030c8e7 (diff) | |
| download | librambutan-b70544a1fd713db6c9fb2cef773da2029cdc8c70.tar.gz librambutan-b70544a1fd713db6c9fb2cef773da2029cdc8c70.zip | |
libmaple/pwr.h: Fix register bits (breaking change).
This is a backwards-incompatible change. It is necessary to fix an
error.
The register bit definitions are given as if they were masks, but
they're actually bit numbers. E.g., PWR_CR_DBP, which should be the
mask for DBP in the power control register PWR_CR, is actually the
number of the bit that should be masked.
Fix this by adding _BIT to the definitions and adding proper
masks. Also add a mask for the PVD level selection bits in
PWR_CSR. Don't add any mask values for particular voltages selected as
these are not portable.
Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
Diffstat (limited to 'libmaple/include')
| -rw-r--r-- | libmaple/include/libmaple/pwr.h | 44 |
1 files changed, 34 insertions, 10 deletions
diff --git a/libmaple/include/libmaple/pwr.h b/libmaple/include/libmaple/pwr.h index 6836e7f..8841518 100644 --- a/libmaple/include/libmaple/pwr.h +++ b/libmaple/include/libmaple/pwr.h @@ -54,28 +54,52 @@ typedef struct pwr_reg_map { /* Control register */ /** Disable backup domain write protection bit */ -#define PWR_CR_DBP 8 +#define PWR_CR_DBP_BIT 8 /** Power voltage detector enable bit */ -#define PWR_CR_PVDE 4 +#define PWR_CR_PVDE_BIT 4 /** Clear standby flag bit */ -#define PWR_CR_CSBF 3 +#define PWR_CR_CSBF_BIT 3 /** Clear wakeup flag bit */ -#define PWR_CR_CWUF 2 +#define PWR_CR_CWUF_BIT 2 /** Power down deepsleep bit */ -#define PWR_CR_PDDS 1 +#define PWR_CR_PDDS_BIT 1 /** Low-power deepsleep bit */ -#define PWR_CR_LPDS 0 +#define PWR_CR_LPDS_BIT 0 + +/** Disable backup domain write protection */ +#define PWR_CR_DBP (1U << PWR_CR_DBP_BIT) +/** Power voltage detector (PVD) level selection */ +#define PWR_CR_PLS (0x7 << 5) +/** Power voltage detector enable */ +#define PWR_CR_PVDE (1U << PWR_CR_PVDE_BIT) +/** Clear standby flag */ +#define PWR_CR_CSBF (1U << PWR_CR_CSBF_BIT) +/** Clear wakeup flag */ +#define PWR_CR_CWUF (1U << PWR_CR_CWUF_BIT) +/** Power down deepsleep */ +#define PWR_CR_PDDS (1U << PWR_CR_PDDS_BIT) +/** Low-power deepsleep */ +#define PWR_CR_LPDS (1U << PWR_CR_LPDS_BIT) /* Control and status register */ /** Enable wakeup pin bit */ -#define PWR_CSR_EWUP 8 +#define PWR_CSR_EWUP_BIT 8 /** PVD output bit */ -#define PWR_CSR_PVDO 2 +#define PWR_CSR_PVDO_BIT 2 /** Standby flag bit */ -#define PWR_CSR_SBF 1 +#define PWR_CSR_SBF_BIT 1 /** Wakeup flag bit */ -#define PWR_CSR_WUF 0 +#define PWR_CSR_WUF_BIT 0 + +/** Enable wakeup pin */ +#define PWR_CSR_EWUP (1U << PWR_CSR_EWUP_BIT) +/** PVD output */ +#define PWR_CSR_PVDO (1U << PWR_CSR_PVDO_BIT) +/** Standby flag */ +#define PWR_CSR_SBF (1U << PWR_CSR_SBF_BIT) +/** Wakeup flag */ +#define PWR_CSR_WUF (1U << PWR_CSR_WUF_BIT) /* * Convenience functions |