Bring back libmaple/dac.h.

Minor variations on F2: DMA underrun interrupts, and a status register
to hold the notification bits.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

5 files changed, 228 insertions, 82 deletions

diff --git a/libmaple/dac.c b/libmaple/dac.c
index 5a00590..d802d2b 100644
--- a/libmaple/dac.c
+++ b/libmaple/dac.c
@@ -2,7 +2,7 @@
  * The MIT License
  *
  * Copyright (c) 2010 Bryan Newbold.
- * Copyright (c) 2011 LeafLabs, LLC.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -30,21 +30,16 @@
  * @brief Digital to analog converter support.
  */
 
+#include <libmaple/dac.h>
 #include <libmaple/libmaple.h>
 #include <libmaple/gpio.h>
-#include <libmaple/dac.h>
-
-#ifdef STM32_HIGH_DENSITY
-
-/**
- * @brief DAC peripheral routines.
- */
 
+#if STM32_HAVE_DAC
 dac_dev dac = {
     .regs = DAC_BASE,
 };
-/** DAC device. */
 const dac_dev *DAC = &dac;
+#endif
 
 /**
  * @brief Initialize the digital to analog converter
@@ -98,11 +93,11 @@ void dac_enable_channel(const dac_dev *dev, uint8 channel) {
      */
     switch (channel) {
     case 1:
-        gpio_set_mode(GPIOA, 4, GPIO_INPUT_ANALOG);
+        gpio_set_mode(GPIOA, 4, GPIO_MODE_ANALOG);
         dev->regs->CR |= DAC_CR_EN1;
         break;
     case 2:
-        gpio_set_mode(GPIOA, 5, GPIO_INPUT_ANALOG);
+        gpio_set_mode(GPIOA, 5, GPIO_MODE_ANALOG);
         dev->regs->CR |= DAC_CR_EN2;
         break;
     }
@@ -123,5 +118,3 @@ void dac_disable_channel(const dac_dev *dev, uint8 channel) {
         break;
     }
 }
-
-#endif  /* STM32_HIGH_DENSITY */
diff --git a/libmaple/include/libmaple/dac.h b/libmaple/include/libmaple/dac.h
index 047f874..56bfdc4 100644
--- a/libmaple/include/libmaple/dac.h
+++ b/libmaple/include/libmaple/dac.h
@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2011 LeafLabs, LLC.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
  * Copyright (c) 2010 Bryan Newbold.
  *
  * Permission is hereby granted, free of charge, to any person
@@ -39,124 +39,112 @@
 extern "C"{
 #endif
 
+#include <series/dac.h>
 #include <libmaple/libmaple_types.h>
 #include <libmaple/rcc.h>
+#include <libmaple/stm32.h>
 
 /*
- * Register maps
+ * Register map base and device pointers.
+ *
+ * The DACs are the same on all supported targets, so it's not worth
+ * repeating these in the series headers.
  */
 
-/** DAC register map. */
-typedef struct dac_reg_map {
-    __io uint32 CR;      /**< Control register */
-    __io uint32 SWTRIGR; /**< Software trigger register */
-    __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
-                              holding register */
-    __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
-                              holding register */
-    __io uint32 DHR8R1;  /**< Channel 1 8-bit left-aligned data
-                              holding register */
-    __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
-                              holding register */
-    __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
-                              holding register */
-    __io uint32 DHR8R2;  /**< Channel 2 8-bit left-aligned data
-                              holding register */
-    __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
-                              holding register */
-    __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
-                              holding register */
-    __io uint32 DHR8RD;  /**< Dual DAC 8-bit right-aligned data holding
-                              register */
-    __io uint32 DOR1;    /**< Channel 1 data output register */
-    __io uint32 DOR2;    /**< Channel 2 data output register */
-} dac_reg_map;
-
-/** DAC register map base address */
 #define DAC_BASE                ((struct dac_reg_map*)0x40007400)
 
-/*
- * Devices
- */
-
 /** DAC device type. */
 typedef struct dac_dev {
     dac_reg_map *regs; /**< Register map */
 } dac_dev;
 
+#if STM32_HAVE_DAC
 extern const dac_dev *DAC;
+#endif
 
 /*
  * Register bit definitions
  */
 
 /* Control register */
+
 /* Channel 1 control */
-#define DAC_CR_EN1                   BIT(0) /* Enable */
-#define DAC_CR_BOFF1                 BIT(1) /* Output buffer disable */
-#define DAC_CR_TEN1                  BIT(2) /* Trigger enable */
-#define DAC_CR_TSEL1             (0x7 << 3) /* Trigger selection */
-#define DAC_CR_WAVE1             (0x3 << 6) /* Noise/triangle wave enable */
-#define DAC_CR_MAMP1             (0xF << 8) /* Mask/amplitude selector */
-#define DAC_CR_DMAEN1               BIT(12) /* DMA enable */
+#define DAC_CR_EN1                  (1U << 0)  /* Enable */
+#define DAC_CR_BOFF1                (1U << 1)  /* Output buffer disable */
+#define DAC_CR_TEN1                 (1U << 2)  /* Trigger enable */
+#define DAC_CR_TSEL1                (0x7 << 3) /* Trigger selection */
+#define DAC_CR_WAVE1                (0x3 << 6) /* Noise/triangle wave */
+#define DAC_CR_MAMP1                (0xF << 8) /* Mask/amplitude selector */
+#define DAC_CR_DMAEN1               (1U << 12) /* DMA enable */
 /* Channel 2 control */
-#define DAC_CR_EN2                  BIT(16) /* Enable */
-#define DAC_CR_BOFF2                BIT(17) /* Output buffer disable */
-#define DAC_CR_TEN2                 BIT(18) /* Trigger enable */
-#define DAC_CR_TSEL2            (0x7 << 19) /* Trigger selection */
-#define DAC_CR_WAVE2            (0x3 << 22) /* Noise/triangle wave generation*/
-#define DAC_CR_MAMP2            (0xF << 24) /* Mask/amplitude selector */
-#define DAC_CR_DMAEN2               BIT(28) /* DMA enable */
+#define DAC_CR_EN2                  (1U << 16)  /* Enable */
+#define DAC_CR_BOFF2                (1U << 17)  /* Output buffer disable */
+#define DAC_CR_TEN2                 (1U << 18)  /* Trigger enable */
+#define DAC_CR_TSEL2                (0x7 << 19) /* Trigger selection */
+#define DAC_CR_WAVE2                (0x3 << 22) /* Noise/triangle wave */
+#define DAC_CR_MAMP2                (0xF << 24) /* Mask/amplitude selector */
+#define DAC_CR_DMAEN2               (1U << 28)  /* DMA enable */
 
 /* Software trigger register */
-#define DAC_SWTRIGR_SWTRIG1          BIT(0) /* Channel 1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2          BIT(1) /* Channel 2 software trigger */
+
+#define DAC_SWTRIGR_SWTRIG1         (1U << 0) /* Channel 1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2         (1U << 1) /* Channel 2 software trigger */
 
 /* Channel 1 12-bit right-aligned data holding register */
-#define DAC_DHR12R1_DACC1DHR     0x00000FFF
+
+#define DAC_DHR12R1_DACC1DHR        0x00000FFF
 
 /* Channel 1 12-bit left-aligned data holding register */
-#define DAC_DHR12L1_DACC1DHR     0x0000FFF0
+
+#define DAC_DHR12L1_DACC1DHR        0x0000FFF0
 
 /* Channel 1 8-bit left-aligned data holding register */
-#define DAC_DHR8R1_DACC1DHR      0x000000FF
+
+#define DAC_DHR8R1_DACC1DHR         0x000000FF
 
 /* Channel 2 12-bit right-aligned data holding register */
-#define DAC_DHR12R2_DACC2DHR     0x00000FFF
+
+#define DAC_DHR12R2_DACC2DHR        0x00000FFF
 
 /* Channel 2 12-bit left-aligned data holding register */
-#define DAC_DHR12L2_DACC2DHR     0x0000FFF0
+
+#define DAC_DHR12L2_DACC2DHR        0x0000FFF0
 
 /* Channel 2 8-bit left-aligned data holding register */
-#define DAC_DHR8R2_DACC2DHR      0x000000FF
+
+#define DAC_DHR8R2_DACC2DHR         0x000000FF
 
 /* Dual DAC 12-bit right-aligned data holding register */
-#define DAC_DHR12RD_DACC1DHR     0x00000FFF
-#define DAC_DHR12RD_DACC2DHR     0x0FFF0000
+
+#define DAC_DHR12RD_DACC1DHR        0x00000FFF
+#define DAC_DHR12RD_DACC2DHR        0x0FFF0000
 
 /* Dual DAC 12-bit left-aligned data holding register */
-#define DAC_DHR12LD_DACC1DHR     0x0000FFF0
-#define DAC_DHR12LD_DACC2DHR     0xFFF00000
+
+#define DAC_DHR12LD_DACC1DHR        0x0000FFF0
+#define DAC_DHR12LD_DACC2DHR        0xFFF00000
 
 /* Dual DAC 8-bit left-aligned data holding register */
-#define DAC_DHR8RD_DACC1DHR      0x000000FF
-#define DAC_DHR8RD_DACC2DHR      0x0000FF00
+
+#define DAC_DHR8RD_DACC1DHR         0x000000FF
+#define DAC_DHR8RD_DACC2DHR         0x0000FF00
 
 /* Channel 1 data output register */
-#define DAC_DOR1_DACC1DOR        0x00000FFF
+
+#define DAC_DOR1_DACC1DOR           0x00000FFF
 
 /* Channel 1 data output register */
-#define DAC_DOR2_DACC2DOR        0x00000FFF
+
+#define DAC_DOR2_DACC2DOR           0x00000FFF
 
 /*
- * Convenience functions
+ * Routines
  */
 
-/* We take the dev argument in these convenience functions for
- * future-proofing */
+/* We take the dev argument in these for future-proofing */
 
-#define DAC_CH1                         0x1
-#define DAC_CH2                         0x2
+#define DAC_CH1 0x1
+#define DAC_CH2 0x2
 void dac_init(const dac_dev *dev, uint32 flags);
 
 void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val);
diff --git a/libmaple/rules.mk b/libmaple/rules.mk
index b39c318..08c4c02 100644
--- a/libmaple/rules.mk
+++ b/libmaple/rules.mk
@@ -12,6 +12,7 @@ CFLAGS_$(d) = $(LIBMAPLE_PRIVATE_INCLUDES) $(LIBMAPLE_INCLUDES) -Wall -Werror
 
 # Local rules and targets
 cSRCS_$(d) := adc.c
+cSRCS_$(d) += dac.c
 # cSRCS_$(d) += dma.c
 cSRCS_$(d) += exti.c
 cSRCS_$(d) += flash.c
@@ -28,7 +29,6 @@ cSRCS_$(d) += usart.c
 cSRCS_$(d) += usart_private.c
 cSRCS_$(d) += util.c
 # These still need to be brought back for F1:
-# cSRCS_$(d) += dac.c
 # cSRCS_$(d) += i2c.c
 
 sSRCS_$(d) := exc.S
diff --git a/libmaple/stm32f1/include/series/dac.h b/libmaple/stm32f1/include/series/dac.h
new file mode 100644
index 0000000..c0d026b
--- /dev/null
+++ b/libmaple/stm32f1/include/series/dac.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/include/series/dac.h
+ * @brief STM32F1 DAC support
+ */
+
+#ifndef _LIBMAPLE_STM32F1_DAC_H_
+#define _LIBMAPLE_STM32F1_DAC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+
+/** STM32F1 DAC register map type. */
+typedef struct dac_reg_map {
+    __io uint32 CR;      /**< Control register */
+    __io uint32 SWTRIGR; /**< Software trigger register */
+    __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8R1;  /**< Channel 1 8-bit left-aligned data
+                              holding register */
+    __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8R2;  /**< Channel 2 8-bit left-aligned data
+                              holding register */
+    __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8RD;  /**< Dual DAC 8-bit right-aligned data holding
+                              register */
+    __io uint32 DOR1;    /**< Channel 1 data output register */
+    __io uint32 DOR2;    /**< Channel 2 data output register */
+} dac_reg_map;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libmaple/stm32f2/include/series/dac.h b/libmaple/stm32f2/include/series/dac.h
new file mode 100644
index 0000000..0a578ca
--- /dev/null
+++ b/libmaple/stm32f2/include/series/dac.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f2/include/series/dac.h
+ * @brief STM32F2 DAC support
+ */
+
+#ifndef _LIBMAPLE_STM32F2_DAC_H_
+#define _LIBMAPLE_STM32F2_DAC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+
+/*
+ * Register map type
+ */
+
+/** STM32F2 DAC register map type. */
+typedef struct dac_reg_map {
+    __io uint32 CR;      /**< Control register */
+    __io uint32 SWTRIGR; /**< Software trigger register */
+    __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8R1;  /**< Channel 1 8-bit left-aligned data
+                              holding register */
+    __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8R2;  /**< Channel 2 8-bit left-aligned data
+                              holding register */
+    __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
+                              holding register */
+    __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
+                              holding register */
+    __io uint32 DHR8RD;  /**< Dual DAC 8-bit right-aligned data holding
+                              register */
+    __io uint32 DOR1;    /**< Channel 1 data output register */
+    __io uint32 DOR2;    /**< Channel 2 data output register */
+    __io uint32 SR;      /**< Status register */
+} dac_reg_map;
+
+/*
+ * Register bit definitions
+ */
+
+/* Control register */
+
+#define DAC_CR_DMAUDRIE1            (1U << 13) /* Channel 1 DMA underrun
+                                                * interrupt enable */
+#define DAC_CR_DMAUDRIE2            (1U << 29) /* Channel 2 DMA underrun
+                                                * interrupt enable */
+
+/* Status register */
+
+#define DAC_SR_DMAUDR1              (1U << 13) /* Channel 1 DMA underrun
+                                                * occurred */
+#define DAC_SR_DMAUDR2              (1U << 29) /* Channel 2 DMA underrun
+                                                * ocurred */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif