librambutan/libmaple, branch newprint

fix timer capture TI1/TI2 bug

2015-06-14T05:02:23Z

Somewhat confusingly, the TI1/TI2 fields for capture/compare channels 2 and 4 are both flipped compared to channels 1 and 3 and do not correspond to the binary numbers. Section 15.4.7 of RM0008 (STM32F1 series) and Section 12.4.7 of RM0368 (STM32F4 series) read: CC1S: Capture/Compare 1 selection 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 CC2S: Capture/Compare 2 selection 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 This commit closes github issue #12 reported by GatorCh.

squelch doxygen complaints about stm32f1 SPI header type signature

2015-06-14T03:28:01Z

stm32f2-f4: refactor header guards, doxygen comments

2015-06-14T03:28:01Z

stm32f2-f4: refactor internal doxygen file references

2015-06-14T03:28:01Z

F401RB is almost identical to F401CC

2015-06-12T10:16:03Z

stm32f2-f4: rcc.h: order RCC_TIMER* numerically, not alphabetically

2015-06-12T10:16:03Z

This avoids a bug with instantiating Wirish HardwareTimers.

Fix hang on usart read overrun.

2015-05-28T03:48:37Z

This is improved on the previous patch: if we get an ORE without RXNE when we don't write a junk byte to our buffer. It also avoids the strange-looking blind read. See issue #107 for more info. Signed-off-by: Joseph Birr-Pixton

stm32f4: add F4-specific IRQ entries

2015-03-03T08:15:30Z

Perhaps these should be in F4-specific files instead of the shared F2-F4 files?

stm32f4: note possibly incorrect max_baud entries

2015-03-03T08:15:30Z

stm32f4: begin filling out F4 suport in headers

2015-03-03T08:15:30Z