librambutan/libmaple, branch legacy

fix timer capture TI1/TI2 bug

2015-06-14T05:01:59Z

Somewhat confusingly, the TI1/TI2 fields for capture/compare channels 2 and 4 are both flipped compared to channels 1 and 3 and do not correspond to the binary numbers. Section 15.4.7 of RM0008 (STM32F1 series) and Section 12.4.7 of RM0368 (STM32F4 series) read: CC1S: Capture/Compare 1 selection 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 CC2S: Capture/Compare 2 selection 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 This commit closes github issue #12 reported by GatorCh.

squelch doxygen complaints about stm32f1 SPI header type signature

2015-06-14T04:23:05Z

libmaple_types.h: add ifndef guards for some macros

2015-05-28T03:51:39Z

Signed-off-by: Marti Bolivar

Revert "always clear ISR DMA bit before even calling handler"

2015-05-28T03:51:19Z

stm32f1: gpio.h: silence yet more __always_inline warnings

2015-05-28T03:50:57Z

Signed-off-by: Marti Bolivar

Fix hang on usart read overrun.

2015-05-28T03:49:27Z

This is improved on the previous patch: if we get an ORE without RXNE when we don't write a junk byte to our buffer. It also avoids the strange-looking blind read. See issue #107 for more info. Signed-off-by: Joseph Birr-Pixton

Removing redundant defines (see #85)

2014-02-21T22:38:28Z

Signed-off-by: Grégoire Passault

Adding support for cm900 and opencm904 boards (robotis)

2014-02-20T21:39:04Z

Signed-off-by: Grégoire Passault

Merge pull request #83 from wesen/bug/clear-dma-irq-flag-first

2014-02-06T13:32:09Z

always clear ISR DMA bit before even calling handler

2014-02-06T11:55:32Z