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| -rw-r--r-- | tmp/anonymization.txt | 13 | ||||
| -rw-r--r-- | tmp/c_coding | 4 | ||||
| -rw-r--r-- | tmp/qucs-debian-wheezy | 8 | ||||
| -rw-r--r-- | tmp/review_nonblocking_verilog_kill | 67 |
4 files changed, 92 insertions, 0 deletions
diff --git a/tmp/anonymization.txt b/tmp/anonymization.txt new file mode 100644 index 0000000..cb6fc86 --- /dev/null +++ b/tmp/anonymization.txt @@ -0,0 +1,13 @@ + +"Policy and Law: Identifiability of de-identified data" +(includes, specifically, medial) +http://latanyasweeney.org/work/identifiability.html + +EFF de-anon tool for browsers +Netflix/IMDB dataset +search query dataset + +"how many bits" type of identification + +https://en.wikipedia.org/wiki/Data_anonymization +https://en.wikipedia.org/wiki/De-anonymization diff --git a/tmp/c_coding b/tmp/c_coding new file mode 100644 index 0000000..68760f9 --- /dev/null +++ b/tmp/c_coding @@ -0,0 +1,4 @@ + +The Lost Art of C Structure Packing +http://www.catb.org/esr/structure-packing/ + diff --git a/tmp/qucs-debian-wheezy b/tmp/qucs-debian-wheezy new file mode 100644 index 0000000..b5d9714 --- /dev/null +++ b/tmp/qucs-debian-wheezy @@ -0,0 +1,8 @@ + +0.15.0 was in squeeze repo; seems to have "just worked"? + +Compiling 0.17.0 from scratch: +- needed: libgd-gd2-perl libxml-libxml-perl + (trying to use debian packages vs. CPAN versions) +- checkout 0.17 tag +- need to use the --enable-maintainer-mode, at least for qucs-core diff --git a/tmp/review_nonblocking_verilog_kill b/tmp/review_nonblocking_verilog_kill new file mode 100644 index 0000000..296f8c5 --- /dev/null +++ b/tmp/review_nonblocking_verilog_kill @@ -0,0 +1,67 @@ +to: team@leaflabs.com +subj: paper review: "Nonblocking Assignments in Verilog Synthesis..." + +TL;DR: this is something like a "goto considered harmful" w/r/t using confusing +blocking assignment in (non-sythesizable?) Verilog. + +# Context + +This paper was written in 2000 and seems to target Verilog programmers who +write non-synthesizable simulation code. Despite the word "Synthesis" in the +title. After reading, the implication that this paper might have any new +insights for an engineer whose failure might "kill" stikes fear in my gut. + +Apparently this won a "Best Paper" award at a conference back when it was +published. + +On page 15 there is a note about about synthesis performance: "The latter would +be inefficient from a simulation time perspective"; perhaps this was the +historical temptation of these bad practices? + +# Judgement + +There's really nothing new here (for jess/aj/bryan at least): for sequential +logic use nonblocking assignment in always@ blocks, and for combinatoral logic +use 'assign' statements outside of a block, unless you have something really +tight and complicated going on, in which case use an always block with a +carefully selected sensitivity list and all blocking assignments inside. + +# Nuggets + +From page 20: "Nonblocking assignments are updated after all $display +commands". I did not know this! The example given is pretty good; $strobe is +recommended as the alternative: + + module display_cmds; + reg a; + initial $monitor("\$monitor: a = %b", a); + initial begin + $strobe ("\$strobe : a = %b", a); + a = 0; + a <= 1; + $display ("\$display: a = %b", a); + #1 $finish; + end + endmodule + +gives: + + $display: a = 0 + $monitor: a = 1 + $strobe : a = 1 + +# Appendix: Verilog Coding Guidelines + +Verbatim from paper: + +1: When modeling sequential logic, use nonblocking assignments. +2: When modeling latches, use nonblocking assignments. +3: When modeling combinational logic with an always block, use blocking +. +4: When modeling both sequential and combinational logic within the same always +nonblocking assignments. +5: Do not mix blocking and nonblocking assignments in the same always block. +6: Do not make assignments to the same variable from more than one always block. +7: Use $strobe to display values that have been assigned using nonblocking +. +8: Do not make assignments using #0 delays. |