From 0aad2482deee8235c5b1d2ba12fe16ebdc841303 Mon Sep 17 00:00:00 2001
From: bnewbold <bnewbold@robocracy.org>
Date: Tue, 30 Dec 2014 03:57:38 +0100
Subject: pull xilinx notes into sphinx docs

---
 notes/.xilinx_filetypes.txt.swp | Bin 12288 -> 0 bytes
 notes/xilinx_filetypes.txt      |  65 ----------------------------------------
 notes/xilinx_toolchain.txt      |  17 -----------
 3 files changed, 82 deletions(-)
 delete mode 100644 notes/.xilinx_filetypes.txt.swp
 delete mode 100644 notes/xilinx_filetypes.txt
 delete mode 100644 notes/xilinx_toolchain.txt

(limited to 'notes')

diff --git a/notes/.xilinx_filetypes.txt.swp b/notes/.xilinx_filetypes.txt.swp
deleted file mode 100644
index 2b39a7d..0000000
Binary files a/notes/.xilinx_filetypes.txt.swp and /dev/null differ
diff --git a/notes/xilinx_filetypes.txt b/notes/xilinx_filetypes.txt
deleted file mode 100644
index 6639d2f..0000000
--- a/notes/xilinx_filetypes.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-
-See also:
-
-https://github.com/JPNaude/X-MimeTypes/blob/master/eda_mime_types.xml
-http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgn_r_core_generator_output_files.htm
-http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ise_r_source_types.htm
-
-also: devref.pdf (UG628)
-
-Extension   Description
----------   --------------------------------------------------------------
-.par        "place and route" output
-.vhd        VHDL source code
-.v          Verilog source code
-.ucf        "constraints file": hardware pinouts, timing, etc
-.prj        [list of files in the project?]
-.wcfg       [waveform configuration (saved from gtkwave?]
-.srp        "Synthesis Report File"
-.xst        [xst settings?]
-.lso
-.vcf
-
-.bgn        bitgen report file
-.bit        Final FPGA bitstream file (binary)
-.xwbt
-.bld        Build report from NGDBuild
-.blc        NGDBuild report file
-.cmd_log
-.drc        Design rule check output
-.ncd
-.wdb
-.exe
-.map        [intermediate step]
-.mrp
-.ncd        [intermediate step? netlist?]
-.ngm
-.xrpt
-.par        [place and route output?]
-.pcf
-.ptwx
-.stx
-.syr
-.twr
-.twx
-.unroutes   unrouted traces; if routing was successful, there should be none
-.ut
-.xpi
-.log
-.xmsgs
-.gise
-.xise       ISE project/workplace
-
-.cgc        [coregen? used to programatically re-gen core?]
-.cgp        Coregen Project
-.ngc        Pre-compiled netlist
-.sym
-.asy        "Symbol file"
-_flist.txt  File list (?)
-.gise
-.ncf
-.sym
-.veo
-.vho
-.xco        [intermediate file?]
-
diff --git a/notes/xilinx_toolchain.txt b/notes/xilinx_toolchain.txt
deleted file mode 100644
index e7d78db..0000000
--- a/notes/xilinx_toolchain.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-
-Chapter Two of "FPGAs!? Now What?" gives a good overview of the full
-compilation process:
-
-Synthesis:
-  the "logic synthesizer" compiles from HDL to a netlist
-
-Implementation:
-  the "translator" takes a set of netlists and design constraints and generates
-      a merged netlist (?).
-  then a "mapper" regroups the netlist so that place and route will be easier
-  then a "place and route" tool decides exactly how the FPGA logic will be
-      configured
-
-Bitstream:
-  the "bitstream generator" translates the configuration into the binary format
-      that the FPGA uses to re-flash itself
-- 
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