From c973b4e327ab0c560ba2428e4cc08d542352eb32 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 2 Apr 2013 10:26:08 -0400 Subject: add old notes and README --- notes/xilinx_toolchain.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 notes/xilinx_toolchain.txt (limited to 'notes/xilinx_toolchain.txt') diff --git a/notes/xilinx_toolchain.txt b/notes/xilinx_toolchain.txt new file mode 100644 index 0000000..e7d78db --- /dev/null +++ b/notes/xilinx_toolchain.txt @@ -0,0 +1,17 @@ + +Chapter Two of "FPGAs!? Now What?" gives a good overview of the full +compilation process: + +Synthesis: + the "logic synthesizer" compiles from HDL to a netlist + +Implementation: + the "translator" takes a set of netlists and design constraints and generates + a merged netlist (?). + then a "mapper" regroups the netlist so that place and route will be easier + then a "place and route" tool decides exactly how the FPGA logic will be + configured + +Bitstream: + the "bitstream generator" translates the configuration into the binary format + that the FPGA uses to re-flash itself -- cgit v1.2.3