From 8bf83ef0145d2afe53d4d94f5ff5a4459fbc6637 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 2 Apr 2013 10:25:15 -0400 Subject: commit old git move --- README | 34 ---------------------------------- 1 file changed, 34 deletions(-) delete mode 100644 README (limited to 'README') diff --git a/README b/README deleted file mode 100644 index 00e6343..0000000 --- a/README +++ /dev/null @@ -1,34 +0,0 @@ -A very basic project template for Verilog simulation and synthesis using Isim -and Xilinx tools. Adapted from an actual project, so there is likely a bit of -unecessary flags and switches on certain commands. I have done my best to remove -everything a can where things will still build. - -Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one -of the conf files) via: - -.synth_project/make.sh - -the toplevel ucf (constraints mapping netlist objects from the verilog -compilation to hardware resources, and place and routing and timing constraints) -is: -./synth_project/project.ucf - -the toplevel verilog module, which does nothing (just sets some pins to zero) -lives in: -./hdl/project.v - - -Simulate with isim via: - -./testbench/fuse.sh -./testbench/simulate_isim -gui - - -In isim, you can open the "signals.wcfg" in the file menu to reload a the logic -analyzer configuration. This cfg file will not be valid if you delete any -signals from your design that are saves in the wcfg. - -./testbench/tb.v is the toplevel testbench file for simulation. - - -Please improve and push! \ No newline at end of file -- cgit v1.2.3