From 8bf83ef0145d2afe53d4d94f5ff5a4459fbc6637 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 2 Apr 2013 10:25:15 -0400 Subject: commit old git move --- README | 34 ---------------------------- hdl/project.v | 26 ---------------------- synth_project/make.sh | 9 -------- synth_project/project.lso | 1 - synth_project/project.prj | 1 - synth_project/project.srp | 32 -------------------------- synth_project/project.ucf | 21 ------------------ synth_project/project.xst | 53 -------------------------------------------- testbench/fuse.sh | 2 -- testbench/signals.wcfg | 42 ----------------------------------- testbench/simulate_isim.exe | Bin 21792 -> 0 bytes testbench/simulate_isim.prj | 3 --- testbench/tb.v | 45 ------------------------------------- 13 files changed, 269 deletions(-) delete mode 100644 README delete mode 100644 hdl/project.v delete mode 100755 synth_project/make.sh delete mode 100755 synth_project/project.lso delete mode 100644 synth_project/project.prj delete mode 100644 synth_project/project.srp delete mode 100755 synth_project/project.ucf delete mode 100644 synth_project/project.xst delete mode 100755 testbench/fuse.sh delete mode 100644 testbench/signals.wcfg delete mode 100755 testbench/simulate_isim.exe delete mode 100644 testbench/simulate_isim.prj delete mode 100755 testbench/tb.v diff --git a/README b/README deleted file mode 100644 index 00e6343..0000000 --- a/README +++ /dev/null @@ -1,34 +0,0 @@ -A very basic project template for Verilog simulation and synthesis using Isim -and Xilinx tools. Adapted from an actual project, so there is likely a bit of -unecessary flags and switches on certain commands. I have done my best to remove -everything a can where things will still build. - -Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one -of the conf files) via: - -.synth_project/make.sh - -the toplevel ucf (constraints mapping netlist objects from the verilog -compilation to hardware resources, and place and routing and timing constraints) -is: -./synth_project/project.ucf - -the toplevel verilog module, which does nothing (just sets some pins to zero) -lives in: -./hdl/project.v - - -Simulate with isim via: - -./testbench/fuse.sh -./testbench/simulate_isim -gui - - -In isim, you can open the "signals.wcfg" in the file menu to reload a the logic -analyzer configuration. This cfg file will not be valid if you delete any -signals from your design that are saves in the wcfg. - -./testbench/tb.v is the toplevel testbench file for simulation. - - -Please improve and push! \ No newline at end of file diff --git a/hdl/project.v b/hdl/project.v deleted file mode 100644 index 753597b..0000000 --- a/hdl/project.v +++ /dev/null @@ -1,26 +0,0 @@ -module project - ( - output wire LED_output_0, - output wire LED_output_1, - output wire LED_output_2, - output wire LED_output_3, - output wire LED_output_4, - output wire LED_output_5, - output wire LED_output_6, - input wire Switch_input_0, - input wire Switch_input_1, - input wire Switch_input_2, - input wire Switch_input_3, - input wire SYSTEMCLOCK, - input wire PUSH_BUTTON_RESET_RAW //Xilinx GTP - this is active low- - ); - - assign LED_output_0 = 1'b0; - assign LED_output_1 = 1'b0; - assign LED_output_2 = 1'b0; - assign LED_output_3 = 1'b0; - assign LED_output_4 = 1'b0; - assign LED_output_5 = 1'b0; - assign LED_output_6 = 1'b0; - -endmodule \ No newline at end of file diff --git a/synth_project/make.sh b/synth_project/make.sh deleted file mode 100755 index 174a6ac..0000000 --- a/synth_project/make.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh -e - -TOP_NAME=project -xst -ifn $TOP_NAME.xst -ngdbuild $TOP_NAME.ngc -verbose -map -pr b -w -detail $TOP_NAME.ngd -par -w $TOP_NAME $TOP_NAME.ncd -bitgen -w $TOP_NAME.ncd - diff --git a/synth_project/project.lso b/synth_project/project.lso deleted file mode 100755 index a340c10..0000000 --- a/synth_project/project.lso +++ /dev/null @@ -1 +0,0 @@ -work \ No newline at end of file diff --git a/synth_project/project.prj b/synth_project/project.prj deleted file mode 100644 index 3262aa0..0000000 --- a/synth_project/project.prj +++ /dev/null @@ -1 +0,0 @@ - verilog work ../hdl/project.v diff --git a/synth_project/project.srp b/synth_project/project.srp deleted file mode 100644 index 3a35165..0000000 --- a/synth_project/project.srp +++ /dev/null @@ -1,32 +0,0 @@ -Release 14.3 - xst P.40xd (lin64) -Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ---> -Parameter TMPDIR set to ./xst/projnav.tmp - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.06 secs - ---> -Parameter xsthdpdir set to ./xst - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.06 secs - ---> -ERROR:Xst:438 - Can not open file : proejct.prj - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs - ---> - - -Total memory usage is 284024 kilobytes - -Number of errors : 1 ( 0 filtered) -Number of warnings : 0 ( 0 filtered) -Number of infos : 0 ( 0 filtered) - diff --git a/synth_project/project.ucf b/synth_project/project.ucf deleted file mode 100755 index 322c05a..0000000 --- a/synth_project/project.ucf +++ /dev/null @@ -1,21 +0,0 @@ -NET "PUSH_BUTTON_RESET_RAW" LOC = F3; - -#100MHz clock -NET "SYSTEMCLOCK" LOC = K21; - -NET "Switch_input_0" LOC = C18; -NET "Switch_input_1" LOC = Y6; -NET "Switch_input_2" LOC = W6; -NET "Switch_input_3" LOC = E4; - -NET "LED_output_1" LOC = D17; -NET "LED_output_2" LOC = AB4; -NET "LED_output_4" LOC = D21; -NET "LED_output_5" LOC = W15; - -# Defines the external differential clock to be 150 MHz with 50% duty -# cycle. - -NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK"; -TIMESPEC TS__SYSTEMCLOCK = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50 % PRIORITY 2; - diff --git a/synth_project/project.xst b/synth_project/project.xst deleted file mode 100644 index 9a29456..0000000 --- a/synth_project/project.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir "./xst/projnav.tmp" -set -xsthdpdir "./xst" -run --ifn project.prj --ifmt mixed --ofn project --ofmt NGC --p xc6slx45t-3-fgg484 --top project --lso project.lso --opt_mode Speed --opt_level 1 --power NO --iuc NO --netlist_hierarchy rebuilt --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints YES --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --lc auto --reduce_control_sets auto --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --shreg_extract YES --rom_style Auto --auto_bram_packing NO --resource_sharing YES --async_to_sync NO --use_dsp48 auto -# use NO for making NGC's and YES for making bitstreams --iobuf YES --max_fanout 100000 --bufg 32 --register_duplication YES --register_balancing No --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 \ No newline at end of file diff --git a/testbench/fuse.sh b/testbench/fuse.sh deleted file mode 100755 index ad08c93..0000000 --- a/testbench/fuse.sh +++ /dev/null @@ -1,2 +0,0 @@ -vlogcomp -prj simulate_isim.prj -fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim.exe unenclib.tb unenclib.glbl diff --git a/testbench/signals.wcfg b/testbench/signals.wcfg deleted file mode 100644 index dbb5e1a..0000000 --- a/testbench/signals.wcfg +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - LED_output_2 - LED_output_2 - - - Switch_input_0 - Switch_input_0 - - - Switch_input_1 - Switch_input_1 - - - Switch_input_2 - Switch_input_2 - - - Switch_input_3 - Switch_input_3 - - - SYSTEMCLOCK - SYSTEMCLOCK - - - PUSH_BUTTON_RESET_RAW - PUSH_BUTTON_RESET_RAW - - diff --git a/testbench/simulate_isim.exe b/testbench/simulate_isim.exe deleted file mode 100755 index 5e50691..0000000 Binary files a/testbench/simulate_isim.exe and /dev/null differ diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj deleted file mode 100644 index e610cc5..0000000 --- a/testbench/simulate_isim.prj +++ /dev/null @@ -1,3 +0,0 @@ -verilog unenclib ../hdl/project.v -verilog unenclib tb.v -verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v diff --git a/testbench/tb.v b/testbench/tb.v deleted file mode 100755 index 19e07bf..0000000 --- a/testbench/tb.v +++ /dev/null @@ -1,45 +0,0 @@ -`timescale 1ps/1ps -module tb; - - reg CLK100; -always @(CLK100) begin - #4980.00 CLK100 <= ~CLK100; -end - -initial begin - #0 CLK100 <= 1'b0; // the first event that sets the clock in motion -end - - -reg [7:0] Switch_input; -wire [7:0] LED_output; -wire FPGA_RESET; - -project project_i ( - .PUSH_BUTTON_RESET_RAW(FPGA_RESET), - .LED_output_0(LED_output[0]), - .LED_output_1(LED_output[1]), - .LED_output_2(LED_output[2]), - .LED_output_3(LED_output[3]), - .LED_output_4(LED_output[4]), - .LED_output_5(LED_output[5]), - .LED_output_6(LED_output[6]), - .SYSTEMCLOCK(CLK100), - .Switch_input_0(Switch_input[0]), - .Switch_input_1(Switch_input[1]), - .Switch_input_2(Switch_input[2]), - .Switch_input_3(Switch_input[3]) - ); - - -initial begin - #0 Switch_input <= 8'h00; - $display("Switch set to zero"); - #1000000 Switch_input <= 8'h01; - $display("Switch set to one"); - #2000000 - $display("TEST COMPLETE"); - $finish(); -end - -endmodule -- cgit v1.2.3