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-rw-r--r--fatcat_scholar/sim_pipeline.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/fatcat_scholar/sim_pipeline.py b/fatcat_scholar/sim_pipeline.py
index 5657cb7..6b52535 100644
--- a/fatcat_scholar/sim_pipeline.py
+++ b/fatcat_scholar/sim_pipeline.py
@@ -116,6 +116,9 @@ class SimPipeline():
continue
try:
full_issue = self.fetch_sim_issue(row)
+ except requests.exceptions.ConnectionError as e:
+ print(str(e), file=sys.stderr)
+ continue
except requests.exceptions.ReadTimeout as e:
print(str(e), file=sys.stderr)
continue