summaryrefslogtreecommitdiffstats
path: root/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-100-avr32.patch
blob: 6512f77ef5fdc8a7aa334a9f4c40c84d1a1f42db (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720
6721
6722
6723
6724
6725
6726
6727
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856
6857
6858
6859
6860
6861
6862
6863
6864
6865
6866
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914
6915
6916
6917
6918
6919
6920
6921
6922
6923
6924
6925
6926
6927
6928
6929
6930
6931
6932
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967
6968
6969
6970
6971
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005
7006
7007
7008
7009
7010
7011
7012
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025
7026
7027
7028
7029
7030
7031
7032
7033
7034
7035
7036
7037
7038
7039
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050
7051
7052
7053
7054
7055
7056
7057
7058
7059
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121
7122
7123
7124
7125
7126
7127
7128
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139
7140
7141
7142
7143
7144
7145
7146
7147
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183
7184
7185
7186
7187
7188
7189
7190
7191
7192
7193
7194
7195
7196
7197
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260
7261
7262
7263
7264
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276
7277
7278
7279
7280
7281
7282
7283
7284
7285
7286
7287
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335
7336
7337
7338
7339
7340
7341
7342
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352
7353
7354
7355
7356
7357
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370
7371
7372
7373
7374
7375
7376
7377
7378
7379
7380
7381
7382
7383
7384
7385
7386
7387
7388
7389
7390
7391
7392
7393
7394
7395
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406
7407
7408
7409
7410
7411
7412
7413
7414
7415
7416
7417
7418
7419
7420
7421
7422
7423
7424
7425
7426
7427
7428
7429
7430
7431
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444
7445
7446
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490
7491
7492
7493
7494
7495
7496
7497
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547
7548
7549
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599
7600
7601
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623
7624
7625
7626
7627
7628
7629
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690
7691
7692
7693
7694
7695
7696
7697
7698
7699
7700
7701
7702
7703
7704
7705
7706
7707
7708
7709
7710
7711
7712
7713
7714
7715
7716
7717
7718
7719
7720
7721
7722
7723
7724
7725
7726
7727
7728
7729
7730
7731
7732
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758
7759
7760
7761
7762
7763
7764
7765
7766
7767
7768
7769
7770
7771
7772
7773
7774
7775
7776
7777
7778
7779
7780
7781
7782
7783
7784
7785
7786
7787
7788
7789
7790
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802
7803
7804
7805
7806
7807
7808
7809
7810
7811
7812
7813
7814
7815
7816
7817
7818
7819
7820
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834
7835
7836
7837
7838
7839
7840
7841
7842
7843
7844
7845
7846
7847
7848
7849
7850
7851
7852
7853
7854
7855
7856
7857
7858
7859
7860
7861
7862
7863
7864
7865
7866
7867
7868
7869
7870
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884
7885
7886
7887
7888
7889
7890
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902
7903
7904
7905
7906
7907
7908
7909
7910
7911
7912
7913
7914
7915
7916
7917
7918
7919
7920
7921
7922
7923
7924
7925
7926
7927
7928
7929
7930
7931
7932
7933
7934
7935
7936
7937
7938
7939
7940
7941
7942
7943
7944
7945
7946
7947
7948
7949
7950
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961
7962
7963
7964
7965
7966
7967
7968
7969
7970
7971
7972
7973
7974
7975
7976
7977
7978
7979
7980
7981
7982
7983
7984
7985
7986
7987
7988
7989
7990
7991
7992
7993
7994
7995
7996
7997
7998
7999
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012
8013
8014
8015
8016
8017
8018
8019
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031
8032
8033
8034
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044
8045
8046
8047
8048
8049
8050
8051
8052
8053
8054
8055
8056
8057
8058
8059
8060
8061
8062
8063
8064
8065
8066
8067
8068
8069
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085
8086
8087
8088
8089
8090
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101
8102
8103
8104
8105
8106
8107
8108
8109
8110
8111
8112
8113
8114
8115
8116
8117
8118
8119
8120
8121
8122
8123
8124
8125
8126
8127
8128
8129
8130
8131
8132
8133
8134
8135
8136
8137
8138
8139
8140
8141
8142
8143
8144
8145
8146
8147
8148
8149
8150
8151
8152
8153
8154
8155
8156
8157
8158
8159
8160
8161
8162
8163
8164
8165
8166
8167
8168
8169
8170
8171
8172
8173
8174
8175
8176
8177
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205
8206
8207
8208
8209
8210
8211
8212
8213
8214
8215
8216
8217
8218
8219
8220
8221
8222
8223
8224
8225
8226
8227
8228
8229
8230
8231
8232
8233
8234
8235
8236
8237
8238
8239
8240
8241
8242
8243
8244
8245
8246
8247
8248
8249
8250
8251
8252
8253
8254
8255
8256
8257
8258
8259
8260
8261
8262
8263
8264
8265
8266
8267
8268
8269
8270
8271
8272
8273
8274
8275
8276
8277
8278
8279
8280
8281
8282
8283
8284
8285
8286
8287
8288
8289
8290
8291
8292
8293
8294
8295
8296
8297
8298
8299
8300
8301
8302
8303
8304
8305
8306
8307
8308
8309
8310
8311
8312
8313
8314
8315
8316
8317
8318
8319
8320
8321
8322
8323
8324
8325
8326
8327
8328
8329
8330
8331
8332
8333
8334
8335
8336
8337
8338
8339
8340
8341
8342
8343
8344
8345
8346
8347
8348
8349
8350
8351
8352
8353
8354
8355
8356
8357
8358
8359
8360
8361
8362
8363
8364
8365
8366
8367
8368
8369
8370
8371
8372
8373
8374
8375
8376
8377
8378
8379
8380
8381
8382
8383
8384
8385
8386
8387
8388
8389
8390
8391
8392
8393
8394
8395
8396
8397
8398
8399
8400
8401
8402
8403
8404
8405
8406
8407
8408
8409
8410
8411
8412
8413
8414
8415
8416
8417
8418
8419
8420
8421
8422
8423
8424
8425
8426
8427
8428
8429
8430
8431
8432
8433
8434
8435
8436
8437
8438
8439
8440
8441
8442
8443
8444
8445
8446
8447
8448
8449
8450
8451
8452
8453
8454
8455
8456
8457
8458
8459
8460
8461
8462
8463
8464
8465
8466
8467
8468
8469
8470
8471
8472
8473
8474
8475
8476
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487
8488
8489
8490
8491
8492
8493
8494
8495
8496
8497
8498
8499
8500
8501
8502
8503
8504
8505
8506
8507
8508
8509
8510
8511
8512
8513
8514
8515
8516
8517
8518
8519
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
8530
8531
8532
8533
8534
8535
8536
8537
8538
8539
8540
8541
8542
8543
8544
8545
8546
8547
8548
8549
8550
8551
8552
8553
8554
8555
8556
8557
8558
8559
8560
8561
8562
8563
8564
8565
8566
8567
8568
8569
8570
8571
8572
8573
8574
8575
8576
8577
8578
8579
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
8590
8591
8592
8593
8594
8595
8596
8597
8598
8599
8600
8601
8602
8603
8604
8605
8606
8607
8608
8609
8610
8611
8612
8613
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623
8624
8625
8626
8627
8628
8629
8630
8631
8632
8633
8634
8635
8636
8637
8638
8639
8640
8641
8642
8643
8644
8645
8646
8647
8648
8649
8650
8651
8652
8653
8654
8655
8656
8657
8658
8659
8660
8661
8662
8663
8664
8665
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676
8677
8678
8679
8680
8681
8682
8683
8684
8685
8686
8687
8688
8689
8690
8691
8692
8693
8694
8695
8696
8697
8698
8699
8700
8701
8702
8703
8704
8705
8706
8707
8708
8709
8710
8711
8712
8713
8714
8715
8716
8717
8718
8719
8720
8721
8722
8723
8724
8725
8726
8727
8728
8729
8730
8731
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742
8743
8744
8745
8746
8747
8748
8749
8750
8751
8752
8753
8754
8755
8756
8757
8758
8759
8760
8761
8762
8763
8764
8765
8766
8767
8768
8769
8770
8771
8772
8773
8774
8775
8776
8777
8778
8779
8780
8781
8782
8783
8784
8785
8786
8787
8788
8789
8790
8791
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801
8802
8803
8804
8805
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815
8816
8817
8818
8819
8820
8821
8822
8823
8824
8825
8826
8827
8828
8829
8830
8831
8832
8833
8834
8835
8836
8837
8838
8839
8840
8841
8842
8843
8844
8845
8846
8847
8848
8849
8850
8851
8852
8853
8854
8855
8856
8857
8858
8859
8860
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870
8871
8872
8873
8874
8875
8876
8877
8878
8879
8880
8881
8882
8883
8884
8885
8886
8887
8888
8889
8890
8891
8892
8893
8894
8895
8896
8897
8898
8899
8900
8901
8902
8903
8904
8905
8906
8907
8908
8909
8910
8911
8912
8913
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923
8924
8925
8926
8927
8928
8929
8930
8931
8932
8933
8934
8935
8936
8937
8938
8939
8940
8941
8942
8943
8944
8945
8946
8947
8948
8949
8950
8951
8952
8953
8954
8955
8956
8957
8958
8959
8960
8961
8962
8963
8964
8965
8966
8967
8968
8969
8970
8971
8972
8973
8974
8975
8976
8977
8978
8979
8980
8981
8982
8983
8984
8985
8986
8987
8988
8989
8990
8991
8992
8993
8994
8995
8996
8997
8998
8999
9000
9001
9002
9003
9004
9005
9006
9007
9008
9009
9010
9011
9012
9013
9014
9015
9016
9017
9018
9019
9020
9021
9022
9023
9024
9025
9026
9027
9028
9029
9030
9031
9032
9033
9034
9035
9036
9037
9038
9039
9040
9041
9042
9043
9044
9045
9046
9047
9048
9049
9050
9051
9052
9053
9054
9055
9056
9057
9058
9059
9060
9061
9062
9063
9064
9065
9066
9067
9068
9069
9070
9071
9072
9073
9074
9075
9076
9077
9078
9079
9080
9081
9082
9083
9084
9085
9086
9087
9088
9089
9090
9091
9092
9093
9094
9095
9096
9097
9098
9099
9100
9101
9102
9103
9104
9105
9106
9107
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121
9122
9123
9124
9125
9126
9127
9128
9129
9130
9131
9132
9133
9134
9135
9136
9137
9138
9139
9140
9141
9142
9143
9144
9145
9146
9147
9148
9149
9150
9151
9152
9153
9154
9155
9156
9157
9158
9159
9160
9161
9162
9163
9164
9165
9166
9167
9168
9169
9170
9171
9172
9173
9174
9175
9176
9177
9178
9179
9180
9181
9182
9183
9184
9185
9186
9187
9188
9189
9190
9191
9192
9193
9194
9195
9196
9197
9198
9199
9200
9201
9202
9203
9204
9205
9206
9207
9208
9209
9210
9211
9212
9213
9214
9215
9216
9217
9218
9219
9220
9221
9222
9223
9224
9225
9226
9227
9228
9229
9230
9231
9232
9233
9234
9235
9236
9237
9238
9239
9240
9241
9242
9243
9244
9245
9246
9247
9248
9249
9250
9251
9252
9253
9254
9255
9256
9257
9258
9259
9260
9261
9262
9263
9264
9265
9266
9267
9268
9269
9270
9271
9272
9273
9274
9275
9276
9277
9278
9279
9280
9281
9282
9283
9284
9285
9286
9287
9288
9289
9290
9291
9292
9293
9294
9295
9296
9297
9298
9299
9300
9301
9302
9303
9304
9305
9306
9307
9308
9309
9310
9311
9312
9313
9314
9315
9316
9317
9318
9319
9320
9321
9322
9323
9324
9325
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336
9337
9338
9339
9340
9341
9342
9343
9344
9345
9346
9347
9348
9349
9350
9351
9352
9353
9354
9355
9356
9357
9358
9359
9360
9361
9362
9363
9364
9365
9366
9367
9368
9369
9370
9371
9372
9373
9374
9375
9376
9377
9378
9379
9380
9381
9382
9383
9384
9385
9386
9387
9388
9389
9390
9391
9392
9393
9394
9395
9396
9397
9398
9399
9400
9401
9402
9403
9404
9405
9406
9407
9408
9409
9410
9411
9412
9413
9414
9415
9416
9417
9418
9419
9420
9421
9422
9423
9424
9425
9426
9427
9428
9429
9430
9431
9432
9433
9434
9435
9436
9437
9438
9439
9440
9441
9442
9443
9444
9445
9446
9447
9448
9449
9450
9451
9452
9453
9454
9455
9456
9457
9458
9459
9460
9461
9462
9463
9464
9465
9466
9467
9468
9469
9470
9471
9472
9473
9474
9475
9476
9477
9478
9479
9480
9481
9482
9483
9484
9485
9486
9487
9488
9489
9490
9491
9492
9493
9494
9495
9496
9497
9498
9499
9500
9501
9502
9503
9504
9505
9506
9507
9508
9509
9510
9511
9512
9513
9514
9515
9516
9517
9518
9519
9520
9521
9522
9523
9524
9525
9526
9527
9528
9529
9530
9531
9532
9533
9534
9535
9536
9537
9538
9539
9540
9541
9542
9543
9544
9545
9546
9547
9548
9549
9550
9551
9552
9553
9554
9555
9556
9557
9558
9559
9560
9561
9562
9563
9564
9565
9566
9567
9568
9569
9570
9571
9572
9573
9574
9575
9576
9577
9578
9579
9580
9581
9582
9583
9584
9585
9586
9587
9588
9589
9590
9591
9592
9593
9594
9595
9596
9597
9598
9599
9600
9601
9602
9603
9604
9605
9606
9607
9608
9609
9610
9611
9612
9613
9614
9615
9616
9617
9618
9619
9620
9621
9622
9623
9624
9625
9626
9627
9628
9629
9630
9631
9632
9633
9634
9635
9636
9637
9638
9639
9640
9641
9642
9643
9644
9645
9646
9647
9648
9649
9650
9651
9652
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662
9663
9664
9665
9666
9667
9668
9669
9670
9671
9672
9673
9674
9675
9676
9677
9678
9679
9680
9681
9682
9683
9684
9685
9686
9687
9688
9689
9690
9691
9692
9693
9694
9695
9696
9697
9698
9699
9700
9701
9702
9703
9704
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714
9715
9716
9717
9718
9719
9720
9721
9722
9723
9724
9725
9726
9727
9728
9729
9730
9731
9732
9733
9734
9735
9736
9737
9738
9739
9740
9741
9742
9743
9744
9745
9746
9747
9748
9749
9750
9751
9752
9753
9754
9755
9756
9757
9758
9759
9760
9761
9762
9763
9764
9765
9766
9767
9768
9769
9770
9771
9772
9773
9774
9775
9776
9777
9778
9779
9780
9781
9782
9783
9784
9785
9786
9787
9788
9789
9790
9791
9792
9793
9794
9795
9796
9797
9798
9799
9800
9801
9802
9803
9804
9805
9806
9807
9808
9809
9810
9811
9812
9813
9814
9815
9816
9817
9818
9819
9820
9821
9822
9823
9824
9825
9826
9827
9828
9829
9830
9831
9832
9833
9834
9835
9836
9837
9838
9839
9840
9841
9842
9843
9844
9845
9846
9847
9848
9849
9850
9851
9852
9853
9854
9855
9856
9857
9858
9859
9860
9861
9862
9863
9864
9865
9866
9867
9868
9869
9870
9871
9872
9873
9874
9875
9876
9877
9878
9879
9880
9881
9882
9883
9884
9885
9886
9887
9888
9889
9890
9891
9892
9893
9894
9895
9896
9897
9898
9899
9900
9901
9902
9903
9904
9905
9906
9907
9908
9909
9910
9911
9912
9913
9914
9915
9916
9917
9918
9919
9920
9921
9922
9923
9924
9925
9926
9927
9928
9929
9930
9931
9932
9933
9934
9935
9936
9937
9938
9939
9940
9941
9942
9943
9944
9945
9946
9947
9948
9949
9950
9951
9952
9953
9954
9955
9956
9957
9958
9959
9960
9961
9962
9963
9964
9965
9966
9967
9968
9969
9970
9971
9972
9973
9974
9975
9976
9977
9978
9979
9980
9981
9982
9983
9984
9985
9986
9987
9988
9989
9990
9991
9992
9993
9994
9995
9996
9997
9998
9999
10000
10001
10002
10003
10004
10005
10006
10007
10008
10009
10010
10011
10012
10013
10014
10015
10016
10017
10018
10019
10020
10021
10022
10023
10024
10025
10026
10027
10028
10029
10030
10031
10032
10033
10034
10035
10036
10037
10038
10039
10040
10041
10042
10043
10044
10045
10046
10047
10048
10049
10050
10051
10052
10053
10054
10055
10056
10057
10058
10059
10060
10061
10062
10063
10064
10065
10066
10067
10068
10069
10070
10071
10072
10073
10074
10075
10076
10077
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087
10088
10089
10090
10091
10092
10093
10094
10095
10096
10097
10098
10099
10100
10101
10102
10103
10104
10105
10106
10107
10108
10109
10110
10111
10112
10113
10114
10115
10116
10117
10118
10119
10120
10121
10122
10123
10124
10125
10126
10127
10128
10129
10130
10131
10132
10133
10134
10135
10136
10137
10138
10139
10140
10141
10142
10143
10144
10145
10146
10147
10148
10149
10150
10151
10152
10153
10154
10155
10156
10157
10158
10159
10160
10161
10162
10163
10164
10165
10166
10167
10168
10169
10170
10171
10172
10173
10174
10175
10176
10177
10178
10179
10180
10181
10182
10183
10184
10185
10186
10187
10188
10189
10190
10191
10192
10193
10194
10195
10196
10197
10198
10199
10200
10201
10202
10203
10204
10205
10206
10207
10208
10209
10210
10211
10212
10213
10214
10215
10216
10217
10218
10219
10220
10221
10222
10223
10224
10225
10226
10227
10228
10229
10230
10231
10232
10233
10234
10235
10236
10237
10238
10239
10240
10241
10242
10243
10244
10245
10246
10247
10248
10249
10250
10251
10252
10253
10254
10255
10256
10257
10258
10259
10260
10261
10262
10263
10264
10265
10266
10267
10268
10269
10270
10271
10272
10273
10274
10275
10276
10277
10278
10279
10280
10281
10282
10283
10284
10285
10286
10287
10288
10289
10290
10291
10292
10293
10294
10295
10296
10297
10298
10299
10300
10301
10302
10303
10304
10305
10306
10307
10308
10309
10310
10311
10312
10313
10314
10315
10316
10317
10318
10319
10320
10321
10322
10323
10324
10325
10326
10327
10328
10329
10330
10331
10332
10333
10334
10335
10336
10337
10338
10339
10340
10341
10342
10343
10344
10345
10346
10347
10348
10349
10350
10351
10352
10353
10354
10355
10356
10357
10358
10359
10360
10361
10362
10363
10364
10365
10366
10367
10368
10369
10370
10371
10372
10373
10374
10375
10376
10377
10378
10379
10380
10381
10382
10383
10384
10385
10386
10387
10388
10389
10390
10391
10392
10393
10394
10395
10396
10397
10398
10399
10400
10401
10402
10403
10404
10405
10406
10407
10408
10409
10410
10411
10412
10413
10414
10415
10416
10417
10418
10419
10420
10421
10422
10423
10424
10425
10426
10427
10428
10429
10430
10431
10432
10433
10434
10435
10436
10437
10438
10439
10440
10441
10442
10443
10444
10445
10446
10447
10448
10449
10450
10451
10452
10453
10454
10455
10456
10457
10458
10459
10460
10461
10462
10463
10464
10465
10466
10467
10468
10469
10470
10471
10472
10473
10474
10475
10476
10477
10478
10479
10480
10481
10482
10483
10484
10485
10486
10487
10488
10489
10490
10491
10492
10493
10494
10495
10496
10497
10498
10499
10500
10501
10502
10503
10504
10505
10506
10507
10508
10509
10510
10511
10512
10513
10514
10515
10516
10517
10518
10519
10520
10521
10522
10523
10524
10525
10526
10527
10528
10529
10530
10531
10532
10533
10534
10535
10536
10537
10538
10539
10540
10541
10542
10543
10544
10545
10546
10547
10548
10549
10550
10551
10552
10553
10554
10555
10556
10557
10558
10559
10560
10561
10562
10563
10564
10565
10566
10567
10568
10569
10570
10571
10572
10573
10574
10575
10576
10577
10578
10579
10580
10581
10582
10583
10584
10585
10586
10587
10588
10589
10590
10591
10592
10593
10594
10595
10596
10597
10598
10599
10600
10601
10602
10603
10604
10605
10606
10607
10608
10609
10610
10611
10612
10613
10614
10615
10616
10617
10618
10619
10620
10621
10622
10623
10624
10625
10626
10627
10628
10629
10630
10631
10632
10633
10634
10635
10636
10637
10638
10639
10640
10641
10642
10643
10644
10645
10646
10647
10648
10649
10650
10651
10652
10653
10654
10655
10656
10657
10658
10659
10660
10661
10662
10663
10664
10665
10666
10667
10668
10669
10670
10671
10672
10673
10674
10675
10676
10677
10678
10679
10680
10681
10682
10683
10684
10685
10686
10687
10688
10689
10690
10691
10692
10693
10694
10695
10696
10697
10698
10699
10700
10701
10702
10703
10704
10705
10706
10707
10708
10709
10710
10711
10712
10713
10714
10715
10716
10717
10718
10719
10720
10721
10722
10723
10724
10725
10726
10727
10728
10729
10730
10731
10732
10733
10734
10735
10736
10737
10738
10739
10740
10741
10742
10743
10744
10745
10746
10747
10748
10749
10750
10751
10752
10753
10754
10755
10756
10757
10758
10759
10760
10761
10762
10763
10764
10765
10766
10767
10768
10769
10770
10771
10772
10773
10774
10775
10776
10777
10778
10779
10780
10781
10782
10783
10784
10785
10786
10787
10788
10789
10790
10791
10792
10793
10794
10795
10796
10797
10798
10799
10800
10801
10802
10803
10804
10805
10806
10807
10808
10809
10810
10811
10812
10813
10814
10815
10816
10817
10818
10819
10820
10821
10822
10823
10824
10825
10826
10827
10828
10829
10830
10831
10832
10833
10834
10835
10836
10837
10838
10839
10840
10841
10842
10843
10844
10845
10846
10847
10848
10849
10850
10851
10852
10853
10854
10855
10856
10857
10858
10859
10860
10861
10862
10863
10864
10865
10866
10867
10868
10869
10870
10871
10872
10873
10874
10875
10876
10877
10878
10879
10880
10881
10882
10883
10884
10885
10886
10887
10888
10889
10890
10891
10892
10893
10894
10895
10896
10897
10898
10899
10900
10901
10902
10903
10904
10905
10906
10907
10908
10909
10910
10911
10912
10913
10914
10915
10916
10917
10918
10919
10920
10921
10922
10923
10924
10925
10926
10927
10928
10929
10930
10931
10932
10933
10934
10935
10936
10937
10938
10939
10940
10941
10942
10943
10944
10945
10946
10947
10948
10949
10950
10951
10952
10953
10954
10955
10956
10957
10958
10959
10960
10961
10962
10963
10964
10965
10966
10967
10968
10969
10970
10971
10972
10973
10974
10975
10976
10977
10978
10979
10980
10981
10982
10983
10984
10985
10986
10987
10988
10989
10990
10991
10992
10993
10994
10995
10996
10997
10998
10999
11000
11001
11002
11003
11004
11005
11006
11007
11008
11009
11010
11011
11012
11013
11014
11015
11016
11017
11018
11019
11020
11021
11022
11023
11024
11025
11026
11027
11028
11029
11030
11031
11032
11033
11034
11035
11036
11037
11038
11039
11040
11041
11042
11043
11044
11045
11046
11047
11048
11049
11050
11051
11052
11053
11054
11055
11056
11057
11058
11059
11060
11061
11062
11063
11064
11065
11066
11067
11068
11069
11070
11071
11072
11073
11074
11075
11076
11077
11078
11079
11080
11081
11082
11083
11084
11085
11086
11087
11088
11089
11090
11091
11092
11093
11094
11095
11096
11097
11098
11099
11100
11101
11102
11103
11104
11105
11106
11107
11108
11109
11110
11111
11112
11113
11114
11115
11116
11117
11118
11119
11120
11121
11122
11123
11124
11125
11126
11127
11128
11129
11130
11131
11132
11133
11134
11135
11136
11137
11138
11139
11140
11141
11142
11143
11144
11145
11146
11147
11148
11149
11150
11151
11152
11153
11154
11155
11156
11157
11158
11159
11160
11161
11162
11163
11164
11165
11166
11167
11168
11169
11170
11171
11172
11173
11174
11175
11176
11177
11178
11179
11180
11181
11182
11183
11184
11185
11186
11187
11188
11189
11190
11191
11192
11193
11194
11195
11196
11197
11198
11199
11200
11201
11202
11203
11204
11205
11206
11207
11208
11209
11210
11211
11212
11213
11214
11215
11216
11217
11218
11219
11220
11221
11222
11223
11224
11225
11226
11227
11228
11229
11230
11231
11232
11233
11234
11235
11236
11237
11238
11239
11240
11241
11242
11243
11244
11245
11246
11247
11248
11249
11250
11251
11252
11253
11254
11255
11256
11257
11258
11259
11260
11261
11262
11263
11264
11265
11266
11267
11268
11269
11270
11271
11272
11273
11274
11275
11276
11277
11278
11279
11280
11281
11282
11283
11284
11285
11286
11287
11288
11289
11290
11291
11292
11293
11294
11295
11296
11297
11298
11299
11300
11301
11302
11303
11304
11305
11306
11307
11308
11309
11310
11311
11312
11313
11314
11315
11316
11317
11318
11319
11320
11321
11322
11323
11324
11325
11326
11327
11328
11329
11330
11331
11332
11333
11334
11335
11336
11337
11338
11339
11340
11341
11342
11343
11344
11345
11346
11347
11348
11349
11350
11351
11352
11353
11354
11355
11356
11357
11358
11359
11360
11361
11362
11363
11364
11365
11366
11367
11368
11369
11370
11371
11372
11373
11374
11375
11376
11377
11378
11379
11380
11381
11382
11383
11384
11385
11386
11387
11388
11389
11390
11391
11392
11393
11394
11395
11396
11397
11398
11399
11400
11401
11402
11403
11404
11405
11406
11407
11408
11409
11410
11411
11412
11413
11414
11415
11416
11417
11418
11419
11420
11421
11422
11423
11424
11425
11426
11427
11428
11429
11430
11431
11432
11433
11434
11435
11436
11437
11438
11439
11440
11441
11442
11443
11444
11445
11446
11447
11448
11449
11450
11451
11452
11453
11454
11455
11456
11457
11458
11459
11460
11461
11462
11463
11464
11465
11466
11467
11468
11469
11470
11471
11472
11473
11474
11475
11476
11477
11478
11479
11480
11481
11482
11483
11484
11485
11486
11487
11488
11489
11490
11491
11492
11493
11494
11495
11496
11497
11498
11499
11500
11501
11502
11503
11504
11505
11506
11507
11508
11509
11510
11511
11512
11513
11514
11515
11516
11517
11518
11519
11520
11521
11522
11523
11524
11525
11526
11527
11528
11529
11530
11531
11532
11533
11534
11535
11536
11537
11538
11539
11540
11541
11542
11543
11544
11545
11546
11547
11548
11549
11550
11551
11552
11553
11554
11555
11556
11557
11558
11559
11560
11561
11562
11563
11564
11565
11566
11567
11568
11569
11570
11571
11572
11573
11574
11575
11576
11577
11578
11579
11580
11581
11582
11583
11584
11585
11586
11587
11588
11589
11590
11591
11592
11593
11594
11595
11596
11597
11598
11599
11600
11601
11602
11603
11604
11605
11606
11607
11608
11609
11610
11611
11612
11613
11614
11615
11616
11617
11618
11619
11620
11621
11622
11623
11624
11625
11626
11627
11628
11629
11630
11631
11632
11633
11634
11635
11636
11637
11638
11639
11640
11641
11642
11643
11644
11645
11646
11647
11648
11649
11650
11651
11652
11653
11654
11655
11656
11657
11658
11659
11660
11661
11662
11663
11664
11665
11666
11667
11668
11669
11670
11671
11672
11673
11674
11675
11676
11677
11678
11679
11680
11681
11682
11683
11684
11685
11686
11687
11688
11689
11690
11691
11692
11693
11694
11695
11696
11697
11698
11699
11700
11701
11702
11703
11704
11705
11706
11707
11708
11709
11710
11711
11712
11713
11714
11715
11716
11717
11718
11719
11720
11721
11722
11723
11724
11725
11726
11727
11728
11729
11730
11731
11732
11733
11734
11735
11736
11737
11738
11739
11740
11741
11742
11743
11744
11745
11746
11747
11748
11749
11750
11751
11752
11753
11754
11755
11756
11757
11758
11759
11760
11761
11762
11763
11764
11765
11766
11767
11768
11769
11770
11771
11772
11773
11774
11775
11776
11777
11778
11779
11780
11781
11782
11783
11784
11785
11786
11787
11788
11789
11790
11791
11792
11793
11794
11795
11796
11797
11798
11799
11800
11801
11802
11803
11804
11805
11806
11807
11808
11809
11810
11811
11812
11813
11814
11815
11816
11817
11818
11819
11820
11821
11822
11823
11824
11825
11826
11827
11828
11829
11830
11831
11832
11833
11834
11835
11836
11837
11838
11839
11840
11841
11842
11843
11844
11845
11846
11847
11848
11849
11850
11851
11852
11853
11854
11855
11856
11857
11858
11859
11860
11861
11862
11863
11864
11865
11866
11867
11868
11869
11870
11871
11872
11873
11874
11875
11876
11877
11878
11879
11880
11881
11882
11883
11884
11885
11886
11887
11888
11889
11890
11891
11892
11893
11894
11895
11896
11897
11898
11899
11900
11901
11902
11903
11904
11905
11906
11907
11908
11909
11910
11911
11912
11913
11914
11915
11916
11917
11918
11919
11920
11921
11922
11923
11924
11925
11926
11927
11928
11929
11930
11931
11932
11933
11934
11935
11936
11937
11938
11939
11940
11941
11942
11943
11944
11945
11946
11947
11948
11949
11950
11951
11952
11953
11954
11955
11956
11957
11958
11959
11960
11961
11962
11963
11964
11965
11966
11967
11968
11969
11970
11971
11972
11973
11974
11975
11976
11977
11978
11979
11980
11981
11982
11983
11984
11985
11986
11987
11988
11989
11990
11991
11992
11993
11994
11995
11996
11997
11998
11999
12000
12001
12002
12003
12004
12005
12006
12007
12008
12009
12010
12011
12012
12013
12014
12015
12016
12017
12018
12019
12020
12021
12022
12023
12024
12025
12026
12027
12028
12029
12030
12031
12032
12033
12034
12035
12036
12037
12038
12039
12040
12041
12042
12043
12044
12045
12046
12047
12048
12049
12050
12051
12052
12053
12054
12055
12056
12057
12058
12059
12060
12061
12062
12063
12064
12065
12066
12067
12068
12069
12070
12071
12072
12073
12074
12075
12076
12077
12078
12079
12080
12081
12082
12083
12084
12085
12086
12087
12088
12089
12090
12091
12092
12093
12094
12095
12096
12097
12098
12099
12100
12101
12102
12103
12104
12105
12106
12107
12108
12109
12110
12111
12112
12113
12114
12115
12116
12117
12118
12119
12120
12121
12122
12123
12124
12125
12126
12127
12128
12129
12130
12131
12132
12133
12134
12135
12136
12137
12138
12139
12140
12141
12142
12143
12144
12145
12146
12147
12148
12149
12150
12151
12152
12153
12154
12155
12156
12157
12158
12159
12160
12161
12162
12163
12164
12165
12166
12167
12168
12169
12170
12171
12172
12173
12174
12175
12176
12177
12178
12179
12180
12181
12182
12183
12184
12185
12186
12187
12188
12189
12190
12191
12192
12193
12194
12195
12196
12197
12198
12199
12200
12201
12202
12203
12204
12205
12206
12207
12208
12209
12210
12211
12212
12213
12214
12215
12216
12217
12218
12219
12220
12221
12222
12223
12224
12225
12226
12227
12228
12229
12230
12231
12232
12233
12234
12235
12236
12237
12238
12239
12240
12241
12242
12243
12244
12245
12246
12247
12248
12249
12250
12251
12252
12253
12254
12255
12256
12257
12258
12259
12260
12261
12262
12263
12264
12265
12266
12267
12268
12269
12270
12271
12272
12273
12274
12275
12276
12277
12278
12279
12280
12281
12282
12283
12284
12285
12286
12287
12288
12289
12290
12291
12292
12293
12294
12295
12296
12297
12298
12299
12300
12301
12302
12303
12304
12305
12306
12307
12308
12309
12310
12311
12312
12313
12314
12315
12316
12317
12318
12319
12320
12321
12322
12323
12324
12325
12326
12327
12328
12329
12330
12331
12332
12333
12334
12335
12336
12337
12338
12339
12340
12341
12342
12343
12344
12345
12346
12347
12348
12349
12350
12351
12352
12353
12354
12355
12356
12357
12358
12359
12360
12361
12362
12363
12364
12365
12366
12367
12368
12369
12370
12371
12372
12373
12374
12375
12376
12377
12378
12379
12380
12381
12382
12383
12384
12385
12386
12387
12388
12389
12390
12391
12392
12393
12394
12395
12396
12397
12398
12399
12400
12401
12402
12403
12404
12405
12406
12407
12408
12409
12410
12411
12412
12413
12414
12415
12416
12417
12418
12419
12420
12421
12422
12423
12424
12425
12426
12427
12428
12429
12430
12431
12432
12433
12434
12435
12436
12437
12438
12439
12440
12441
12442
12443
12444
12445
12446
12447
12448
12449
12450
12451
12452
12453
12454
12455
12456
12457
12458
12459
12460
12461
12462
12463
12464
12465
12466
12467
12468
12469
12470
12471
12472
12473
12474
12475
12476
12477
12478
12479
12480
12481
12482
12483
12484
12485
12486
12487
12488
12489
12490
12491
12492
12493
12494
12495
12496
12497
12498
12499
12500
12501
12502
12503
12504
12505
12506
12507
12508
12509
12510
12511
12512
12513
12514
12515
12516
12517
12518
12519
12520
12521
12522
12523
12524
12525
12526
12527
12528
12529
12530
12531
12532
12533
12534
12535
12536
12537
12538
12539
12540
12541
12542
12543
12544
12545
12546
12547
12548
12549
12550
12551
12552
12553
12554
12555
12556
12557
12558
12559
12560
12561
12562
12563
12564
12565
12566
12567
12568
12569
12570
12571
12572
12573
12574
12575
12576
12577
12578
12579
12580
12581
12582
12583
12584
12585
12586
12587
12588
12589
12590
12591
12592
12593
12594
12595
12596
12597
12598
12599
12600
12601
12602
12603
12604
12605
12606
12607
12608
12609
12610
12611
12612
12613
12614
12615
12616
12617
12618
12619
12620
12621
12622
12623
12624
12625
12626
12627
12628
12629
12630
12631
12632
12633
12634
12635
12636
12637
12638
12639
12640
12641
12642
12643
12644
12645
12646
12647
12648
12649
12650
12651
12652
12653
12654
12655
12656
12657
12658
12659
12660
12661
12662
12663
12664
12665
12666
12667
12668
12669
12670
12671
12672
12673
12674
12675
12676
12677
12678
12679
12680
12681
12682
12683
12684
12685
12686
12687
12688
12689
12690
12691
12692
12693
12694
12695
12696
12697
12698
12699
12700
12701
12702
12703
12704
12705
12706
12707
12708
12709
12710
12711
12712
12713
12714
12715
12716
12717
12718
12719
12720
12721
12722
12723
12724
12725
12726
12727
12728
12729
12730
12731
12732
12733
12734
12735
12736
12737
12738
12739
12740
12741
12742
12743
12744
12745
12746
12747
12748
12749
12750
12751
12752
12753
12754
12755
12756
12757
12758
12759
12760
12761
12762
12763
12764
12765
12766
12767
12768
12769
12770
12771
12772
12773
12774
12775
12776
12777
12778
12779
12780
12781
12782
12783
12784
12785
12786
12787
12788
12789
12790
12791
12792
12793
12794
12795
12796
12797
12798
12799
12800
12801
12802
12803
12804
12805
12806
12807
12808
12809
12810
12811
12812
12813
12814
12815
12816
12817
12818
12819
12820
12821
12822
12823
12824
12825
12826
12827
12828
12829
12830
12831
12832
12833
12834
12835
12836
12837
12838
12839
12840
12841
12842
12843
12844
12845
12846
12847
12848
12849
12850
12851
12852
12853
12854
12855
12856
12857
12858
12859
12860
12861
12862
12863
12864
12865
12866
12867
12868
12869
12870
12871
12872
12873
12874
12875
12876
12877
12878
12879
12880
12881
12882
12883
12884
12885
12886
12887
12888
12889
12890
12891
12892
12893
12894
12895
12896
12897
12898
12899
12900
12901
12902
12903
12904
12905
12906
12907
12908
12909
12910
12911
12912
12913
12914
12915
12916
12917
12918
12919
12920
12921
12922
12923
12924
12925
12926
12927
12928
12929
12930
12931
12932
12933
12934
12935
12936
12937
12938
12939
12940
12941
12942
12943
12944
12945
12946
12947
12948
12949
12950
12951
12952
12953
12954
12955
12956
12957
12958
12959
12960
12961
12962
12963
12964
12965
12966
12967
12968
12969
12970
12971
12972
12973
12974
12975
12976
12977
12978
12979
12980
12981
12982
12983
12984
12985
12986
12987
12988
12989
12990
12991
12992
12993
12994
12995
12996
12997
12998
12999
13000
13001
13002
13003
13004
13005
13006
13007
13008
13009
13010
13011
13012
13013
13014
13015
13016
13017
13018
13019
13020
13021
13022
13023
13024
13025
13026
13027
13028
13029
13030
13031
13032
13033
13034
13035
13036
13037
13038
13039
13040
13041
13042
13043
13044
13045
13046
13047
13048
13049
13050
13051
13052
13053
13054
13055
13056
13057
13058
13059
13060
13061
13062
13063
13064
13065
13066
13067
13068
13069
13070
13071
13072
13073
13074
13075
13076
13077
13078
13079
13080
13081
13082
13083
13084
13085
13086
13087
13088
13089
13090
13091
13092
13093
13094
13095
13096
13097
13098
13099
13100
13101
13102
13103
13104
13105
13106
13107
13108
13109
13110
13111
13112
13113
13114
13115
13116
13117
13118
13119
13120
13121
13122
13123
13124
13125
13126
13127
13128
13129
13130
13131
13132
13133
13134
13135
13136
13137
13138
13139
13140
13141
13142
13143
13144
13145
13146
13147
13148
13149
13150
13151
13152
13153
13154
13155
13156
13157
13158
13159
13160
13161
13162
13163
13164
13165
13166
13167
13168
13169
13170
13171
13172
13173
13174
13175
13176
13177
13178
13179
13180
13181
13182
13183
13184
13185
13186
13187
13188
13189
13190
13191
13192
13193
13194
13195
13196
13197
13198
13199
13200
13201
13202
13203
13204
13205
13206
13207
13208
13209
13210
13211
13212
13213
13214
13215
13216
13217
13218
13219
13220
13221
13222
13223
13224
13225
13226
13227
13228
13229
13230
13231
13232
13233
13234
13235
13236
13237
13238
13239
13240
13241
13242
13243
13244
13245
13246
13247
13248
13249
13250
13251
13252
13253
13254
13255
13256
13257
13258
13259
13260
13261
13262
13263
13264
13265
13266
13267
13268
13269
13270
13271
13272
13273
13274
13275
13276
13277
13278
13279
13280
13281
13282
13283
13284
13285
13286
13287
13288
13289
13290
13291
13292
13293
13294
13295
13296
13297
13298
13299
13300
13301
13302
13303
13304
13305
13306
13307
13308
13309
13310
13311
13312
13313
13314
13315
13316
13317
13318
13319
13320
13321
13322
13323
13324
13325
13326
13327
13328
13329
13330
13331
13332
13333
13334
13335
13336
13337
13338
13339
13340
13341
13342
13343
13344
13345
13346
13347
13348
13349
13350
13351
13352
13353
13354
13355
13356
13357
13358
13359
13360
13361
13362
13363
13364
13365
13366
13367
13368
13369
13370
13371
13372
13373
13374
13375
13376
13377
13378
13379
13380
13381
13382
13383
13384
13385
13386
13387
13388
13389
13390
13391
13392
13393
13394
13395
13396
13397
13398
13399
13400
13401
13402
13403
13404
13405
13406
13407
13408
13409
13410
13411
13412
13413
13414
13415
13416
13417
13418
13419
13420
13421
13422
13423
13424
13425
13426
13427
13428
13429
13430
13431
13432
13433
13434
13435
13436
13437
13438
13439
13440
13441
13442
13443
13444
13445
13446
13447
13448
13449
13450
13451
13452
13453
13454
13455
13456
13457
13458
13459
13460
13461
13462
13463
13464
13465
13466
13467
13468
13469
13470
13471
13472
13473
13474
13475
13476
13477
13478
13479
13480
13481
13482
13483
13484
13485
13486
13487
13488
13489
13490
13491
13492
13493
13494
13495
13496
13497
13498
13499
13500
13501
13502
13503
13504
13505
13506
13507
13508
13509
13510
13511
13512
13513
13514
13515
13516
13517
13518
13519
13520
13521
13522
13523
13524
13525
13526
13527
13528
13529
13530
13531
13532
13533
13534
13535
13536
13537
13538
13539
13540
13541
13542
13543
13544
13545
13546
13547
13548
13549
13550
13551
13552
13553
13554
13555
13556
13557
13558
13559
13560
13561
13562
13563
13564
13565
13566
13567
13568
13569
13570
13571
13572
13573
13574
13575
13576
13577
13578
13579
13580
13581
13582
13583
13584
13585
13586
13587
13588
13589
13590
13591
13592
13593
13594
13595
13596
13597
13598
13599
13600
13601
13602
13603
13604
13605
13606
13607
13608
13609
13610
13611
13612
13613
13614
13615
13616
13617
13618
13619
13620
13621
13622
13623
13624
13625
13626
13627
13628
13629
13630
13631
13632
13633
13634
13635
13636
13637
13638
13639
13640
13641
13642
13643
13644
13645
13646
13647
13648
13649
13650
13651
13652
13653
13654
13655
13656
13657
13658
13659
13660
13661
13662
13663
13664
13665
13666
13667
13668
13669
13670
13671
13672
13673
13674
13675
13676
13677
13678
13679
13680
13681
13682
13683
13684
13685
13686
13687
13688
13689
13690
13691
13692
13693
13694
13695
13696
13697
13698
13699
13700
13701
13702
13703
13704
13705
13706
13707
13708
13709
13710
13711
13712
13713
13714
13715
13716
13717
13718
13719
13720
13721
13722
13723
13724
13725
13726
13727
13728
13729
13730
13731
13732
13733
13734
13735
13736
13737
13738
13739
13740
13741
13742
13743
13744
13745
13746
13747
13748
13749
13750
13751
13752
13753
13754
13755
13756
13757
13758
13759
13760
13761
13762
13763
13764
13765
13766
13767
13768
13769
13770
13771
13772
13773
13774
13775
13776
13777
13778
13779
13780
13781
13782
13783
13784
13785
13786
13787
13788
13789
13790
13791
13792
13793
13794
13795
13796
13797
13798
13799
13800
13801
13802
13803
13804
13805
13806
13807
13808
13809
13810
13811
13812
13813
13814
13815
13816
13817
13818
13819
13820
13821
13822
13823
13824
13825
13826
13827
13828
13829
13830
13831
13832
13833
13834
13835
13836
13837
13838
13839
13840
13841
13842
13843
13844
13845
13846
13847
13848
13849
13850
13851
13852
13853
13854
13855
13856
13857
13858
13859
13860
13861
13862
13863
13864
13865
13866
13867
13868
13869
13870
13871
13872
13873
13874
13875
13876
13877
13878
13879
13880
13881
13882
13883
13884
13885
13886
13887
13888
13889
13890
13891
13892
13893
13894
13895
13896
13897
13898
13899
13900
13901
13902
13903
13904
13905
13906
13907
13908
13909
13910
13911
13912
13913
13914
13915
13916
13917
13918
13919
13920
13921
13922
13923
13924
13925
13926
13927
13928
13929
13930
13931
13932
13933
13934
13935
13936
13937
13938
13939
13940
13941
13942
13943
13944
13945
13946
13947
13948
13949
13950
13951
13952
13953
13954
13955
13956
13957
13958
13959
13960
13961
13962
13963
13964
13965
13966
13967
13968
13969
13970
13971
13972
13973
13974
13975
13976
13977
13978
13979
13980
13981
13982
13983
13984
13985
13986
13987
13988
13989
13990
13991
13992
13993
13994
13995
13996
13997
13998
13999
14000
14001
14002
14003
14004
14005
14006
14007
14008
14009
14010
14011
14012
14013
14014
14015
14016
14017
14018
14019
14020
14021
14022
14023
14024
14025
14026
14027
14028
14029
14030
14031
14032
14033
14034
14035
14036
14037
14038
14039
14040
14041
14042
14043
14044
14045
14046
14047
14048
14049
14050
14051
14052
14053
14054
14055
14056
14057
14058
14059
14060
14061
14062
14063
14064
14065
14066
14067
14068
14069
14070
14071
14072
14073
14074
14075
14076
14077
14078
14079
14080
14081
14082
14083
14084
14085
14086
14087
14088
14089
14090
14091
14092
14093
14094
14095
14096
14097
14098
14099
14100
14101
14102
14103
14104
14105
14106
14107
14108
14109
14110
14111
14112
14113
14114
14115
14116
14117
14118
14119
14120
14121
14122
14123
14124
14125
14126
14127
14128
14129
14130
14131
14132
14133
14134
14135
14136
14137
14138
14139
14140
14141
14142
14143
14144
14145
14146
14147
14148
14149
14150
14151
14152
14153
14154
14155
14156
14157
14158
14159
14160
14161
14162
14163
14164
14165
14166
14167
14168
14169
14170
14171
14172
14173
14174
14175
14176
14177
14178
14179
14180
14181
14182
14183
14184
14185
14186
14187
14188
14189
14190
14191
14192
14193
14194
14195
14196
14197
14198
14199
14200
14201
14202
14203
14204
14205
14206
14207
14208
14209
14210
14211
14212
14213
14214
14215
14216
14217
14218
14219
14220
14221
14222
14223
14224
14225
14226
14227
14228
14229
14230
14231
14232
14233
14234
14235
14236
14237
14238
14239
14240
14241
14242
14243
14244
14245
14246
14247
14248
14249
14250
14251
14252
14253
14254
14255
14256
14257
14258
14259
14260
14261
14262
14263
14264
14265
14266
14267
14268
14269
14270
14271
14272
14273
14274
14275
14276
14277
14278
14279
14280
14281
14282
14283
14284
14285
14286
14287
14288
14289
14290
14291
14292
14293
14294
14295
14296
14297
14298
14299
14300
14301
14302
14303
14304
14305
14306
14307
14308
14309
14310
14311
14312
14313
14314
14315
14316
14317
14318
14319
14320
14321
14322
14323
14324
14325
14326
14327
14328
14329
14330
14331
14332
14333
14334
14335
14336
14337
14338
14339
14340
14341
14342
14343
14344
14345
14346
14347
14348
14349
14350
14351
14352
14353
14354
14355
14356
14357
14358
14359
14360
14361
14362
14363
14364
14365
14366
14367
14368
14369
14370
14371
14372
14373
14374
14375
14376
14377
14378
14379
14380
14381
14382
14383
14384
14385
14386
14387
14388
14389
14390
14391
14392
14393
14394
14395
14396
14397
14398
14399
14400
14401
14402
14403
14404
14405
14406
14407
14408
14409
14410
14411
14412
14413
14414
14415
14416
14417
14418
14419
14420
14421
14422
14423
14424
14425
14426
14427
14428
14429
14430
14431
14432
14433
14434
14435
14436
14437
14438
14439
14440
14441
14442
14443
14444
14445
14446
14447
14448
14449
14450
14451
14452
14453
14454
14455
14456
14457
14458
14459
14460
14461
14462
14463
14464
14465
14466
14467
14468
14469
14470
14471
14472
14473
14474
14475
14476
14477
14478
14479
14480
14481
14482
14483
14484
14485
14486
14487
14488
14489
14490
14491
14492
14493
14494
14495
14496
14497
14498
14499
14500
14501
14502
14503
14504
14505
14506
14507
14508
14509
14510
14511
14512
14513
14514
14515
14516
14517
14518
14519
14520
14521
14522
14523
14524
14525
14526
14527
14528
14529
14530
14531
14532
14533
14534
14535
14536
14537
14538
14539
14540
14541
14542
14543
14544
14545
14546
14547
14548
14549
14550
14551
14552
14553
14554
14555
14556
14557
14558
14559
14560
14561
14562
14563
14564
14565
14566
14567
14568
14569
14570
14571
14572
14573
14574
14575
14576
14577
14578
14579
14580
14581
14582
14583
14584
14585
14586
14587
14588
14589
14590
14591
14592
14593
14594
14595
14596
14597
14598
14599
14600
14601
14602
14603
14604
14605
14606
14607
14608
14609
14610
14611
14612
14613
14614
14615
14616
14617
14618
14619
14620
14621
14622
14623
14624
14625
14626
14627
14628
14629
14630
14631
14632
14633
14634
14635
14636
14637
14638
14639
14640
14641
14642
14643
14644
14645
14646
14647
14648
14649
14650
14651
14652
14653
14654
14655
14656
14657
14658
14659
14660
14661
14662
14663
14664
14665
14666
14667
14668
14669
14670
14671
14672
14673
14674
14675
14676
14677
14678
14679
14680
14681
14682
14683
14684
14685
14686
14687
14688
14689
14690
14691
14692
14693
14694
14695
14696
14697
14698
14699
14700
14701
14702
14703
14704
14705
14706
14707
14708
14709
14710
14711
14712
14713
14714
14715
14716
14717
14718
14719
14720
14721
14722
14723
14724
14725
14726
14727
14728
14729
14730
14731
14732
14733
14734
14735
14736
14737
14738
14739
14740
14741
14742
14743
14744
14745
14746
14747
14748
14749
14750
14751
14752
14753
14754
14755
14756
14757
14758
14759
14760
14761
14762
14763
14764
14765
14766
14767
14768
14769
14770
14771
14772
14773
14774
14775
14776
14777
14778
14779
14780
14781
14782
14783
14784
14785
14786
14787
14788
14789
14790
14791
14792
14793
14794
14795
14796
14797
14798
14799
14800
14801
14802
14803
14804
14805
14806
14807
14808
14809
14810
14811
14812
14813
14814
14815
14816
14817
14818
14819
14820
14821
14822
14823
14824
14825
14826
14827
14828
14829
14830
14831
14832
14833
14834
14835
14836
14837
14838
14839
14840
14841
14842
14843
14844
14845
14846
14847
14848
14849
14850
14851
14852
14853
14854
14855
14856
14857
14858
14859
14860
14861
14862
14863
14864
14865
14866
14867
14868
14869
14870
14871
14872
14873
14874
14875
14876
14877
14878
14879
14880
14881
14882
14883
14884
14885
14886
14887
14888
14889
14890
14891
14892
14893
14894
14895
14896
14897
14898
14899
14900
14901
14902
14903
14904
14905
14906
14907
14908
14909
14910
14911
14912
14913
14914
14915
14916
14917
14918
14919
14920
14921
14922
14923
14924
14925
14926
14927
14928
14929
14930
14931
14932
14933
14934
14935
14936
14937
14938
14939
14940
14941
14942
14943
14944
14945
14946
14947
14948
14949
14950
14951
14952
14953
14954
14955
14956
14957
14958
14959
14960
14961
14962
14963
14964
14965
14966
14967
14968
14969
14970
14971
14972
14973
14974
14975
14976
14977
14978
14979
14980
14981
14982
14983
14984
14985
14986
14987
14988
14989
14990
14991
14992
14993
14994
14995
14996
14997
14998
14999
15000
15001
15002
15003
15004
15005
15006
15007
15008
15009
15010
15011
15012
15013
15014
15015
15016
15017
15018
15019
15020
15021
15022
15023
15024
15025
15026
15027
15028
15029
15030
15031
15032
15033
15034
15035
15036
15037
15038
15039
15040
15041
15042
15043
15044
15045
15046
15047
15048
15049
15050
15051
15052
15053
15054
15055
15056
15057
15058
15059
15060
15061
15062
15063
15064
15065
15066
15067
15068
15069
15070
15071
15072
15073
15074
15075
15076
15077
15078
15079
15080
15081
15082
15083
15084
15085
15086
15087
15088
15089
15090
15091
15092
15093
15094
15095
15096
15097
15098
15099
15100
15101
15102
15103
15104
15105
15106
15107
15108
15109
15110
15111
15112
15113
15114
15115
15116
15117
15118
15119
15120
15121
15122
15123
15124
15125
15126
15127
15128
15129
15130
15131
15132
15133
15134
15135
15136
15137
15138
15139
15140
15141
15142
15143
15144
15145
15146
15147
15148
15149
15150
15151
15152
15153
15154
15155
15156
15157
15158
15159
15160
15161
15162
15163
15164
15165
15166
15167
15168
15169
15170
15171
15172
15173
15174
15175
15176
15177
15178
15179
15180
15181
15182
15183
15184
15185
15186
15187
15188
15189
15190
15191
15192
15193
15194
15195
15196
15197
15198
15199
15200
15201
15202
15203
15204
15205
15206
15207
15208
15209
15210
15211
15212
15213
15214
15215
15216
15217
15218
15219
15220
15221
15222
15223
15224
15225
15226
15227
15228
15229
15230
15231
15232
15233
15234
15235
15236
15237
15238
15239
15240
15241
15242
15243
15244
15245
15246
15247
15248
15249
15250
15251
15252
15253
15254
15255
15256
15257
15258
15259
15260
15261
15262
15263
15264
15265
15266
15267
15268
15269
15270
15271
15272
15273
15274
15275
15276
15277
15278
15279
15280
15281
15282
15283
15284
15285
15286
15287
15288
15289
15290
15291
15292
15293
15294
15295
15296
15297
15298
15299
15300
15301
15302
15303
15304
15305
15306
15307
15308
15309
15310
15311
15312
15313
15314
15315
15316
15317
15318
15319
15320
15321
15322
15323
15324
15325
15326
15327
15328
15329
15330
15331
15332
15333
15334
15335
15336
15337
15338
15339
15340
15341
15342
15343
15344
15345
15346
15347
15348
15349
15350
15351
15352
15353
15354
15355
15356
15357
15358
15359
15360
15361
15362
15363
15364
15365
15366
15367
15368
15369
15370
15371
15372
15373
15374
15375
15376
15377
15378
15379
15380
15381
15382
15383
15384
15385
15386
15387
15388
15389
15390
15391
15392
15393
15394
15395
15396
15397
15398
15399
15400
15401
15402
15403
15404
15405
15406
15407
15408
15409
15410
15411
15412
15413
15414
15415
15416
15417
15418
15419
15420
15421
15422
15423
15424
15425
15426
15427
15428
15429
15430
15431
15432
15433
15434
15435
15436
15437
15438
15439
15440
15441
15442
15443
15444
15445
15446
15447
15448
15449
15450
15451
15452
15453
15454
15455
15456
15457
15458
15459
15460
15461
15462
15463
15464
15465
15466
15467
15468
15469
15470
15471
15472
15473
15474
15475
15476
15477
15478
15479
15480
15481
15482
15483
15484
15485
15486
15487
15488
15489
15490
15491
15492
15493
15494
15495
15496
15497
15498
15499
15500
15501
15502
15503
15504
15505
15506
15507
15508
15509
15510
15511
15512
15513
15514
15515
15516
15517
15518
15519
15520
15521
15522
15523
15524
15525
15526
15527
15528
15529
15530
15531
15532
15533
15534
15535
15536
15537
15538
15539
15540
15541
15542
15543
15544
15545
15546
15547
15548
15549
15550
15551
15552
15553
15554
15555
15556
15557
15558
15559
15560
15561
15562
15563
15564
15565
15566
15567
15568
15569
15570
15571
15572
15573
15574
15575
15576
15577
15578
15579
15580
15581
15582
15583
15584
15585
15586
15587
15588
15589
15590
15591
15592
15593
15594
15595
15596
15597
15598
15599
15600
15601
15602
15603
15604
15605
15606
15607
15608
15609
15610
15611
15612
15613
15614
15615
15616
15617
15618
15619
15620
15621
15622
15623
15624
15625
15626
15627
15628
15629
15630
15631
15632
15633
15634
15635
15636
15637
15638
15639
15640
15641
15642
15643
15644
15645
15646
15647
15648
15649
15650
15651
15652
15653
15654
15655
15656
15657
15658
15659
15660
15661
15662
15663
15664
15665
15666
15667
15668
15669
15670
15671
15672
15673
15674
15675
15676
15677
15678
15679
15680
15681
15682
15683
15684
15685
15686
15687
15688
15689
15690
15691
15692
15693
15694
15695
15696
15697
15698
15699
15700
15701
15702
15703
15704
15705
15706
15707
15708
15709
15710
15711
15712
15713
15714
15715
15716
15717
15718
15719
15720
15721
15722
15723
15724
15725
15726
15727
15728
15729
15730
15731
15732
15733
15734
15735
15736
15737
15738
15739
15740
15741
15742
15743
15744
15745
15746
15747
15748
15749
15750
15751
15752
15753
15754
15755
15756
15757
15758
15759
15760
15761
15762
15763
15764
15765
15766
15767
15768
15769
15770
15771
15772
15773
15774
15775
15776
15777
15778
15779
15780
15781
15782
15783
15784
15785
15786
15787
15788
15789
15790
15791
15792
15793
15794
15795
15796
15797
15798
15799
15800
15801
15802
15803
15804
15805
15806
15807
15808
15809
15810
15811
15812
15813
15814
15815
15816
15817
15818
15819
15820
15821
15822
15823
15824
15825
15826
15827
15828
15829
15830
15831
15832
15833
15834
15835
15836
15837
15838
15839
15840
15841
15842
15843
15844
15845
15846
15847
15848
15849
15850
15851
15852
15853
15854
15855
15856
15857
15858
15859
15860
15861
15862
15863
15864
15865
15866
15867
15868
15869
15870
15871
15872
15873
15874
15875
15876
15877
15878
15879
15880
15881
15882
15883
15884
15885
15886
15887
15888
15889
15890
15891
15892
15893
15894
15895
15896
15897
15898
15899
15900
15901
15902
15903
15904
15905
15906
15907
15908
15909
15910
15911
15912
15913
15914
15915
15916
15917
15918
15919
15920
15921
15922
15923
15924
15925
15926
15927
15928
15929
15930
15931
15932
15933
15934
15935
15936
15937
15938
15939
15940
15941
15942
15943
15944
15945
15946
15947
15948
15949
15950
15951
15952
15953
15954
15955
15956
15957
15958
15959
15960
15961
15962
15963
15964
15965
15966
15967
15968
15969
15970
15971
15972
15973
15974
15975
15976
15977
15978
15979
15980
15981
15982
15983
15984
15985
15986
15987
15988
15989
15990
15991
15992
15993
15994
15995
15996
15997
15998
15999
16000
16001
16002
16003
16004
16005
16006
16007
16008
16009
16010
16011
16012
16013
16014
16015
16016
16017
16018
16019
16020
16021
16022
16023
16024
16025
16026
16027
16028
16029
16030
16031
16032
16033
16034
16035
16036
16037
16038
16039
16040
16041
16042
16043
16044
16045
16046
16047
16048
16049
16050
16051
16052
16053
16054
16055
16056
16057
16058
16059
16060
16061
16062
16063
16064
16065
16066
16067
16068
16069
16070
16071
16072
16073
16074
16075
16076
16077
16078
16079
16080
16081
16082
16083
16084
16085
16086
16087
16088
16089
16090
16091
16092
16093
16094
16095
16096
16097
16098
16099
16100
16101
16102
16103
16104
16105
16106
16107
16108
16109
16110
16111
16112
16113
16114
16115
16116
16117
16118
16119
16120
16121
16122
16123
16124
16125
16126
16127
16128
16129
16130
16131
16132
16133
16134
16135
16136
16137
16138
16139
16140
16141
16142
16143
16144
16145
16146
16147
16148
16149
16150
16151
16152
16153
16154
16155
16156
16157
16158
16159
16160
16161
16162
16163
16164
16165
16166
16167
16168
16169
16170
16171
16172
16173
16174
16175
16176
16177
16178
16179
16180
16181
16182
16183
16184
16185
16186
16187
16188
16189
16190
16191
16192
16193
16194
16195
16196
16197
16198
16199
16200
16201
16202
16203
16204
16205
16206
16207
16208
16209
16210
16211
16212
16213
16214
16215
16216
16217
16218
16219
16220
16221
16222
16223
16224
16225
16226
16227
16228
16229
16230
16231
16232
16233
16234
16235
16236
16237
16238
16239
16240
16241
16242
16243
16244
16245
16246
16247
16248
16249
16250
16251
16252
16253
16254
16255
16256
16257
16258
16259
16260
16261
16262
16263
16264
16265
16266
16267
16268
16269
16270
16271
16272
16273
16274
16275
16276
16277
16278
16279
16280
16281
16282
16283
16284
16285
16286
16287
16288
16289
16290
16291
16292
16293
16294
16295
16296
16297
16298
16299
16300
16301
16302
16303
16304
16305
16306
16307
16308
16309
16310
16311
16312
16313
16314
16315
16316
16317
16318
16319
16320
16321
16322
16323
16324
16325
16326
16327
16328
16329
16330
16331
16332
16333
16334
16335
16336
16337
16338
16339
16340
16341
16342
16343
16344
16345
16346
16347
16348
16349
16350
16351
16352
16353
16354
16355
16356
16357
16358
16359
16360
16361
16362
16363
16364
16365
16366
16367
16368
16369
16370
16371
16372
16373
16374
16375
16376
16377
16378
16379
16380
16381
16382
16383
16384
16385
16386
16387
16388
16389
16390
16391
16392
16393
16394
16395
16396
16397
16398
16399
16400
16401
16402
16403
16404
16405
16406
16407
16408
16409
16410
16411
16412
16413
16414
16415
16416
16417
16418
16419
16420
16421
16422
16423
16424
16425
16426
16427
16428
16429
16430
16431
16432
16433
16434
16435
16436
16437
16438
16439
16440
16441
16442
16443
16444
16445
16446
16447
16448
16449
16450
16451
16452
16453
16454
16455
16456
16457
16458
16459
16460
16461
16462
16463
16464
16465
16466
16467
16468
16469
16470
16471
16472
16473
16474
16475
16476
16477
16478
16479
16480
16481
16482
16483
16484
16485
16486
16487
16488
16489
16490
16491
16492
16493
16494
16495
16496
16497
16498
16499
16500
16501
16502
16503
16504
16505
16506
16507
16508
16509
16510
16511
16512
16513
16514
16515
16516
16517
16518
16519
16520
16521
16522
16523
16524
16525
16526
16527
16528
16529
16530
16531
16532
16533
16534
16535
16536
16537
16538
16539
16540
16541
16542
16543
16544
16545
16546
16547
16548
16549
16550
16551
16552
16553
16554
16555
16556
16557
16558
16559
16560
16561
16562
16563
16564
16565
16566
16567
16568
16569
16570
16571
16572
16573
16574
16575
16576
16577
16578
16579
16580
16581
16582
16583
16584
16585
16586
16587
16588
16589
16590
16591
16592
16593
16594
16595
16596
16597
16598
16599
16600
16601
16602
16603
16604
16605
16606
16607
16608
16609
16610
16611
16612
16613
16614
16615
16616
16617
16618
16619
16620
16621
16622
16623
16624
16625
16626
16627
16628
16629
16630
16631
16632
16633
16634
16635
16636
16637
16638
16639
16640
16641
16642
16643
16644
16645
16646
16647
16648
16649
16650
16651
16652
16653
16654
16655
16656
16657
16658
16659
16660
16661
16662
16663
16664
16665
16666
16667
16668
16669
16670
16671
16672
16673
16674
16675
16676
16677
16678
16679
16680
16681
16682
16683
16684
16685
16686
16687
16688
16689
16690
16691
16692
16693
16694
16695
16696
16697
16698
16699
16700
16701
16702
16703
16704
16705
16706
16707
16708
16709
16710
16711
16712
16713
16714
16715
16716
16717
16718
16719
16720
16721
16722
16723
16724
16725
16726
16727
16728
16729
16730
16731
16732
16733
16734
16735
16736
16737
16738
16739
16740
16741
16742
16743
16744
16745
16746
16747
16748
16749
16750
16751
16752
16753
16754
16755
16756
16757
16758
16759
16760
16761
16762
16763
16764
16765
16766
16767
16768
16769
16770
16771
16772
16773
16774
16775
16776
16777
16778
16779
16780
16781
16782
16783
16784
16785
16786
16787
16788
16789
16790
16791
16792
16793
16794
16795
16796
16797
16798
16799
16800
16801
16802
16803
16804
16805
16806
16807
16808
16809
16810
16811
16812
16813
diff -urN linux-2.6.28.2-0rig//arch/arm/mach-at91/include/mach/cpu.h linux-2.6.28.2/arch/arm/mach-at91/include/mach/cpu.h
--- linux-2.6.28.2-0rig//arch/arm/mach-at91/include/mach/cpu.h	2009-01-29 08:39:33.000000000 +0100
+++ linux-2.6.28.2/arch/arm/mach-at91/include/mach/cpu.h	2009-01-29 08:52:44.000000000 +0100
@@ -99,5 +99,6 @@
  * definitions may reduce clutter in common drivers.
  */
 #define cpu_is_at32ap7000()	(0)
+#define cpu_is_at32ap7200()	(0)
 
 #endif
diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/atstk1005.c linux-2.6.28.2/arch/avr32/boards/atstk1000/atstk1005.c
--- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/atstk1005.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/atstk1005.c	2009-01-29 08:52:48.000000000 +0100
@@ -0,0 +1,225 @@
+/*
+ * ATSTK1005 daughterboard-specific init code
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/string.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+
+#include <asm/atmel-mci.h>
+#include <asm/setup.h>
+
+#include <mach/at32ap720x.h>
+#include <mach/board.h>
+#include <mach/init.h>
+#include <mach/portmux.h>
+#include <mach/smc.h>
+
+#include "atstk1000.h"
+
+/* Oscillator frequencies. These are board specific */
+unsigned long at32_board_osc_rates[4] = {
+	[0] = 20000000,	/* 20 MHz on osc0 */
+	[1] = 0,	/* Nothing on osc1 */
+	[2] = 12000000,	/* 12 MHz on osc2 */
+	[3] = 32768,	/* 32.768 kHz on RTC osc */
+};
+
+struct eth_addr {
+	u8 addr[6];
+};
+
+static struct eth_addr __initdata hw_addr;
+static struct eth_platform_data __initdata eth_data;
+
+static struct mci_platform_data mci_data __initdata = {
+	.slot[0]	= {
+		.detect_pin		= GPIO_PIN_NONE,
+		.wp_pin			= GPIO_PIN_NONE,
+		.bus_width		= 4,
+	},
+	.slot[1]	= {
+		.detect_pin		= GPIO_PIN_PA(30),
+		.wp_pin			= GPIO_PIN_PA(31),
+		.bus_width		= 8,
+	},
+};
+
+static struct spi_board_info spi0_board_info[] __initdata = {
+	{
+		/* AT45DB642D: 8MB DataFlash */
+		.modalias	= "mtd_dataflash",
+		.max_speed_hz	= 8000000,
+		.chip_select	= 0,
+		.mode		= SPI_MODE_0,
+	}, {
+		/* QVGA display */
+		.modalias	= "ltv350qv",
+		.max_speed_hz	= 8000000,
+		.chip_select	= 2,
+		.mode		= SPI_MODE_3,
+	},
+};
+
+static struct smc_timing nand_timing __initdata = {
+	.ncs_read_setup		= 0,
+	.nrd_setup		= 10,
+	.ncs_write_setup	= 0,
+	.nwe_setup		= 10,
+
+	.ncs_read_pulse		= 30,
+	.nrd_pulse		= 15,
+	.ncs_write_pulse	= 30,
+	.nwe_pulse		= 15,
+
+	.read_cycle		= 30,
+	.write_cycle		= 30,
+
+	.ncs_read_recover	= 0,
+	.nrd_recover		= 15,
+	.ncs_write_recover	= 0,
+	.nwe_recover		= 50,
+};
+
+static struct smc_config nand_config __initdata = {
+	.bus_width		= 1,
+	.nrd_controlled		= 1,
+	.nwe_controlled		= 1,
+	.nwait_mode		= 0,
+	.byte_write		= 0,
+	.tdf_cycles		= 3,
+	.tdf_mode		= 0,
+};
+
+static struct mtd_partition nand_partitions[] = {
+	{
+		.name	= "u-boot",
+		.offset	= 0,
+		.size	= 131072,
+	}, {
+		.name	= "kernel",
+		.offset	= 262144,
+		.size	= 2097152,
+	}, {
+		.name	= "user",
+		.offset	= 2359296,
+		.size	= MTDPART_SIZ_FULL,
+	},
+};
+
+/* Isn't this rather more complicated than necessary? */
+static struct mtd_partition *nand_part_info(int size, int *num_partitions)
+{
+	*num_partitions = ARRAY_SIZE(nand_partitions);
+	return nand_partitions;
+}
+
+static struct atmel_nand_data nand_data __initdata = {
+	.cle		= 21,
+	.ale		= 22,
+	.rdy_pin	= GPIO_PIN_PE(31),
+	.enable_pin	= GPIO_PIN_PF(2),
+	.det_pin	= GPIO_PIN_NONE,
+	.partition_info	= nand_part_info,
+};
+
+
+/*
+ * Grab ethernet address and PHY address provided by the boot loader.
+ */
+static int __init parse_tag_ethernet(struct tag *tag)
+{
+	struct tag_ethernet *etag = &tag->u.ethernet;
+
+	if (etag->mac_index == 0) {
+		eth_data.phy_mask = ~(1U << etag->mii_phy_addr);
+		memcpy(&hw_addr.addr, etag->hw_address, sizeof(hw_addr.addr));
+	}
+
+	return 0;
+}
+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
+
+/*
+ * We need to get rid of this crap and pass the mac address to the
+ * driver explicitly.
+ */
+#include <linux/clk.h>
+#include <linux/etherdevice.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+static void __init set_hw_addr(struct platform_device *pdev)
+{
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	const u8 *addr;
+	void __iomem *regs;
+	struct clk *pclk;
+
+	if (!res)
+		return;
+	if (pdev->id != 0)
+		return;
+
+	addr = hw_addr.addr;
+	if (!is_valid_ether_addr(addr))
+		return;
+
+	/*
+	 * Since this is board-specific code, we'll cheat and use the
+	 * physical address directly as we happen to know that it's
+	 * the same as the virtual address.
+	 */
+	regs = (void __iomem __force *)res->start;
+	pclk = clk_get(&pdev->dev, "pclk");
+	if (!pclk)
+		return;
+
+	clk_enable(pclk);
+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
+		     | (addr[1] << 8) | addr[0], regs + 0x98);
+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
+	clk_disable(pclk);
+	clk_put(pclk);
+}
+
+void __init setup_board(void)
+{
+	at32_map_usart(4, 0);	/* USART4: /dev/ttyS0, DB9 */
+	at32_setup_serial_console(0);
+}
+
+static int __init atstk1005_init(void)
+{
+	struct platform_device	*lcdc_pdev;
+
+	at32_add_device_usart(0);
+
+	set_hw_addr(at32_add_device_eth(0, &eth_data));
+	lcdc_pdev = at32_add_device_lcdc(0, &atstk1000_lcdc_data,
+			fbmem_start, fbmem_size, 0);
+	at32_add_device_mpop(0, lcdc_pdev, fbmem_start, fbmem_size);
+	at32_add_device_mci(0, &mci_data);
+	at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
+
+	/* NAND Flash */
+	smc_set_timing(&nand_config, &nand_timing);
+	smc_set_configuration(3, &nand_config);
+	at32_add_device_nand(0, &nand_data);
+
+	/* USB OHCI/EHCI host */
+	at32_add_device_ohci(0);
+	at32_add_device_ehci(0);
+
+	return 0;
+}
+postcore_initcall(atstk1005_init);
diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Kconfig linux-2.6.28.2/arch/avr32/boards/atstk1000/Kconfig
--- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Kconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/Kconfig	2009-01-29 08:52:48.000000000 +0100
@@ -18,6 +18,10 @@
 	bool "ATSTK1004"
 	select CPU_AT32AP7002
 
+config BOARD_ATSTK1005
+	bool "ATSTK1005"
+	select CPU_AT32AP7200
+
 config BOARD_ATSTK1006
 	bool "ATSTK1006"
 	select CPU_AT32AP7000
diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Makefile linux-2.6.28.2/arch/avr32/boards/atstk1000/Makefile
--- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Makefile	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/Makefile	2009-01-29 08:52:48.000000000 +0100
@@ -2,4 +2,5 @@
 obj-$(CONFIG_BOARD_ATSTK1002)	+= atstk1002.o
 obj-$(CONFIG_BOARD_ATSTK1003)	+= atstk1003.o
 obj-$(CONFIG_BOARD_ATSTK1004)	+= atstk1004.o
+obj-$(CONFIG_BOARD_ATSTK1005)	+= atstk1005.o
 obj-$(CONFIG_BOARD_ATSTK1006)	+= atstk1002.o
diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atngw100_defconfig linux-2.6.28.2/arch/avr32/configs/atngw100_defconfig
--- linux-2.6.28.2-0rig//arch/avr32/configs/atngw100_defconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/configs/atngw100_defconfig	2009-01-29 08:52:48.000000000 +0100
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc1
-# Tue Aug  5 16:00:47 2008
+# Linux kernel version: 2.6.27.4
+# Thu Nov 13 14:33:33 2008
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -130,11 +130,15 @@
 CONFIG_SUBARCH_AVR32B=y
 CONFIG_MMU=y
 CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PORTMUX_PIO=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
 # CONFIG_BOARD_ATSTK1000 is not set
 CONFIG_BOARD_ATNGW100=y
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MIMC200 is not set
+# CONFIG_BOARD_ATNGW100_EVKLCD10X is not set
 CONFIG_LOADER_U_BOOT=y
 
 #
@@ -177,7 +181,7 @@
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
@@ -615,6 +619,7 @@
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=m
 
 #
@@ -664,6 +669,7 @@
 #
 # SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL_HAVE_PDC=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
 
@@ -706,7 +712,7 @@
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT32AP700X_WDT=y
+CONFIG_AT32_WDT=y
 
 #
 # Sonics Silicon Backplane
@@ -720,6 +726,7 @@
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -751,11 +758,14 @@
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -806,6 +816,7 @@
 #
 # CONFIG_MMC_SDHCI is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -880,11 +891,13 @@
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
+# CONFIG_RTC_DRV_AVR32_AST is not set
 CONFIG_DMADEVICES=y
 
 #
 # DMA Devices
 #
+# CONFIG_ATMEL_PDCA is not set
 CONFIG_DW_DMAC=y
 CONFIG_DMA_ENGINE=y
 
@@ -898,13 +911,13 @@
 #
 # File systems
 #
-CONFIG_EXT2_FS=m
+CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 # CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=m
+CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
@@ -944,7 +957,7 @@
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_CONFIGFS_FS=m
+CONFIG_CONFIGFS_FS=y
 
 #
 # Miscellaneous filesystems
diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1002_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1002_defconfig
--- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1002_defconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/configs/atstk1002_defconfig	2009-01-29 08:52:49.000000000 +0100
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc1
-# Mon Aug  4 16:02:27 2008
+# Linux kernel version: 2.6.27.4
+# Wed Nov 12 10:28:45 2008
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -129,20 +129,24 @@
 CONFIG_SUBARCH_AVR32B=y
 CONFIG_MMU=y
 CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PORTMUX_PIO=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
 CONFIG_BOARD_ATSTK1000=y
 # CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MIMC200 is not set
 CONFIG_BOARD_ATSTK1002=y
 # CONFIG_BOARD_ATSTK1003 is not set
 # CONFIG_BOARD_ATSTK1004 is not set
+# CONFIG_BOARD_ATSTK1005 is not set
 # CONFIG_BOARD_ATSTK1006 is not set
 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
-# CONFIG_BOARD_ATSTK1000_J2_LED is not set
+CONFIG_BOARD_ATSTK1000_J2_LED=y
 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+CONFIG_BOARD_ATSTK1000_J2_RGB=y
 CONFIG_BOARD_ATSTK1000_EXTDAC=y
 CONFIG_LOADER_U_BOOT=y
 
@@ -186,7 +190,7 @@
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
@@ -360,7 +364,8 @@
 #
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -421,12 +426,23 @@
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
 # CONFIG_MTD_NAND is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -502,7 +518,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
-CONFIG_TUN=m
+# CONFIG_TUN is not set
 # CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
@@ -561,7 +577,7 @@
 #
 # Input device support
 #
-CONFIG_INPUT=m
+CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 CONFIG_INPUT_POLLDEV=m
 
@@ -590,6 +606,8 @@
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MOUSE_GPIO=m
 # CONFIG_INPUT_JOYSTICK is not set
@@ -606,8 +624,12 @@
 #
 # Character devices
 #
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -634,6 +656,7 @@
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=m
 
 #
@@ -663,7 +686,7 @@
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-CONFIG_AT24=m
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
@@ -683,6 +706,7 @@
 #
 # SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL_HAVE_PDC=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
 
@@ -725,7 +749,7 @@
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT32AP700X_WDT=y
+CONFIG_AT32_WDT=y
 
 #
 # Sonics Silicon Backplane
@@ -739,6 +763,7 @@
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -784,6 +809,7 @@
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
+# CONFIG_FB_ATMEL_MPOP is not set
 # CONFIG_FB_VIRTUAL is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
@@ -797,6 +823,12 @@
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
 # CONFIG_LOGO is not set
 CONFIG_SOUND=m
 CONFIG_SND=m
@@ -820,11 +852,14 @@
 # CONFIG_SOUND_PRIME is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -876,6 +911,7 @@
 #
 # CONFIG_MMC_SDHCI is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -952,11 +988,13 @@
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
+# CONFIG_RTC_DRV_AVR32_AST is not set
 CONFIG_DMADEVICES=y
 
 #
 # DMA Devices
 #
+# CONFIG_ATMEL_PDCA is not set
 CONFIG_DW_DMAC=y
 CONFIG_DMA_ENGINE=y
 
@@ -1017,7 +1055,7 @@
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONFIGFS_FS=y
 
 #
 # Miscellaneous filesystems
@@ -1031,7 +1069,8 @@
 # CONFIG_EFS_FS is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_WRITEBUFFER is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
@@ -1039,6 +1078,12 @@
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=m
@@ -1173,7 +1218,7 @@
 #
 # Crypto core or helper
 #
-CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_AEAD=m
 CONFIG_CRYPTO_BLKCIPHER=m
 CONFIG_CRYPTO_HASH=m
@@ -1247,8 +1292,8 @@
 #
 # Compression
 #
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_HW is not set
 
 #
@@ -1258,7 +1303,7 @@
 # CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=m
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
@@ -1266,6 +1311,8 @@
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1003_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1003_defconfig
--- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1003_defconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/configs/atstk1003_defconfig	2009-01-29 08:52:49.000000000 +0100
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc1
-# Tue Aug  5 15:34:44 2008
+# Linux kernel version: 2.6.27.4
+# Wed Nov 12 10:33:33 2008
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -34,12 +34,9 @@
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-# CONFIG_TASK_XACCT is not set
-CONFIG_AUDIT=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_CGROUPS is not set
@@ -71,7 +68,7 @@
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
+CONFIG_SLUB_DEBUG=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
@@ -90,6 +87,7 @@
 CONFIG_HAVE_CLK=y
 CONFIG_PROC_PAGE_MONITOR=y
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
@@ -131,20 +129,24 @@
 CONFIG_SUBARCH_AVR32B=y
 CONFIG_MMU=y
 CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PORTMUX_PIO=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7001=y
 CONFIG_BOARD_ATSTK1000=y
 # CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MIMC200 is not set
 # CONFIG_BOARD_ATSTK1002 is not set
 CONFIG_BOARD_ATSTK1003=y
 # CONFIG_BOARD_ATSTK1004 is not set
+# CONFIG_BOARD_ATSTK1005 is not set
 # CONFIG_BOARD_ATSTK1006 is not set
 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
-# CONFIG_BOARD_ATSTK1000_J2_LED is not set
+CONFIG_BOARD_ATSTK1000_J2_LED=y
 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+CONFIG_BOARD_ATSTK1000_J2_RGB=y
 CONFIG_BOARD_ATSTK1000_EXTDAC=y
 CONFIG_LOADER_U_BOOT=y
 
@@ -188,7 +190,7 @@
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
@@ -239,40 +241,71 @@
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
 # CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
+CONFIG_LLC=m
 # CONFIG_LLC2 is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
@@ -331,7 +364,8 @@
 #
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -397,7 +431,15 @@
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -458,9 +500,7 @@
 # CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_DH is not set
 CONFIG_ATA=m
 # CONFIG_ATA_NONSTANDARD is not set
@@ -477,7 +517,32 @@
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_NET_ETHERNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -509,7 +574,7 @@
 #
 # Input device support
 #
-CONFIG_INPUT=m
+CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 CONFIG_INPUT_POLLDEV=m
 
@@ -521,7 +586,7 @@
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_EVBUG is not set
 
 #
@@ -538,6 +603,8 @@
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MOUSE_GPIO=m
 # CONFIG_INPUT_JOYSTICK is not set
@@ -555,7 +622,7 @@
 # Character devices
 #
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -582,6 +649,7 @@
 CONFIG_I2C=m
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_ALGOBIT=m
 
 #
@@ -611,7 +679,7 @@
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-CONFIG_AT24=m
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
@@ -631,6 +699,7 @@
 #
 # SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL_HAVE_PDC=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
 
@@ -673,7 +742,7 @@
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT32AP700X_WDT=y
+CONFIG_AT32_WDT=y
 
 #
 # Sonics Silicon Backplane
@@ -687,6 +756,7 @@
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -726,8 +796,8 @@
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PCM_OSS_PLUGINS=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
 # CONFIG_SND_DRIVERS is not set
@@ -738,11 +808,14 @@
 # CONFIG_SOUND_PRIME is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -750,7 +823,7 @@
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_DEBUG_FS=y
+# CONFIG_USB_GADGET_DEBUG_FS is not set
 CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 CONFIG_USB_GADGET_ATMEL_USBA=y
@@ -787,33 +860,34 @@
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
-CONFIG_MMC_TEST=m
+# CONFIG_MMC_TEST is not set
 
 #
 # MMC/SD Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
 CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
 CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS=m
 
 #
 # LED drivers
 #
 CONFIG_LEDS_ATMEL_PWM=m
 # CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO=m
 # CONFIG_LEDS_PCA955X is not set
 
 #
 # LED Triggers
 #
 CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -870,11 +944,13 @@
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
+# CONFIG_RTC_DRV_AVR32_AST is not set
 CONFIG_DMADEVICES=y
 
 #
 # DMA Devices
 #
+# CONFIG_ATMEL_PDCA is not set
 CONFIG_DW_DMAC=y
 CONFIG_DMA_ENGINE=y
 
@@ -888,13 +964,13 @@
 #
 # File systems
 #
-CONFIG_EXT2_FS=m
+CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 # CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=m
+CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
@@ -935,7 +1011,7 @@
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_CONFIGFS_FS=m
+CONFIG_CONFIGFS_FS=y
 
 #
 # Miscellaneous filesystems
@@ -958,16 +1034,39 @@
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
+CONFIG_MINIX_FS=m
 # CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
 
 #
 # Partition Types
@@ -1036,6 +1135,8 @@
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1068,7 +1169,88 @@
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
@@ -1077,15 +1259,16 @@
 # CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=m
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 CONFIG_CRC7=m
 # CONFIG_LIBCRC32C is not set
-CONFIG_AUDIT_GENERIC=y
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1004_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1004_defconfig
--- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1004_defconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/configs/atstk1004_defconfig	2009-01-29 08:52:49.000000000 +0100
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc1
-# Tue Aug  5 15:38:56 2008
+# Linux kernel version: 2.6.27.4
+# Wed Nov 12 10:35:14 2008
 #
 CONFIG_AVR32=y
 CONFIG_GENERIC_GPIO=y
@@ -30,8 +30,10 @@
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
@@ -41,14 +43,16 @@
 # CONFIG_GROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
+CONFIG_RELAY=y
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
@@ -56,19 +60,23 @@
 CONFIG_ELF_CORE=y
 # CONFIG_COMPAT_BRK is not set
 # CONFIG_BASE_FULL is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
 # CONFIG_SLAB is not set
-# CONFIG_SLUB is not set
-CONFIG_SLOB=y
-# CONFIG_PROFILING is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
 # CONFIG_MARKERS is not set
+CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
 # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
 # CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
@@ -77,36 +85,68 @@
 # CONFIG_HAVE_DMA_ATTRS is not set
 # CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_PROC_PAGE_MONITOR=y
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=1
-# CONFIG_MODULES is not set
-# CONFIG_BLOCK is not set
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_CLASSIC_RCU=y
 
 #
 # System Type and features
 #
-# CONFIG_TICK_ONESHOT is not set
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_SUBARCH_AVR32B=y
 CONFIG_MMU=y
 CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PORTMUX_PIO=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7002=y
 CONFIG_BOARD_ATSTK1000=y
 # CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MIMC200 is not set
 # CONFIG_BOARD_ATSTK1002 is not set
 # CONFIG_BOARD_ATSTK1003 is not set
 CONFIG_BOARD_ATSTK1004=y
+# CONFIG_BOARD_ATSTK1005 is not set
 # CONFIG_BOARD_ATSTK1006 is not set
 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
-# CONFIG_BOARD_ATSTK1000_J2_LED is not set
+CONFIG_BOARD_ATSTK1000_J2_LED=y
+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
+CONFIG_BOARD_ATSTK1000_J2_RGB=y
 CONFIG_BOARD_ATSTK1000_EXTDAC=y
 CONFIG_LOADER_U_BOOT=y
 
@@ -144,25 +184,43 @@
 CONFIG_NR_QUICK=2
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_OWNERSHIP_TRACE is not set
-# CONFIG_NMI_DEBUGGING is not set
+CONFIG_NMI_DEBUGGING=y
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
 # CONFIG_HZ_300 is not set
 # CONFIG_HZ_1000 is not set
 CONFIG_HZ=250
-# CONFIG_SCHED_HRTICK is not set
+CONFIG_SCHED_HRTICK=y
 CONFIG_CMDLINE=""
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # CPU Frequency scaling
 #
-# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AT32AP=y
 
 #
 # Bus options
@@ -183,40 +241,71 @@
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
 # CONFIG_ARPD is not set
 # CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
 # CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
+CONFIG_LLC=m
 # CONFIG_LLC2 is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
@@ -230,6 +319,7 @@
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
@@ -257,6 +347,8 @@
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
@@ -271,6 +363,14 @@
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
 # CONFIG_MTD_OOPS is not set
 
 #
@@ -311,11 +411,13 @@
 #
 # Self-contained MTD device drivers
 #
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_DATAFLASH=m
+CONFIG_MTD_M25P80=m
+CONFIG_M25PXX_USE_FAST_READ=y
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
 
 #
 # Disk-On-Chip Device Drivers
@@ -329,24 +431,186 @@
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
-# CONFIG_MISC_DEVICES is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=m
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=m
+# CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_HAVE_IDE is not set
 
 #
 # SCSI device support
 #
-# CONFIG_SCSI_DMA is not set
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
-# CONFIG_NETDEVICES is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+CONFIG_PATA_AT32=m
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MOUSE_GPIO=m
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
@@ -357,8 +621,12 @@
 #
 # Character devices
 #
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -371,7 +639,7 @@
 #
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_SERIAL_ATMEL_PDC is not set
+CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
@@ -380,14 +648,62 @@
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL_HAVE_PDC=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
 
@@ -395,15 +711,19 @@
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
-# CONFIG_SPI_SPIDEV is not set
+CONFIG_SPI_SPIDEV=m
 # CONFIG_SPI_TLE62X0 is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
-# CONFIG_GPIO_SYSFS is not set
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
 
 #
 # PCI GPIO expanders:
@@ -426,7 +746,7 @@
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT32AP700X_WDT=y
+CONFIG_AT32_WDT=y
 
 #
 # Sonics Silicon Backplane
@@ -440,6 +760,7 @@
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -485,6 +806,7 @@
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
+# CONFIG_FB_ATMEL_MPOP is not set
 # CONFIG_FB_VIRTUAL is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
@@ -498,20 +820,51 @@
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
 # CONFIG_LOGO is not set
-# CONFIG_SOUND is not set
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_AT73C213=m
+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
 CONFIG_USB_GADGET_SELECTED=y
 # CONFIG_USB_GADGET_AMD5536UDC is not set
 CONFIG_USB_GADGET_ATMEL_USBA=y
@@ -528,18 +881,54 @@
 # CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
 CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=y
-# CONFIG_USB_ETH_RNDIS is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_MMC is not set
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
+CONFIG_MMC_SPI=m
 # CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_ATMEL_PWM=m
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -551,12 +940,28 @@
 # RTC interfaces
 #
 CONFIG_RTC_INTF_SYSFS=y
-# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
 # CONFIG_RTC_DRV_TEST is not set
 
 #
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
 # SPI RTC drivers
 #
 # CONFIG_RTC_DRV_M41T94 is not set
@@ -580,18 +985,62 @@
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
-# CONFIG_DMADEVICES is not set
+# CONFIG_RTC_DRV_AVR32_AST is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_ATMEL_PDCA is not set
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+CONFIG_DMATEST=m
 # CONFIG_UIO is not set
 
 #
 # File systems
 #
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
 
 #
 # Pseudo filesystems
@@ -603,14 +1052,22 @@
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONFIGFS_FS=y
 
 #
 # Miscellaneous filesystems
 #
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_WRITEBUFFER is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
@@ -618,8 +1075,85 @@
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_NLS is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
 # CONFIG_DLM is not set
 
 #
@@ -631,11 +1165,43 @@
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 
 #
@@ -644,7 +1210,88 @@
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_HW is not set
 
 #
 # Library routines
@@ -652,16 +1299,19 @@
 CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_FIRST_BIT is not set
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
+CONFIG_CRC7=m
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1005_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1005_defconfig
--- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1005_defconfig	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/configs/atstk1005_defconfig	2009-01-29 08:52:49.000000000 +0100
@@ -0,0 +1,1505 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27.4
+# Fri Nov  7 10:22:27 2008
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_MARKERS is not set
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+# CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type and features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SUBARCH_AVR32B=y
+CONFIG_MMU=y
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PORTMUX_GPIO_V2=y
+CONFIG_TIMER_AST=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP720X=y
+CONFIG_CPU_AT32AP7200=y
+CONFIG_BOARD_ATSTK1000=y
+# CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_FAVR_32 is not set
+# CONFIG_BOARD_MIMC200 is not set
+# CONFIG_BOARD_ATSTK1002 is not set
+# CONFIG_BOARD_ATSTK1003 is not set
+# CONFIG_BOARD_ATSTK1004 is not set
+CONFIG_BOARD_ATSTK1005=y
+# CONFIG_BOARD_ATSTK1006 is not set
+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
+CONFIG_BOARD_ATSTK1000_J2_LED=y
+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
+CONFIG_BOARD_ATSTK1000_J2_RGB=y
+CONFIG_BOARD_ATSTK1000_EXTDAC=y
+CONFIG_LOADER_U_BOOT=y
+
+#
+# Atmel AVR32 AP options
+#
+CONFIG_LOAD_ADDRESS=0x10000000
+CONFIG_ENTRY_ADDRESS=0x90000000
+CONFIG_PHYS_OFFSET=0x10000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_QUICKLIST=y
+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=2
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_OWNERSHIP_TRACE is not set
+CONFIG_NMI_DEBUGGING=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_CMDLINE=""
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AT32AP=y
+
+#
+# Bus options
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=m
+CONFIG_MTD_M25P80=m
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=m
+# CONFIG_ATMEL_TCLIB is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=m
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HAVE_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+CONFIG_PATA_AT32=m
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+CONFIG_MACB=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MOUSE_GPIO=m
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=m
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+CONFIG_I2C_TINY_USB=m
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT32_WDT=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_ATMEL_MPOP is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_AT73C213=m
+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_ATMEL_USBA=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+CONFIG_MMC_TEST=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_ATMELMCI=y
+# CONFIG_MMC_ATMELMCI_DMA is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_ATMEL_PWM=m
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT32AP700X is not set
+CONFIG_RTC_DRV_AVR32_AST=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_ATMEL_PDCA=y
+CONFIG_DW_DMAC=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+CONFIG_DMATEST=m
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=m
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1006_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1006_defconfig
--- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1006_defconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/configs/atstk1006_defconfig	2009-01-29 09:11:15.000000000 +0100
@@ -124,6 +124,7 @@
 CONFIG_SUBARCH_AVR32B=y
 CONFIG_MMU=y
 CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PORTMUX_PIO=y
 CONFIG_PLATFORM_AT32AP=y
 CONFIG_CPU_AT32AP700X=y
 CONFIG_CPU_AT32AP7000=y
@@ -137,9 +138,9 @@
 CONFIG_BOARD_ATSTK1006=y
 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
-# CONFIG_BOARD_ATSTK1000_J2_LED is not set
+CONFIG_BOARD_ATSTK1000_J2_LED=y
 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+CONFIG_BOARD_ATSTK1000_J2_RGB=y
 CONFIG_BOARD_ATSTK1000_EXTDAC=y
 CONFIG_LOADER_U_BOOT=y
 
@@ -355,7 +356,8 @@
 CONFIG_MTD_CHAR=y
 CONFIG_HAVE_MTD_OTP=y
 CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -419,7 +421,7 @@
 # CONFIG_MTD_DOC2001PLUS is not set
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_ECC_SMC=y
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
@@ -519,7 +521,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
-CONFIG_TUN=m
+# CONFIG_TUN is not set
 # CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
@@ -581,7 +583,7 @@
 #
 # Input device support
 #
-CONFIG_INPUT=m
+CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 CONFIG_INPUT_POLLDEV=m
 
@@ -610,6 +612,8 @@
 CONFIG_INPUT_MOUSE=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MOUSE_GPIO=m
 # CONFIG_INPUT_JOYSTICK is not set
@@ -626,8 +630,12 @@
 #
 # Character devices
 #
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -704,6 +712,7 @@
 #
 # SPI Master Controller Drivers
 #
+CONFIG_SPI_ATMEL_HAVE_PDC=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_SPI_BITBANG is not set
 
@@ -752,6 +761,7 @@
 # CONFIG_SOFT_WATCHDOG is not set
 CONFIG_AT32AP700X_WDT=y
 CONFIG_SSB_POSSIBLE=y
+CONFIG_AT32_WDT=y
 
 #
 # Sonics Silicon Backplane
@@ -814,6 +824,7 @@
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
+# CONFIG_FB_ATMEL_MPOP is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
@@ -830,6 +841,12 @@
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
 # CONFIG_LOGO is not set
 CONFIG_SOUND=m
 CONFIG_SOUND_OSS_CORE=y
@@ -846,11 +863,7 @@
 # CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_DRIVERS is not set
 CONFIG_SND_SPI=y
 CONFIG_SND_AT73C213=m
 CONFIG_SND_AT73C213_TARGET_BITRATE=48000
@@ -858,9 +871,9 @@
 # CONFIG_SOUND_PRIME is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_MUSB_HDRC is not set
@@ -900,7 +913,7 @@
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_USB_CDC_COMPOSITE=m
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -1002,11 +1015,13 @@
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_AT32AP700X=y
+# CONFIG_RTC_DRV_AVR32_AST is not set
 CONFIG_DMADEVICES=y
 
 #
 # DMA Devices
 #
+# CONFIG_ATMEL_PDCA is not set
 CONFIG_DW_DMAC=y
 CONFIG_DMA_ENGINE=y
 
@@ -1022,17 +1037,17 @@
 #
 # File systems
 #
-CONFIG_EXT2_FS=m
+CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_EXT4_FS=m
-CONFIG_EXT4DEV_COMPAT=y
+# CONFIG_EXT4_FS is not set
+# CONFIG_EXT4DEV_COMPAT=y
 # CONFIG_EXT4_FS_XATTR is not set
-CONFIG_JBD=m
+CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
-CONFIG_JBD2=m
+# CONFIG_JBD2 is not set
 # CONFIG_JBD2_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
@@ -1075,7 +1090,7 @@
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONFIGFS_FS=y
 
 #
 # Miscellaneous filesystems
diff -urN linux-2.6.28.2-0rig//arch/avr32/include/asm/ast_regs.h linux-2.6.28.2/arch/avr32/include/asm/ast_regs.h
--- linux-2.6.28.2-0rig//arch/avr32/include/asm/ast_regs.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/include/asm/ast_regs.h	2009-01-29 08:52:49.000000000 +0100
@@ -0,0 +1,88 @@
+/*
+ * Register definitions for the Asynchronous Timer (AST)
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __AST_REGS_H__
+#define __AST_REGS_H__
+
+/* Control Register */
+#define AST_CR				0x0000
+# define AST_CR_EN_BIT			0	/* Enable */
+# define AST_CR_PCLR_BIT		1	/* Prescaler Clear */
+# define AST_CR_CA0_BIT			8	/* Clear on Alarm */
+# define AST_CR_CA1_BIT			9
+# define AST_CR_PSEL_START		16	/* Prescale Select */
+# define AST_CR_PSEL_SIZE		4
+
+/* Counter Value */
+#define AST_CV				0x0004
+
+/* Status, Status Clear, Interrupt Enable/Disable/Mask, Wake Enable */
+#define AST_SR				0x0008
+#define AST_SCR				0x000c
+#define AST_IER				0x0010
+#define AST_IDR				0x0014
+#define AST_IMR				0x0018
+#define AST_WER				0x001c
+# define AST_OVF_BIT			0	/* Overflow */
+# define AST_ALARM0_BIT			8	/* Alarm event */
+# define AST_ALARM1_BIT			9
+# define AST_PER0_BIT			16	/* Periodic event */
+# define AST_PER1_BIT			17
+# define AST_BUSY_BIT			24	/* AST busy */
+# define AST_READY_BIT			25	/* BUSY 1 -> 0 event */
+# define AST_CLK_BUSY_BIT		28	/* CLOCK busy */
+# define AST_CLK_READY_BIT		29	/* CKL_BUSY 1 -> 0 event */
+
+/* Alarm registers */
+#define AST_AR0				0x0020
+#define AST_AR1				0x0024
+
+/* Periodic Interval registers */
+#define AST_PIR0			0x0030
+#define AST_PIR1			0x0034
+# define AST_PIRx_INSEL_START		0	/* Interval select */
+# define AST_PIRx_INSEL_SIZE		4
+
+/* Clock Select register */
+#define AST_CLOCK			0x0040
+# define AST_CLOCK_CEN_BIT		0	/* Clock Enable */
+# define AST_CLOCK_CSSEL_START		8	/* Clock Source */
+# define AST_CLOCK_CSSEL_SIZE		2
+#  define AST_CLOCK_SLOW		0	/* RC oscillator */
+#  define AST_CLOCK_OSC32		1	/* 32 kHz oscillator */
+#  define AST_CLOCK_PB			2	/* Peripheral Bus clock */
+#  define AST_CLOCK_GC			3	/* Generic clock */
+
+/* Version register */
+#define AST_VERSION			0x00fc
+
+/* Bit manipulation macros */
+#define AST_BIT(name)						\
+	(1 << AST_##name##_BIT)
+#define AST_BF(name,value)					\
+	(((value) & ((1 << AST_##name##_SIZE) - 1))		\
+	 << AST_##name##_START)
+#define AST_BFEXT(name,value)					\
+	(((value) >> AST_##name##_START)			\
+	 & ((1 << AST_##name##_SIZE) - 1))
+#define AST_BFINS(name,value,old)				\
+	(((old) & ~(((1 << AST_##name##_SIZE) - 1)		\
+		    << AST_##name##_START))			\
+	 | AST_BF(name,value))
+
+/* Register access macros */
+#define ast_readl(base, reg)					\
+	__raw_readl(base + AST_##reg)
+#define ast_writel(base, reg, value)				\
+	__raw_writel(value, base + AST_##reg)
+
+struct platform_device;
+void ast_time_init(struct platform_device *pdev, unsigned int clksel);
+
+#endif /* __AST_REGS_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/Kconfig linux-2.6.28.2/arch/avr32/Kconfig
--- linux-2.6.28.2-0rig//arch/avr32/Kconfig	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/Kconfig	2009-01-29 08:52:44.000000000 +0100
@@ -85,6 +85,18 @@
 config PERFORMANCE_COUNTERS
 	bool
 
+# The old "PIO" portmux/GPIO module used on AT32AP700x
+config PORTMUX_PIO
+	bool
+
+# The new "GPIO" portmux/GPIO module, version 2
+config PORTMUX_GPIO_V2
+	bool
+
+# Asynchronous Timer clocksource/clockevent driver
+config TIMER_AST
+	bool
+
 config PLATFORM_AT32AP
 	bool
 	select SUBARCH_AVR32B
@@ -101,6 +113,7 @@
 config CPU_AT32AP700X
 	bool
 	select PLATFORM_AT32AP
+	select PORTMUX_PIO
 config CPU_AT32AP7000
 	bool
 	select CPU_AT32AP700X
@@ -111,6 +124,16 @@
 	bool
 	select CPU_AT32AP700X
 
+# AP7200 derivatives
+config CPU_AT32AP720X
+	bool
+	select PLATFORM_AT32AP
+	select TIMER_AST
+	select PORTMUX_GPIO_V2
+config CPU_AT32AP7200
+	bool
+	select CPU_AT32AP720X
+
 choice
 	prompt "AVR32 board type"
 	default BOARD_ATSTK1000
@@ -148,14 +171,17 @@
 config LOAD_ADDRESS
 	hex
 	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
+	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
 
 config ENTRY_ADDRESS
 	hex
 	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
+	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
 
 config PHYS_OFFSET
 	hex
 	default 0x10000000 if CPU_AT32AP700X=y
+	default 0x10000000 if CPU_AT32AP720X=y
 
 source "kernel/Kconfig.preempt"
 
diff -urN linux-2.6.28.2-0rig//arch/avr32/kernel/cpu.c linux-2.6.28.2/arch/avr32/kernel/cpu.c
--- linux-2.6.28.2-0rig//arch/avr32/kernel/cpu.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/kernel/cpu.c	2009-01-29 08:52:49.000000000 +0100
@@ -208,6 +208,7 @@
 
 static const struct chip_id_map chip_names[] = {
 	{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
+	{ .mid = 0x1f, .pn = 0x1e83, .name = "AT32AP720x" },
 };
 #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
 
diff -urN linux-2.6.28.2-0rig//arch/avr32/kernel/entry-avr32b.S linux-2.6.28.2/arch/avr32/kernel/entry-avr32b.S
--- linux-2.6.28.2-0rig//arch/avr32/kernel/entry-avr32b.S	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/kernel/entry-avr32b.S	2009-01-29 08:52:49.000000000 +0100
@@ -112,7 +112,9 @@
 
 	/* Second level lookup */
 	ld.w	r2, r3[r1 << 2]
+#ifdef CONFIG_CPU_AT32AP700X
 	mfsr	r0, SYSREG_TLBARLO
+#endif
 	bld	r2, _PAGE_BIT_PRESENT
 	brcc	page_not_present
 
@@ -124,6 +126,8 @@
 	andl	r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
 	mtsr	SYSREG_TLBELO, r2
 
+	/* Later CPUs do this algorithm in hardware */
+#ifdef CONFIG_CPU_AT32AP700X
 	/* Figure out which entry we want to replace */
 	mfsr	r1, SYSREG_MMUCR
 	clz	r2, r0
@@ -134,6 +138,7 @@
 
 1:	bfins	r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
 	mtsr	SYSREG_MMUCR, r1
+#endif /* CONFIG_CPU_AT32AP700X */
 	tlbw
 
 	tlbmiss_restore
@@ -751,8 +756,10 @@
 
 	lddsp	r4, sp[REG_SR]
 	bfextu	r4, r4, SYSREG_M0_OFFSET, 3
+#ifdef CONFIG_CPU_AT32AP700X
 	cp.w	r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
 	breq	2f
+#endif
 	cp.w	r4, MODE_USER >> SYSREG_M0_OFFSET
 #ifdef CONFIG_PREEMPT
 	brne	3f
@@ -786,6 +793,7 @@
 	rete
 #endif
 
+#ifdef CONFIG_CPU_AT32AP700X
 2:	get_thread_info	r0
 	ld.w	r1, r0[TI_flags]
 	bld	r1, TIF_CPU_GOING_TO_SLEEP
@@ -796,6 +804,7 @@
 #endif
 	sub	r1, pc, . - cpu_idle_skip_sleep
 	stdsp	sp[REG_PC], r1
+#endif
 #ifdef CONFIG_PREEMPT
 3:	get_thread_info r0
 	ld.w	r2, r0[TI_preempt_count]
diff -urN linux-2.6.28.2-0rig//arch/avr32/kernel/time.c linux-2.6.28.2/arch/avr32/kernel/time.c
--- linux-2.6.28.2-0rig//arch/avr32/kernel/time.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/kernel/time.c	2009-01-29 08:52:49.000000000 +0100
@@ -15,6 +15,8 @@
 
 #include <asm/sysreg.h>
 
+#include <mach/cpu.h>
+#include <mach/init.h>
 #include <mach/pm.h>
 
 
@@ -116,6 +118,9 @@
 	unsigned long counter_hz;
 	int ret;
 
+	/* Make sure we don't get any interrupts until we ask for it. */
+	sysreg_write(COMPARE, 0);
+
 	xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
 	xtime.tv_nsec = 0;
 
@@ -130,12 +135,16 @@
 	if (ret)
 		pr_debug("timer: could not register clocksource: %d\n", ret);
 
+	if (!cpu_has_working_compare()) {
+		platform_time_init();
+		return;
+	}
+
 	/* setup COMPARE clockevent */
 	comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
 	comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
 	comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
 
-	sysreg_write(COMPARE, 0);
 	timer_irqaction.dev_id = &comparator;
 
 	ret = setup_irq(0, &timer_irqaction);
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap700x.c linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap700x.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap700x.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap700x.c	2009-01-29 08:52:49.000000000 +0100
@@ -23,6 +23,7 @@
 #include <mach/at32ap700x.h>
 #include <mach/board.h>
 #include <mach/hmatrix.h>
+#include <mach/pm.h>
 #include <mach/portmux.h>
 #include <mach/sram.h>
 
@@ -30,7 +31,7 @@
 
 #include "clock.h"
 #include "pio.h"
-#include "pm.h"
+#include "pm-v1.h"
 
 
 #define PBMEM(base)					\
@@ -996,6 +997,7 @@
 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 {
 	struct platform_device *pdev;
+	u32 pin_mask;
 
 	switch (hw_id) {
 	case 0:
@@ -1155,6 +1157,7 @@
 static struct resource atmel_spi0_resource[] = {
 	PBMEM(0xffe00000),
 	IRQ(3),
+	{ 0 },	/* SRAM buffer, if available */
 };
 DEFINE_DEV(atmel_spi, 0);
 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
@@ -1162,6 +1165,7 @@
 static struct resource atmel_spi1_resource[] = {
 	PBMEM(0xffe00400),
 	IRQ(4),
+	{ 0 },	/* SRAM buffer, if available */
 };
 DEFINE_DEV(atmel_spi, 1);
 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
@@ -1191,6 +1195,8 @@
 struct platform_device *__init
 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 {
+	unsigned long sram_buf;
+
 	/*
 	 * Manage the chipselects as GPIOs, normally using the same pins
 	 * the SPI controller expects; but boards can use other pins.
@@ -1231,6 +1237,13 @@
 		return NULL;
 	}
 
+	sram_buf = sram_alloc(4096);
+	if (sram_buf) {
+		pdev->resource[2].start = sram_buf;
+		pdev->resource[2].end = sram_buf + 4096 - 1;
+		pdev->resource[2].flags = IORESOURCE_MEM;
+	}
+
 	spi_register_board_info(b, n);
 	platform_device_register(pdev);
 	return pdev;
@@ -1738,6 +1751,7 @@
 		struct usba_ep_data ep[7];
 	} usba_data;
 	struct platform_device *pdev;
+	u32 pin_mask;
 
 	if (id != 0)
 		return NULL;
@@ -1940,6 +1954,7 @@
 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
 {
 	struct platform_device *pdev;
+	u32 pin_mask;
 
 	if (id != 0 || !data)
 		return NULL;
@@ -2272,6 +2287,11 @@
 	at32_init_pio(&pio4_device);
 }
 
+unsigned long at32_get_reset_cause(void)
+{
+	return pm_readl(RCAUSE);
+}
+
 struct gen_pool *sram_pool;
 
 static int __init sram_init(void)
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap720x.c linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap720x.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap720x.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap720x.c	2009-01-29 08:52:49.000000000 +0100
@@ -0,0 +1,2303 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/atmel_pdca.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/dw_dmac.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/spinlock.h>
+#include <linux/spi/atmel_spi.h>
+#include <linux/spi/spi.h>
+#include <video/atmel_lcdc.h>
+#include <video/atmel_mpop.h>
+
+#include <asm/ast_regs.h>
+#include <asm/atmel-mci.h>
+
+#include <mach/at32ap720x.h>
+#include <mach/board.h>
+#include <mach/hmatrix.h>
+#include <mach/init.h>
+#include <mach/pm.h>
+#include <mach/portmux.h>
+#include <mach/sram.h>
+
+#include "clock.h"
+#include "gpio-v2.h"
+#include "pm-v3.h"
+#include "sdc.h"
+
+#define PBMEM(base)					\
+	{						\
+		.start		= base,			\
+		.end		= base + 0x3ff,		\
+		.flags		= IORESOURCE_MEM,	\
+	}
+#define IRQ(num)					\
+	{						\
+		.start		= num,			\
+		.end		= num,			\
+		.flags		= IORESOURCE_IRQ,	\
+	}
+
+#define select_peripheral(port, pin_mask, periph, flags)	\
+	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
+			   GPIO_##periph, flags)
+
+#define DEV_CLK(_name, devname, bus, _index)			\
+static struct clk devname##_##_name = {				\
+	.name		= #_name,				\
+	.dev		= &devname##_device.dev,		\
+	.parent		= &bus##_clk,				\
+	.mode		= bus##_clk_mode,			\
+	.get_rate	= bus##_clk_get_rate,			\
+	.index		= _index,				\
+}
+
+static DEFINE_SPINLOCK(pm_lock);
+
+static unsigned long rcosc_get_rate(struct clk *clk)
+{
+	return 32768;
+}
+
+static unsigned long osc_get_rate(struct clk *clk)
+{
+	return at32_board_osc_rates[clk->index];
+}
+
+static void osc32_mode(struct clk *clk, int enabled)
+{
+	/* We never disable the 32 kHz oscillator */
+	if (!enabled)
+		return;
+
+	/* If it's already running, we're done. */
+	if (pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY))
+		return;
+
+	/* Enable it, unless someone did it for us already */
+	if (!(sdc_readl(OSCCTRL32) & SDC_BIT(OSCCTRL32_OSC32EN))) {
+		u32 value;
+
+		value = SDC_BF(OSCCTRL32_STARTUP, 5)
+			| SDC_BF(OSCCTRL32_MODE, 0xd)
+			| SDC_BIT(OSCCTRL32_OSC32EN);
+
+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0x55));
+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0xaa));
+	}
+
+	pr_info("Waiting for 32 kHz crystal oscillator to start...\n");
+
+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY)))
+		cpu_relax();
+}
+
+static void oscn_mode(struct clk *clk, int enabled)
+{
+	unsigned int	i = clk->index;
+	u32		mcctrl;
+
+	BUG_ON(i > 2);
+
+	/* Let's keep oscillators running for now... */
+	if (!enabled)
+		goto out;
+
+	/* If it's already running, we're done */
+	if (pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i))
+		goto out;
+
+	/* Enable it, unless someone did it for us already */
+	mcctrl = pm_readl(MCCTRL);
+	if (!(mcctrl & (PM_BIT(MCCTRL_OSC0EN) << i))) {
+		/* TODO: Make OSC startup parameters configurable */
+		pm_writel(OSCCTRL[i], PM_BF(OSCCTRLx_STARTUP, 5)
+				| PM_BF(OSCCTRLx_MODE, 0xa));
+		pm_writel(MCCTRL, mcctrl | (PM_BIT(MCCTRL_OSC0EN) << i));
+	}
+
+	pr_debug("clk %s: waiting for clock to become ready...\n", clk->name);
+	pr_debug("clk %s: MCCTRL=%08x OSCCTRL%u=%08x\n", clk->name,
+			pm_readl(MCCTRL), i, pm_readl(OSCCTRL[i]));
+
+	while (!(pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i)))
+		cpu_relax();
+
+out:
+	pr_debug("clk %s: running\n", clk->name);
+}
+
+static struct clk rcosc = {
+	.name		= "rcosc",
+	.get_rate	= rcosc_get_rate,
+	.users		= 1,
+};
+static struct clk osc0 = {
+	.name		= "osc0",
+	.get_rate	= osc_get_rate,
+	.mode		= oscn_mode,
+	.users		= 1,
+	.index		= 0,
+};
+static struct clk osc1 = {
+	.name		= "osc1",
+	.get_rate	= osc_get_rate,
+	.mode		= oscn_mode,
+	.index		= 1,
+};
+static struct clk osc2 = {
+	.name		= "osc2",
+	.get_rate	= osc_get_rate,
+	.mode		= oscn_mode,
+	.index		= 2,
+};
+static struct clk osc32 = {
+	.name		= "osc32k",
+	.get_rate	= osc_get_rate,
+	.mode		= osc32_mode,
+	.index		= 3,
+};
+
+static void pll_mode(struct clk *clk, int enabled)
+{
+	unsigned long timeout;
+	unsigned int index = clk->index;
+	u32 status;
+	u32 ctrl;
+
+	ctrl = pm_readl(PLL[index]);
+
+	if (enabled) {
+		if (PM_BFEXT(PLLx_PLLMUL, ctrl) <= 1) {
+			pr_debug("clk %s: failed to enable, rate not set\n",
+					clk->name);
+			return;
+		}
+
+		ctrl |= PM_BIT(PLLx_PLLEN);
+		pm_writel(PLL[index], ctrl);
+
+		pr_debug("clk %s: waiting for lock...\n", clk->name);
+		for (timeout = 10000; timeout; timeout--) {
+			status = pm_readl(POSCSR);
+			if (status & (PM_BIT(POSCSR_LOCK0) << index))
+				break;
+			udelay(10);
+		}
+
+		if (!(status & (PM_BIT(POSCSR_LOCK0) << index)))
+			pr_err("clk %s: timeout waiting for lock\n",
+					clk->name);
+		else
+			pr_debug("clk %s: running\n", clk->name);
+	} else {
+		ctrl &= ~PM_BIT(PLLx_PLLEN);
+		pm_writel(PLL[index], ctrl);
+		pr_debug("clk %s: stopped\n", clk->name);
+	}
+}
+
+
+static unsigned long pll_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+	unsigned int div;
+	unsigned int mul;
+	u32 ctrl;
+
+	ctrl = pm_readl(PLL[clk->index]);
+
+	div = PM_BFEXT(PLLx_PLLDIV, ctrl);
+	mul = PM_BFEXT(PLLx_PLLMUL, ctrl);
+
+	rate = clk->parent->get_rate(clk->parent);
+	if (div != 0)
+		rate = (rate + div / 2) / div;
+	else
+		rate = rate * 2;
+	rate *= mul;
+
+	if (ctrl & PM_BF(PLLx_PLLOPT, 4))
+		rate = (rate + 1) / 2;
+
+	return rate;
+}
+
+static long pll_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+	unsigned long mul_best_fit = 0;
+	unsigned long div;
+	unsigned long div_min;
+	unsigned long div_max;
+	unsigned long div_best_fit = 0;
+	unsigned long base;
+	unsigned long fvco;
+	unsigned long actual = 0;
+	unsigned long rate_error_prev = ~0UL;
+	u32 ctrl;
+
+	/* Rate must be between 25 MHz and 400 Mhz. */
+	if (rate < 25000000UL || rate > 400000000UL)
+		return -EINVAL;
+
+	base = clk->parent->get_rate(clk->parent);
+
+	/* PLL input frequency must be between 10 MHz and 200 MHz. */
+	div_min = DIV_ROUND_UP(base, 200000000UL);
+	div_max = base / 10000000UL;
+
+	if (div_max < div_min)
+		return -EINVAL;
+
+	for (div = div_min; div <= div_max; div++) {
+		unsigned long mul;
+		unsigned long pll_in;
+		unsigned long rate_error;
+
+		pll_in = (base + div / 2) / div;
+		mul = (rate + pll_in / 2) / pll_in;
+
+		if (mul < 1)
+			continue;
+
+		actual = pll_in * mul;
+		rate_error = abs(actual - rate);
+
+		if (rate_error < rate_error_prev) {
+			mul_best_fit = mul;
+			div_best_fit = div;
+			rate_error_prev = rate_error;
+		}
+
+		if (rate_error == 0)
+			break;
+	}
+
+	if (div_best_fit == 0)
+		return -EINVAL;
+
+	ctrl = 0;
+	fvco = actual;
+
+	/*
+	 * MUL=1 is not allowed. So we must double it and set the
+	 * divide-by-two bit.
+	 */
+	if (mul_best_fit == 1) {
+		ctrl |= PM_BF(PLLx_PLLOPT, 4);
+		mul_best_fit *= 2;
+		fvco = actual * 2;
+	}
+
+	if (fvco > 200000000)
+		ctrl |= PM_BF(PLLx_PLLOPT, 3);
+	else if (fvco > 100000000)
+		ctrl |= PM_BF(PLLx_PLLOPT, 2);
+	else if (fvco > 50000000)
+		ctrl |= PM_BF(PLLx_PLLOPT, 1);
+
+	ctrl |= PM_BF(PLLx_PLLCOUNT, 31);
+	ctrl |= PM_BF(PLLx_PLLMUL, mul_best_fit);
+	ctrl |= PM_BF(PLLx_PLLDIV, div_best_fit);
+	ctrl |= PM_BF(PLLx_PLLOSC, clk->parent->index);
+
+	if (apply) {
+		if (actual != rate)
+			return -EINVAL;
+		if (clk->users > 0)
+			return -EBUSY;
+		pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
+				clk->name, rate, actual);
+		pm_writel(PLL[clk->index], ctrl);
+	}
+
+	return actual;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+	unsigned int index = clk->index;
+	u32 ctrl;
+
+	if (clk->users > 0)
+		return -EBUSY;
+
+	ctrl = pm_readl(PLL[index]);
+	BUG_ON(ctrl & PM_BIT(PLLx_PLLEN));
+
+	ctrl = PM_BFINS(PLLx_PLLOSC, parent->index, ctrl);
+	pm_writel(PLL[index], ctrl);
+
+	clk->parent = parent;
+
+	return 0;
+}
+
+static struct clk pll0 = {
+	.name		= "pll0",
+	.mode		= pll_mode,
+	.get_rate	= pll_get_rate,
+	.set_rate	= pll_set_rate,
+	.set_parent	= pll_set_parent,
+	.users		= 1,
+	.index		= 0,
+};
+static struct clk pll1 = {
+	.name		= "pll1",
+	.mode		= pll_mode,
+	.get_rate	= pll_get_rate,
+	.set_rate	= pll_set_rate,
+	.set_parent	= pll_set_parent,
+	.users		= 0,
+	.index		= 1,
+};
+static struct clk pll2 = {
+	.name		= "pll2",
+	.mode		= pll_mode,
+	.get_rate	= pll_get_rate,
+	.set_rate	= pll_set_rate,
+	.set_parent	= pll_set_parent,
+	.users		= 0,
+	.index		= 2,
+};
+
+/*
+ * The main clock can be either rcosc, osc0 or pll0.  The boot loader
+ * may have chosen one for us, so we don't really know which one until
+ * we have a look at the PM registers.
+ */
+static struct clk *main_clock;
+
+/*
+ * Synchronous clocks are generated from the main clock. The clocks
+ * must satisfy the constraint
+ *   fCPU >= fHSB >= fPB
+ * i.e. each clock must not be faster than its parent.
+ */
+static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
+{
+	return main_clock->get_rate(main_clock) >> shift;
+};
+
+static void cpu_clk_mode(struct clk *clk, int enabled)
+{
+	unsigned long flags;
+	u32 mask;
+
+	spin_lock_irqsave(&pm_lock, flags);
+
+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
+		cpu_relax();
+
+	mask = pm_readl(CPUMASK);
+	if (enabled)
+		mask |= 1 << clk->index;
+	else
+		mask &= ~(1 << clk->index);
+	pm_writel(CPUMASK, mask);
+	spin_unlock_irqrestore(&pm_lock, flags);
+}
+
+static unsigned long cpu_clk_get_rate(struct clk *clk)
+{
+	unsigned long cksel, shift = 0;
+
+	cksel = pm_readl(CKSEL);
+	if (cksel & PM_BIT(CKSEL_CPUDIV))
+		shift = PM_BFEXT(CKSEL_CPUSEL, cksel) + 1;
+
+	return bus_clk_get_rate(clk, shift);
+}
+
+static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+	u32 control;
+	unsigned long parent_rate, child_div, actual_rate, div;
+
+	parent_rate = clk->parent->get_rate(clk->parent);
+	control = pm_readl(CKSEL);
+
+	if (control & PM_BIT(CKSEL_HSBDIV))
+		child_div = 1 << (PM_BFEXT(CKSEL_HSBSEL, control) + 1);
+	else
+		child_div = 1;
+
+	if (rate > 3 * (parent_rate / 4) || child_div == 1) {
+		actual_rate = parent_rate;
+		control &= ~PM_BIT(CKSEL_CPUDIV);
+	} else {
+		unsigned int cpusel;
+		div = (parent_rate + rate / 2) / rate;
+		if (div > child_div)
+			div = child_div;
+		cpusel = (div > 1) ? (fls(div) - 2) : 0;
+		control = PM_BIT(CKSEL_CPUDIV)
+			| PM_BFINS(CKSEL_CPUSEL, cpusel, control);
+		actual_rate = parent_rate / (1 << (cpusel + 1));
+	}
+
+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
+			clk->name, rate, actual_rate);
+
+	if (apply) {
+		while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_CKRDY)))
+			cpu_relax();
+
+		pm_writel(CKSEL, control);
+	}
+
+	return actual_rate;
+}
+
+static void hsb_clk_mode(struct clk *clk, int enabled)
+{
+	unsigned long flags;
+	u32 mask;
+
+	spin_lock_irqsave(&pm_lock, flags);
+
+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
+		cpu_relax();
+
+	mask = pm_readl(HSBMASK);
+	if (enabled)
+		mask |= 1 << clk->index;
+	else
+		mask &= ~(1 << clk->index);
+	pm_writel(HSBMASK, mask);
+	spin_unlock_irqrestore(&pm_lock, flags);
+}
+
+static unsigned long hsb_clk_get_rate(struct clk *clk)
+{
+	unsigned long cksel, shift = 0;
+
+	cksel = pm_readl(CKSEL);
+	if (cksel & PM_BIT(CKSEL_HSBDIV))
+		shift = PM_BFEXT(CKSEL_HSBSEL, cksel) + 1;
+
+	return bus_clk_get_rate(clk, shift);
+}
+
+static void pba_clk_mode(struct clk *clk, int enabled)
+{
+	unsigned long flags;
+	u32 mask;
+
+	spin_lock_irqsave(&pm_lock, flags);
+
+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
+		cpu_relax();
+
+	mask = pm_readl(PBAMASK);
+	if (enabled)
+		mask |= 1 << clk->index;
+	else
+		mask &= ~(1 << clk->index);
+	pm_writel(PBAMASK, mask);
+	spin_unlock_irqrestore(&pm_lock, flags);
+}
+
+static unsigned long pba_clk_get_rate(struct clk *clk)
+{
+	unsigned long cksel, shift = 0;
+
+	cksel = pm_readl(CKSEL);
+	if (cksel & PM_BIT(CKSEL_PBADIV))
+		shift = PM_BFEXT(CKSEL_PBASEL, cksel) + 1;
+
+	return bus_clk_get_rate(clk, shift);
+}
+
+static void pbb_clk_mode(struct clk *clk, int enabled)
+{
+	unsigned long flags;
+	u32 mask;
+
+	spin_lock_irqsave(&pm_lock, flags);
+
+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
+		cpu_relax();
+
+	mask = pm_readl(PBBMASK);
+	if (enabled)
+		mask |= 1 << clk->index;
+	else
+		mask &= ~(1 << clk->index);
+	pm_writel(PBBMASK, mask);
+	spin_unlock_irqrestore(&pm_lock, flags);
+}
+
+static unsigned long pbb_clk_get_rate(struct clk *clk)
+{
+	unsigned long cksel, shift = 0;
+
+	cksel = pm_readl(CKSEL);
+	if (cksel & PM_BIT(CKSEL_PBBDIV))
+		shift = PM_BFEXT(CKSEL_PBBSEL, cksel) + 1;
+
+	return bus_clk_get_rate(clk, shift);
+}
+
+static struct clk cpu_clk = {
+	.name		= "cpu",
+	.get_rate	= cpu_clk_get_rate,
+	.set_rate	= cpu_clk_set_rate,
+	.users		= 1,
+};
+static struct clk hsb_clk = {
+	.name		= "hsb",
+	.parent		= &cpu_clk,
+	.get_rate	= hsb_clk_get_rate,
+};
+static struct clk pba_clk = {
+	.name		= "pba",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= pba_clk_get_rate,
+	.users		= 1,
+	.index		= 1,
+};
+static struct clk pbb_clk = {
+	.name		= "pbb",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.users		= 1,
+	.index		= 2,
+};
+static struct clk pbc_clk = {
+	.name		= "pbc",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.index		= 3,
+};
+
+/* --------------------------------------------------------------------
+ *  Generic Clocks
+ * -------------------------------------------------------------------- */
+
+/* Mapping from GCCTRL:OSCSEL values to parent clocks */
+static struct clk *const genclk_parent[] = {
+	&rcosc,
+	&osc32,
+	&osc0,
+	&osc1,
+	&osc2,
+	&pll0,
+	&pll1,
+	&pll2,
+	&cpu_clk,
+	&hsb_clk,
+	&pba_clk,
+	&pbb_clk,
+};
+
+#define NR_GENERIC_CLOCKS	8
+
+static void genclk_mode(struct clk *clk, int enabled)
+{
+	u32 control;
+
+	control = pm_readl(GCCTRL[clk->index]);
+	if (enabled)
+		control |= PM_BIT(GCCTRL_CEN);
+	else
+		control &= PM_BIT(GCCTRL_CEN);
+	pm_writel(GCCTRL[clk->index], control);
+}
+
+static unsigned long genclk_get_rate(struct clk *clk)
+{
+	u32 control;
+	unsigned long div = 1;
+
+	control = pm_readl(GCCTRL[clk->index]);
+	if (control & PM_BIT(GCCTRL_DIVEN))
+		div = 2 * (PM_BFEXT(GCCTRL_DIV, control) + 1);
+
+	return clk->parent->get_rate(clk->parent) / div;
+}
+
+static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+	unsigned long	parent_rate;
+	unsigned long	actual_rate;
+	unsigned long	div;
+	u32		control;
+
+	parent_rate = clk->parent->get_rate(clk->parent);
+	control = pm_readl(GCCTRL[clk->index]);
+
+	if (rate > 3 * parent_rate / 4) {
+		actual_rate = parent_rate;
+		control &= ~PM_BIT(GCCTRL_DIVEN);
+	} else {
+		div = (parent_rate + rate) / (2 * rate) - 1;
+		control = PM_BFINS(GCCTRL_DIV, div, control)
+				| PM_BIT(GCCTRL_DIVEN);
+		actual_rate = parent_rate / (2 * (div + 1));
+	}
+
+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
+			clk->name, rate, actual_rate);
+
+	if (apply)
+		pm_writel(GCCTRL[clk->index], control);
+
+	return actual_rate;
+}
+
+static int genclk_set_parent(struct clk *clk, struct clk *parent)
+{
+	unsigned int	i;
+	u32		control;
+
+	pr_debug("clk %s: new parent %s (was %s)\n",
+			clk->name, parent->name,
+			clk->parent ? clk->parent->name : "<none>");
+
+	control = pm_readl(GCCTRL[clk->index]);
+
+	for (i = 0; i < ARRAY_SIZE(genclk_parent); i++) {
+		if (parent == genclk_parent[i]) {
+			control = PM_BFINS(GCCTRL_OSCSEL, i, control);
+			break;
+		}
+	}
+
+	if (i >= ARRAY_SIZE(genclk_parent))
+		return -EINVAL;
+
+	pm_writel(GCCTRL[clk->index], control);
+	clk->parent = parent;
+
+	return 0;
+}
+
+#define DEFINE_GCLK(_name, i)				\
+	static struct clk _name = {			\
+		.name		= #_name,		\
+		.mode		= genclk_mode,		\
+		.get_rate	= genclk_get_rate,	\
+		.set_rate	= genclk_set_rate,	\
+		.set_parent	= genclk_set_parent,	\
+		.index		= i,			\
+	}
+
+DEFINE_GCLK(gclk0, 0);
+DEFINE_GCLK(gclk1, 1);
+DEFINE_GCLK(gclk2, 2);
+DEFINE_GCLK(gclk3, 3);
+DEFINE_GCLK(gclk4, 4);
+DEFINE_GCLK(gclk5, 5);
+
+static void __init genclk_init_parent(struct clk *clk)
+{
+	unsigned int	parent;
+	u32		control;
+
+	BUG_ON(clk->index > NR_GENERIC_CLOCKS);
+
+	control = pm_readl(GCCTRL[clk->index]);
+	parent = PM_BFEXT(GCCTRL_OSCSEL, control);
+	if (parent >= ARRAY_SIZE(genclk_parent)) {
+		/* Current parent is invalid. Reset to a sane value */
+		parent = 0;
+		control = PM_BF(GCCTRL_OSCSEL, parent);
+	}
+
+	clk->parent = genclk_parent[parent];
+}
+
+
+/* --------------------------------------------------------------------
+ *  System peripherals
+ * -------------------------------------------------------------------- */
+static struct dw_dma_platform_data dw_dmac0_data = {
+	.nr_channels	= 4,
+};
+static struct pdca_pdata pdca_data = {
+	.nr_channels	= 20,
+};
+
+static struct resource intc_resource[] = {
+	PBMEM(0xffd00000),
+};
+static struct resource pm_resource[] = {
+	PBMEM(0xffd00400),
+	IRQ(10),
+};
+static struct resource sdc_resource[] = {
+	PBMEM(0xffd00800),
+	IRQ(45),
+};
+static struct resource ast0_resource[] = {
+	PBMEM(0xffd00c00),
+	IRQ(11),
+};
+static struct resource ast1_resource[] = {
+	PBMEM(0xffd01000),
+	IRQ(12),
+};
+static struct resource wdt_resource[] = {
+	PBMEM(0xffd01400),
+};
+static struct resource gpio_resource[] = {
+	PBMEM(0xffd02000),
+	{
+		.start	= 16,
+		.end	= 19,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+static struct resource pdca_resource[] = {
+	{
+		.start	= 0xffe00000,
+		.end	= 0xffe01fff,
+		.flags	= IORESOURCE_MEM,
+	},
+	IRQ(1),
+};
+static struct resource smc_resource[] = {
+	PBMEM(0xffe04400),
+};
+static struct resource dw_dmac0_resource[] = {
+	{
+		.start	= 0xff100000,
+		.end	= 0xff1003ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	IRQ(5),
+};
+
+struct platform_device at32_intc0_device = {
+	.name		= "intc",
+	.resource	= intc_resource,
+	.num_resources	= ARRAY_SIZE(intc_resource),
+};
+static struct platform_device pm_device = {
+	.name		= "pm",
+	.resource	= pm_resource,
+	.num_resources	= ARRAY_SIZE(pm_resource),
+};
+static struct platform_device sdc_device = {
+	.name		= "sdc",
+	.resource	= sdc_resource,
+	.num_resources	= ARRAY_SIZE(sdc_resource),
+};
+static struct platform_device ast0_device = {
+	.name		= "rtc-ast",
+	.id		= 0,
+	.resource	= ast0_resource,
+	.num_resources	= ARRAY_SIZE(ast0_resource),
+};
+static struct platform_device ast1_device = {
+	.name		= "timer-ast",
+	.id		= 1,
+	.resource	= ast1_resource,
+	.num_resources	= ARRAY_SIZE(ast1_resource),
+};
+static struct platform_device wdt_device = {
+	.name		= "at32_wdt",
+	.id		= 0,
+	.resource	= wdt_resource,
+	.num_resources	= ARRAY_SIZE(wdt_resource),
+};
+static struct platform_device gpio_device = {
+	.name		= "gpio",
+	.id		= 0,
+	.resource	= gpio_resource,
+	.num_resources	= ARRAY_SIZE(gpio_resource),
+};
+static struct platform_device pdca_device = {
+	.dev.platform_data = &pdca_data,
+	.name		= "atmel_pdca",
+	.id		= 0,
+	.resource	= pdca_resource,
+	.num_resources	= ARRAY_SIZE(pdca_resource),
+};
+static struct platform_device smc_device = {
+	.name		= "smc",
+	.id		= 0,
+	.resource	= smc_resource,
+	.num_resources	= ARRAY_SIZE(smc_resource),
+};
+static struct platform_device dw_dmac0_device = {
+	.dev.platform_data = &dw_dmac0_data,
+	.name		= "dw_dmac",
+	.id		= 0,
+	.resource	= dw_dmac0_resource,
+	.num_resources	= ARRAY_SIZE(dw_dmac0_resource),
+};
+
+DEV_CLK(pclk, at32_intc0, pba, 0);
+DEV_CLK(pclk, pm, pba, 1);
+DEV_CLK(pclk, sdc, pba, 2);
+DEV_CLK(pclk, ast0, pba, 3);
+DEV_CLK(pclk, ast1, pba, 4);
+DEV_CLK(pclk, wdt, pba, 5);
+DEV_CLK(pclk, gpio, pba, 8);
+DEV_CLK(hclk, pdca, hsb, 9);
+DEV_CLK(pclk, pdca, pbb, 0);
+DEV_CLK(pclk, smc, pbb, 5);
+DEV_CLK(hclk, dw_dmac0, hsb, 10);
+
+static struct clk ebi_hclk = {
+	.name		= "ebi_hclk",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= hsb_clk_get_rate,
+	.users		= 1,
+};
+static struct clk hramc_clk = {
+	.name		= "hramc",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= hsb_clk_get_rate,
+	.users		= 1,
+	.index		= 4,
+};
+static struct clk sdramc_clk = {
+	.name		= "sdramc_clk",
+	.parent		= &pbb_clk,
+	.mode		= pbb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.users		= 1,
+	.index		= 6,
+};
+
+static int __init system_device_init(void)
+{
+	platform_device_register(&at32_intc0_device);
+	platform_device_register(&pm_device);
+	platform_device_register(&sdc_device);
+	platform_device_register(&ast0_device);
+	platform_device_register(&ast1_device);
+	platform_device_register(&wdt_device);
+	platform_device_register(&gpio_device);
+	platform_device_register(&pdca_device);
+	platform_device_register(&smc_device);
+	platform_device_register(&dw_dmac0_device);
+
+	return 0;
+}
+core_initcall(system_device_init);
+
+/* --------------------------------------------------------------------
+ * HMATRIX
+ * -------------------------------------------------------------------- */
+
+struct clk at32_hmatrix_clk = {
+	.name		= "hmatrix_clk",
+	.parent		= &pbb_clk,
+	.mode		= pbb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.index		= 8,
+	.users		= 0,
+};
+
+/* --------------------------------------------------------------------
+ *  USART
+ * -------------------------------------------------------------------- */
+
+static struct atmel_uart_data atmel_usart0_data = {
+	.use_dma_tx	= 0,
+	.use_dma_rx	= 0,
+};
+static struct resource atmel_usart0_resource[] = {
+	PBMEM(0xffd03000),
+	IRQ(24),
+};
+static struct platform_device atmel_usart0_device = {
+	.name		= "atmel_usart",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &atmel_usart0_data,
+	},
+	.resource	= atmel_usart0_resource,
+	.num_resources	= ARRAY_SIZE(atmel_usart0_resource),
+};
+DEV_CLK(usart, atmel_usart0, pba, 9);
+
+static struct atmel_uart_data atmel_usart1_data = {
+	.use_dma_tx	= 0,
+	.use_dma_rx	= 0,
+};
+static struct resource atmel_usart1_resource[] = {
+	PBMEM(0xffd03400),
+	IRQ(25),
+};
+static struct platform_device atmel_usart1_device = {
+	.name		= "atmel_usart",
+	.id		= 1,
+	.dev		= {
+		.platform_data	= &atmel_usart1_data,
+	},
+	.resource	= atmel_usart1_resource,
+	.num_resources	= ARRAY_SIZE(atmel_usart1_resource),
+};
+DEV_CLK(usart, atmel_usart1, pba, 10);
+
+static struct atmel_uart_data atmel_usart2_data = {
+	.use_dma_tx	= 0,
+	.use_dma_rx	= 0,
+};
+static struct resource atmel_usart2_resource[] = {
+	PBMEM(0xffd03800),
+	IRQ(26),
+};
+static struct platform_device atmel_usart2_device = {
+	.name		= "atmel_usart",
+	.id		= 2,
+	.dev		= {
+		.platform_data	= &atmel_usart2_data,
+	},
+	.resource	= atmel_usart2_resource,
+	.num_resources	= ARRAY_SIZE(atmel_usart2_resource),
+};
+DEV_CLK(usart, atmel_usart2, pba, 11);
+
+static struct atmel_uart_data atmel_usart3_data = {
+	.use_dma_tx	= 0,
+	.use_dma_rx	= 0,
+};
+static struct resource atmel_usart3_resource[] = {
+	PBMEM(0xffd03c00),
+	IRQ(27),
+};
+static struct platform_device atmel_usart3_device = {
+	.name		= "atmel_usart",
+	.id		= 3,
+	.dev		= {
+		.platform_data	= &atmel_usart3_data,
+	},
+	.resource	= atmel_usart3_resource,
+	.num_resources	= ARRAY_SIZE(atmel_usart3_resource),
+};
+DEV_CLK(usart, atmel_usart3, pba, 12);
+
+static struct atmel_uart_data atmel_usart4_data = {
+	.use_dma_tx	= 0,
+	.use_dma_rx	= 0,
+};
+static struct resource atmel_usart4_resource[] = {
+	PBMEM(0xffd04000),
+	IRQ(28),
+};
+static struct platform_device atmel_usart4_device = {
+	.name		= "atmel_usart",
+	.id		= 4,
+	.dev		= {
+		.platform_data	= &atmel_usart4_data,
+	},
+	.resource	= atmel_usart4_resource,
+	.num_resources	= ARRAY_SIZE(atmel_usart4_resource),
+};
+DEV_CLK(usart, atmel_usart4, pba, 13);
+
+static struct atmel_uart_data atmel_usart5_data = {
+	.use_dma_tx	= 0,
+	.use_dma_rx	= 0,
+};
+static struct resource atmel_usart5_resource[] = {
+	PBMEM(0xffd04400),
+	IRQ(29),
+};
+static struct platform_device atmel_usart5_device = {
+	.name		= "atmel_usart",
+	.id		= 5,
+	.dev		= {
+		.platform_data	= &atmel_usart5_data,
+	},
+	.resource	= atmel_usart5_resource,
+	.num_resources	= ARRAY_SIZE(atmel_usart5_resource),
+};
+DEV_CLK(usart, atmel_usart5, pba, 14);
+
+static void __init configure_usart0_pins(void)
+{
+	/* RXD | TXD */
+	select_peripheral(PB, (1 << 14) | (1 << 15), PERIPH_B, 0);
+}
+
+static void __init configure_usart1_pins(void)
+{
+	/* TXD | RXD */
+	select_peripheral(PA, (1 << 8) | (1 << 9), PERIPH_A, 0);
+}
+
+static void __init configure_usart2_pins(void)
+{
+	/* TXD | RXD */
+	select_peripheral(PA, (1 << 16) | (1 << 17), PERIPH_A, 0);
+}
+
+static void __init configure_usart3_pins(void)
+{
+	/* RXD | TXD */
+	select_peripheral(PC, (1 << 10) | (1 << 11), PERIPH_A, 0);
+}
+
+static void __init configure_usart4_pins(void)
+{
+	/* TXD | RXD */
+	select_peripheral(PA, (1 << 14) | (1 << 15), PERIPH_A, 0);
+}
+
+static void __init configure_usart5_pins(void)
+{
+	/* RXD | TXD */
+	select_peripheral(PA, (1 << 22) | (1 << 23), PERIPH_A, 0);
+}
+
+static struct platform_device *__initdata at32_usarts[6];
+
+void __init at32_map_usart(unsigned int hw_id, unsigned int line)
+{
+	struct platform_device *pdev;
+
+	switch (hw_id) {
+	case 0:
+		pdev = &atmel_usart0_device;
+		configure_usart0_pins();
+		break;
+	case 1:
+		pdev = &atmel_usart1_device;
+		configure_usart1_pins();
+		break;
+	case 2:
+		pdev = &atmel_usart2_device;
+		configure_usart2_pins();
+		break;
+	case 3:
+		pdev = &atmel_usart3_device;
+		configure_usart3_pins();
+		break;
+	case 4:
+		pdev = &atmel_usart4_device;
+		configure_usart4_pins();
+		break;
+	case 5:
+		pdev = &atmel_usart5_device;
+		configure_usart5_pins();
+		break;
+	default:
+		return;
+	}
+
+	if (PXSEG(pdev->resource[0].start) == P4SEG) {
+		/* Addresses in the P4 segment are permanently mapped 1:1 */
+		struct atmel_uart_data *data = pdev->dev.platform_data;
+		data->regs = (void __iomem __force *)pdev->resource[0].start;
+	}
+
+	pdev->id = line;
+	at32_usarts[line] = pdev;
+}
+
+struct platform_device *__init at32_add_device_usart(unsigned int id)
+{
+	platform_device_register(at32_usarts[id]);
+	return at32_usarts[id];
+}
+
+struct platform_device *atmel_default_console_device;
+
+void __init at32_setup_serial_console(unsigned int usart_id)
+{
+	atmel_default_console_device = at32_usarts[usart_id];
+}
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+static u64 macb0_dma_mask = DMA_32BIT_MASK;
+static struct resource macb0_resource[] __initdata = {
+	PBMEM(0xffe04000),
+	IRQ(8),
+};
+static struct clk macb0_hclk = {
+	.name		= "hclk",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= hsb_clk_get_rate,
+	.index		= 8,
+};
+static struct clk macb0_pclk = {
+	.name		= "pclk",
+	.parent		= &pbb_clk,
+	.mode		= pbb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.index		= 4,
+};
+
+struct platform_device *__init
+at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
+{
+	struct platform_device *pdev;
+	u32 pin_mask_a;
+	u32 pin_mask_c;
+
+	if (id != 0 || !data)
+		return NULL;
+
+	pdev = platform_device_alloc("macb", id);
+	if (!pdev)
+		return NULL;
+
+	if (platform_device_add_resources(pdev, macb0_resource,
+				ARRAY_SIZE(macb0_resource)))
+		goto out_free_pdev;
+
+	if (platform_device_add_data(pdev, data,
+				sizeof(struct eth_platform_data)))
+		goto out_free_pdev;
+
+	pin_mask_a  = (1 << 4);  /* RXDV */
+	pin_mask_c  = (1 << 10); /* MDC  */
+	pin_mask_c |= (1 << 11); /* MDIO */
+	pin_mask_c |= (1 << 12); /* TXCK */
+	pin_mask_c |= (1 << 14); /* RXD0 */
+	pin_mask_c |= (1 << 15); /* RXD1 */
+	pin_mask_c |= (1 << 16); /* RXER */
+	pin_mask_c |= (1 << 18); /* TXEN */
+	pin_mask_c |= (1 << 19); /* TXD0 */
+	pin_mask_c |= (1 << 20); /* TXD1 */
+
+	if (!data->is_rmii) {
+		pin_mask_a |= (1<<0);  /* COL  */
+		pin_mask_a |= (1<<1);  /* RXD2 */
+		pin_mask_a |= (1<<2);  /* RXD3 */
+		pin_mask_a |= (1<<3);  /* RXCK */
+		pin_mask_a |= (1<<5);  /* TXER */
+		pin_mask_a |= (1<<6);  /* TXD2 */
+		pin_mask_a |= (1<<7);  /* TXD3 */
+		pin_mask_c |= (1<<13); /* CRS  */
+		pin_mask_c |= (1<<17); /* SPD  */
+	}
+
+	select_peripheral(PA, pin_mask_a, PERIPH_B, 0);
+	select_peripheral(PC, pin_mask_c, PERIPH_C, 0);
+
+	pdev->dev.dma_mask = &macb0_dma_mask;
+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
+
+	macb0_hclk.dev = &pdev->dev;
+	macb0_pclk.dev = &pdev->dev;
+
+	platform_device_add(pdev);
+
+	return pdev;
+
+out_free_pdev:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* --------------------------------------------------------------------
+ * SPI
+ * -------------------------------------------------------------------- */
+static struct resource atmel_spi_resource[][2] __initdata = {
+	{
+		PBMEM(0xffe05400),
+		IRQ(36),
+	}, {
+		PBMEM(0xffe05800),
+		IRQ(37),
+	}, {
+		PBMEM(0xffe05c00),
+		IRQ(38),
+	}, {
+		PBMEM(0xffe06000),
+		IRQ(39),
+	}
+};
+static struct clk atmel_spi_clk[] = {
+	{
+		.name		= "spi_clk",
+		.parent		= &pbb_clk,
+		.mode		= pbb_clk_mode,
+		.get_rate	= pbb_clk_get_rate,
+		.index		= 9,
+	}, {
+		.name		= "spi_clk",
+		.parent		= &pbb_clk,
+		.mode		= pbb_clk_mode,
+		.get_rate	= pbb_clk_get_rate,
+		.index		= 10,
+	}, {
+		.name		= "spi_clk",
+		.parent		= &pbb_clk,
+		.mode		= pbb_clk_mode,
+		.get_rate	= pbb_clk_get_rate,
+		.index		= 11,
+	}, {
+		.name		= "spi_clk",
+		.parent		= &pbb_clk,
+		.mode		= pbb_clk_mode,
+		.get_rate	= pbb_clk_get_rate,
+		.index		= 12,
+	}
+};
+static int __initdata atmel_spi_pins[][4] = {
+	{
+		/* SPI0 */
+		GPIO_PIN_PB(3), GPIO_PIN_PB(4),
+		GPIO_PIN_PB(5), GPIO_PIN_PB(6),
+	}, {
+		/* SPI1 */
+		GPIO_PIN_PB(4), -1, -1, -1,
+	}, {
+		/* SPI2 */
+		GPIO_PIN_PA(28), -1, -1, -1,
+	}, {
+		/* SPI3 */
+		GPIO_PIN_PA(27), GPIO_PIN_PA(20),
+		GPIO_PIN_PA(29), GPIO_PIN_PA(30),
+	}
+};
+
+
+static void __init at32_spi_setup_dw_dma(unsigned int id,
+		struct atmel_spi_pdata *pdata)
+{
+	struct dw_dma_slave	*rx_dws;
+	struct dw_dma_slave	*tx_dws;
+
+	if (pdata->rx_dma_slave)
+		rx_dws = kmemdup(to_dw_dma_slave(pdata->rx_dma_slave),
+				sizeof(struct dw_dma_slave), GFP_KERNEL);
+	else
+		rx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
+	if (pdata->tx_dma_slave)
+		tx_dws = kmemdup(to_dw_dma_slave(pdata->tx_dma_slave),
+				sizeof(struct dw_dma_slave), GFP_KERNEL);
+	else
+		tx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
+
+	rx_dws->slave.dma_dev = tx_dws->slave.dma_dev = &dw_dmac0_device.dev;
+	rx_dws->slave.reg_width = tx_dws->slave.reg_width
+		= DMA_SLAVE_WIDTH_8BIT;
+
+	rx_dws->cfg_hi = DWC_CFGH_SRC_PER(2);
+	tx_dws->cfg_hi = DWC_CFGH_DST_PER(3);
+	rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
+				| DWC_CFGL_HS_SRC_POL);
+	tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
+				| DWC_CFGL_HS_SRC_POL);
+
+	pdata->rx_dma_slave = &rx_dws->slave;
+	pdata->tx_dma_slave = &tx_dws->slave;
+}
+
+static void __init at32_spi_setup_pdca(unsigned int id,
+		struct atmel_spi_pdata *pdata)
+{
+	struct pdca_slave	*rx_pslave;
+	struct pdca_slave	*tx_pslave;
+
+	if (pdata->rx_dma_slave)
+		rx_pslave = kmemdup(dma_to_pdca_slave(pdata->rx_dma_slave),
+				sizeof(struct pdca_slave), GFP_KERNEL);
+	else
+		rx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
+	if (pdata->tx_dma_slave)
+		tx_pslave = kmemdup(dma_to_pdca_slave(pdata->tx_dma_slave),
+				sizeof(struct pdca_slave), GFP_KERNEL);
+	else
+		tx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
+
+	rx_pslave->slave.dma_dev = &pdca_device.dev;
+	tx_pslave->slave.dma_dev = &pdca_device.dev;
+	rx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
+	tx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
+
+	rx_pslave->tx_periph_id = -1;
+	tx_pslave->rx_periph_id = -1;
+
+	switch (id) {
+	case 1:
+		rx_pslave->rx_periph_id = 6;
+		tx_pslave->tx_periph_id = 17;
+		break;
+	case 2:
+		rx_pslave->rx_periph_id = 7;
+		tx_pslave->tx_periph_id = 18;
+		break;
+	case 3:
+		rx_pslave->rx_periph_id = 8;
+		tx_pslave->tx_periph_id = 19;
+		break;
+	}
+
+	pdata->rx_dma_slave = &rx_pslave->slave;
+	pdata->tx_dma_slave = &tx_pslave->slave;
+}
+
+static void __init
+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
+		unsigned int n, const int *pins)
+{
+	unsigned int	mode;
+	unsigned int	cs;
+	int		pin;
+
+	for (; n; n--, b++) {
+		b->bus_num = bus_num;
+		cs = b->chip_select;
+		if (cs >= 4 || !gpio_is_valid(pins[cs]))
+			continue;
+
+		pin = (int)b->controller_data;
+		if (!pin || !gpio_is_valid(pin)) {
+			pin = pins[cs];
+			b->controller_data = (void *)pin;
+		}
+
+		mode = AT32_GPIOF_OUTPUT;
+		if (!(b->mode & SPI_CS_HIGH))
+			mode |= AT32_GPIOF_HIGH;
+		at32_select_gpio(pin, mode);
+	}
+}
+
+struct platform_device *__init at32_add_device_spi(unsigned int id,
+		struct spi_board_info *b, unsigned int n)
+{
+	struct atmel_spi_pdata	pdata;
+	struct platform_device	*pdev;
+
+	BUILD_BUG_ON(ARRAY_SIZE(atmel_spi_resource)
+			!= ARRAY_SIZE(atmel_spi_clk));
+
+	if (id >= ARRAY_SIZE(atmel_spi_resource))
+		return NULL;
+
+	pdev = platform_device_alloc("atmel_spi", id);
+	if (!pdev)
+		goto fail;
+
+	if (platform_device_add_resources(pdev, atmel_spi_resource[id],
+				ARRAY_SIZE(atmel_spi_resource[id])))
+		goto fail;
+
+	memset(&pdata, 0, sizeof(struct atmel_spi_pdata));
+
+	if (id == 0)
+		at32_spi_setup_dw_dma(id, &pdata);
+	else
+		at32_spi_setup_pdca(id, &pdata);
+	pdata.rx_dma_slave->dev = pdata.tx_dma_slave->dev = &pdev->dev;
+
+	if (platform_device_add_data(pdev, &pdata,
+				sizeof(struct atmel_spi_pdata)))
+		goto fail;
+
+	switch (id) {
+	case 0:
+		/* pullup MISO so a level is always defined */
+		select_peripheral(PB, (1 << 1), PERIPH_A, AT32_GPIOF_PULLUP);
+		/* MOSI | SCK */
+		select_peripheral(PB, (1 << 0) | (1 << 2), PERIPH_A, 0);
+
+		at32_spi_setup_slaves(0, b, n, atmel_spi_pins[0]);
+		break;
+
+	case 1:
+		/* pullup MISO so a level is always defined */
+		select_peripheral(PB, (1 << 7), PERIPH_B, AT32_GPIOF_PULLUP);
+		/* MOSI | SCK */
+		select_peripheral(PB, (1 << 6) | (1 << 5), PERIPH_B, 0);
+
+		at32_spi_setup_slaves(1, b, n, atmel_spi_pins[1]);
+		break;
+
+	case 2:
+		/* pullup MISO so a level is always defined */
+		select_peripheral(PA, (1 << 30), PERIPH_B, AT32_GPIOF_PULLUP);
+		/* MOSI | SCK */
+		select_peripheral(PA, (1 << 31) || (1 << 29), PERIPH_B, 0);
+
+		at32_spi_setup_slaves(2, b, n, atmel_spi_pins[2]);
+		break;
+
+	case 3:
+		/* pullup MISO so a level is always defined */
+		select_peripheral(PA, (1 << 25), PERIPH_A, AT32_GPIOF_PULLUP);
+		/* MOSI | SCK */
+		select_peripheral(PA, (1 << 24) | (1 << 26), PERIPH_A, 0);
+
+		at32_spi_setup_slaves(3, b, n, atmel_spi_pins[3]);
+		break;
+
+	default:
+		goto fail;
+	}
+
+	atmel_spi_clk[id].dev = &pdev->dev;
+	spi_register_board_info(b, n);
+	platform_device_add(pdev);
+
+	return pdev;
+
+fail:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* --------------------------------------------------------------------
+ * MMC
+ * -------------------------------------------------------------------- */
+static struct resource atmel_mci0_resource[] __initdata = {
+	PBMEM(0xfff00000),
+	IRQ(43),
+};
+/* MCI is on the PBC bus, but it is controlled by the PBBMASK register */
+static struct clk atmel_mci0_pclk = {
+	.name		= "mci_clk",
+	.parent		= &pbc_clk,
+	.mode		= pbb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.index		= 16,
+};
+
+struct platform_device *__init
+at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
+{
+	struct platform_device		*pdev;
+	struct dw_dma_slave		*dws;
+	u32 pin_mask_1 = 0;
+	u32 pin_mask_2 = 0;
+
+	if (id != 0)
+		return NULL;
+
+	/* Must have at least one usable slot */
+	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
+		return NULL;
+
+	pdev = platform_device_alloc("atmel_mci", id);
+	if (!pdev)
+		goto fail;
+
+	if (platform_device_add_resources(pdev, atmel_mci0_resource,
+				ARRAY_SIZE(atmel_mci0_resource)))
+		goto fail;
+
+	if (data->dma_slave)
+		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
+				sizeof(struct dw_dma_slave), GFP_KERNEL);
+	else
+		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
+
+	dws->slave.dev = &pdev->dev;
+	dws->slave.dma_dev = &dw_dmac0_device.dev;
+	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
+	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
+				| DWC_CFGH_DST_PER(1));
+	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
+				| DWC_CFGL_HS_SRC_POL);
+
+	data->dma_slave = &dws->slave;
+
+	if (platform_device_add_data(pdev, data,
+				sizeof(struct mci_platform_data)))
+		goto fail;
+
+	switch (data->slot[0].bus_width) {
+	case 8:
+		pin_mask_1 |= (1 << 20); /* DATA4 */
+		pin_mask_1 |= (1 << 21); /* DATA5 */
+		pin_mask_1 |= (1 << 22); /* DATA6 */
+		pin_mask_1 |= (1 << 23); /* DATA7 */
+		/* fall through */
+	case 4:
+		pin_mask_2 |= (1 << 19); /* DATA1 */
+		pin_mask_2 |= (1 << 20); /* DATA2 */
+		pin_mask_2 |= (1 << 21); /* DATA3 */
+		/* fall through */
+	case 1:
+		pin_mask_2 |= (1 << 18); /* DATA0 */
+		pin_mask_2 |= (1 << 17); /* CMD   */
+
+		select_peripheral(PA, pin_mask_1, PERIPH_D, AT32_GPIOF_PULLUP);
+		select_peripheral(PB, pin_mask_2, PERIPH_A, AT32_GPIOF_PULLUP);
+		select_peripheral(PB, (1 << 16),  PERIPH_A, 0);	/* CLK */
+
+		if (gpio_is_valid(data->slot[0].detect_pin))
+			at32_select_gpio(data->slot[0].detect_pin, 0);
+		if (gpio_is_valid(data->slot[0].wp_pin))
+			at32_select_gpio(data->slot[0].wp_pin, 0);
+
+		break;
+	case 0:
+		/* Slot is unused */
+		break;
+	default:
+		goto fail;
+	}
+
+	pin_mask_1 = 0;
+
+	switch (data->slot[1].bus_width) {
+	case 8:
+		pin_mask_1 |= (1 << 9); /* DATA7 */
+		pin_mask_1 |= (1 << 8); /* DATA6 */
+		pin_mask_1 |= (1 << 7); /* DATA5 */
+		pin_mask_1 |= (1 << 6); /* DATA4 */
+		/* fall through */
+	case 4:
+		pin_mask_1 |= (1 << 5); /* DATA3 */
+		pin_mask_1 |= (1 << 4); /* DATA2 */
+		pin_mask_1 |= (1 << 3); /* DATA1 */
+		/* fall through */
+	case 1:
+		pin_mask_1 |= (1 << 2); /* DATA0 */
+		pin_mask_1 |= (1 << 1); /* CMD   */
+
+		select_peripheral(PC, pin_mask_1, PERIPH_A, AT32_GPIOF_PULLUP);
+		select_peripheral(PC, (1 << 0),   PERIPH_A, 0);	/* CLK */
+
+		if (gpio_is_valid(data->slot[1].detect_pin))
+			at32_select_gpio(data->slot[1].detect_pin, 0);
+		if (gpio_is_valid(data->slot[1].wp_pin))
+			at32_select_gpio(data->slot[1].wp_pin, 0);
+
+		break;
+	case 0:
+		/* Slot is unused */
+		break;
+	default:
+		goto fail;
+	}
+
+	atmel_mci0_pclk.dev = &pdev->dev;
+
+	platform_device_add(pdev);
+	return pdev;
+
+fail:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* --------------------------------------------------------------------
+ *  LCDC
+ * -------------------------------------------------------------------- */
+static u64 atmel_lcdfb0_dma_mask = DMA_32BIT_MASK;
+static struct resource atmel_lcdfb0_resource[] __initdata = {
+	{
+		.start	= 0xff000000,
+		.end	= 0xff000fff,
+		.flags	= IORESOURCE_MEM,
+	},
+	IRQ(3),
+	{
+		/* Placeholder for pre-allocated fb memory */
+		.start	= 0x00000000,
+		.end	= 0x00000000,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct clk atmel_lcdfb0_hck1 = {
+	.name		= "hck1",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= hsb_clk_get_rate,
+	.index		= 7,
+};
+static struct clk atmel_lcdfb0_pixclk = {
+	.name		= "lcdc_clk",
+	.mode		= genclk_mode,
+	.get_rate	= genclk_get_rate,
+	.set_rate	= genclk_set_rate,
+	.set_parent	= genclk_set_parent,
+	.index		= 6,
+};
+
+struct platform_device *__init
+at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
+		unsigned long fbmem_start, unsigned long fbmem_len,
+		u64 pin_mask)
+{
+	struct {
+		struct atmel_lcdfb_info	info;
+		struct fb_monspecs	monspecs;
+		struct fb_videomode	modedb[0];
+	} *all_data;
+	struct platform_device	*pdev;
+	unsigned int		data_size;
+	unsigned int		modedb_size;
+	unsigned int		num_resources;
+	int			ret;
+
+	if (id > 0 || !data)
+		return NULL;
+
+	pdev = platform_device_alloc("atmel_lcdfb", id);
+	if (!pdev)
+		return NULL;
+
+	num_resources = ARRAY_SIZE(atmel_lcdfb0_resource);
+	if (fbmem_len) {
+		atmel_lcdfb0_resource[num_resources - 1].start = fbmem_start;
+		atmel_lcdfb0_resource[num_resources - 1].end
+			= fbmem_start + fbmem_len - 1;
+	} else {
+		num_resources--;
+	}
+
+	if (platform_device_add_resources(pdev, atmel_lcdfb0_resource,
+				num_resources))
+		goto error;
+
+	/*
+	 * Allocate all data -- info struct, monspecs and modedb -- in
+	 * a single chunk.
+	 */
+	modedb_size = data->default_monspecs->modedb_len
+			* sizeof(struct fb_videomode);
+	data_size = sizeof(*all_data) + modedb_size;
+	all_data = kmalloc(data_size, GFP_KERNEL);
+	if (!all_data)
+		goto error;
+
+	memcpy(&all_data->info, data, sizeof(struct atmel_lcdfb_info));
+	memcpy(&all_data->monspecs, data->default_monspecs,
+			sizeof(struct fb_monspecs));
+	memcpy(&all_data->modedb, data->default_monspecs->modedb, modedb_size);
+
+	ret = platform_device_add_data(pdev, all_data, data_size);
+	kfree(all_data);
+	if (ret)
+		goto error;
+
+	/*
+	 * Update internal pointers to use memory allocated by
+	 * platform_device_add_data().
+	 */
+	all_data = pdev->dev.platform_data;
+	all_data->info.default_monspecs = &all_data->monspecs;
+	all_data->monspecs.modedb = all_data->modedb;
+
+	select_peripheral(PD, 0x7fffffff,  PERIPH_A, 0);
+
+	pdev->dev.dma_mask = &atmel_lcdfb0_dma_mask;
+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
+
+	atmel_lcdfb0_hck1.dev = &pdev->dev;
+	atmel_lcdfb0_pixclk.dev = &pdev->dev;
+
+	clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
+	clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
+
+	platform_device_add(pdev);
+	return pdev;
+
+error:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* --------------------------------------------------------------------
+ *  Media Post-Processor (MPOP)
+ * -------------------------------------------------------------------- */
+
+static u64 atmel_mpopfb0_dma_mask = DMA_32BIT_MASK;
+static struct resource atmel_mpopfb0_resource[] = {
+	{
+		/* Configuration interface */
+		.start	= 0xffe02000,
+		.end	= 0xffe02fff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		/* Data interface (output) */
+		.start	= 0xf0000000,
+		.end	= 0xf0ffffff,
+		.flags	= IORESOURCE_MEM,
+	},
+	IRQ(4),
+	{
+		/* Placeholder for pre-allocated fb memory */
+		.start	= 0x00000000,
+		.end	= 0x00000000,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct clk atmel_mpopfb0_hclk = {
+	.name		= "hclk",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= hsb_clk_get_rate,
+	.index		= 12,
+};
+static struct clk atmel_mpopfb0_pclk = {
+	.name		= "pclk",
+	.parent		= &pbb_clk,
+	.mode		= pbb_clk_mode,
+	.get_rate	= pbb_clk_get_rate,
+	.index		= 2,
+};
+
+struct platform_device *__init at32_add_device_mpop(unsigned int id,
+		struct platform_device *lcdc_pdev,
+		unsigned long fbmem_start, unsigned long fbmem_len)
+{
+	struct platform_device		*pdev;
+	struct atmel_mpopfb_info	info;
+	unsigned int			num_resources;
+
+	if (id != 0)
+		return NULL;
+
+	pdev = platform_device_alloc("atmel_mpopfb", id);
+	if (!pdev)
+		return NULL;
+
+	num_resources = ARRAY_SIZE(atmel_mpopfb0_resource);
+	if (fbmem_len) {
+		atmel_mpopfb0_resource[num_resources - 1].start = fbmem_start;
+		atmel_mpopfb0_resource[num_resources - 1].end
+			= fbmem_start + fbmem_len - 1;
+	} else {
+		num_resources--;
+	}
+	if (platform_device_add_resources(pdev, atmel_mpopfb0_resource,
+				num_resources))
+		goto error;
+
+	info.lcdc_pdev = lcdc_pdev;
+	if (platform_device_add_data(pdev, &info, sizeof(info)))
+		goto error;
+
+	pdev->dev.dma_mask = &atmel_mpopfb0_dma_mask;
+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
+
+	atmel_mpopfb0_hclk.dev = &pdev->dev;
+	atmel_mpopfb0_pclk.dev = &pdev->dev;
+
+	platform_device_add(pdev);
+	return pdev;
+
+error:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* -------------------------------------------------------------------
+ *  USB Host (OHCI/EHCI)
+ * ------------------------------------------------------------------- */
+
+static u64 usbh_dma_mask = DMA_32BIT_MASK;
+
+static unsigned long parent_clk_get_rate(struct clk *clk)
+{
+	return clk->parent->get_rate(clk->parent);
+}
+
+static void parent_clk_mode(struct clk *clk, int enabled)
+{
+	/* Parent clk enabled by clk core */
+}
+
+/*
+ * The UTMI clock is an internally controlled PLL. It is hardwired to
+ * OSC2 and will run at 30 MHz or 60 MHz depending on the internal
+ * UTMI <-> host controller data bus width.
+ *
+ * We can turn it on and off through the Power Manager. That's all.
+ */
+static void utmi_clk_mode(struct clk *clk, int enabled)
+{
+	u32 ppcr = pm_readl(PPCR);
+
+	if (enabled)
+		/* Clear UTMI suspend signal */
+		ppcr |= PM_BIT(PPCR_UTMI_CTRL);
+	else
+		/* Set UTMI suspend signal */
+		ppcr &= ~PM_BIT(PPCR_UTMI_CTRL);
+
+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0x55));
+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0xaa));
+
+	if (enabled)
+		/* PLL startup time is 2.5 ms */
+		udelay(2500);
+}
+
+static unsigned long utmi_clk_get_rate(struct clk *clk)
+{
+	/*
+	 * Not sure about this, but I think the UTMI interface on
+	 * AP7200 is 16 bits wide, which means 30 MHz PHY clock.
+	 */
+	return 30000000;
+}
+
+static struct clk usbh_utmi_clk = {
+	.name		= "usbh_utmi_clk",
+	.parent		= &osc2,
+	.mode		= utmi_clk_mode,
+	.get_rate	= utmi_clk_get_rate,
+};
+
+static struct clk usbh_hclk = {
+	.name		= "usbh_hclk",
+	.parent		= &hsb_clk,
+	.mode		= hsb_clk_mode,
+	.get_rate	= hsb_clk_get_rate,
+	.index		= 6,
+};
+
+/*
+ * UTMI and HSB clocks are shared between OHCI and EHCI. These wrappers
+ * make sure both can use the clocks as if they had their own.
+ */
+static struct clk ohci_utmi_clk = {
+	.name		= "utmi_clk",
+	.parent		= &usbh_utmi_clk,
+	.mode		= parent_clk_mode,
+	.get_rate	= parent_clk_get_rate,
+};
+static struct clk ohci_hclk = {
+	.name		= "hclk",
+	.parent		= &usbh_hclk,
+	.mode		= parent_clk_mode,
+	.get_rate	= parent_clk_get_rate,
+};
+
+static struct clk ehci_utmi_clk = {
+	.name		= "utmi_clk",
+	.parent		= &usbh_utmi_clk,
+	.mode		= parent_clk_mode,
+	.get_rate	= parent_clk_get_rate,
+};
+static struct clk ehci_hclk = {
+	.name		= "hclk",
+	.parent		= &usbh_hclk,
+	.mode		= parent_clk_mode,
+	.get_rate	= parent_clk_get_rate,
+};
+
+/*
+ * The USBH needs both a 48 MHz and a 12 MHz clock, and the 12 MHz
+ * must be generated by dividing the 48 MHz clock. There's only one
+ * generic clock hooked up to the USBH which we must use to generate
+ * both.
+ *
+ * This can be done because GCLK0 generates an additional "divided
+ * clock", which is the normal clock output further divided by four
+ * (this is hardcoded, but not surprisingly, exactly what we need.)
+ *
+ * So we generate the clocks as follows:
+ *    OSC2 (12 MHz) -> PLL2 (48 MHz) --> GCLK0 undivided (48 MHz)
+ *                                   |-> GCLK0 divided (12 MHz)
+ *
+ * This clock is only used by the OHCI part of the controller, not the
+ * EHCI part.
+ */
+static struct clk ohci_gclk = {
+	.name		= "ohci_clk",
+	.parent		= &gclk0,
+	.mode		= parent_clk_mode,
+	.get_rate	= parent_clk_get_rate,
+};
+
+static struct resource usbh_ohci_resource[] __initdata = {
+	{
+		.start	= 0xff400000,
+		.end	= 0xff400400,
+		.flags	= IORESOURCE_MEM,
+	},
+	IRQ(7),
+};
+
+static struct resource usbh_ehci_resource[] __initdata = {
+	{
+		.start	= 0xff300000,
+		.end	= 0xff300400,
+		.flags	= IORESOURCE_MEM,
+	},
+	IRQ(7),
+};
+
+static void __init usbh_setup_pins(void)
+{
+	static bool already_done __initdata;
+
+	if (!already_done) {
+		already_done = true;
+		/* OC_EN_N | OC_FLAG_N */
+		select_peripheral(PA, (1 << 18) | (1 << 19), PERIPH_D, 0);
+	}
+}
+
+struct platform_device *__init at32_add_device_ohci(unsigned int id)
+{
+	struct platform_device *pdev;
+
+	if (id != 0)
+		return NULL;
+
+	pdev = platform_device_alloc("ohci", id);
+	if (!pdev)
+		goto error;
+
+	if (platform_device_add_resources(pdev, usbh_ohci_resource,
+				ARRAY_SIZE(usbh_ohci_resource)))
+		goto error;
+
+	pdev->dev.dma_mask = &usbh_dma_mask;
+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
+
+	clk_set_parent(&pll2, &osc2);
+	if (clk_round_rate(&pll2, 48000000) != 48000000) {
+		pr_debug("USBH OHCI: Cannot generate 48 MHz clock\n");
+		goto error;
+	}
+	clk_set_rate(&pll2, 48000000);
+
+	clk_set_parent(&gclk0, &pll2);
+	clk_set_rate(&gclk0, 48000000);
+
+	ohci_utmi_clk.dev = &pdev->dev;
+	ohci_hclk.dev = &pdev->dev;
+	ohci_gclk.dev = &pdev->dev;
+
+	usbh_setup_pins();
+
+	platform_device_add(pdev);
+	return pdev;
+
+error:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+struct platform_device *__init at32_add_device_ehci(unsigned int id)
+{
+	struct platform_device *pdev;
+
+	if (id != 0)
+		return NULL;
+
+	pdev = platform_device_alloc("ehci", id);
+	if (!pdev)
+		goto error;
+
+	if (platform_device_add_resources(pdev, usbh_ehci_resource,
+				ARRAY_SIZE(usbh_ehci_resource)))
+		goto error;
+
+	pdev->dev.dma_mask = &usbh_dma_mask;
+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
+
+	ehci_utmi_clk.dev = &pdev->dev;
+	ehci_hclk.dev = &pdev->dev;
+
+	usbh_setup_pins();
+
+	platform_device_add(pdev);
+	return pdev;
+
+error:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* -------------------------------------------------------------------
+ *  NAND Flash / SmartMedia
+ * ------------------------------------------------------------------- */
+static struct resource smc_cs3_resource[] __initdata = {
+	{
+		.start	= 0x24000000,
+		.end	= 0x27ffffff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= 0xffe04c00,
+		.end	= 0xffe04fff,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device *__init
+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
+{
+	struct platform_device *pdev;
+
+	if (id != 0 || !data)
+		return NULL;
+
+	pdev = platform_device_alloc("atmel_nand", id);
+	if (!pdev)
+		goto error;
+
+	if (platform_device_add_resources(pdev, smc_cs3_resource,
+				ARRAY_SIZE(smc_cs3_resource)))
+		goto error;
+
+	if (platform_device_add_data(pdev, data,
+				sizeof(struct atmel_nand_data)))
+		goto error;
+
+	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
+
+	/* NANDOE | NANDWE */
+	select_peripheral(PF, (1 << 0) | (1 << 1), PERIPH_A, 0);
+
+	if (gpio_is_valid(data->enable_pin))
+		at32_select_gpio(data->enable_pin,
+				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
+	if (gpio_is_valid(data->det_pin))
+		at32_select_gpio(data->det_pin, 0);
+	if (gpio_is_valid(data->rdy_pin))
+		at32_select_gpio(data->rdy_pin, 0);
+
+	platform_device_add(pdev);
+	return pdev;
+
+error:
+	platform_device_put(pdev);
+	return NULL;
+}
+
+/* -------------------------------------------------------------------
+ * Clock list
+ * ------------------------------------------------------------------- */
+static __initdata struct clk *init_clocks[] = {
+	&rcosc,
+	&osc0,
+	&osc1,
+	&osc2,
+	&osc32,
+	&pll0,
+	&pll1,
+	&pll2,
+	&cpu_clk,
+	&hsb_clk,
+	&pba_clk,
+	&pbb_clk,
+	&pbc_clk,
+	&gclk0,
+	&gclk1,
+	&gclk2,
+	&gclk3,
+	&gclk4,
+	&gclk5,
+	&at32_intc0_pclk,
+	&pm_pclk,
+	&sdc_pclk,
+	&ast0_pclk,
+	&ast1_pclk,
+	&wdt_pclk,
+	&gpio_pclk,
+	&pdca_hclk,
+	&pdca_pclk,
+	&ebi_hclk,
+	&hramc_clk,
+	&smc_pclk,
+	&sdramc_clk,
+	&dw_dmac0_hclk,
+	&atmel_usart0_usart,
+	&atmel_usart1_usart,
+	&atmel_usart2_usart,
+	&atmel_usart3_usart,
+	&atmel_usart4_usart,
+	&atmel_usart5_usart,
+	&atmel_spi_clk[0],
+	&atmel_spi_clk[1],
+	&atmel_spi_clk[2],
+	&atmel_spi_clk[3],
+	&macb0_hclk,
+	&macb0_pclk,
+	&atmel_mci0_pclk,
+	&atmel_lcdfb0_hck1,
+	&atmel_lcdfb0_pixclk,
+	&atmel_mpopfb0_hclk,
+	&atmel_mpopfb0_pclk,
+	&usbh_utmi_clk,
+	&usbh_hclk,
+	&ohci_utmi_clk,
+	&ohci_hclk,
+	&ohci_gclk,
+	&ehci_utmi_clk,
+	&ehci_hclk,
+};
+
+static void pll_init_parent(struct clk *pll)
+{
+	u32 ctrl;
+
+	ctrl = pm_readl(PLL[pll->index]);
+	switch (PM_BFEXT(PLLx_PLLOSC, ctrl)) {
+	case 0:
+		pll->parent = &osc0;
+		break;
+	case 1:
+		pll->parent = &osc1;
+		break;
+	case 2:
+		pll->parent = &osc2;
+		break;
+	}
+}
+
+static void ap7200_power_off(void)
+{
+	/*
+	 * Clear all wakeup events so that we don't wake up
+	 * immediately after we shut down.
+	 */
+	sdc_writel(ECR, ~0UL);
+	sdc_readl(STATUS);
+	asm volatile("sleep %0; sub pc, -2"
+			:: "i"(CPU_SLEEP_SHUTDOWN)
+			: "memory");
+}
+
+void __init setup_platform(void)
+{
+	unsigned int	i;
+	u32		cpu_mask;
+	u32		hsb_mask;
+	u32		pba_mask;
+	u32		pbb_mask;
+
+	switch (PM_BFEXT(MCCTRL_MCSEL, pm_readl(MCCTRL))) {
+	case 0:
+		main_clock = &rcosc;
+		break;
+	case 1:
+		main_clock = &osc0;
+		break;
+	case 2:
+		main_clock = &pll0;
+		break;
+	}
+
+	cpu_clk.parent = main_clock;
+
+	pll_init_parent(&pll0);
+	pll_init_parent(&pll1);
+	pll_init_parent(&pll2);
+
+	genclk_init_parent(&gclk0);
+	genclk_init_parent(&gclk1);
+	genclk_init_parent(&gclk2);
+	genclk_init_parent(&gclk3);
+	genclk_init_parent(&gclk4);
+	genclk_init_parent(&gclk5);
+	genclk_init_parent(&atmel_lcdfb0_pixclk);
+
+	/*
+	 * Turn on all clocks that have at least one user already, and
+	 * turn off everything else. We only do this for module
+	 * clocks, and even though it isn't particularly pretty to
+	 * check the address of the mode function, it should do the
+	 * trick...
+	 */
+	cpu_mask = 0x10003;
+	hsb_mask = pba_mask = pbb_mask = 0;
+
+	/* Make sure we don't disable the power manager or the SDRAM */
+	pm_pclk.users = 1;
+	pm_pclk.parent->users = 1;
+	ebi_hclk.users = 1;
+
+	/* Can't recursively call clk_enable() from any of the clk ops */
+	sdc_pclk.users = 1;
+
+	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
+		struct clk *clk = init_clocks[i];
+
+		/* first, register clock */
+		at32_clk_register(clk);
+
+		if (clk->users == 0)
+			continue;
+
+		if (clk->mode == &cpu_clk_mode)
+			cpu_mask |= 1 << clk->index;
+		else if (clk->mode == &hsb_clk_mode)
+			hsb_mask |= 1 << clk->index;
+		else if (clk->mode == &pba_clk_mode)
+			pba_mask |= 1 << clk->index;
+		else if (clk->mode == &pbb_clk_mode)
+			pbb_mask |= 1 << clk->index;
+	}
+
+	pm_writel(CPUMASK, cpu_mask);
+	pm_writel(HSBMASK, hsb_mask);
+	pm_writel(PBAMASK, pba_mask);
+	pm_writel(PBBMASK, pbb_mask);
+
+	at32_gpio_init(&gpio_device);
+
+	/* Enter shutdown mode when powering off. This happens very
+	 * early, so board code may still override this. */
+	pm_power_off = ap7200_power_off;
+
+	/* Enable WAKE pin */
+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
+			| SDC_BF(CTRL_KEY, 0x55));
+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
+			| SDC_BF(CTRL_KEY, 0xaa));
+}
+
+void __init platform_time_init(void)
+{
+	ast_time_init(&ast1_device, AST_CLOCK_PB);
+}
+
+unsigned long at32_get_reset_cause(void)
+{
+	return pm_readl(RCAUSE);
+}
+
+struct gen_pool *sram_pool;
+
+static int __init sram_init(void)
+{
+	struct gen_pool *pool;
+
+	/* 1KiB granularity */
+	pool = gen_pool_create(10, -1);
+	if (!pool)
+		goto fail;
+
+	if (gen_pool_add(pool, 0x08000000, 0x10000, -1))
+		goto err_pool_add;
+
+	sram_pool = pool;
+	return 0;
+
+err_pool_add:
+	gen_pool_destroy(pool);
+fail:
+	pr_err("Failed to create SRAM pool\n");
+	return -ENOMEM;
+}
+core_initcall(sram_init);
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/extint.c linux-2.6.28.2/arch/avr32/mach-at32ap/extint.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/extint.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/extint.c	2009-01-29 08:52:49.000000000 +0100
@@ -17,6 +17,8 @@
 
 #include <asm/io.h>
 
+#include <mach/cpu.h>
+
 /* EIC register offsets */
 #define EIC_IER					0x0000
 #define EIC_IDR					0x0004
@@ -26,24 +28,18 @@
 #define EIC_MODE				0x0014
 #define EIC_EDGE				0x0018
 #define EIC_LEVEL				0x001c
-#define EIC_NMIC				0x0024
 
-/* Bitfields in NMIC */
-#define EIC_NMIC_ENABLE				(1 << 0)
+/* This is only valid on v1 (AP700x) */
+#define EIC_NMIC				0x0024
+# define EIC_NMIC_ENABLE			(1 << 0)
 
-/* Bit manipulation macros */
-#define EIC_BIT(name)					\
-	(1 << EIC_##name##_OFFSET)
-#define EIC_BF(name,value)				\
-	(((value) & ((1 << EIC_##name##_SIZE) - 1))	\
-	 << EIC_##name##_OFFSET)
-#define EIC_BFEXT(name,value)				\
-	(((value) >> EIC_##name##_OFFSET)		\
-	 & ((1 << EIC_##name##_SIZE) - 1))
-#define EIC_BFINS(name,value,old)			\
-	(((old) & ~(((1 << EIC_##name##_SIZE) - 1)	\
-		    << EIC_##name##_OFFSET))		\
-	 | EIC_BF(name,value))
+/* These are only valid on v3 (AP720x) */
+#define EIC_FILTER				0x0020
+#define EIC_TEST				0x0024
+#define EIC_ASYNC				0x0028
+#define EIC_EN					0x0030
+#define EIC_DIS					0x0034
+#define EIC_CTRL				0x0038
 
 /* Register access macros */
 #define eic_readl(port,reg)				\
@@ -60,36 +56,68 @@
 static struct eic *nmi_eic;
 static bool nmi_enabled;
 
+static inline int eic_version(struct eic *eic)
+{
+	if (cpu_is_at32ap7000())
+		return 1;
+	if (cpu_is_at32ap7200())
+		return 3;
+
+	BUG();
+}
+
+static inline int eic_irq_bitmask(struct eic *eic, unsigned int irq)
+{
+	irq -= eic->first_irq;
+
+	if (eic_version(eic) > 2)
+		irq++;
+	return 1 << irq;
+}
+
 static void eic_ack_irq(unsigned int irq)
 {
 	struct eic *eic = get_irq_chip_data(irq);
-	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
 }
 
 static void eic_mask_irq(unsigned int irq)
 {
 	struct eic *eic = get_irq_chip_data(irq);
-	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
 }
 
 static void eic_mask_ack_irq(unsigned int irq)
 {
 	struct eic *eic = get_irq_chip_data(irq);
-	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
-	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
 }
 
 static void eic_unmask_irq(unsigned int irq)
 {
 	struct eic *eic = get_irq_chip_data(irq);
-	eic_writel(eic, IER, 1 << (irq - eic->first_irq));
+	eic_writel(eic, IER, eic_irq_bitmask(eic, irq));
+}
+
+/* The following two hooks are only used on v2+ controllers */
+static void eic_enable_irq(unsigned int irq)
+{
+	struct eic *eic = get_irq_chip_data(irq);
+	eic_writel(eic, EN, eic_irq_bitmask(eic, irq));
+}
+
+static void eic_disable_irq(unsigned int irq)
+{
+	struct eic *eic = get_irq_chip_data(irq);
+	eic_writel(eic, DIS, eic_irq_bitmask(eic, irq));
 }
 
 static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
 {
 	struct eic *eic = get_irq_chip_data(irq);
 	struct irq_desc *desc;
-	unsigned int i = irq - eic->first_irq;
+	unsigned int irq_bitmask = eic_irq_bitmask(eic, irq);
 	u32 mode, edge, level;
 	int ret = 0;
 
@@ -105,20 +133,20 @@
 
 	switch (flow_type) {
 	case IRQ_TYPE_LEVEL_LOW:
-		mode |= 1 << i;
-		level &= ~(1 << i);
+		mode |= irq_bitmask;
+		level &= ~irq_bitmask;
 		break;
 	case IRQ_TYPE_LEVEL_HIGH:
-		mode |= 1 << i;
-		level |= 1 << i;
+		mode |= irq_bitmask;
+		level |= irq_bitmask;
 		break;
 	case IRQ_TYPE_EDGE_RISING:
-		mode &= ~(1 << i);
-		edge |= 1 << i;
+		mode &= ~irq_bitmask;
+		edge |= irq_bitmask;
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
-		mode &= ~(1 << i);
-		edge &= ~(1 << i);
+		mode &= ~irq_bitmask;
+		edge &= ~irq_bitmask;
 		break;
 	default:
 		ret = -EINVAL;
@@ -160,6 +188,11 @@
 	status = eic_readl(eic, ISR);
 	pending = status & eic_readl(eic, IMR);
 
+	if (eic_version(eic) > 1) {
+		status >>= 1;
+		pending >>= 1;
+	}
+
 	while (pending) {
 		i = fls(pending) - 1;
 		pending &= ~(1 << i);
@@ -172,16 +205,34 @@
 {
 	nmi_enabled = true;
 
-	if (nmi_eic)
-		eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
+	if (nmi_eic) {
+		if (eic_version(nmi_eic) > 2) {
+			eic_writel(nmi_eic, EN, 1 << 0);
+			eic_writel(nmi_eic, IER, 1 << 0);
+		} else if (eic_version(nmi_eic) > 1) {
+			eic_writel(nmi_eic, EN, 1 << 8);
+			eic_writel(nmi_eic, IER, 1 << 8);
+		} else {
+			eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
+		}
+	}
 
 	return 0;
 }
 
 void nmi_disable(void)
 {
-	if (nmi_eic)
-		eic_writel(nmi_eic, NMIC, 0);
+	if (nmi_eic) {
+		if (eic_version(nmi_eic) > 2) {
+			eic_writel(nmi_eic, IDR, 1 << 0);
+			eic_writel(nmi_eic, DIS, 1 << 0);
+		} else if (eic_version(nmi_eic) > 1) {
+			eic_writel(nmi_eic, IDR, 1 << 8);
+			eic_writel(nmi_eic, DIS, 1 << 8);
+		} else {
+			eic_writel(nmi_eic, NMIC, 0);
+		}
+	}
 
 	nmi_enabled = false;
 }
@@ -230,6 +281,15 @@
 	eic_writel(eic, EDGE, 0UL);
 	eic_writel(eic, LEVEL, 0UL);
 
+	/*
+	 * v2+ controllers have an extra enable/disable/mask set of
+	 * registers.
+	 */
+	if (eic_version(eic) >= 2) {
+		eic_chip.enable = eic_enable_irq;
+		eic_chip.disable = eic_disable_irq;
+	}
+
 	eic->chip = &eic_chip;
 
 	for (i = 0; i < nr_of_irqs; i++) {
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.c linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.c	2009-01-29 08:52:49.000000000 +0100
@@ -0,0 +1,534 @@
+/*
+ * Atmel GPIO Port Multiplexer support
+ *
+ * Copyright (C) 2004-2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <mach/portmux.h>
+#include <mach/chip.h>
+
+#include "gpio-v2.h"
+
+/*
+ * One chip corresponds with one bank of I/O registers. They're really
+ * all on the same controller.
+ */
+struct atmel_gpio_chip {
+	void __iomem	*regs;
+	u32		pinmux_mask;
+	struct		gpio_chip chip;
+	char		name[8];
+	unsigned int	bank;
+	int		irq;
+};
+
+/* ...which means we only have one clock and one platform device */
+static struct clk *gpio_clk;
+static struct atmel_gpio_chip gpio_dev[NR_GPIO_BANKS];
+
+/* Pin multiplexing API */
+static DEFINE_SPINLOCK(gpio_lock);
+
+static struct atmel_gpio_chip *to_atmel_gpio_chip(struct gpio_chip *chip)
+{
+	return container_of(chip, struct atmel_gpio_chip, chip);
+}
+
+static struct atmel_gpio_chip *pin_to_chip(unsigned int gpio)
+{
+	struct atmel_gpio_chip *chip;
+	unsigned int index;
+
+	index = gpio >> 5;
+	if (index >= NR_GPIO_BANKS)
+		return NULL;
+	chip = &gpio_dev[index];
+	if (!chip->regs)
+		return NULL;
+
+	return chip;
+}
+
+/* Pin multiplexing API */
+
+void __init at32_select_periph(unsigned int port, u32 pin_mask,
+		unsigned int periph, unsigned long flags)
+{
+	struct atmel_gpio_chip *chip;
+
+	chip = pin_to_chip(port);
+	if (unlikely(!chip)) {
+		printk("GPIO: invalid port %u\n", port);
+		goto fail;
+	}
+
+	/* Test if any of the requested pins is already muxed */
+	spin_lock(&gpio_lock);
+	if (unlikely(gpiochip_is_requested(&chip->chip, port)
+			|| unlikely(pin_mask & chip->pinmux_mask))) {
+		printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
+		       chip->name, pin_mask, chip->pinmux_mask & pin_mask);
+		spin_unlock(&gpio_lock);
+		goto fail;
+	}
+
+	switch (periph) {
+	case GPIO_PERIPH_A:
+		gpio_writel(chip, PMR0C, pin_mask);
+		gpio_writel(chip, PMR1C, pin_mask);
+		break;
+	case GPIO_PERIPH_B:
+		gpio_writel(chip, PMR0S, pin_mask);
+		gpio_writel(chip, PMR1C, pin_mask);
+		break;
+	case GPIO_PERIPH_C:
+		gpio_writel(chip, PMR0C, pin_mask);
+		gpio_writel(chip, PMR1S, pin_mask);
+		break;
+	case GPIO_PERIPH_D:
+		gpio_writel(chip, PMR0S, pin_mask);
+		gpio_writel(chip, PMR1S, pin_mask);
+		break;
+	default:
+		printk("%s: unknown function for pin mask %u\n",
+				chip->name, pin_mask);
+		goto fail;
+	}
+
+	gpio_writel(chip, PUERS, pin_mask);
+
+	gpio_writel(chip, GPERC, pin_mask);
+	if (!(flags & AT32_GPIOF_PULLUP))
+		gpio_writel(chip, PUERC, pin_mask);
+
+	spin_unlock(&gpio_lock);
+
+	return;
+
+fail:
+	dump_stack();
+}
+
+void __init at32_select_gpio(unsigned int pin, unsigned long flags)
+{
+	struct atmel_gpio_chip *chip;
+	unsigned int pin_index = pin & 0x1f;
+	u32 mask = 1 << pin_index;
+
+	chip = pin_to_chip(pin);
+	if (unlikely(!chip)) {
+		printk("GPIO: invalid pin %u\n", pin);
+		goto fail;
+	}
+
+	if (unlikely(test_and_set_bit(pin_index, &chip->pinmux_mask))) {
+		printk("%s: pin %u is busy\n", chip->name, pin_index);
+		goto fail;
+	}
+
+	if (flags & AT32_GPIOF_PULLUP)
+		gpio_writel(chip, PUERS, mask);
+	else
+		gpio_writel(chip, PUERC, mask);
+	if (flags & AT32_GPIOF_MULTIDRV)
+		gpio_writel(chip, ODMERS, mask);
+	else
+		gpio_writel(chip, ODMERC, mask);
+	if (flags & AT32_GPIOF_DEGLITCH)
+		gpio_writel(chip, GFERS, mask);
+	else
+		gpio_writel(chip, GFERC, mask);
+
+	if (flags & AT32_GPIOF_OUTPUT) {
+		if (flags & AT32_GPIOF_HIGH)
+			gpio_writel(chip, OVRS, mask);
+		else
+			gpio_writel(chip, OVRC, mask);
+		gpio_writel(chip, ODERS, mask);
+	} else {
+		gpio_writel(chip, ODERC, mask);
+	}
+
+	gpio_writel(chip, GPERS, mask);
+
+	return;
+
+fail:
+	dump_stack();
+}
+
+/* Reserve a pin, preventing anyone else from changing its configuration. */
+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
+{
+	struct atmel_gpio_chip *chip;
+
+	chip = pin_to_chip(port);
+	if (unlikely(!chip)) {
+		printk("GPIO: invalid port %u\n", port);
+		goto fail;
+	}
+
+	/* Test if any of the requested pins is already muxed */
+	spin_lock(&gpio_lock);
+	if (unlikely(pin_mask & chip->pinmux_mask)) {
+		printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
+			chip->name, pin_mask, chip->pinmux_mask & pin_mask);
+		spin_unlock(&gpio_lock);
+		goto fail;
+	}
+
+	/* Reserve pins */
+	chip->pinmux_mask |= pin_mask;
+	spin_unlock(&gpio_lock);
+	return;
+
+fail:
+	dump_stack();
+}
+
+/*--------------------------------------------------------------------------*/
+
+/* GPIO API */
+
+static int get_pin_state(struct gpio_chip *chip, unsigned int offset)
+{
+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
+
+	return (gpio_readl(gpio, PVR) >> offset) & 1;
+}
+
+static void set_pin_state(struct gpio_chip *chip, unsigned int offset, int high)
+{
+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
+	u32 mask = 1 << offset;
+
+	if (high)
+		gpio_writel(gpio, OVRS, mask);
+	else
+		gpio_writel(gpio, OVRC, mask);
+}
+
+static int direction_input(struct gpio_chip *chip, unsigned int offset)
+{
+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
+	u32 mask = 1 << offset;
+
+	if (!(gpio_readl(gpio, GPER) & mask))
+		return -EINVAL;
+
+	gpio_writel(gpio, ODERC, mask);
+	return 0;
+}
+
+static int direction_output(struct gpio_chip *chip, unsigned int offset,
+		int high)
+{
+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
+	u32 mask = 1 << offset;
+
+	if (!(gpio_readl(gpio, GPER) & mask))
+		return -EINVAL;
+
+	set_pin_state(chip, offset, high);
+	gpio_writel(gpio, ODERS, mask);
+	return 0;
+}
+
+/*--------------------------------------------------------------------------*/
+
+/* GPIO IRQ support */
+
+static void gpio_irq_mask(unsigned irq)
+{
+	unsigned int		pin = irq_to_gpio(irq);
+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
+
+	gpio_writel(chip, IERC, 1 << (pin & 0x1f));
+}
+
+static void gpio_irq_unmask(unsigned irq)
+{
+	unsigned int		pin = irq_to_gpio(irq);
+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
+
+	gpio_writel(chip, IERS, 1 << (pin & 0x1f));
+}
+
+static int gpio_irq_type(unsigned irq, unsigned type)
+{
+	unsigned int		pin = irq_to_gpio(irq);
+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
+	u32			mask = 1 << (pin & 0x1f);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_FALLING:
+		gpio_writel(chip, IMR0C, mask);
+		gpio_writel(chip, IMR1S, mask);
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		gpio_writel(chip, IMR0S, mask);
+		gpio_writel(chip, IMR1C, mask);
+		break;
+	case IRQ_TYPE_NONE:
+		/* fall through */
+	case IRQ_TYPE_EDGE_BOTH:
+		gpio_writel(chip, IMR0C, mask);
+		gpio_writel(chip, IMR1C, mask);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static struct irq_chip gpio_irqchip = {
+	.name		= "gpio",
+	.mask		= gpio_irq_mask,
+	.unmask		= gpio_irq_unmask,
+	.set_type	= gpio_irq_type,
+};
+
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+	struct atmel_gpio_chip	*chip = get_irq_chip_data(irq);
+	unsigned int		gpio_irq;
+
+	gpio_irq = (unsigned int) get_irq_data(irq);
+	for (;;) {
+		u32		ifr;
+		struct irq_desc	*d;
+
+		/* ack pending GPIO interrupts */
+		ifr = gpio_readl(chip, IFR);
+		if (!ifr)
+			break;
+		do {
+			int pin;
+
+			pin = ffs(ifr) - 1;
+			ifr &= ~(1 << pin);
+			gpio_writel(chip, IFRC, (1 << pin));
+
+			pin += gpio_irq;
+			d = &irq_desc[pin];
+
+			d->handle_irq(pin, d);
+		} while (ifr);
+	}
+}
+
+static void __init
+gpio_irq_setup(struct atmel_gpio_chip *chip, int irq, int gpio_irq)
+{
+	unsigned	i;
+
+	set_irq_chip_data(irq, chip);
+	set_irq_data(irq, (void *) gpio_irq);
+
+	for (i = 0; i < 32; i++, gpio_irq++) {
+		set_irq_chip_data(gpio_irq, chip);
+		set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
+				handle_simple_irq);
+	}
+
+	set_irq_chained_handler(irq, gpio_irq_handler);
+}
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/seq_file.h>
+
+/*
+ * This shows more info than the generic gpio dump code:
+ * pullups, deglitching, open drain drive.
+ */
+static void gpio_bank_show(struct seq_file *s, struct gpio_chip *chip)
+{
+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
+	u32		oder, ovr, puer, pder, gfer, odmer, ier, imr0, imr1;
+	unsigned int	i;
+	u32		mask;
+
+	oder = gpio_readl(gpio, ODER);
+	ovr = gpio_readl(gpio, OVR);
+	puer = gpio_readl(gpio, PUER);
+	pder = gpio_readl(gpio, PDER);
+	gfer = gpio_readl(gpio, GFER);
+	odmer = gpio_readl(gpio, ODMER);
+	ier = gpio_readl(gpio, IER);
+	imr0 = gpio_readl(gpio, IMR0);
+	imr1 = gpio_readl(gpio, IMR1);
+
+	for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
+		const char *label;
+
+		label = gpiochip_is_requested(chip, i);
+		if (!label)
+			continue;
+
+		seq_printf(s, " gpio-%-3d ", chip->base + i);
+		gpio_decode_pin(s, gpio->bank, i);
+		seq_printf(s, " (%-12s) %s %s", label,
+				(oder & mask) ? "out" : "in",
+				(ovr & mask) ? "hi" : "lo");
+		if ((puer & mask) && !(pder & mask))
+			seq_printf(s, " pull-up");
+		else if (!(puer & mask) && (pder & mask))
+			seq_printf(s, " pull-down");
+		else if ((puer & mask) && (pder & mask))
+			seq_printf(s, " buskeeper");
+		if (gfer & mask)
+			seq_printf(s, " deglitch");
+		if (odmer & mask)
+			seq_printf(s, " open-drain");
+		if ((gpio->irq >= 0) && (ier & mask)) {
+			seq_printf(s, " irq-%d edge-",
+					gpio_to_irq(chip->base + i));
+			if (!(imr0 & mask) && !(imr1 & mask))
+				seq_printf(s, "both");
+			else if ((imr0 & mask) && !(imr1 & mask))
+				seq_printf(s, "rising");
+			else if (!(imr0 & mask) && (imr1 & mask))
+				seq_printf(s, "falling");
+			else
+				seq_printf(s, "INVALID");
+		}
+		seq_printf(s, "\n");
+	}
+}
+
+#else
+#define gpio_bank_show	NULL
+#endif
+
+static int __init gpio_probe(struct platform_device *pdev)
+{
+	struct resource *regs;
+	struct resource *irqs;
+	int irq = -1;
+	unsigned int i;
+
+	BUG_ON(pdev->id >= 1);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(&pdev->dev, "no mmio resource defined\n");
+		return -ENXIO;
+	}
+	irqs = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (irqs)
+		irq = irqs->start;
+
+	for (i = 0; i < NR_GPIO_BANKS; i++) {
+		unsigned int gpio_irq_base;
+		struct atmel_gpio_chip *chip;
+
+		chip = &gpio_dev[i];
+		BUG_ON(!chip->regs);
+
+		chip->chip.label = chip->name;
+		chip->chip.base = i * 32;
+		chip->chip.ngpio = 32;
+
+		chip->chip.direction_input = direction_input;
+		chip->chip.get = get_pin_state;
+		chip->chip.direction_output = direction_output;
+		chip->chip.set = set_pin_state;
+		chip->chip.dbg_show = gpio_bank_show;
+
+		gpiochip_add(&chip->chip);
+
+		gpio_irq_base = GPIO_IRQ_BASE + (i * 32);
+		if (irqs && irq <= irqs->end) {
+			gpio_irq_setup(chip, irq, gpio_irq_base);
+			chip->irq = irq;
+			irq++;
+		} else {
+			chip->irq = -1;
+		}
+
+		platform_set_drvdata(pdev, chip);
+
+		printk(KERN_DEBUG "%s: base 0x%p", chip->name, chip->regs);
+		if (chip->irq >= 0)
+			printk(" irq %d chains %d..%d", irq,
+					gpio_irq_base, gpio_irq_base + 31);
+		printk("\n");
+	}
+
+	return 0;
+}
+
+static struct platform_driver gpio_driver = {
+	.probe		= gpio_probe,
+	.driver		= {
+		.name		= "gpio",
+	},
+};
+
+static int __init gpio_init(void)
+{
+	return platform_driver_register(&gpio_driver);
+}
+postcore_initcall(gpio_init);
+
+void __init at32_gpio_init(struct platform_device *pdev)
+{
+	int i;
+	struct clk *clk;
+	struct resource *regs;
+	void __iomem *iomem_base;
+	struct atmel_gpio_chip *chip;
+
+	if (pdev->id > 0) {
+		dev_err(&pdev->dev, "only one GPIO controller supported\n");
+		return;
+	}
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(&pdev->dev, "no mmio resource defined\n");
+		return;
+	}
+
+	clk = clk_get(&pdev->dev, "pclk");
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "no mck clock defined\n");
+		return;
+	}
+	clk_enable(clk);
+
+	gpio_clk = clk;
+
+	/*
+	 * We may get called too early for ioremap() to work. But we
+	 * know that the GPIO registers are permanently mapped 1:1
+	 */
+	iomem_base = (void __iomem __force *)regs->start;
+
+	for (i = 0; i < NR_GPIO_BANKS; i++) {
+		chip = &gpio_dev[i];
+		snprintf(chip->name, sizeof(chip->name), "gpio%d", i);
+		chip->regs = iomem_base + (i * 0x200);
+		chip->bank = i;
+
+		/* start with irqs disabled and acked */
+		gpio_writel(chip, IERC, ~0UL);
+		gpio_writel(chip, IFRC, ~0UL);
+	}
+}
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.h linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.h	2009-01-29 08:52:49.000000000 +0100
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __GPIO_REGS_H__
+#define __GPIO_REGS_H__
+
+/* Register offsets */
+struct gpio_regs {
+	u32	GPER;
+	u32	GPERS;
+	u32	GPERC;
+	u32	GPERT;
+	u32	PMR0;
+	u32	PMR0S;
+	u32	PMR0C;
+	u32	PMR0T;
+	u32	PMR1;
+	u32	PMR1S;
+	u32	PMR1C;
+	u32	PMR1T;
+	u32	__reserved0[4];
+	u32	ODER;
+	u32	ODERS;
+	u32	ODERC;
+	u32	ODERT;
+	u32	OVR;
+	u32	OVRS;
+	u32	OVRC;
+	u32	OVRT;
+	u32	PVR;
+	u32	__reserved_PVRS;
+	u32	__reserved_PVRC;
+	u32	__reserved_PVRT;
+	u32	PUER;
+	u32	PUERS;
+	u32	PUERC;
+	u32	PUERT;
+	u32	PDER;
+	u32	PDERS;
+	u32	PDERC;
+	u32	PDERT;
+	u32	IER;
+	u32	IERS;
+	u32	IERC;
+	u32	IERT;
+	u32	IMR0;
+	u32	IMR0S;
+	u32	IMR0C;
+	u32	IMR0T;
+	u32	IMR1;
+	u32	IMR1S;
+	u32	IMR1C;
+	u32	IMR1T;
+	u32	GFER;
+	u32	GFERS;
+	u32	GFERC;
+	u32	GFERT;
+	u32	IFR;
+	u32	__reserved_IFRS;
+	u32	IFRC;
+	u32	__reserved_IFRT;
+	u32	ODMER;
+	u32	ODMERS;
+	u32	ODMERC;
+	u32	ODMERT;
+	u32	__reserved1[4];
+	u32	ODCR0;
+	u32	ODCR0S;
+	u32	ODCR0C;
+	u32	ODCR0T;
+	u32	ODCR1;
+	u32	ODCR1S;
+	u32	ODCR1C;
+	u32	ODCR1T;
+	u32	__reserved2[4];
+	u32	OSRR0;
+	u32	OSRR0S;
+	u32	OSRR0C;
+	u32	OSRR0T;
+	u32	__reserved3[8];
+	u32	STER;
+	u32	STERS;
+	u32	STERC;
+	u32	STERT;
+	u32	__reserved4[35];
+	u32	VERSION;
+};
+
+/* Register access macros */
+#define __gpio_regs(bank) ((struct gpio_regs __iomem *)(bank)->regs)
+#define gpio_readl(bank, reg)						\
+	__raw_readl(&__gpio_regs(bank)->reg)
+#define gpio_writel(bank, reg, value)					\
+	__raw_writel(value, &__gpio_regs(bank)->reg)
+
+void at32_gpio_init(struct platform_device *pdev);
+
+#endif /* __GPIO_REGS_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hmatrix.c linux-2.6.28.2/arch/avr32/mach-at32ap/hmatrix.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hmatrix.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/hmatrix.c	2009-01-29 08:52:49.000000000 +0100
@@ -54,6 +54,81 @@
 }
 
 /**
+ * hmatrix_set_default_master - set default master on a given slave
+ * @slave: HSB slave interface ID
+ * @master: HSB master interface ID
+ */
+void hmatrix_set_default_master(unsigned int slave, unsigned int master)
+{
+	u32 value;
+	unsigned int reg;
+
+	WARN_ON(slave > HMATRIX_MAX_SLAVE
+			|| master > HMATRIX_MASTER_LAST);
+
+	reg = HMATRIX_SCFG(slave);
+
+	clk_enable(&at32_hmatrix_clk);
+	value = __hmatrix_read_reg(reg);
+	value &= ~(HMATRIX_SCFG_FIXED_DEFMSTR(HMATRIX_MAX_SLAVE)
+			| HMATRIX_SCFG_DEFMSTR_MASK);
+
+	switch (master) {
+	case HMATRIX_MASTER_NONE:
+		value |= HMATRIX_SCFG_DEFMSTR_NONE;
+		break;
+	case HMATRIX_MASTER_LAST:
+		value |= HMATRIX_SCFG_DEFMSTR_LAST;
+		break;
+	default:
+		value |= HMATRIX_SCFG_DEFMSTR_FIXED;
+		value |= HMATRIX_SCFG_FIXED_DEFMSTR(master);
+		break;
+	}
+
+	__hmatrix_write_reg(reg, value);
+	__hmatrix_read_reg(reg);
+	clk_disable(&at32_hmatrix_clk);
+}
+
+/**
+ * hmatrix_set_priority - set the priority of a master on a given slave
+ * @slave: HSB slave interface ID
+ * @master: HSB master interface ID
+ * @priority: Priority of @master when competing for access to @slave.
+ *
+ * Note that this is currently broken -- we need some way to enable
+ * fixed-priority arbitration, and that happens to be broken on AP7000
+ * rev C.
+ */
+void hmatrix_set_priority(unsigned int slave, unsigned int master,
+		unsigned int priority)
+{
+	u32 value;
+	unsigned int reg;
+
+	WARN_ON(slave > HMATRIX_MAX_SLAVE
+			|| master > HMATRIX_MAX_MASTER
+			|| priority > HMATRIX_MAX_PRIO);
+
+	clk_enable(&at32_hmatrix_clk);
+	if (master < 8) {
+		reg = HMATRIX_PRAS(slave);
+		value = __hmatrix_read_reg(reg);
+		value &= ~HMATRIX_PRAS_PRIO(master, HMATRIX_MAX_PRIO);
+		value |= HMATRIX_PRAS_PRIO(master, priority);
+	} else {
+		reg = HMATRIX_PRBS(slave);
+		value = __hmatrix_read_reg(reg);
+		value &= ~HMATRIX_PRBS_PRIO(master, HMATRIX_MAX_PRIO);
+		value |= HMATRIX_PRBS_PRIO(master, priority);
+	}
+	__hmatrix_write_reg(reg, value);
+	__hmatrix_read_reg(reg);
+	clk_disable(&at32_hmatrix_clk);
+}
+
+/**
  * hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
  * @slave_id: operate on the SFR belonging to this slave
  * @mask: mask of bits to be set in the SFR
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hsmc.c linux-2.6.28.2/arch/avr32/mach-at32ap/hsmc.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hsmc.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/hsmc.c	2009-01-29 08:52:49.000000000 +0100
@@ -229,10 +229,8 @@
 	if (IS_ERR(pclk))
 		return PTR_ERR(pclk);
 	mck = clk_get(&pdev->dev, "mck");
-	if (IS_ERR(mck)) {
-		ret = PTR_ERR(mck);
-		goto out_put_pclk;
-	}
+	if (IS_ERR(mck))
+		mck = pclk;
 
 	ret = -ENOMEM;
 	hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
@@ -260,8 +258,8 @@
 	clk_disable(pclk);
 	kfree(hsmc);
 out_put_clocks:
-	clk_put(mck);
-out_put_pclk:
+	if (mck != pclk)
+		clk_put(mck);
 	clk_put(pclk);
 	hsmc = NULL;
 	return ret;
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap700x.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap700x.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap700x.h	2009-01-29 08:52:49.000000000 +0100
@@ -211,4 +211,135 @@
 
 #define ATMEL_LCDC_ALT_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
 
+/* Bitmask for all EBI data (D16..D31) pins on port E */
+#define ATMEL_EBI_PE_DATA_ALL  (0x0000FFFF)
+
+/* LCDC on port C */
+#define ATMEL_LCDC_PC_CC	(1ULL << 19)
+#define ATMEL_LCDC_PC_HSYNC	(1ULL << 20)
+#define ATMEL_LCDC_PC_PCLK	(1ULL << 21)
+#define ATMEL_LCDC_PC_VSYNC	(1ULL << 22)
+#define ATMEL_LCDC_PC_DVAL	(1ULL << 23)
+#define ATMEL_LCDC_PC_MODE	(1ULL << 24)
+#define ATMEL_LCDC_PC_PWR	(1ULL << 25)
+#define ATMEL_LCDC_PC_DATA0	(1ULL << 26)
+#define ATMEL_LCDC_PC_DATA1	(1ULL << 27)
+#define ATMEL_LCDC_PC_DATA2	(1ULL << 28)
+#define ATMEL_LCDC_PC_DATA3	(1ULL << 29)
+#define ATMEL_LCDC_PC_DATA4	(1ULL << 30)
+#define ATMEL_LCDC_PC_DATA5	(1ULL << 31)
+
+/* LCDC on port D */
+#define ATMEL_LCDC_PD_DATA6	(1ULL << 0)
+#define ATMEL_LCDC_PD_DATA7	(1ULL << 1)
+#define ATMEL_LCDC_PD_DATA8	(1ULL << 2)
+#define ATMEL_LCDC_PD_DATA9	(1ULL << 3)
+#define ATMEL_LCDC_PD_DATA10	(1ULL << 4)
+#define ATMEL_LCDC_PD_DATA11	(1ULL << 5)
+#define ATMEL_LCDC_PD_DATA12	(1ULL << 6)
+#define ATMEL_LCDC_PD_DATA13	(1ULL << 7)
+#define ATMEL_LCDC_PD_DATA14	(1ULL << 8)
+#define ATMEL_LCDC_PD_DATA15	(1ULL << 9)
+#define ATMEL_LCDC_PD_DATA16	(1ULL << 10)
+#define ATMEL_LCDC_PD_DATA17	(1ULL << 11)
+#define ATMEL_LCDC_PD_DATA18	(1ULL << 12)
+#define ATMEL_LCDC_PD_DATA19	(1ULL << 13)
+#define ATMEL_LCDC_PD_DATA20	(1ULL << 14)
+#define ATMEL_LCDC_PD_DATA21	(1ULL << 15)
+#define ATMEL_LCDC_PD_DATA22	(1ULL << 16)
+#define ATMEL_LCDC_PD_DATA23	(1ULL << 17)
+
+/* LCDC on port E */
+#define ATMEL_LCDC_PE_CC	(1ULL << (32 + 0))
+#define ATMEL_LCDC_PE_DVAL	(1ULL << (32 + 1))
+#define ATMEL_LCDC_PE_MODE	(1ULL << (32 + 2))
+#define ATMEL_LCDC_PE_DATA0	(1ULL << (32 + 3))
+#define ATMEL_LCDC_PE_DATA1	(1ULL << (32 + 4))
+#define ATMEL_LCDC_PE_DATA2	(1ULL << (32 + 5))
+#define ATMEL_LCDC_PE_DATA3	(1ULL << (32 + 6))
+#define ATMEL_LCDC_PE_DATA4	(1ULL << (32 + 7))
+#define ATMEL_LCDC_PE_DATA8	(1ULL << (32 + 8))
+#define ATMEL_LCDC_PE_DATA9	(1ULL << (32 + 9))
+#define ATMEL_LCDC_PE_DATA10	(1ULL << (32 + 10))
+#define ATMEL_LCDC_PE_DATA11	(1ULL << (32 + 11))
+#define ATMEL_LCDC_PE_DATA12	(1ULL << (32 + 12))
+#define ATMEL_LCDC_PE_DATA16	(1ULL << (32 + 13))
+#define ATMEL_LCDC_PE_DATA17	(1ULL << (32 + 14))
+#define ATMEL_LCDC_PE_DATA18	(1ULL << (32 + 15))
+#define ATMEL_LCDC_PE_DATA19	(1ULL << (32 + 16))
+#define ATMEL_LCDC_PE_DATA20	(1ULL << (32 + 17))
+#define ATMEL_LCDC_PE_DATA21	(1ULL << (32 + 18))
+
+
+#define ATMEL_LCDC(PORT, PIN)	(ATMEL_LCDC_##PORT##_##PIN)
+
+
+#define ATMEL_LCDC_PRI_24B_DATA	(					\
+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
+		ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) |	\
+		ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) |	\
+		ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) |	\
+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
+
+#define ATMEL_LCDC_ALT_24B_DATA (					\
+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
+		ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) |	\
+		ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) |	\
+		ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) |	\
+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
+
+#define ATMEL_LCDC_PRI_15B_DATA (					\
+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA16) |	\
+		ATMEL_LCDC(PD, DATA17) | ATMEL_LCDC(PD, DATA18) |	\
+		ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20))
+
+#define ATMEL_LCDC_ALT_15B_DATA	(					\
+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PE, DATA16) |	\
+		ATMEL_LCDC(PE, DATA17) | ATMEL_LCDC(PE, DATA18) |	\
+		ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20))
+
+#define ATMEL_LCDC_PRI_CONTROL (					\
+		ATMEL_LCDC(PC, CC)   | ATMEL_LCDC(PC, DVAL) |		\
+		ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))
+
+#define ATMEL_LCDC_ALT_CONTROL (					\
+		ATMEL_LCDC(PE, CC)   | ATMEL_LCDC(PE, DVAL) |		\
+		ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))
+
+#define ATMEL_LCDC_CONTROL (						\
+		ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) |		\
+		ATMEL_LCDC(PC, PCLK))
+
+#define ATMEL_LCDC_PRI_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)
+
+#define ATMEL_LCDC_ALT_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)
+
+#define ATMEL_LCDC_PRI_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)
+
+#define ATMEL_LCDC_ALT_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
+
 #endif /* __ASM_ARCH_AT32AP700X_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap720x.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap720x.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap720x.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap720x.h	2009-01-29 08:52:49.000000000 +0100
@@ -0,0 +1,105 @@
+/*
+ * Pin definitions for AT32AP7200
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_AT32AP7200_H__
+#define __ASM_ARCH_AT32AP7200_H__
+
+#define GPIO_PERIPH_A	0x00
+#define GPIO_PERIPH_B	0x01
+#define GPIO_PERIPH_C	0x02
+#define GPIO_PERIPH_D	0x03
+
+#define NR_GPIO_BANKS	8
+
+/*
+ * Pin numbers identifying specific GPIO pins on the chip. They can
+ * also be converted to IRQ numbers by passing them through
+ * gpio_to_irq().
+ */
+#define GPIO_BASE	(0)
+
+#define GPIO_PA_BASE	(GPIO_BASE + 0 * 32)
+#define GPIO_PB_BASE	(GPIO_BASE + 1 * 32)
+#define GPIO_PC_BASE	(GPIO_BASE + 2 * 32)
+#define GPIO_PD_BASE	(GPIO_BASE + 3 * 32)
+#define GPIO_PE_BASE	(GPIO_BASE + 4 * 32)
+#define GPIO_PF_BASE	(GPIO_BASE + 5 * 32)
+#define GPIO_PX_BASE	(GPIO_BASE + 6 * 32)
+
+#define GPIO_PIN_PA(N)	(GPIO_PA_BASE + (N))
+#define GPIO_PIN_PB(N)	(GPIO_PB_BASE + (N))
+#define GPIO_PIN_PC(N)	(GPIO_PC_BASE + (N))
+#define GPIO_PIN_PD(N)	(GPIO_PD_BASE + (N))
+#define GPIO_PIN_PE(N)	(GPIO_PE_BASE + (N))
+#define GPIO_PIN_PF(N)	(GPIO_PF_BASE + (N))
+#define GPIO_PIN_PX(N)	(GPIO_PX_BASE + (N))
+
+#define gpio_decode_pin(s, bank, offset)				\
+	do {								\
+		switch (bank) {						\
+		case 7:							\
+			offset += 32;					\
+			/* fall through */				\
+		case 6:							\
+			seq_printf(s, "PX%-2u", offset);		\
+			break;						\
+		default:						\
+			seq_printf(s, "P%c%-2u", bank + 'A', offset);	\
+			break;						\
+		}							\
+	} while (0)
+
+/* HSB master IDs */
+#define HMATRIX_MASTER_CPU_ICACHE		 0
+#define HMATRIX_MASTER_CPU_DCACHE		 1
+#define HMATRIX_MASTER_PDCA			 2
+#define HMATRIX_MASTER_LCDC			 4
+#define HMATRIX_MASTER_MPOP_IBI			 5
+#define HMATRIX_MASTER_MPOP_OBI			 6
+#define HMATRIX_MASTER_MPOP_OM			 7
+#define HMATRIX_MASTER_DMACA_M0			 8
+#define HMATRIX_MASTER_DMACA_M1			 9
+#define HMATRIX_MASTER_USBB			10
+#define HMATRIX_MASTER_USBH_EHCI		11
+#define HMATRIX_MASTER_USBH_OHCI		12
+#define HMATRIX_MASTER_MACB			13
+
+/* HSB slave IDs */
+#define HMATRIX_SLAVE_BOOTROM			 0
+#define HMATRIX_SLAVE_PBA			 1
+#define HMATRIX_SLAVE_PBB			 2
+#define HMATRIX_SLAVE_PBC			 3
+#define HMATRIX_SLAVE_SRAM0			 4
+#define HMATRIX_SLAVE_SRAM1			 5
+#define HMATRIX_SLAVE_EBI			 6
+#define HMATRIX_SLAVE_LCDC			 7
+#define HMATRIX_SLAVE_MPOP			 8
+#define HMATRIX_SLAVE_DMACA			 9
+#define HMATRIX_SLAVE_USBB			10
+#define HMATRIX_SLAVE_EHCI			11
+#define HMATRIX_SLAVE_OHCI			12
+
+/* Bits in HMATRIX SFR6 (EBI) */
+#define HMATRIX_EBI_SDRAM_ENABLE		(1 << 1)
+#define HMATRIX_EBI_NAND_ENABLE			(1 << 3)
+#define HMATRIX_EBI_CF0_ENABLE			(1 << 4)
+#define HMATRIX_EBI_CF1_ENABLE			(1 << 5)
+
+/*
+ * Base addresses of controllers that may be accessed early by
+ * platform code.
+ */
+#define GPIO_HW_BASE	0xffd02000
+#define INTC_BASE	0xffd00000
+#define PM_BASE		0xffd00400
+#define SDC_BASE	0xffd00800
+#define SDRAMC_BASE	0xffe04800
+#define HMATRIX_BASE	0xffe05000
+
+#endif /* __ASM_ARCH_AT32AP7200_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/chip.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/chip.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/chip.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/chip.h	2009-01-29 08:52:49.000000000 +0100
@@ -12,6 +12,8 @@
 
 #if defined(CONFIG_CPU_AT32AP700X)
 # include <mach/at32ap700x.h>
+#elif defined(CONFIG_CPU_AT32AP720X)
+# include <mach/at32ap720x.h>
 #else
 # error Unknown chip type selected
 #endif
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/cpu.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/cpu.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/cpu.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/cpu.h	2009-01-29 08:52:49.000000000 +0100
@@ -20,6 +20,19 @@
 # define cpu_is_at32ap7000()	(0)
 #endif
 
+#ifdef CONFIG_CPU_AT32AP720X
+# define cpu_is_at32ap7200()	(1)
+#else
+# define cpu_is_at32ap7200()	(0)
+#endif
+
+/*
+ * Unfortunately, only AP700x has a non-broken COUNT/COMPARE
+ * implementation. Other chips need to use different timers. The good
+ * news is that these timers are usually better anyway.
+ */
+#define cpu_has_working_compare()	(cpu_is_at32ap7000())
+
 /*
  * Since this is AVR32, we will never run on any AT91 CPU. But these
  * definitions may reduce clutter in common drivers.
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/hmatrix.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/hmatrix.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/hmatrix.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/hmatrix.h	2009-01-29 08:52:49.000000000 +0100
@@ -15,6 +15,9 @@
 void hmatrix_write_reg(unsigned long offset, u32 value);
 u32 hmatrix_read_reg(unsigned long offset);
 
+void hmatrix_set_default_master(unsigned int slave, unsigned int master);
+void hmatrix_set_priority(unsigned int slave, unsigned int master,
+		unsigned int priority);
 void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask);
 void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
 
@@ -33,6 +36,7 @@
 # define HMATRIX_SCFG_DEFMSTR_NONE	(  0 << 16)	/* No default master */
 # define HMATRIX_SCFG_DEFMSTR_LAST	(  1 << 16)	/* Last def master */
 # define HMATRIX_SCFG_DEFMSTR_FIXED	(  2 << 16)	/* Fixed def master */
+# define HMATRIX_SCFG_DEFMSTR_MASK	(  3 << 16)
 # define HMATRIX_SCFG_FIXED_DEFMSTR(m)	((m) << 18)	/* Fixed master ID */
 # define HMATRIX_SCFG_ARBT_ROUND_ROBIN	(  0 << 24)	/* RR arbitration */
 # define HMATRIX_SCFG_ARBT_FIXED_PRIO	(  1 << 24)	/* Fixed priority */
@@ -52,4 +56,12 @@
 /* Special Function Register. Bit definitions are chip-specific */
 #define HMATRIX_SFR(s)			(0x0110 + 4 * (s))
 
+#define HMATRIX_MAX_SLAVE	15
+#define HMATRIX_MAX_MASTER	15
+#define HMATRIX_MAX_PRIO	15
+
+/* Special master IDs for use with hmatrix_set_default_master() */
+#define HMATRIX_MASTER_NONE	16	/* No default master */
+#define HMATRIX_MASTER_LAST	17	/* Last master stays connected */
+
 #endif /* __HMATRIX_H */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/init.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/init.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/init.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/init.h	2009-01-29 08:52:49.000000000 +0100
@@ -15,4 +15,10 @@
 
 void at32_setup_serial_console(unsigned int usart_id);
 
+/*
+ * Called from time_init() when a broken COUNT/COMPARE implementation
+ * is detected.
+ */
+void platform_time_init(void);
+
 #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/irq.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/irq.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/irq.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/irq.h	2009-01-29 08:52:49.000000000 +0100
@@ -6,7 +6,7 @@
 #define AT32_EXTINT(n)	(EIM_IRQ_BASE + (n))
 
 #define GPIO_IRQ_BASE	(EIM_IRQ_BASE + NR_EIM_IRQS)
-#define NR_GPIO_CTLR	(5 /*internal*/ + 1 /*external*/)
+#define NR_GPIO_CTLR	(8 /*internal*/ + 1 /*external*/)
 #define NR_GPIO_IRQS	(NR_GPIO_CTLR * 32)
 
 #define NR_IRQS		(GPIO_IRQ_BASE + NR_GPIO_IRQS)
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/pm.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/pm.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/pm.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/pm.h	2009-01-29 08:52:49.000000000 +0100
@@ -11,13 +11,17 @@
 #define __ASM_AVR32_ARCH_PM_H
 
 /* Possible arguments to the "sleep" instruction */
-#define CPU_SLEEP_IDLE		0
-#define CPU_SLEEP_FROZEN	1
-#define CPU_SLEEP_STANDBY	2
-#define CPU_SLEEP_STOP		3
-#define CPU_SLEEP_STATIC	5
+#define CPU_SLEEP_IDLE		0x00
+#define CPU_SLEEP_FROZEN	0x01
+#define CPU_SLEEP_STANDBY	0x02
+#define CPU_SLEEP_STOP		0x03
+#define CPU_SLEEP_DEEPSTOP	0x04	/* Not valid on AP700x */
+#define CPU_SLEEP_STATIC	0x05
+#define CPU_SLEEP_SHUTDOWN	0x06	/* Not valid on AP700x */
+#define CPU_SLEEP_UNMASK_IRQ	0x80	/* Not valid on AP700x */
 
 #ifndef __ASSEMBLY__
+#if defined(CONFIG_CPU_AT32AP700X)
 extern void cpu_enter_idle(void);
 extern void cpu_enter_standby(unsigned long sdramc_base);
 
@@ -37,15 +41,57 @@
 {
 	/*
 	 * If we're using the COUNT and COMPARE registers for
-	 * timekeeping, we can't use the IDLE state.
+	 * timekeeping on AP7000, we can't use the IDLE state.
 	 */
 	if (disable_idle_sleep)
 		cpu_relax();
 	else
 		cpu_enter_idle();
 }
+#else
+static inline void cpu_disable_idle_sleep(void)
+{
+
+}
+
+static inline void cpu_enable_idle_sleep(void)
+{
+
+}
+
+static inline void cpu_enter_idle(void)
+{
+	/* Enable interrupts and sleep */
+	asm volatile("sleep %0"
+			:
+			: "i"(CPU_SLEEP_IDLE | CPU_SLEEP_UNMASK_IRQ)
+			: "memory");
+}
+
+static inline void cpu_idle_sleep(void)
+{
+	local_irq_disable();
+	if (!test_thread_flag(TIF_NEED_RESCHED))
+		cpu_enter_idle();
+	local_irq_enable();
+}
+#endif
 
 void intc_set_suspend_handler(unsigned long offset);
+
+extern unsigned long at32_get_reset_cause(void);
+
 #endif
 
+#define AT32_RCAUSE_POR		(1 <<  0)	/* Power-On Reset */
+#define AT32_RCAUSE_BOD		(1 <<  1)	/* Brown-Out Detected */
+#define AT32_RCAUSE_EXT		(1 <<  2)	/* External Reset */
+#define AT32_RCAUSE_WDT		(1 <<  3)	/* Watchdog Timeout */
+#define AT32_RCAUSE_JTAG	(1 <<  4)	/* JTAG Reset */
+#define AT32_RCAUSE_NTAE	(1 <<  5)	/* NanoTrace Access Error */
+#define AT32_RCAUSE_SLEEP	(1 <<  6)	/* Shutdown or Static mode */
+#define AT32_RCAUSE_CPUERR	(1 <<  7)	/* CPU Error */
+#define AT32_RCAUSE_OCDRST	(1 <<  8)	/* OCD Reset */
+#define AT32_RCAUSE_JTAGHARD	(1 <<  9)	/* JTAG Hard Reset */
+
 #endif /* __ASM_AVR32_ARCH_PM_H */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/Makefile linux-2.6.28.2/arch/avr32/mach-at32ap/Makefile
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/Makefile	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/Makefile	2009-01-29 08:52:49.000000000 +0100
@@ -1,9 +1,14 @@
-obj-y				+= pdc.o clock.o intc.o extint.o pio.o hsmc.o
+obj-y				+= pdc.o clock.o intc.o extint.o hsmc.o
 obj-y				+= hmatrix.o
-obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
+obj-$(CONFIG_PORTMUX_PIO)	+= pio.o
+obj-$(CONFIG_PORTMUX_GPIO_V2)	+= gpio-v2.o
+obj-$(CONFIG_TIMER_AST)		+= timer-ast.o
 obj-$(CONFIG_CPU_FREQ_AT32AP)	+= cpufreq.o
 obj-$(CONFIG_PM)		+= pm.o
 
+obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
+obj-$(CONFIG_CPU_AT32AP720X)	+= at32ap720x.o pm-at32ap720x.o
+
 ifeq ($(CONFIG_PM_DEBUG),y)
 CFLAGS_pm.o	+= -DDEBUG
 endif
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap700x.S linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap700x.S
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap700x.S	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap700x.S	2009-01-29 08:52:50.000000000 +0100
@@ -12,12 +12,9 @@
 #include <asm/thread_info.h>
 #include <mach/pm.h>
 
-#include "pm.h"
+#include "pm-v1.h"
 #include "sdramc.h"
 
-/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
-#define PM_BASE	-0x100000
-
 	.section .bss, "wa", @nobits
 	.global	disable_idle_sleep
 	.type	disable_idle_sleep, @object
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap720x.S linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap720x.S
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap720x.S	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap720x.S	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,110 @@
+/*
+ * Low-level Power Management code.
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <mach/pm.h>
+
+#include "pm-v3.h"
+#include "sdramc.h"
+
+#ifdef CONFIG_PM
+	.section .init.text, "ax", @progbits
+
+	.global	pm_exception
+	.type	pm_exception, @function
+pm_exception:
+	/*
+	 * Exceptions are masked when we switch to this handler, so
+	 * we'll only get "unrecoverable" exceptions (offset 0.)
+	 */
+	sub	r12, pc, . - .Lpanic_msg
+	lddpc	pc, .Lpanic_addr
+
+	.align	2
+.Lpanic_addr:
+	.long	panic
+.Lpanic_msg:
+	.asciz	"Unrecoverable exception during suspend\n"
+	.size	pm_exception, . - pm_exception
+
+	.global	pm_irq0
+	.type	pm_irq0, @function
+pm_irq0:
+	/* Disable interrupts and return after the sleep instruction */
+	mfsr	r9, SYSREG_RSR_INT0
+	mtsr	SYSREG_RAR_INT0, r8
+	sbr	r9, SYSREG_GM_OFFSET
+	mtsr	SYSREG_RSR_INT0, r9
+	rete
+
+	/*
+	 * void cpu_enter_standby(unsigned long sdramc_base)
+	 *
+	 * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
+	 * are suspended and interrupts are disabled. Interrupts
+	 * marked as 'wakeup' event sources may still come along and
+	 * get us out of here.
+	 *
+	 * The SDRAM will be put into self-refresh mode (which does
+	 * not require a clock from the CPU), and the CPU will be put
+	 * into "frozen" mode (HSB bus stopped). The SDRAM controller
+	 * will automatically bring the SDRAM into normal mode on the
+	 * first access, and the power manager will automatically
+	 * start the HSB and CPU clocks upon a wakeup event.
+	 */
+	.global	pm_standby
+	.type	pm_standby, @function
+pm_standby:
+	/*
+	 * interrupts are already masked at this point, and EVBA
+	 * points to pm_exception above.
+	 */
+	ld.w	r10, r12[SDRAMC_LPR]
+	sub	r8, pc, . - 1f		/* return address for irq handler */
+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
+	bfins	r10, r11, 0, 2		/* LPCB <- self Refresh */
+	sync	0			/* flush write buffer */
+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
+	ld.w	r11, r12[SDRAMC_LPR]
+	sleep	CPU_SLEEP_FROZEN | CPU_SLEEP_UNMASK_IRQ
+1:	mask_interrupts
+	retal	r12
+	.size	pm_standby, . - pm_standby
+
+	.global	pm_suspend_to_ram
+	.type	pm_suspend_to_ram, @function
+pm_suspend_to_ram:
+	/*
+	 * interrupts are already masked at this point, and EVBA
+	 * points to pm_exception above.
+	 */
+	mov	r11, 0
+	cache	r11[2], 8		/* clean all dcache lines */
+	sync	0			/* flush write buffer */
+	ld.w	r10, r12[SDRAMC_LPR]
+	sub	r8, pc, . - 1f		/* return address for irq handler */
+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
+	bfins	r10, r11, 0, 2		/* LPCB <- self refresh */
+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
+	ld.w	r11, r12[SDRAMC_LPR]
+
+	sleep	CPU_SLEEP_STOP | CPU_SLEEP_UNMASK_IRQ
+1:	mask_interrupts
+
+	retal	r12
+	.size	pm_suspend_to_ram, . - pm_suspend_to_ram
+
+	.global	pm_sram_end
+	.type	pm_sram_end, @function
+pm_sram_end:
+	.size	pm_sram_end, 0
+
+#endif /* CONFIG_PM */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm.h linux-2.6.28.2/arch/avr32/mach-at32ap/pm.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm.h	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm.h	1970-01-01 01:00:00.000000000 +0100
@@ -1,112 +0,0 @@
-/*
- * Register definitions for the Power Manager (PM)
- */
-#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
-#define __ARCH_AVR32_MACH_AT32AP_PM_H__
-
-/* PM register offsets */
-#define PM_MCCTRL				0x0000
-#define PM_CKSEL				0x0004
-#define PM_CPU_MASK				0x0008
-#define PM_HSB_MASK				0x000c
-#define PM_PBA_MASK				0x0010
-#define PM_PBB_MASK				0x0014
-#define PM_PLL0					0x0020
-#define PM_PLL1					0x0024
-#define PM_IER					0x0040
-#define PM_IDR					0x0044
-#define PM_IMR					0x0048
-#define PM_ISR					0x004c
-#define PM_ICR					0x0050
-#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
-#define PM_RCAUSE				0x00c0
-
-/* Bitfields in CKSEL */
-#define PM_CPUSEL_OFFSET			0
-#define PM_CPUSEL_SIZE				3
-#define PM_CPUDIV_OFFSET			7
-#define PM_CPUDIV_SIZE				1
-#define PM_HSBSEL_OFFSET			8
-#define PM_HSBSEL_SIZE				3
-#define PM_HSBDIV_OFFSET			15
-#define PM_HSBDIV_SIZE				1
-#define PM_PBASEL_OFFSET			16
-#define PM_PBASEL_SIZE				3
-#define PM_PBADIV_OFFSET			23
-#define PM_PBADIV_SIZE				1
-#define PM_PBBSEL_OFFSET			24
-#define PM_PBBSEL_SIZE				3
-#define PM_PBBDIV_OFFSET			31
-#define PM_PBBDIV_SIZE				1
-
-/* Bitfields in PLL0 */
-#define PM_PLLEN_OFFSET				0
-#define PM_PLLEN_SIZE				1
-#define PM_PLLOSC_OFFSET			1
-#define PM_PLLOSC_SIZE				1
-#define PM_PLLOPT_OFFSET			2
-#define PM_PLLOPT_SIZE				3
-#define PM_PLLDIV_OFFSET			8
-#define PM_PLLDIV_SIZE				8
-#define PM_PLLMUL_OFFSET			16
-#define PM_PLLMUL_SIZE				8
-#define PM_PLLCOUNT_OFFSET			24
-#define PM_PLLCOUNT_SIZE			6
-#define PM_PLLTEST_OFFSET			31
-#define PM_PLLTEST_SIZE				1
-
-/* Bitfields in ICR */
-#define PM_LOCK0_OFFSET				0
-#define PM_LOCK0_SIZE				1
-#define PM_LOCK1_OFFSET				1
-#define PM_LOCK1_SIZE				1
-#define PM_WAKE_OFFSET				2
-#define PM_WAKE_SIZE				1
-#define PM_CKRDY_OFFSET				5
-#define PM_CKRDY_SIZE				1
-#define PM_MSKRDY_OFFSET			6
-#define PM_MSKRDY_SIZE				1
-
-/* Bitfields in GCCTRL0 */
-#define PM_OSCSEL_OFFSET			0
-#define PM_OSCSEL_SIZE				1
-#define PM_PLLSEL_OFFSET			1
-#define PM_PLLSEL_SIZE				1
-#define PM_CEN_OFFSET				2
-#define PM_CEN_SIZE				1
-#define PM_DIVEN_OFFSET				4
-#define PM_DIVEN_SIZE				1
-#define PM_DIV_OFFSET				8
-#define PM_DIV_SIZE				8
-
-/* Bitfields in RCAUSE */
-#define PM_POR_OFFSET				0
-#define PM_POR_SIZE				1
-#define PM_EXT_OFFSET				2
-#define PM_EXT_SIZE				1
-#define PM_WDT_OFFSET				3
-#define PM_WDT_SIZE				1
-#define PM_NTAE_OFFSET				4
-#define PM_NTAE_SIZE				1
-
-/* Bit manipulation macros */
-#define PM_BIT(name)					\
-	(1 << PM_##name##_OFFSET)
-#define PM_BF(name,value)				\
-	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
-	 << PM_##name##_OFFSET)
-#define PM_BFEXT(name,value)				\
-	(((value) >> PM_##name##_OFFSET)		\
-	 & ((1 << PM_##name##_SIZE) - 1))
-#define PM_BFINS(name,value,old)\
-	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
-		    << PM_##name##_OFFSET))		\
-	 | PM_BF(name,value))
-
-/* Register access macros */
-#define pm_readl(reg)							\
-	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
-#define pm_writel(reg,value)						\
-	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
-
-#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v1.h linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v1.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v1.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v1.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,112 @@
+/*
+ * Register definitions for the Power Manager (PM)
+ */
+#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
+#define __ARCH_AVR32_MACH_AT32AP_PM_H__
+
+/* PM register offsets */
+#define PM_MCCTRL				0x0000
+#define PM_CKSEL				0x0004
+#define PM_CPU_MASK				0x0008
+#define PM_HSB_MASK				0x000c
+#define PM_PBA_MASK				0x0010
+#define PM_PBB_MASK				0x0014
+#define PM_PLL0					0x0020
+#define PM_PLL1					0x0024
+#define PM_IER					0x0040
+#define PM_IDR					0x0044
+#define PM_IMR					0x0048
+#define PM_ISR					0x004c
+#define PM_ICR					0x0050
+#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
+#define PM_RCAUSE				0x00c0
+
+/* Bitfields in CKSEL */
+#define PM_CPUSEL_OFFSET			0
+#define PM_CPUSEL_SIZE				3
+#define PM_CPUDIV_OFFSET			7
+#define PM_CPUDIV_SIZE				1
+#define PM_HSBSEL_OFFSET			8
+#define PM_HSBSEL_SIZE				3
+#define PM_HSBDIV_OFFSET			15
+#define PM_HSBDIV_SIZE				1
+#define PM_PBASEL_OFFSET			16
+#define PM_PBASEL_SIZE				3
+#define PM_PBADIV_OFFSET			23
+#define PM_PBADIV_SIZE				1
+#define PM_PBBSEL_OFFSET			24
+#define PM_PBBSEL_SIZE				3
+#define PM_PBBDIV_OFFSET			31
+#define PM_PBBDIV_SIZE				1
+
+/* Bitfields in PLL0 */
+#define PM_PLLEN_OFFSET				0
+#define PM_PLLEN_SIZE				1
+#define PM_PLLOSC_OFFSET			1
+#define PM_PLLOSC_SIZE				1
+#define PM_PLLOPT_OFFSET			2
+#define PM_PLLOPT_SIZE				3
+#define PM_PLLDIV_OFFSET			8
+#define PM_PLLDIV_SIZE				8
+#define PM_PLLMUL_OFFSET			16
+#define PM_PLLMUL_SIZE				8
+#define PM_PLLCOUNT_OFFSET			24
+#define PM_PLLCOUNT_SIZE			6
+#define PM_PLLTEST_OFFSET			31
+#define PM_PLLTEST_SIZE				1
+
+/* Bitfields in ICR */
+#define PM_LOCK0_OFFSET				0
+#define PM_LOCK0_SIZE				1
+#define PM_LOCK1_OFFSET				1
+#define PM_LOCK1_SIZE				1
+#define PM_WAKE_OFFSET				2
+#define PM_WAKE_SIZE				1
+#define PM_CKRDY_OFFSET				5
+#define PM_CKRDY_SIZE				1
+#define PM_MSKRDY_OFFSET			6
+#define PM_MSKRDY_SIZE				1
+
+/* Bitfields in GCCTRL0 */
+#define PM_OSCSEL_OFFSET			0
+#define PM_OSCSEL_SIZE				1
+#define PM_PLLSEL_OFFSET			1
+#define PM_PLLSEL_SIZE				1
+#define PM_CEN_OFFSET				2
+#define PM_CEN_SIZE				1
+#define PM_DIVEN_OFFSET				4
+#define PM_DIVEN_SIZE				1
+#define PM_DIV_OFFSET				8
+#define PM_DIV_SIZE				8
+
+/* Bitfields in RCAUSE */
+#define PM_POR_OFFSET				0
+#define PM_POR_SIZE				1
+#define PM_EXT_OFFSET				2
+#define PM_EXT_SIZE				1
+#define PM_WDT_OFFSET				3
+#define PM_WDT_SIZE				1
+#define PM_NTAE_OFFSET				4
+#define PM_NTAE_SIZE				1
+
+/* Bit manipulation macros */
+#define PM_BIT(name)					\
+	(1 << PM_##name##_OFFSET)
+#define PM_BF(name,value)				\
+	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
+	 << PM_##name##_OFFSET)
+#define PM_BFEXT(name,value)				\
+	(((value) >> PM_##name##_OFFSET)		\
+	 & ((1 << PM_##name##_SIZE) - 1))
+#define PM_BFINS(name,value,old)\
+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
+		    << PM_##name##_OFFSET))		\
+	 | PM_BF(name,value))
+
+/* Register access macros */
+#define pm_readl(reg)							\
+	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
+#define pm_writel(reg,value)						\
+	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
+
+#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v3.h linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v3.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v3.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v3.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PM_V3_H__
+#define __PM_V3_H__
+
+#include <mach/chip.h>
+
+/* PM Register offsets */
+#ifndef __ASSEMBLY__
+struct pm_regs {
+	u32	MCCTRL;			/* Main Clock Control */
+	u32	CKSEL;			/* Clock Select */
+	u32	CPUMASK;		/* CPU Clock Mask */
+	u32	HSBMASK;		/* HSB Clock Mask */
+	u32	PBAMASK;		/* PBA Clock Mask */
+	u32	PBBMASK;		/* PBB Clock Mask */
+	u32	PBADIVMASK;		/* Divided PBA Clock Mask */
+	u32	PBBDIVMASK;		/* Divided PBB Clock Mask */
+	u32	__reserved1[8];
+	u32	PLL[3];			/* PLL Control */
+	u32	__reserved2[13];
+	u32	OSCCTRL[3];		/* Oscillator Control */
+	u32	__reserved3[5];
+	u32	OSCCTRL32;		/* 32 kHz Oscillator Control */
+	u32	__reserved4[7];
+	u32	IER;			/* Interrupt Enable */
+	u32	IDR;			/* Interrupt Disable */
+	u32	IMR;			/* Interrupt Mask */
+	u32	ISR;			/* Interrupt Status */
+	u32	ICR;			/* Interrupt Clear */
+	u32	POSCSR;			/* Power and Oscillator Status */
+	u32	__reserved5[10];
+	u32	GCCTRL[8];		/* Generic Clock Control */
+	u32	__reserved6[8];
+	u32	RCCR;			/* RC Oscillator Calibration */
+	u32	BGCR;			/* Bandgap Calibration */
+	u32	VREGCR;			/* Buck Regulator Calibration */
+	u32	BOD;			/* BOD Level */
+	u32	PPCR;			/* Peripheral Power Control */
+	u32	__reserved7[11];
+	u32	RCAUSE;			/* Reset Cause */
+	u32	WCAUSE;			/* Wake Cause */
+	u32	AWEN;			/* Asynchronous Wake Enable */
+	u32	__reserved8[14];
+	u32	GPLP;			/* General Purpose Low-Power */
+};
+#endif
+
+/* Assembly-friendly register offsets; same as above */
+#define PM_MCCTRL			0x0000
+#define PM_CKSEL			0x0004
+#define PM_CPUMASK			0x0008
+#define PM_HSBMASK			0x000c
+#define PM_PBAMASK			0x0010
+#define PM_PBBMASK			0x0014
+#define PM_PBADIVMASK			0x0018
+#define PM_PBBDIVMASK			0x001c
+#define PM_PLL0				0x0040
+#define PM_PLL1				0x0044
+#define PM_PLL2				0x0048
+#define PM_OSCCTRL0			0x0080
+#define PM_OSCCTRL1			0x0084
+#define PM_OSCCTRL2			0x0088
+#define PM_OSCCTRL32			0x00a0
+#define PM_IER				0x00c0
+#define PM_IDR				0x00c4
+#define PM_IMR				0x00c8
+#define PM_ISR				0x00cc
+#define PM_ICR				0x00d0
+#define PM_POSCSR			0x00d4
+#define PM_GCCTRL			0x0100
+#define PM_RCCR				0x0140
+#define PM_BGCR				0x0144
+#define PM_VREGCR			0x0148
+#define PM_BOD				0x014c
+#define PM_PPCR				0x0150
+#define PM_RC_RCAUSE			0x0180
+#define PM_WCAUSE			0x0184
+#define PM_AWEN				0x0188
+#define PM_GPLP				0x01c0
+
+/* Bits in MCCTRL */
+#define PM_MCCTRL_MCSEL_START		0
+#define PM_MCCTRL_MCSEL_SIZE		2
+#define PM_MCCTRL_OSC0EN_BIT		2
+#define PM_MCCTRL_OSC1EN_BIT		3
+#define PM_MCCTRL_OSC2EN_BIT		4
+#define PM_MCCTRL_CRIPEL_BIT		24
+
+/* Bits in CKSEL */
+#define PM_CKSEL_CPUSEL_START		0
+#define PM_CKSEL_CPUSEL_SIZE		3
+#define PM_CKSEL_CPUDIV_BIT		7
+#define PM_CKSEL_HSBSEL_START		8
+#define PM_CKSEL_HSBSEL_SIZE		3
+#define PM_CKSEL_HSBDIV_BIT		15
+#define PM_CKSEL_PBASEL_START		16
+#define PM_CKSEL_PBASEL_SIZE		3
+#define PM_CKSEL_PBADIV_BIT		23
+#define PM_CKSEL_PBBSEL_START		24
+#define PM_CKSEL_PBBSEL_SIZE		3
+#define PM_CKSEL_PBBDIV_BIT		31
+
+/* Bits in CPUMASK */
+#define PM_CPUMASK_SYSTIMER_BIT		16
+
+/* Bits in PLLx */
+#define PM_PLLx_PLLEN_BIT		0
+#define PM_PLLx_PLLOSC_START		1
+#define PM_PLLx_PLLOSC_SIZE		2
+#define PM_PLLx_PLLOPT_START		3
+#define PM_PLLx_PLLOPT_SIZE		3
+#define PM_PLLx_PLLBPL_BIT		7
+#define PM_PLLx_PLLDIV_START		8
+#define PM_PLLx_PLLDIV_SIZE		6
+#define PM_PLLx_PLLMUL_START		16
+#define PM_PLLx_PLLMUL_SIZE		6
+#define PM_PLLx_PLLCOUNT_START		24
+#define PM_PLLx_PLLCOUNT_SIZE		6
+#define PM_PLLx_PLLIOTESTEN_BIT		30
+#define PM_PLLx_PLLTEST_BIT		31
+
+/* Bits in OSCCTRLx */
+#define PM_OSCCTRLx_MODE_START		0
+#define PM_OSCCTRLx_MODE_SIZE		4
+#define PM_OSCCTRLx_STARTUP_START	8
+#define PM_OSCCTRLx_STARTUP_SIZE	3
+
+/* Bits in OSCCTRL32 */
+#define PM_OSCCTRL32_OSC32EN_BIT	0
+#define PM_OSCCTRL32_MODE_START		8
+#define PM_OSCCTRL32_MODE_SIZE		3
+#define PM_OSCCTRL32_STARTUP_START	16
+#define PM_OSCCTRL32_STARTUP_SIZE	3
+
+/* Bits in IER/IDR/IMR/ISR/ICR */
+#define PM_ISR_OSC0RDY_BIT		0
+#define PM_ISR_OSC1RDY_BIT		1
+#define PM_ISR_OSC2RDY_BIT		2
+#define PM_ISR_OSC32RDY_BIT		7
+#define PM_ISR_LOCK0_BIT		8
+#define PM_ISR_LOCK1_BIT		9
+#define PM_ISR_LOCK2_BIT		10
+#define PM_ISR_LOCK0LOST_BIT		16
+#define PM_ISR_LOCK1LOST_BIT		17
+#define PM_ISR_LOCK2LOST_BIT		18
+#define PM_ISR_CKRDY_BIT		24
+#define PM_ISR_MSKRDY_BIT		25
+#define PM_ISR_WAKE_BIT			26
+#define PM_ISR_BODDET_BIT		27
+#define PM_ISR_PERRDY_BIT		28
+
+/* Bits in POSCSR */
+#define PM_POSCSR_OSC0RDY_BIT		0
+#define PM_POSCSR_OSC1RDY_BIT		1
+#define PM_POSCSR_OSC32RDY_BIT		7
+#define PM_POSCSR_LOCK0_BIT		8
+#define PM_POSCSR_LOCK1_BIT		9
+#define PM_POSCSR_LOCK0LOST_BIT		16
+#define PM_POSCSR_LOCK1LOST_BIT		17
+#define PM_POSCSR_CKRDY_BIT		24
+#define PM_POSCSR_MSKRDY_BIT		25
+#define PM_POSCSR_WAKE_BIT		26
+#define PM_POSCSR_BODDET_BIT		27
+#define PM_POSCSR_PERRDY_BIT		28
+
+/* Bits in GCCTRL */
+#define PM_GCCTRL_CEN_BIT		0
+#define PM_GCCTRL_DIVEN_BIT		1
+#define PM_GCCTRL_OSCSEL_START		8
+#define PM_GCCTRL_OSCSEL_SIZE		4
+#define PM_GCCTRL_DIV_START		16
+#define PM_GCCTRL_DIV_SIZE		8
+
+/* Bits in RCCR */
+#define PM_RCCR_CALIB_START		0
+#define PM_RCCR_CALIB_SIZE		10
+#define PM_RCCR_FCD_BIT			16
+#define PM_RCCR_KEY_START		24
+#define PM_RCCR_KEY_SIZE		8
+
+/* Bits in BGCR */
+#define PM_BGCR_CALIB_START		0
+#define PM_BGCR_CALIB_SIZE		3
+#define PM_BGCR_FCD_BIT			16
+#define PM_BGCR_KEY_START		24
+#define PM_BGCR_KEY_SIZE		8
+
+/* Bits in VREGCR */
+#define PM_VREGCR_CALIB_START		0
+#define PM_VREGCR_CALIB_SIZE		3
+#define PM_VREGCR_FCD_BIT		16
+#define PM_VREGCR_KEY_START		24
+#define PM_VREGCR_KEY_SIZE		8
+
+/* Bits in BOD */
+#define PM_BOD_LEVEL_START		0
+#define PM_BOD_LEVEL_SIZE		6
+#define PM_BOD_HYST_BIT			6
+#define PM_BOD_CTRL_START		8
+#define PM_BOD_CTRL_SIZE		2
+#define PM_BOD_FCD_BIT			16
+#define PM_BOD_KEY_START		24
+#define PM_BOD_KEY_SIZE			8
+
+/* Bits in PPCR */
+#define PM_PPCR_EBI_VOLT_BIT		0
+#define PM_PPCR_UTMI_CTRL_BIT		1
+#define PM_PPCR_KEY_START		24
+#define PM_PPCR_KEY_SIZE		8
+
+/* Bits in RC_RCAUSE */
+#define PM_RC_RCAUSE_POR_BIT		0
+#define PM_RC_RCAUSE_BOD_BIT		1
+#define PM_RC_RCAUSE_EXT_BIT		2
+#define PM_RC_RCAUSE_WDT_BIT		3
+#define PM_RC_RCAUSE_JTAG_BIT		4
+#define PM_RC_RCAUSE_NTAE_BIT		5
+#define PM_RC_RCAUSE_SLEEP_BIT		6
+#define PM_RC_RCAUSE_CPUERR_BIT		7
+#define PM_RC_RCAUSE_OCDRST_BIT		8
+#define PM_RC_RCAUSE_JTAGHARD_BIT	9
+
+/* Bits in WCAUSE */
+#define PM_WCAUSE_PERIPH0_BIT		0
+#define PM_WCAUSE_PERIPH1_BIT		1
+#define PM_WCAUSE_EIC_BIT		16
+#define PM_WCAUSE_RTC_BIT		17
+
+/* Constants for MCCTRL:MCSEL */
+#define PM_MCSEL_SLOW			0
+#define PM_MCSEL_OSC0			1
+#define PM_MCSEL_PLL0			2
+
+/* Constants for OSCCTRLx:MODE */
+#define PM_MODE_EXT_CLOCK		0
+#define PM_MODE_CRYSTAL_ACG		1
+#define PM_MODE_CRYSTAL_G0		4
+#define PM_MODE_CRYSTAL_G1		5
+#define PM_MODE_CRYSTAL_G2		6
+#define PM_MODE_CRYSTAL_G3		7
+
+/* Constants for GCCTRL:OSCSEL */
+#define PM_OSCSEL_SLOW			0
+#define PM_OSCSEL_CLK32			1
+#define PM_OSCSEL_OSC0			2
+#define PM_OSCSEL_OSC1			3
+#define PM_OSCSEL_PLL0			4
+#define PM_OSCSEL_PLL1			5
+
+/* Constants for BOD:CTRL */
+#define PM_CTRL_OFF1			0
+#define PM_CTRL_ENABLED			1
+#define PM_CTRL_ENABLED_NORESET		2
+#define PM_CTRL_OFF2			3
+
+/* Bit manipulation macros */
+#define PM_BIT(name)						\
+	(1 << PM_##name##_BIT)
+#define PM_BF(name,value)					\
+	(((value) & ((1 << PM_##name##_SIZE) - 1))		\
+	 << PM_##name##_START)
+#define PM_BFEXT(name,value)					\
+	(((value) >> PM_##name##_START)				\
+	 & ((1 << PM_##name##_SIZE) - 1))
+#define PM_BFINS(name,value,old)				\
+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)		\
+		    << PM_##name##_START))			\
+	 | PM_BF(name,value))
+
+/* Register access macros */
+#define __pm_regs ((struct pm_regs __iomem __force *)PM_BASE)
+#define pm_readl(reg)						\
+	__raw_readl(&__pm_regs->reg)
+#define pm_writel(reg, value)					\
+	__raw_writel(value, &__pm_regs->reg)
+
+#endif /* __PM_V3_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/sdc.h linux-2.6.28.2/arch/avr32/mach-at32ap/sdc.h
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/sdc.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/sdc.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,103 @@
+/* SDC */
+
+/* Register offsets */
+#define SDC_CTRL			0x0000
+#define SDC_ASYNC			0x0004
+#define SDC_SYNC			0x0008
+#define SDC_FILTERDUR			0x000c
+#define SDC_OSCCTRL32			0x0010
+#define SDC_STATUS			0x0014
+#define SDC_ECR				0x0018
+#define SDC_IER				0x001c
+#define SDC_IDR				0x0020
+#define SDC_IMR				0x0024
+#define SDC_GPLP			0x0040
+
+/* Bits in CTRL */
+#define SDC_CTRL_PIN_EN_BIT		0
+#define SDC_CTRL_AST_EN_BIT		8
+#define SDC_CTRL_WDT_EN_BIT		9
+#define SDC_CTRL_OCD_EN_BIT		10
+#define SDC_CTRL_JTAG_EN_BIT		11
+#define SDC_CTRL_CORE_POR_TEST_BIT	23
+#define SDC_CTRL_KEY_START		24
+#define SDC_CTRL_KEY_SIZE		8
+
+/* Bits in ASYNC */
+#define SDC_ASYNC_MODE_BIT		4
+#define SDC_ASYNC_POL_BIT		8
+#define SDC_ASYNC_KEY_START		24
+#define SDC_ASYNC_KEY_SIZE		8
+
+/* Bits in SYNC */
+#define SDC_SYNC_EN_BIT			0
+#define SDC_SYNC_MODE_BIT		4
+#define SDC_SYNC_POL_BIT		8
+#define SDC_SYNC_FILTER_BIT		12
+#define SDC_SYNC_KEY_START		24
+#define SDC_SYNC_KEY_SIZE		8
+
+/* Bits in FILTERDUR */
+#define SDC_FILTERDUR_Duration_START	0
+#define SDC_FILTERDUR_Duration_SIZE	16
+#define SDC_FILTERDUR_KEY_START		24
+#define SDC_FILTERDUR_KEY_SIZE		8
+
+/* Bits in OSCCTRL32 */
+#define SDC_OSCCTRL32_OSC32EN_BIT	0
+#define SDC_OSCCTRL32_MODE_START	8
+#define SDC_OSCCTRL32_MODE_SIZE		4
+#define SDC_OSCCTRL32_STARTUP_START	16
+#define SDC_OSCCTRL32_STARTUP_SIZE	3
+#define SDC_OSCCTRL32_KEY_START		24
+#define SDC_OSCCTRL32_KEY_SIZE		8
+
+/* Bits in STATUS */
+#define SDC_STATUS_PIN_EVENT_BIT	0
+#define SDC_STATUS_AST_EVENT_BIT	8
+#define SDC_STATUS_WDT_EVENT_BIT	9
+#define SDC_STATUS_OCD_EVENT_BIT	10
+#define SDC_STATUS_JTAG_EVENT_BIT	11
+#define SDC_STATUS_PIN_BIT		16
+#define SDC_STATUS_BUSY_BIT		24
+#define SDC_STATUS_SWTCH_BIT		30
+#define SDC_STATUS_VBAT_BIT		31
+
+/* Bits in ECR */
+#define SDC_ECR_PIN_EVENT_BIT		0
+#define SDC_ECR_AST_EVENT_BIT		8
+#define SDC_ECR_WDT_EVENT_BIT		9
+#define SDC_ECR_OCD_EVENT_BIT		10
+#define SDC_ECR_JTAG_EVENT_BIT		11
+
+/* Bits in IER */
+#define SDC_IER_PIN_EVENT_BIT		0
+#define SDC_IER_READY_BIT		24
+
+/* Bits in IDR */
+#define SDC_IDR_PIN_EVENT_BIT		0
+#define SDC_IDR_READY_BIT		24
+
+/* Bits in IMR */
+#define SDC_IMR_PIN_EVENT_BIT		0
+#define SDC_IMR_READY_BIT		24
+
+/* Bit manipulation macros */
+#define SDC_BIT(name)						\
+	(1 << SDC_##name##_BIT)
+#define SDC_BF(name,value)					\
+	(((value) & ((1 << SDC_##name##_SIZE) - 1))		\
+	 << SDC_##name##_START)
+#define SDC_BFEXT(name,value)					\
+	(((value) >> SDC_##name##_START)			\
+	 & ((1 << SDC_##name##_SIZE) - 1))
+#define SDC_BFINS(name,value,old)				\
+	(((old) & ~(((1 << SDC_##name##_SIZE) - 1)		\
+		    << SDC_##name##_START))			\
+	 | SDC_BF(name,value))
+
+/* Register access macros */
+#define sdc_readl(reg)						\
+	__raw_readl((void __iomem __force *)(SDC_BASE + SDC_##reg))
+#define sdc_writel(reg, value)					\
+	__raw_writel(value, (void __iomem __force *)(SDC_BASE + SDC_##reg))
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/timer-ast.c linux-2.6.28.2/arch/avr32/mach-at32ap/timer-ast.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/timer-ast.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/timer-ast.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,191 @@
+/*
+ * Asynchronous Timer (AST) used as clocksource / clockevent
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <asm/ast_regs.h>
+
+static void __iomem *ast_regs;
+
+static inline void ast_wait_ready(void)
+{
+	while (ast_readl(ast_regs, SR) & AST_BIT(BUSY))
+		cpu_relax();
+}
+
+static cycle_t read_ast_counter(void)
+{
+	return ast_readl(ast_regs, CV);
+}
+
+static struct clocksource ast_clksrc = {
+	.name	= "ast",
+	.rating	= 400,
+	.read	= read_ast_counter,
+	.mask	= CLOCKSOURCE_MASK(32),
+	.shift	= 16,
+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static irqreturn_t ast_clkevt_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *clkevt = dev_id;
+
+	/*
+	 * We make sure delta is always long enough so that the BUSY
+	 * bit is never set at this point.
+	 */
+	ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
+	clkevt->event_handler(clkevt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction ast_clkevt_irqaction = {
+	.handler	= ast_clkevt_interrupt,
+	.flags		= IRQF_TIMER | IRQF_DISABLED,
+	.name		= "timer-ast",
+};
+
+static int ast_next_event(unsigned long delta,
+		struct clock_event_device *clkevt)
+{
+	ast_wait_ready();
+	ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) + delta);
+
+	return 0;
+}
+
+static void ast_mode(enum clock_event_mode mode,
+		struct clock_event_device *evdev)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_ONESHOT:
+	case CLOCK_EVT_MODE_RESUME:
+		/* Make sure we don't trigger an alarm before we get
+		 * around to reprogramming it.
+		 */
+		ast_wait_ready();
+		ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) - 1);
+		ast_wait_ready();
+		ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
+		ast_wait_ready();
+		ast_writel(ast_regs, IER, AST_BIT(ALARM0));
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		ast_writel(ast_regs, IDR, AST_BIT(ALARM0));
+		break;
+	default:
+		BUG();
+	}
+}
+
+static struct clock_event_device ast_clkevt = {
+	.name		= "ast",
+	.features	= CLOCK_EVT_FEAT_ONESHOT,
+	.shift		= 16,
+	.rating		= 400,
+	.cpumask	= CPU_MASK_CPU0,
+	.set_next_event	= ast_next_event,
+	.set_mode	= ast_mode,
+};
+
+void __init ast_time_init(struct platform_device *pdev, unsigned int clksel)
+{
+	struct clk *clk, *pclk;
+	struct resource *regs;
+	unsigned long ast_hz;
+	int irq;
+	int ret;
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		pr_debug("AST: No MMIO resource\n");
+		return;
+	}
+
+	pclk = clk_get(&pdev->dev, "pclk");
+	if (!pclk) {
+		pr_debug("AST: No peripheral clock (pclk)\n");
+		return;
+	}
+	clk_enable(pclk);
+
+	/* Too early for ioremap() */
+	ast_regs = (void __iomem __force *)regs->start;
+
+	switch (clksel) {
+	case AST_CLOCK_SLOW:
+		clk = clk_get(NULL, "rcosc");
+		break;
+	case AST_CLOCK_OSC32:
+		clk = clk_get(NULL, "osc32");
+		break;
+	case AST_CLOCK_PB:
+		clk = pclk;
+		break;
+	case AST_CLOCK_GC:
+		clk = clk_get(&pdev->dev, "gclk");
+		break;
+	default:
+		clk = NULL;
+		break;
+	}
+
+	if (!clk) {
+		pr_debug("AST: clock %u invalid, using pb clock\n", clksel);
+		clk = pclk;
+	}
+	clk_enable(clk);
+
+	ast_writel(ast_regs, CLOCK,
+			AST_BF(CLOCK_CSSEL, clksel) | AST_BIT(CLOCK_CEN));
+	ast_writel(ast_regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR));
+
+	/* Using hardcoded divide-by-two prescaler */
+	ast_hz = clk_get_rate(clk) / 2;
+	ast_clksrc.mult = clocksource_hz2mult(ast_hz, ast_clksrc.shift);
+
+	ret = clocksource_register(&ast_clksrc);
+	if (ret)
+		pr_debug("AST: could not register clocksource: %d\n", ret);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		pr_debug("AST: No IRQ resource, won't setup clockevent\n");
+		return;
+	}
+
+	ast_clkevt.mult = div_sc(ast_hz, NSEC_PER_SEC, ast_clkevt.shift);
+	ast_clkevt.max_delta_ns = clockevent_delta2ns((u32)~0U, &ast_clkevt);
+	ast_clkevt.min_delta_ns = clockevent_delta2ns(2, &ast_clkevt) + 100;
+
+	ast_clkevt_irqaction.dev_id = &ast_clkevt;
+
+	ret = setup_irq(irq, &ast_clkevt_irqaction);
+	if (ret) {
+		pr_debug("AST: Could not request IRQ %d: %d\n", irq, ret);
+		return;
+	}
+
+	clockevents_register_device(&ast_clkevt);
+
+	pr_info("Using Asynchronous Timer %d @ %lu.%03lu Mhz"
+			" (regs 0x%p, irq %d)\n",
+			pdev->id, ((ast_hz + 500) / 1000) / 1000,
+			((ast_hz + 500) / 1000) % 1000, ast_regs, irq);
+}
diff -urN linux-2.6.28.2-0rig//arch/avr32/mm/tlb.c linux-2.6.28.2/arch/avr32/mm/tlb.c
--- linux-2.6.28.2-0rig//arch/avr32/mm/tlb.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mm/tlb.c	2009-01-29 08:52:50.000000000 +0100
@@ -12,7 +12,13 @@
 #include <asm/mmu_context.h>
 
 /* TODO: Get the correct number from the CONFIG1 system register */
-#define NR_TLB_ENTRIES 32
+#if defined(CONFIG_CPU_AT32AP700X)
+# define NR_TLB_ENTRIES 32
+#elif defined(CONFIG_CPU_AT32AP720X)
+# define NR_TLB_ENTRIES 64
+#else
+# error Unknown CPU type
+#endif
 
 static void show_dtlb_entry(unsigned int index)
 {
@@ -85,9 +91,15 @@
 		u32 tlbar = sysreg_read(TLBARLO);
 
 		rp = 32 - fls(tlbar);
-		if (rp == 32) {
+		if (NR_TLB_ENTRIES > 32 && rp >= 32) {
+			tlbar = sysreg_read(TLBARHI);
+			rp = 64 - fls(tlbar);
+		}
+		if (rp >= NR_TLB_ENTRIES) {
 			rp = 0;
 			sysreg_write(TLBARLO, -1L);
+			if (NR_TLB_ENTRIES > 32)
+				sysreg_write(TLBARHI, -1L);
 		}
 
 		mmucr = SYSREG_BFINS(DRP, rp, mmucr);
@@ -131,16 +143,22 @@
 
 	if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
 		unsigned int entry;
-		u32 tlbarlo;
+		u32 tlbarlo, tlbarhi;
 
 		/* Clear the "valid" bit */
 		sysreg_write(TLBEHI, tlbehi);
 
 		/* mark the entry as "not accessed" */
 		entry = SYSREG_BFEXT(DRP, mmucr);
-		tlbarlo = sysreg_read(TLBARLO);
-		tlbarlo |= (0x80000000UL >> entry);
-		sysreg_write(TLBARLO, tlbarlo);
+		if (NR_TLB_ENTRIES > 32 && entry > 32) {
+			tlbarhi = sysreg_read(TLBARHI);
+			tlbarhi |= (0x80000000UL >> (entry - 32));
+			sysreg_write(TLBARHI, tlbarhi);
+		} else {
+			tlbarlo = sysreg_read(TLBARLO);
+			tlbarlo |= (0x80000000UL >> entry);
+			sysreg_write(TLBARLO, tlbarlo);
+		}
 
 		/* update the entry with valid bit clear */
 		__builtin_tlbw();
@@ -179,9 +197,10 @@
 		unsigned long flags;
 		int size;
 
-		local_irq_save(flags);
 		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 
+		local_irq_save(flags);
+
 		if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
 			mm->context = NO_CONTEXT;
 			if (mm == current->mm)
diff -urN linux-2.6.28.2-0rig//drivers/dma/atmel_pdca.c linux-2.6.28.2/drivers/dma/atmel_pdca.c
--- linux-2.6.28.2-0rig//drivers/dma/atmel_pdca.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/drivers/dma/atmel_pdca.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,668 @@
+/*
+ * Driver for the Atmel PDCA Peripheral DMA Controller
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define DEBUG
+#include <linux/atmel_pdca.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+#include <linux/spinlock.h>
+
+/*
+ * Since each descriptor can hold a whole scatterlist, we don't need
+ * many of them.
+ */
+#define NR_DESCS_PER_CHANNEL	8
+
+static struct pdca_desc *pdca_desc_entry(struct list_head *node)
+{
+	return list_entry(node, struct pdca_desc, desc_node);
+}
+
+static struct pdca_desc *pdca_next_desc(struct pdca_chan *pch,
+		struct pdca_desc *desc)
+{
+	if (desc->desc_node.next != &pch->queue)
+		return pdca_desc_entry(desc->desc_node.next);
+	return NULL;
+}
+
+static struct pdca_desc *pdca_desc_get(struct pdca_chan *pch)
+{
+	struct pdca_desc		*desc = NULL;
+
+	spin_lock_bh(&pch->lock);
+	if (likely(!list_empty(&pch->freelist))) {
+		desc = pdca_desc_entry(pch->freelist.next);
+		list_del(&desc->desc_node);
+	}
+	spin_unlock_bh(&pch->lock);
+
+	return desc;
+}
+
+static dma_cookie_t pdca_assign_cookie(struct pdca_chan *pch,
+		struct pdca_desc *desc)
+{
+	dma_cookie_t cookie = pch->chan.cookie;
+
+	if (++cookie < 0)
+		cookie = 1;
+
+	pch->chan.cookie = cookie;
+	desc->txd.cookie = cookie;
+
+	return cookie;
+}
+
+static void pdca_desc_done(struct pdca_chan *pch, struct pdca_desc *desc)
+{
+	struct dma_async_tx_descriptor	*txd = &desc->txd;
+	dma_async_tx_callback		callback;
+	void				*param;
+
+	pch->completed = txd->cookie;
+	callback = txd->callback;
+	param = txd->callback_param;
+
+	dev_vdbg(&pch->chan.dev, "  completed %u\n", txd->cookie);
+
+	/*
+	 * We can only handle scatterlists, so this is easy. No other
+	 * drivers do the right thing with scatterlists though...
+	 *
+	 * Note that we ensure that at least one of these flags are
+	 * set when the descriptor is prepared, as we never need to
+	 * unmap the peripheral side.
+	 */
+	if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP))
+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
+				DMA_FROM_DEVICE);
+	if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
+				DMA_TO_DEVICE);
+
+	list_move(&desc->desc_node, &pch->freelist);
+
+	if (callback)
+		callback(param);
+}
+
+static void pdca_chan_tasklet(unsigned long param)
+{
+	struct pdca_chan		*pch = (struct pdca_chan *)param;
+	void __iomem			*regs = pch->regs;
+	struct pdca_desc		*cur;
+	struct pdca_desc		*next;
+	struct scatterlist		*cur_sg;
+	struct scatterlist		*next_sg;
+	u32				intflags;
+	u32				status;
+
+	spin_lock(&pch->lock);
+
+	cur = pdca_desc_entry(pch->queue.next);
+	next = pdca_next_desc(pch, cur);
+
+	cur_sg = pch->cur_sg;
+	next_sg = pch->next_sg;
+
+	intflags = PDCA_TERR | PDCA_TRC | PDCA_RCZ;
+
+	status = pdca_readl(regs, ISR);
+	dev_vdbg(&pch->chan.dev, "tasklet: status=%08x\n", status);
+
+	if (status & PDCA_TRC) {
+		if (cur_sg) {
+			if (sg_is_last(cur_sg)) {
+				dev_vdbg(&pch->chan.dev,
+						"  cur sg was last in %u\n",
+						cur->txd.cookie);
+				pdca_desc_done(pch, cur);
+				cur = next;
+				next = NULL;
+			}
+			if (next_sg && sg_is_last(next_sg)) {
+				dev_vdbg(&pch->chan.dev,
+						"  next sg was last in %u\n",
+						cur->txd.cookie);
+				pdca_desc_done(pch, cur);
+				cur = next;
+				next = NULL;
+			}
+			if (!cur) {
+				dev_vdbg(&pch->chan.dev, "  all done\n");
+				pdca_writel(regs, CR, PDCA_CR_TDIS);
+				cur_sg = next_sg = NULL;
+				intflags = 0;
+				goto done;
+			}
+			cur_sg = next_sg ? sg_next(next_sg) : NULL;
+		}
+
+		if (!cur_sg) {
+			dev_vdbg(&pch->chan.dev, "  load sg from %u\n",
+					cur->txd.cookie);
+			cur_sg = cur->sg;
+			pdca_writel(regs, PSR, cur->periph_id);
+			pdca_writel(regs, MR, cur->reg_width);
+		}
+		dev_vdbg(&pch->chan.dev, "  START: %08x count: %08x\n",
+				sg_dma_address(cur_sg),
+				sg_dma_len(cur_sg) >> cur->reg_width);
+		pdca_writel(regs, MAR, sg_dma_address(cur_sg));
+		pdca_writel(regs, TCR, sg_dma_len(cur_sg) >> cur->reg_width);
+
+		next_sg = sg_next(cur_sg);
+		if (!next_sg) {
+			next = pdca_next_desc(pch, cur);
+			if (next && next->reg_width == cur->reg_width
+					&& next->periph_id == cur->periph_id) {
+				dev_vdbg(&pch->chan.dev,
+						"loading next_sg from %u\n",
+						next->txd.cookie);
+				next_sg = next->sg;
+			}
+		}
+		if (next_sg) {
+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
+					sg_dma_address(next_sg),
+					sg_dma_len(next_sg) >> cur->reg_width);
+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
+			pdca_writel(regs, TCRR,
+					sg_dma_len(next_sg) >> cur->reg_width);
+		} else {
+			intflags &= ~PDCA_RCZ;
+		}
+	} else if (next_sg && (status & PDCA_RCZ)) {
+		if (sg_is_last(cur_sg)) {
+			dev_vdbg(&pch->chan.dev, "  cur sg was last in %u\n",
+					cur->txd.cookie);
+			next = pdca_next_desc(pch, cur);
+			pdca_desc_done(pch, cur);
+			cur = next;
+			next = NULL;
+		}
+
+		cur_sg = next_sg;
+		next_sg = sg_next(cur_sg);
+		if (!next_sg) {
+			next = pdca_next_desc(pch, cur);
+			if (next && next->reg_width == cur->reg_width
+					&& next->periph_id == cur->periph_id)
+				next_sg = next->sg;
+		}
+
+		if (next_sg) {
+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
+					sg_dma_address(next_sg),
+					sg_dma_len(next_sg) >> cur->reg_width);
+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
+			pdca_writel(regs, TCRR,
+					sg_dma_len(next_sg) >> cur->reg_width);
+		} else {
+			dev_vdbg(&pch->chan.dev, "  no next sg\n");
+			intflags &= ~PDCA_RCZ;
+		}
+	}
+
+done:
+	if (status & PDCA_TERR) {
+		/*
+		 * Head of queue is busted. We must remove it, clear
+		 * the error and restart the queue.
+		 */
+		pdca_writel(regs, TCRR, 0);
+		pdca_writel(regs, TCR, 0);
+		pdca_writel(regs, CR, PDCA_CR_ECLR);
+		cur_sg = next_sg = NULL;
+
+		if (!cur)
+			dev_err(&pch->chan.dev,
+					"Transfer Error with empty queue\n");
+		else {
+			dev_vdbg(&pch->chan.dev,
+					"  %u is busted\n", cur->txd.cookie);
+			pdca_desc_done(pch, cur);
+		}
+
+		if (list_empty(&pch->queue)) {
+			pdca_writel(regs, CR, PDCA_CR_TDIS);
+			intflags = 0;
+		}
+	}
+
+	pch->cur_sg = cur_sg;
+	pch->next_sg = next_sg;
+
+	dev_vdbg(&pch->chan.dev, "  enabling interrupts: %08x\n", intflags);
+	pdca_writel(regs, IER, intflags);
+	pdca_readl(regs, SR);
+
+	spin_unlock(&pch->lock);
+}
+
+static irqreturn_t pdca_interrupt(int irq, void *dev_id)
+{
+	struct pdca_dev			*pdca = dev_id;
+	struct pdca_chan		*pch;
+	void __iomem			*regs;
+	unsigned long			pending;
+	unsigned int			chan;
+
+	pending = intc_get_pending(irq);
+	if (unlikely(!pending))
+		return IRQ_NONE;
+
+	do {
+		chan = __ffs(pending);
+		pch = &pdca->chan[chan];
+		regs = pch->regs;
+		pdca_writel(regs, IDR, ~0UL);
+		tasklet_schedule(&pch->tasklet);
+		pdca_readl(regs, IMR);
+		pending &= ~(1 << chan);
+	} while (pending);
+
+	return IRQ_HANDLED;
+}
+
+static dma_cookie_t pdca_tx_submit(struct dma_async_tx_descriptor *txd)
+{
+	struct pdca_desc		*desc = txd_to_pdca_desc(txd);
+	struct pdca_chan		*pch = dma_to_pdca_chan(txd->chan);
+	void __iomem			*regs = pch->regs;
+	dma_cookie_t			cookie;
+
+	spin_lock_bh(&pch->lock);
+	cookie = pdca_assign_cookie(pch, desc);
+	dev_vdbg(&pch->chan.dev, "submitted %u\n", cookie);
+	list_add_tail(&desc->desc_node, &pch->queue);
+	pdca_writel(regs, CR, PDCA_CR_TEN);
+	pdca_writel(regs, IER, PDCA_TERR | PDCA_RCZ);
+	/* The tasklet will kickstart the queue if necessary */
+	spin_unlock_bh(&pch->lock);
+
+	return cookie;
+}
+
+static struct dma_async_tx_descriptor *pdca_prep_slave_sg(struct dma_chan *chan,
+		struct scatterlist *sgl, unsigned int sg_len,
+		enum dma_data_direction direction, unsigned long flags)
+{
+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
+	struct pdca_slave		*pslave = pch->pslave;
+	struct pdca_desc		*desc;
+	unsigned int			periph_id;
+
+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
+			sg_len, flags);
+
+	switch (direction) {
+	case DMA_TO_DEVICE:
+		periph_id = pslave->tx_periph_id;
+		flags |= DMA_COMPL_SKIP_DEST_UNMAP;
+		break;
+	case DMA_FROM_DEVICE:
+		periph_id = pslave->rx_periph_id;
+		flags |= DMA_COMPL_SKIP_SRC_UNMAP;
+		break;
+	default:
+		return NULL;
+	}
+
+	desc = pdca_desc_get(pch);
+	if (!desc) {
+		dev_err(&chan->dev,
+			"not enough descriptors available\n");
+		return NULL;
+	}
+	desc->sg = sgl;
+	desc->sg_len = sg_len;
+	desc->periph_id = periph_id;
+	desc->reg_width = pslave->slave.reg_width;
+	desc->txd.flags = flags;
+
+	return &desc->txd;
+}
+
+static void pdca_terminate_all(struct dma_chan *chan)
+{
+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
+	struct pdca_desc		*desc, *_desc;
+	void __iomem			*regs = pch->regs;
+
+	spin_lock_bh(&pch->lock);
+	pdca_writel(regs, CR, PDCA_CR_TDIS);
+	pdca_writel(regs, TCRR, 0);
+	pdca_writel(regs, TCR, 0);
+	while (pdca_readl(regs, SR) & PDCA_SR_TEN)
+		cpu_relax();
+
+	list_for_each_entry_safe(desc, _desc, &pch->queue, desc_node)
+		pdca_desc_done(pch, desc);
+	spin_unlock_bh(&pch->lock);
+}
+
+static enum dma_status pdca_is_tx_complete(struct dma_chan *chan,
+		dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
+{
+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
+	dma_cookie_t			last_used;
+	dma_cookie_t			last_complete;
+
+	last_complete = pch->completed;
+	last_used = chan->cookie;
+
+	if (done)
+		*done = last_complete;
+	if (used)
+		*used = last_used;
+
+	return dma_async_is_complete(cookie, last_complete, last_used);
+}
+
+static void pdca_issue_pending(struct dma_chan *chan)
+{
+	/* We always issue descriptors ASAP */
+}
+
+static int pdca_alloc_chan_resources(struct dma_chan *chan,
+		struct dma_client *client)
+{
+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
+	struct dma_slave		*slave = client->slave;
+	void __iomem			*regs = pch->regs;
+
+	/*
+	 * Channels doing slave DMA can only handle one client. This
+	 * controller can only do slave DMA.
+	 */
+	if (chan->client_count)
+		return -EBUSY;
+	if (!slave || !slave->dma_dev || slave->dma_dev != pdca->dma.dev)
+		return -EINVAL;
+
+	if (pdca_readl(regs, SR) & PDCA_SR_TEN)
+		dev_err(&chan->dev, "DMA channel not idle!\n");
+
+	/*
+	 * We may get called multiple times if a client rejects the
+	 * channel...
+	 */
+	if (!pch->enabled) {
+		pch->enabled = true;
+		clk_enable(pdca->pclk);
+		clk_enable(pdca->hclk);
+	}
+
+	pch->chan.cookie = pch->completed = 1;
+	pch->pslave = dma_to_pdca_slave(slave);
+
+	while (pch->descs_allocated < NR_DESCS_PER_CHANNEL) {
+		struct pdca_desc	*desc;
+
+		desc = kzalloc(sizeof(struct pdca_desc), GFP_KERNEL);
+		if (!desc) {
+			dev_info(&chan->dev, "only allocated %d descriptors\n",
+					pch->descs_allocated);
+			break;
+		}
+
+		dma_async_tx_descriptor_init(&desc->txd, chan);
+		desc->txd.tx_submit = pdca_tx_submit;
+		desc->txd.flags = DMA_CTRL_ACK;
+		INIT_LIST_HEAD(&desc->txd.tx_list);
+		list_add(&desc->desc_node, &pch->freelist);
+		pch->descs_allocated++;
+	}
+
+	return pch->descs_allocated ? 0 : -ENOMEM;
+}
+
+static void pdca_free_chan_resources(struct dma_chan *chan)
+{
+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
+	struct pdca_desc		*desc, *_desc;
+
+	WARN_ON(!list_empty(&pch->queue));
+	WARN_ON(pdca_readl(pch->regs, SR) & PDCA_SR_TEN);
+	WARN_ON(pdca_readl(pch->regs, IMR));
+
+	clk_disable(pdca->hclk);
+	clk_disable(pdca->pclk);
+	pch->enabled = false;
+
+	list_for_each_entry_safe(desc, _desc, &pch->freelist, desc_node) {
+		list_del(&desc->desc_node);
+		kfree(desc);
+	}
+
+	pch->descs_allocated = 0;
+}
+
+static void pdca_suspend_channel(struct pdca_dev *pdca, struct pdca_chan *pch)
+{
+	void __iomem			*regs = pch->regs;
+
+	/*
+	 * REVISIT this whole business.
+	 *
+	 * The plan is to ensure that the PDCA doesn't do any bus
+	 * transactions when we're suspended or shut down. Ideally,
+	 * the client should make sure that all transfers have already
+	 * been completed or terminated when we reach suspend_late(),
+	 * but just in case that didn't happen, we should just stop
+	 * the controller and turn it back on when resuming. Hopefully
+	 * it will simply continue where it left off.
+	 *
+	 * We _probably_ need to save some sort of state to make this
+	 * happen. Or we can just rely on interrupts being globally
+	 * disabled at least until we reach resume_early. But that
+	 * might not be the case for shutdown.
+	 */
+	tasklet_kill(&pch->tasklet);
+	spin_lock_bh(&pch->lock);
+	if (pdca_readl(regs, SR) & PDCA_SR_TEN) {
+		pdca_writel(regs, CR, PDCA_CR_TDIS);
+		while (pdca_readl(regs, SR) & PDCA_SR_TEN)
+			cpu_relax();
+
+		clk_disable(pdca->hclk);
+		clk_disable(pdca->pclk);
+	}
+	spin_unlock_bh(&pch->lock);
+}
+
+static void __init pdca_init_channel(struct pdca_dev *pdca, unsigned int i)
+{
+	struct pdca_chan		*pch = &pdca->chan[i];
+
+	pch->chan.device = &pdca->dma;
+	pch->chan.chan_id = i;
+	pch->regs = pdca->regs + i * PDCA_CHAN_SIZE;
+	tasklet_init(&pch->tasklet, pdca_chan_tasklet, (unsigned long)pch);
+	spin_lock_init(&pch->lock);
+	INIT_LIST_HEAD(&pch->freelist);
+	INIT_LIST_HEAD(&pch->queue);
+
+	list_add_tail(&pch->chan.device_node, &pdca->dma.channels);
+}
+
+static int __init pdca_probe(struct platform_device *pdev)
+{
+	struct pdca_pdata		*pdata;
+	struct resource			*mmio;
+	struct pdca_dev			*pdca;
+	size_t				mmio_len;
+	size_t				size;
+	unsigned int			i;
+	int				irq;
+	int				ret;
+
+	pdata = pdev->dev.platform_data;
+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+	if (!pdata || pdata->nr_channels > 32 || !mmio || !irq) {
+		dev_dbg(&pdev->dev, "invalid params from platform code\n");
+		return -EINVAL;
+	}
+
+	mmio_len = mmio->end - mmio->start + 1;
+	if (!request_mem_region(mmio->start, mmio_len, "atmel_pdca")) {
+		dev_dbg(&pdev->dev, "mmio resource busy\n");
+		return -EBUSY;
+	}
+
+	size = sizeof(struct pdca_dev);
+	size += pdata->nr_channels * sizeof(struct pdca_chan);
+	pdca = kzalloc(size, GFP_KERNEL);
+	if (!pdca) {
+		dev_dbg(&pdev->dev, "insufficient memory\n");
+		ret = -ENOMEM;
+		goto err_alloc_pdca;
+	}
+
+	pdca->hclk = clk_get(&pdev->dev, "hclk");
+	if (IS_ERR(pdca->hclk)) {
+		dev_dbg(&pdev->dev, "no HSB clock\n");
+		ret = PTR_ERR(pdca->hclk);
+		goto err_get_hclk;
+	}
+	pdca->pclk = clk_get(&pdev->dev, "pclk");
+	if (IS_ERR(pdca->pclk)) {
+		dev_dbg(&pdev->dev, "no PB clock\n");
+		ret = PTR_ERR(pdca->pclk);
+		goto err_get_pclk;
+	}
+
+	pdca->regs = ioremap(mmio->start, mmio_len);
+	if (!pdca->regs) {
+		dev_dbg(&pdev->dev, "ioremap failed\n");
+		ret = -ENOMEM;
+		goto err_ioremap;
+	}
+
+	INIT_LIST_HEAD(&pdca->dma.channels);
+	for (i = 0; i < pdata->nr_channels; i++, pdca->dma.chancnt++)
+		pdca_init_channel(pdca, i);
+
+	ret = request_irq(irq, pdca_interrupt, 0, pdev->dev.bus_id, pdca);
+	if (ret) {
+		dev_dbg(&pdev->dev, "request_irq failed\n");
+		goto err_irq;
+	}
+
+	dma_cap_set(DMA_SLAVE, pdca->dma.cap_mask);
+	pdca->dma.dev = &pdev->dev;
+	pdca->dma.device_alloc_chan_resources = pdca_alloc_chan_resources;
+	pdca->dma.device_free_chan_resources = pdca_free_chan_resources;
+	pdca->dma.device_prep_slave_sg = pdca_prep_slave_sg;
+	pdca->dma.device_terminate_all = pdca_terminate_all;
+	pdca->dma.device_is_tx_complete = pdca_is_tx_complete;
+	pdca->dma.device_issue_pending = pdca_issue_pending;
+
+	platform_set_drvdata(pdev, pdca);
+	dma_async_device_register(&pdca->dma);
+
+	dev_info(&pdev->dev, "Atmel PDCA at 0x%08lx (irq %d) %u channels\n",
+			(unsigned long)mmio->start, irq, pdca->dma.chancnt);
+
+	return 0;
+
+err_irq:
+	iounmap(pdca->regs);
+err_ioremap:
+	clk_put(pdca->pclk);
+err_get_pclk:
+	clk_put(pdca->hclk);
+err_get_hclk:
+	kfree(pdca);
+err_alloc_pdca:
+	release_resource(mmio);
+	return ret;
+}
+
+static int __exit pdca_remove(struct platform_device *pdev)
+{
+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
+	struct pdca_chan	*pch;
+	struct resource		*mmio;
+
+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
+		pdca_suspend_channel(pdca, pch);
+
+	dma_async_device_unregister(&pdca->dma);
+	free_irq(platform_get_irq(pdev, 0), pdca);
+	clk_put(pdca->pclk);
+	clk_put(pdca->hclk);
+	iounmap(pdca->regs);
+	kfree(pdca);
+
+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_resource(mmio);
+
+	return 0;
+}
+
+static void pdca_shutdown(struct platform_device *pdev)
+{
+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
+	struct pdca_chan	*pch;
+
+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
+		pdca_suspend_channel(pdca, pch);
+}
+
+static int pdca_suspend_late(struct platform_device *pdev, pm_message_t state)
+{
+	return 0;
+}
+
+static int pdca_resume_early(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver pdca_driver = {
+	.remove		= __exit_p(pdca_remove),
+	.shutdown	= pdca_shutdown,
+	.suspend_late	= pdca_suspend_late,
+	.resume_early	= pdca_resume_early,
+	.driver		= {
+		.name	= "atmel_pdca",
+	},
+};
+
+static int __init pdca_init(void)
+{
+	return platform_driver_probe(&pdca_driver, pdca_probe);
+}
+subsys_initcall(pdca_init);
+
+static void __exit pdca_exit(void)
+{
+	platform_driver_unregister(&pdca_driver);
+}
+module_exit(pdca_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Atmel PDCA DMA Controller driver");
+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
diff -urN linux-2.6.28.2-0rig//drivers/dma/dw_dmac.c linux-2.6.28.2/drivers/dma/dw_dmac.c
--- linux-2.6.28.2-0rig//drivers/dma/dw_dmac.c	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/dma/dw_dmac.c	2009-01-29 08:52:50.000000000 +0100
@@ -545,109 +545,51 @@
 	return NULL;
 }
 
-static struct dma_async_tx_descriptor *
-dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-		unsigned int sg_len, enum dma_data_direction direction,
-		unsigned long flags)
+static struct dw_desc *dwc_init_slave_descs(struct dw_dma_chan *dwc,
+		struct scatterlist *sgl, unsigned int sg_len,
+		u32 ctllo, dma_addr_t src_reg, dma_addr_t dst_reg,
+		unsigned int reg_width, unsigned long flags)
 {
-	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-	struct dw_dma_slave	*dws = dwc->dws;
-	struct dw_desc		*prev;
-	struct dw_desc		*first;
-	u32			ctllo;
-	dma_addr_t		reg;
-	unsigned int		reg_width;
-	unsigned int		mem_width;
-	unsigned int		i;
+	struct dma_chan		*chan = &dwc->chan;
 	struct scatterlist	*sg;
+	struct dw_desc		*desc;
+	struct dw_desc		*first = NULL;
+	struct dw_desc		*prev = NULL;
+	unsigned int		align_mask;
+	unsigned int		i;
 	size_t			total_len = 0;
 
-	dev_vdbg(&chan->dev, "prep_dma_slave\n");
-
-	if (unlikely(!dws || !sg_len))
-		return NULL;
-
-	reg_width = dws->slave.reg_width;
-	prev = first = NULL;
-
-	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
-
-	switch (direction) {
-	case DMA_TO_DEVICE:
-		ctllo = (DWC_DEFAULT_CTLLO
-				| DWC_CTLL_DST_WIDTH(reg_width)
-				| DWC_CTLL_DST_FIX
-				| DWC_CTLL_SRC_INC
-				| DWC_CTLL_FC_M2P);
-		reg = dws->slave.tx_reg;
-		for_each_sg(sgl, sg, sg_len, i) {
-			struct dw_desc	*desc;
-			u32		len;
-			u32		mem;
+	align_mask = (1 << reg_width) - 1;
+	for_each_sg(sgl, sg, sg_len, i) {
+		u32		len;
+		u32		desc_len;
+		u32		mem;
+
+		mem = sg_phys(sg);
+		len = sg_dma_len(sg);
+		total_len += len;
 
+		while (len) {
+			desc_len = min(len, DWC_MAX_COUNT << reg_width);
 			desc = dwc_desc_get(dwc);
 			if (!desc) {
 				dev_err(&chan->dev,
 					"not enough descriptors available\n");
 				goto err_desc_get;
 			}
+			len -= desc_len;
 
-			mem = sg_phys(sg);
-			len = sg_dma_len(sg);
-			mem_width = 2;
-			if (unlikely(mem & 3 || len & 3))
-				mem_width = 0;
-
-			desc->lli.sar = mem;
-			desc->lli.dar = reg;
-			desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
-			desc->lli.ctlhi = len >> mem_width;
+			if (unlikely((mem & align_mask) || (len & align_mask)))
+				goto err_align;
 
-			if (!first) {
-				first = desc;
-			} else {
-				prev->lli.llp = desc->txd.phys;
-				dma_sync_single_for_device(chan->dev.parent,
-						prev->txd.phys,
-						sizeof(prev->lli),
-						DMA_TO_DEVICE);
-				list_add_tail(&desc->desc_node,
-						&first->txd.tx_list);
-			}
-			prev = desc;
-			total_len += len;
-		}
-		break;
-	case DMA_FROM_DEVICE:
-		ctllo = (DWC_DEFAULT_CTLLO
-				| DWC_CTLL_SRC_WIDTH(reg_width)
-				| DWC_CTLL_DST_INC
-				| DWC_CTLL_SRC_FIX
-				| DWC_CTLL_FC_P2M);
-
-		reg = dws->slave.rx_reg;
-		for_each_sg(sgl, sg, sg_len, i) {
-			struct dw_desc	*desc;
-			u32		len;
-			u32		mem;
-
-			desc = dwc_desc_get(dwc);
-			if (!desc) {
-				dev_err(&chan->dev,
-					"not enough descriptors available\n");
-				goto err_desc_get;
-			}
-
-			mem = sg_phys(sg);
-			len = sg_dma_len(sg);
-			mem_width = 2;
-			if (unlikely(mem & 3 || len & 3))
-				mem_width = 0;
-
-			desc->lli.sar = reg;
-			desc->lli.dar = mem;
-			desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
-			desc->lli.ctlhi = len >> reg_width;
+			desc->lli.sar = src_reg ? src_reg : mem;
+			desc->lli.dar = dst_reg ? dst_reg : mem;
+			desc->lli.ctllo = ctllo;
+			desc->lli.ctlhi = desc_len >> reg_width;
+			dev_vdbg(&dwc->chan.dev,
+					"  s%08x d%08x c%08x:%08x\n",
+					desc->lli.sar, desc->lli.dar,
+					ctllo, desc_len >> reg_width);
 
 			if (!first) {
 				first = desc;
@@ -661,11 +603,8 @@
 						&first->txd.tx_list);
 			}
 			prev = desc;
-			total_len += len;
+			mem += desc_len;
 		}
-		break;
-	default:
-		return NULL;
 	}
 
 	if (flags & DMA_PREP_INTERRUPT)
@@ -679,13 +618,69 @@
 
 	first->len = total_len;
 
-	return &first->txd;
+	return first;
 
+err_align:
+	dwc_desc_put(dwc, desc);
 err_desc_get:
 	dwc_desc_put(dwc, first);
 	return NULL;
 }
 
+static struct dma_async_tx_descriptor *
+dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_data_direction direction,
+		unsigned long flags)
+{
+	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
+	struct dw_dma_slave	*dws = dwc->dws;
+	struct dw_desc		*first;
+	u32			ctllo;
+	unsigned int		reg_width;
+
+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
+			sg_len, flags);
+
+	if (unlikely(!dws || !sg_len))
+		return NULL;
+
+	reg_width = dws->slave.reg_width;
+	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
+
+	switch (direction) {
+	case DMA_TO_DEVICE:
+		ctllo = (DWC_DEFAULT_CTLLO
+				| DWC_CTLL_DST_WIDTH(reg_width)
+				| DWC_CTLL_SRC_WIDTH(reg_width)
+				| DWC_CTLL_DST_FIX
+				| DWC_CTLL_SRC_INC
+				| DWC_CTLL_FC_M2P);
+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
+				0, dws->slave.tx_reg, reg_width, flags);
+		break;
+	case DMA_FROM_DEVICE:
+		ctllo = (DWC_DEFAULT_CTLLO
+				| DWC_CTLL_SRC_WIDTH(reg_width)
+				| DWC_CTLL_DST_WIDTH(reg_width)
+				| DWC_CTLL_DST_INC
+				| DWC_CTLL_SRC_FIX
+				| DWC_CTLL_FC_P2M);
+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
+				dws->slave.rx_reg, 0, reg_width, flags);
+		break;
+	default:
+		return NULL;
+	}
+
+	if (unlikely(!first)) {
+		dma_unmap_sg(chan->dev.parent, sgl, sg_len, direction);
+		return NULL;
+	}
+
+	return &first->txd;
+}
+
 static void dwc_terminate_all(struct dma_chan *chan)
 {
 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
@@ -1109,7 +1104,7 @@
 {
 	return platform_driver_probe(&dw_driver, dw_probe);
 }
-module_init(dw_init);
+subsys_initcall(dw_init);
 
 static void __exit dw_exit(void)
 {
diff -urN linux-2.6.28.2-0rig//drivers/dma/Kconfig linux-2.6.28.2/drivers/dma/Kconfig
--- linux-2.6.28.2-0rig//drivers/dma/Kconfig	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/dma/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -38,6 +38,20 @@
 	help
 	  Enable support for the Intel(R) IOP Series RAID engines.
 
+config ATMEL_PDCA
+	tristate "Atmel Peripheral DMA Controller A support"
+	depends on AVR32
+	select DMA_ENGINE
+	default y if CPU_AT32AP7200
+	help
+	  Support the Atmel Peripheral DMA Controller found on AVR32
+	  UC3 chips as well as newer AP7 chips. This controller is
+	  similar to the PDC found on AT32AP7000 and various AT91
+	  chips, but has its own register bank.
+
+	  This controller only supports peripheral (slave) transfers,
+	  not memory-to-memory transfers.
+
 config DW_DMAC
 	tristate "Synopsys DesignWare AHB DMA support"
 	depends on AVR32
diff -urN linux-2.6.28.2-0rig//drivers/dma/Makefile linux-2.6.28.2/drivers/dma/Makefile
--- linux-2.6.28.2-0rig//drivers/dma/Makefile	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/dma/Makefile	2009-01-29 08:52:50.000000000 +0100
@@ -4,6 +4,7 @@
 obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
 ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
 obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
+obj-$(CONFIG_ATMEL_PDCA) += atmel_pdca.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
diff -urN linux-2.6.28.2-0rig//drivers/mmc/host/atmel-mci-regs.h linux-2.6.28.2/drivers/mmc/host/atmel-mci-regs.h
--- linux-2.6.28.2-0rig//drivers/mmc/host/atmel-mci-regs.h	2009-01-29 08:39:27.000000000 +0100
+++ linux-2.6.28.2/drivers/mmc/host/atmel-mci-regs.h	2009-01-29 08:52:50.000000000 +0100
@@ -10,13 +10,21 @@
 #ifndef __DRIVERS_MMC_ATMEL_MCI_H__
 #define __DRIVERS_MMC_ATMEL_MCI_H__
 
-/* MCI Register Definitions */
+/*
+ * MCI Register Definitions. Registers and bitfields marked with [2]
+ * are only available in MCI2.
+ */
 #define MCI_CR			0x0000	/* Control */
 # define MCI_CR_MCIEN		(  1 <<  0)	/* MCI Enable */
 # define MCI_CR_MCIDIS		(  1 <<  1)	/* MCI Disable */
+# define MCI_CR_PWSEN		(  1 <<  2)	/* Powersave Enable[2] */
+# define MCI_CR_PWSDIS		(  1 <<  3)	/* Powersave Disable[2] */
+# define MCI_CR_IOWAITEN	(  1 <<  4)	/* SDIO Read Wait Enable[2] */
+# define MCI_CR_IOWAITDIS	(  1 <<  5)	/* SDIO Read Wait Disable[2] */
 # define MCI_CR_SWRST		(  1 <<  7)	/* Software Reset */
 #define MCI_MR			0x0004	/* Mode */
 # define MCI_MR_CLKDIV(x)	((x) <<  0)	/* Clock Divider */
+# define MCI_MR_PWSDIV(x)	((x) <<  8)	/* Powersave Divider[2] */
 # define MCI_MR_RDPROOF		(  1 << 11)	/* Read Proof */
 # define MCI_MR_WRPROOF		(  1 << 12)	/* Write Proof */
 #define MCI_DTOR		0x0008	/* Data Timeout */
@@ -56,6 +64,9 @@
 #define MCI_BLKR		0x0018	/* Block */
 # define MCI_BCNT(x)		((x) <<  0)	/* Data Block Count */
 # define MCI_BLKLEN(x)		((x) << 16)	/* Data Block Length */
+#define MCI_CSTOR		0x001c	/* Completion Signal Timeout[2] */
+# define MCI_CSTOCYC(x)		((x) <<  0)	/* CST cycles */
+# define MCI_CSTOMUL(x)		((x) <<  4)	/* CST multiplier */
 #define MCI_RSPR		0x0020	/* Response 0 */
 #define MCI_RSPR1		0x0024	/* Response 1 */
 #define MCI_RSPR2		0x0028	/* Response 2 */
@@ -66,24 +77,45 @@
 #define MCI_IER			0x0044	/* Interrupt Enable */
 #define MCI_IDR			0x0048	/* Interrupt Disable */
 #define MCI_IMR			0x004c	/* Interrupt Mask */
-# define MCI_CMDRDY		(  1 <<   0)	/* Command Ready */
-# define MCI_RXRDY		(  1 <<   1)	/* Receiver Ready */
-# define MCI_TXRDY		(  1 <<   2)	/* Transmitter Ready */
-# define MCI_BLKE		(  1 <<   3)	/* Data Block Ended */
-# define MCI_DTIP		(  1 <<   4)	/* Data Transfer In Progress */
-# define MCI_NOTBUSY		(  1 <<   5)	/* Data Not Busy */
-# define MCI_SDIOIRQA		(  1 <<   8)	/* SDIO IRQ in slot A */
-# define MCI_SDIOIRQB		(  1 <<   9)	/* SDIO IRQ in slot B */
-# define MCI_RINDE		(  1 <<  16)	/* Response Index Error */
-# define MCI_RDIRE		(  1 <<  17)	/* Response Direction Error */
-# define MCI_RCRCE		(  1 <<  18)	/* Response CRC Error */
-# define MCI_RENDE		(  1 <<  19)	/* Response End Bit Error */
-# define MCI_RTOE		(  1 <<  20)	/* Response Time-Out Error */
-# define MCI_DCRCE		(  1 <<  21)	/* Data CRC Error */
-# define MCI_DTOE		(  1 <<  22)	/* Data Time-Out Error */
-# define MCI_OVRE		(  1 <<  30)	/* RX Overrun Error */
-# define MCI_UNRE		(  1 <<  31)	/* TX Underrun Error */
+# define MCI_CMDRDY		(  1 <<  0)	/* Command Ready */
+# define MCI_RXRDY		(  1 <<  1)	/* Receiver Ready */
+# define MCI_TXRDY		(  1 <<  2)	/* Transmitter Ready */
+# define MCI_BLKE		(  1 <<  3)	/* Data Block Ended */
+# define MCI_DTIP		(  1 <<  4)	/* Data Transfer In Progress */
+# define MCI_NOTBUSY		(  1 <<  5)	/* Data Not Busy */
+# define MCI_SDIOIRQA		(  1 <<  8)	/* SDIO IRQ in slot A */
+# define MCI_SDIOIRQB		(  1 <<  9)	/* SDIO IRQ in slot B */
+# define MCI_RINDE		(  1 << 16)	/* Response Index Error */
+# define MCI_RDIRE		(  1 << 17)	/* Response Direction Error */
+# define MCI_RCRCE		(  1 << 18)	/* Response CRC Error */
+# define MCI_RENDE		(  1 << 19)	/* Response End Bit Error */
+# define MCI_RTOE		(  1 << 20)	/* Response Time-Out Error */
+# define MCI_DCRCE		(  1 << 21)	/* Data CRC Error */
+# define MCI_DTOE		(  1 << 22)	/* Data Time-Out Error */
+# define MCI_OVRE		(  1 << 30)	/* RX Overrun Error */
+# define MCI_UNRE		(  1 << 31)	/* TX Underrun Error */
+#define MCI_DMA			0x0050	/* DMA Configuration[2] */
+# define MCI_DMA_OFFSET(x)	((x) <<  0)	/* DMA write buffer offset */
+# define MCI_DMA_CHKSIZE_1	(  0 <<  5)	/* DMA chunk size */
+# define MCI_DMA_CHKSIZE_4	(  1 <<  5)	/* DMA chunk size */
+# define MCI_DMA_CHKSIZE_8	(  2 <<  5)	/* DMA chunk size */
+# define MCI_DMA_CHKSIZE_16	(  3 <<  5)	/* DMA chunk size */
+# define MCI_DMAEN		(  1 <<  8)	/* DMA HW handshake enable */
+#define MCI_CFG			0x0054	/* Configuration[2] */
+# define MCI_CFG_FIFOMODE	(  1 <<  0)	/* Start transfer ASAP */
+# define MCI_CFG_FERRCTRL	(  1 <<  4)	/* xrun flags clear-on-read */
+# define MCI_CFG_HSMODE		(  1 <<  8)	/* Use high-speed signaling */
+# define MCI_CFG_LSYNC		(  1 << 12)	/* Synchronize on last block */
+#define MCI_WPMR		0x00e4	/* Write Protect Mode[2] */
+# define MCI_WP_EN		(  1 <<  0)	/* WP Enable */
+# define MCI_WP_KEY		(0x4d4349 << 8)	/* WP Key */
+#define MCI_WPSR		0x00e8	/* Write Protect Status[2] */
+# define MCI_GET_WP_VS(x)	((x) & 0x0f)
+# define MCI_GET_WP_VSRC(x)	(((x) >> 8) & 0xffff)
+#define MCI_VERSION		0x00fc	/* MCI Core Version[2] */
+#define MCI_FIFO_APERTURE	0x0200	/* FIFO Aperture[2] */
 
+/* This is not including the FIFO Aperture on MCI2 */
 #define MCI_REGS_SIZE		0x100
 
 /* Register access macros */
diff -urN linux-2.6.28.2-0rig//drivers/mmc/host/Kconfig linux-2.6.28.2/drivers/mmc/host/Kconfig
--- linux-2.6.28.2-0rig//drivers/mmc/host/Kconfig	2009-01-29 08:39:27.000000000 +0100
+++ linux-2.6.28.2/drivers/mmc/host/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -125,6 +125,17 @@
 
 	  If unsure, say N.
 
+config MMC_ATMELMCI_DMA
+	bool "Atmel MCI DMA support (EXPERIMENTAL)"
+	depends on MMC_ATMELMCI && DMA_ENGINE && EXPERIMENTAL
+	help
+	  Say Y here to have the Atmel MCI driver use a DMA engine to
+	  do data transfers and thus increase the throughput and
+	  reduce the CPU utilization. Note that this is highly
+	  experimental and may cause the driver to lock up.
+
+	  If unsure, say N.
+
 config MMC_IMX
 	tristate "Motorola i.MX Multimedia Card Interface support"
 	depends on ARCH_IMX
diff -urN linux-2.6.28.2-0rig//drivers/mtd/nand/atmel_nand.c linux-2.6.28.2/drivers/mtd/nand/atmel_nand.c
--- linux-2.6.28.2-0rig//drivers/mtd/nand/atmel_nand.c	2009-01-29 08:39:27.000000000 +0100
+++ linux-2.6.28.2/drivers/mtd/nand/atmel_nand.c	2009-01-29 08:52:50.000000000 +0100
@@ -456,7 +456,7 @@
 	platform_set_drvdata(pdev, host);
 	atmel_nand_enable(host);
 
-	if (host->board->det_pin) {
+	if (gpio_is_valid(host->board->det_pin)) {
 		if (gpio_get_value(host->board->det_pin)) {
 			printk("No SmartMedia card inserted.\n");
 			res = ENXIO;
diff -urN linux-2.6.28.2-0rig//drivers/rtc/Kconfig linux-2.6.28.2/drivers/rtc/Kconfig
--- linux-2.6.28.2-0rig//drivers/rtc/Kconfig	2009-01-29 08:39:30.000000000 +0100
+++ linux-2.6.28.2/drivers/rtc/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -633,6 +633,22 @@
 	  will be used.  The default of zero is normally OK to use, but
 	  on some systems other software needs to use that register.
 
+config RTC_DRV_AVR32_AST
+	tristate "AVR32 Asynchronous Timer"
+	depends on AVR32
+	help
+	  RTC driver for the AVR32 Asynchronous Timers. The AST is a
+	  simple and flexible timer that can be used both as a
+	  high-resolution system timer and an RTC, depending on what
+	  clock source it is running from.
+
+	  If you say yes here, and add one or more platform_device
+	  called "rtc-ast", those devices will be clocked from a
+	  32.768 kHz crystal oscillator and used as RTCs.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called rtc-ast.
+
 config RTC_DRV_BFIN
 	tristate "Blackfin On-Chip RTC"
 	depends on BLACKFIN && !BF561
diff -urN linux-2.6.28.2-0rig//drivers/rtc/Makefile linux-2.6.28.2/drivers/rtc/Makefile
--- linux-2.6.28.2-0rig//drivers/rtc/Makefile	2009-01-29 08:39:30.000000000 +0100
+++ linux-2.6.28.2/drivers/rtc/Makefile	2009-01-29 08:52:50.000000000 +0100
@@ -20,6 +20,7 @@
 obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
 obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
 obj-$(CONFIG_RTC_DRV_AT91SAM9)	+= rtc-at91sam9.o
+obj-$(CONFIG_RTC_DRV_AVR32_AST)	+= rtc-ast.o
 obj-$(CONFIG_RTC_DRV_BFIN)	+= rtc-bfin.o
 obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
 obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
diff -urN linux-2.6.28.2-0rig//drivers/rtc/rtc-ast.c linux-2.6.28.2/drivers/rtc/rtc-ast.c
--- linux-2.6.28.2-0rig//drivers/rtc/rtc-ast.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/drivers/rtc/rtc-ast.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,546 @@
+/*
+ * An RTC driver for the AVR32 Asynchronous Timer
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+
+#include <asm/ast_regs.h>
+
+/*
+ * The AST - ASynchronous Timer - is built around a simple cycle
+ * counter that can be driven from one of four selectable clocks with
+ * a selectable power-of-two prescaler. It also has two alarms (ALARM0
+ * and ALARM1) and two periodic event generators (PER0 and PER1). The
+ * latter can be driven by different tappings of the same prescaler
+ * that drives the counter.
+ *
+ * This driver uses the 32.768 kHz crystal oscillator as a clock
+ * source and a prescaler that gives a 1 Hz counter frequency. It uses
+ * ALARM0 to support both "old-school" and "wake" alarms, PER0 to
+ * support periodic interrupts (PIE) up to 16.384 kHz (at power-of-two
+ * intervals), and PER1 to support a 1 Hz update interrupt (UIE).
+ *
+ * Watchdog interrupts seem to be undocumented and unsupported by
+ * everyone else, so those are not supported for now.
+ *
+ * The AST can wake the system from any sleep mode given that the
+ * source clock is running. On AT32AP720x, the 32.768 kHz crystal
+ * oscillator runs in all sleep modes except "static" and "shutdown".
+ */
+
+/* 32768 Hz means up to 60 us for synchronization + a bit of slack */
+#define AST_SYNC_TIMEOUT_US	100
+
+#define AST_CLK_RATE		32768
+#define AST_1S_PRESCALER	14	/* log2(32768) - 1 */
+
+struct rtc_ast {
+	/* Protects I/O registers */
+	spinlock_t		lock;
+
+	struct rtc_device	*rtc;
+	void __iomem		*regs;
+	struct clk		*osc32;
+	struct clk		*pclk;
+};
+
+/*
+ * Because the AST is, well, asynchronous, we must make sure we don't
+ * write to certain registers while the previous write is being
+ * synchronized between clock domains. This affects writes to CR, CV,
+ * SCR, WER, PIRx and ARx. To keep the delays minimal, we always
+ * synchronize _before_ writes to these registers.
+ *
+ * This function is also used to synchronize when changing the clock
+ * source, using a different bit in the status register.
+ */
+static int ast_wait_ready(void __iomem *regs, unsigned int busy_mask)
+{
+	unsigned long	timeout = AST_SYNC_TIMEOUT_US;
+
+	while (ast_readl(regs, SR) & busy_mask) {
+		udelay(1);
+		if (--timeout == 0)
+			return -ETIMEDOUT;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static void rtc_ast_release(struct device *dev)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+
+	/* Disable all interrupts */
+	clk_enable(ast->pclk);
+	ast_writel(ast->regs, IDR, ~0UL);
+	clk_disable(ast->pclk);
+}
+
+static int rtc_ast_ioctl(struct device *dev, unsigned int cmd,
+		unsigned long arg)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+	int		ret = 0;
+
+	clk_enable(ast->pclk);
+
+	switch (cmd) {
+		/* REVISIT: Should perhaps verify that irq_task is NULL */
+	case RTC_AIE_ON:
+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
+		break;
+	case RTC_AIE_OFF:
+		ast_writel(ast->regs, IDR, AST_BIT(ALARM0));
+		break;
+	case RTC_UIE_ON:
+		spin_lock_irq(&ast->lock);
+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+		if (!ret) {
+			ast_writel(ast->regs, SCR, AST_BIT(PER1));
+			ast_writel(ast->regs, IER, AST_BIT(PER1));
+		}
+		spin_unlock_irq(&ast->lock);
+
+		break;
+	case RTC_UIE_OFF:
+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
+		break;
+#if 0
+	case RTC_PIE_ON:
+		spin_lock_irq(&ast->lock);
+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+		if (ret)
+			break;
+		ast_writel(ast->regs, SCR, AST_BIT(PER0));
+		spin_unlock_irq(&ast->lock);
+
+		ast_writel(ast->regs, IER, AST_BIT(PER0));
+		break;
+	case RTC_PIE_OFF:
+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
+		break;
+#endif
+	default:
+		ret = -ENOIOCTLCMD;
+		break;
+	}
+
+	clk_disable(ast->pclk);
+
+	return ret;
+}
+
+static int rtc_ast_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+
+	clk_enable(ast->pclk);
+	rtc_time_to_tm(ast_readl(ast->regs, CV), tm);
+	clk_disable(ast->pclk);
+
+	return 0;
+}
+
+static int rtc_ast_set_mmss(struct device *dev, unsigned long secs)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+	int		ret;
+
+	clk_enable(ast->pclk);
+
+	spin_lock_irq(&ast->lock);
+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	if (!ret)
+		ast_writel(ast->regs, CV, secs);
+	spin_unlock_irq(&ast->lock);
+
+	clk_disable(ast->pclk);
+
+	return ret;
+}
+
+static int rtc_ast_set_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned long	secs;
+	int		ret;
+
+	ret = rtc_tm_to_time(tm, &secs);
+	if (!ret)
+		ret = rtc_ast_set_mmss(dev, secs);
+
+	return ret;
+}
+
+static int rtc_ast_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+
+	clk_enable(ast->pclk);
+
+	spin_lock_irq(&ast->lock);
+	rtc_time_to_tm(ast_readl(ast->regs, AR0), &alrm->time);
+	alrm->enabled = !!(ast_readl(ast->regs, IMR) & AST_BIT(ALARM0));
+	alrm->pending = !!(ast_readl(ast->regs, SR) & AST_BIT(ALARM0));
+	spin_unlock_irq(&ast->lock);
+
+	clk_disable(ast->pclk);
+
+	return 0;
+}
+
+static int rtc_ast_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+	unsigned long	seconds;
+	int		ret;
+
+	ret = rtc_tm_to_time(&alrm->time, &seconds);
+	if (ret)
+		return ret;
+
+	clk_enable(ast->pclk);
+
+	/*
+	 * REVISIT: The alarm may trigger before we are done here.
+	 * Who's responsible for handling that?
+	 *
+	 * We don't want to clear the ALARM0 flag before we update AR0
+	 * because the previous value of AR0 might trigger an alarm
+	 * right after we clear the flag.
+	 */
+	spin_lock_irq(&ast->lock);
+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	if (ret)
+		goto unlock;
+	ast_writel(ast->regs, AR0, seconds);
+
+	/* Try to avoid synchronization penalty */
+	if (ast_readl(ast->regs, SR) & AST_BIT(ALARM0)) {
+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+		if (ret)
+			goto unlock;
+		ast_writel(ast->regs, SCR, AST_BIT(ALARM0));
+	}
+
+	if (alrm->enabled)
+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
+
+unlock:
+	spin_unlock_irq(&ast->lock);
+	clk_disable(ast->pclk);
+
+	return ret;
+}
+
+static int rtc_ast_proc(struct device *dev, struct seq_file *seq)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+	u32		imr;
+
+	clk_enable(ast->pclk);
+	imr = ast_readl(ast->regs, IMR);
+	clk_disable(ast->pclk);
+
+	return seq_printf(seq,
+			"periodic_IRQ\t: %s\n"
+			"update_IRQ\t: %s\n"
+			"periodic_freq\t: %d\n",
+			(imr & AST_BIT(PER0)) ? "yes" : "no",
+			(imr & AST_BIT(PER1)) ? "yes" : "no",
+			ast->rtc->irq_freq);
+}
+
+static int rtc_ast_irq_set_freq(struct device *dev, int freq)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+	unsigned int	pres_bit;
+	int		ret;
+
+	/* RTC core currently ensures this. */
+	BUG_ON(!freq);
+
+	pres_bit = __ffs(freq);
+	if (pres_bit > AST_1S_PRESCALER)
+		return -EINVAL;
+	pres_bit = AST_1S_PRESCALER - pres_bit;
+
+	clk_enable(ast->pclk);
+
+	spin_lock_irq(&ast->lock);
+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	if (ret)
+		goto unlock;
+
+	ast_writel(ast->regs, PIR0, pres_bit);
+
+unlock:
+	spin_unlock_irq(&ast->lock);
+	clk_disable(ast->pclk);
+
+	return ret;
+}
+
+static int rtc_ast_irq_set_state(struct device *dev, int enabled)
+{
+	struct rtc_ast	*ast = dev_get_drvdata(dev);
+	int		ret = 0;
+
+	clk_enable(ast->pclk);
+
+	if (enabled) {
+		spin_lock_irq(&ast->lock);
+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
+		if (!ret) {
+			ast_writel(ast->regs, SCR, AST_BIT(PER0));
+			ast_writel(ast->regs, IER, AST_BIT(PER0));
+		}
+		spin_unlock_irq(&ast->lock);
+	} else {
+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
+	}
+
+	clk_disable(ast->pclk);
+
+	return ret;
+}
+
+static const struct rtc_class_ops rtc_ast_ops = {
+	.release	= rtc_ast_release,
+	.ioctl		= rtc_ast_ioctl,
+	.read_time	= rtc_ast_read_time,
+	.set_time	= rtc_ast_set_time,
+	.read_alarm	= rtc_ast_read_alarm,
+	.set_alarm	= rtc_ast_set_alarm,
+	.proc		= rtc_ast_proc,
+	.set_mmss	= rtc_ast_set_mmss,
+	.irq_set_freq	= rtc_ast_irq_set_freq,
+	.irq_set_state	= rtc_ast_irq_set_state,
+};
+
+static irqreturn_t rtc_ast_interrupt(int irq, void *dev_id)
+{
+	struct rtc_ast	*ast = dev_id;
+	unsigned long	events;
+	unsigned long	num;
+	u32		status;
+	u32		pending;
+	irqreturn_t	ret = IRQ_NONE;
+
+	clk_enable(ast->pclk);
+	spin_lock(&ast->lock);
+
+	status = ast_readl(ast->regs, SR);
+	pending = status & ast_readl(ast->regs, IMR);
+	if (unlikely(!pending))
+		goto out;
+
+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	ast_writel(ast->regs, SCR, pending);
+
+	events = RTC_IRQF;
+	num = 0;
+	if (pending & AST_BIT(ALARM0)) {
+		num++;
+		events |= RTC_AF;
+	}
+	if (pending & AST_BIT(PER0)) {
+		num++;
+		events |= RTC_PF;
+	}
+	if (pending & AST_BIT(PER1)) {
+		num++;
+		events |= RTC_UF;
+	}
+
+	rtc_update_irq(ast->rtc, num, events);
+	ret = IRQ_HANDLED;
+
+out:
+	spin_unlock(&ast->lock);
+	clk_disable(ast->pclk);
+
+	return IRQ_HANDLED;
+}
+
+static int __init rtc_ast_probe(struct platform_device *pdev)
+{
+	struct resource	*regs;
+	struct rtc_ast	*ast;
+	int		irq;
+	int		ret;
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_dbg(&pdev->dev, "no mmio resource\n");
+		return -ENXIO;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_dbg(&pdev->dev, "no irq\n");
+		return -ENXIO;
+	}
+
+	ast = kzalloc(sizeof(struct rtc_ast), GFP_KERNEL);
+	if (!ast) {
+		dev_dbg(&pdev->dev, "out of memory\n");
+		return -ENOMEM;
+	}
+
+	ast->osc32 = clk_get(NULL, "osc32k");
+	if (IS_ERR(ast->osc32)) {
+		ret = PTR_ERR(ast->osc32);
+		dev_dbg(&pdev->dev, "no 32 kHz oscillator\n");
+		goto err_osc32;
+	}
+
+	ast->pclk = clk_get(&pdev->dev, "pclk");
+	if (IS_ERR(ast->pclk)) {
+		ret = PTR_ERR(ast->pclk);
+		dev_dbg(&pdev->dev, "no peripheral clock\n");
+		goto err_pclk;
+	}
+
+	spin_lock_init(&ast->lock);
+
+	ast->regs = ioremap(regs->start, regs->end - regs->start + 1);
+	if (!ast->regs) {
+		dev_dbg(&pdev->dev, "failed to map registers\n");
+		ret = -ENOMEM;
+		goto err_ioremap;
+	}
+
+	clk_enable(ast->osc32);
+	clk_enable(ast->pclk);
+
+	/* Initialize the AST if it isn't running already */
+	if (!(ast_readl(ast->regs, CR) & AST_BIT(CR_EN))) {
+		ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
+		ast_writel(ast->regs, CLOCK,
+				AST_BF(CLOCK_CSSEL, AST_CLOCK_OSC32)
+				| AST_BIT(CLOCK_CEN));
+		ret = ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
+		if (ret) {
+			dev_dbg(&pdev->dev,
+				"timed out selecting clock source\n");
+			goto err_clksel;
+		}
+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
+		ast_writel(ast->regs, CV, 0);
+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
+		ast_writel(ast->regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR)
+				| AST_BF(CR_PSEL, AST_1S_PRESCALER));
+	}
+
+	ast_writel(ast->regs, IDR, ~0UL);
+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	ast_writel(ast->regs, WER, 0);
+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	ast_writel(ast->regs, PIR0, AST_1S_PRESCALER);
+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	ast_writel(ast->regs, PIR1, AST_1S_PRESCALER);
+
+	ret = request_irq(irq, rtc_ast_interrupt, 0, "rtc-ast", ast);
+	if (ret) {
+		dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
+		goto err_request_irq;
+	}
+
+	ast->rtc = rtc_device_register("rtc-ast", &pdev->dev,
+			&rtc_ast_ops, THIS_MODULE);
+	if (IS_ERR(ast->rtc)) {
+		dev_dbg(&pdev->dev, "could not register rtc device\n");
+		ret = PTR_ERR(ast->rtc);
+		goto err_register;
+	}
+
+	ast->rtc->max_user_freq = AST_CLK_RATE / 2;
+	ast->rtc->irq_freq = 1;
+
+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
+	clk_disable(ast->pclk);
+	platform_set_drvdata(pdev, ast);
+	device_init_wakeup(&pdev->dev, 1);
+
+	dev_info(&pdev->dev, "AVR32 Asynchronous Timer at %08lx irq %d\n",
+			(unsigned long)regs->start, irq);
+
+	return 0;
+
+err_register:
+	free_irq(irq, ast);
+err_request_irq:
+err_clksel:
+	clk_disable(ast->pclk);
+	clk_disable(ast->osc32);
+	iounmap(ast->regs);
+err_ioremap:
+	clk_put(ast->pclk);
+err_pclk:
+	clk_put(ast->osc32);
+err_osc32:
+	kfree(ast);
+	return ret;
+}
+
+static int __exit rtc_ast_remove(struct platform_device *pdev)
+{
+	struct rtc_ast *ast = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	clk_enable(ast->pclk);
+	ast_writel(ast->regs, IDR, ~0UL);
+	ast_readl(ast->regs, IMR);
+	clk_disable(ast->pclk);
+
+	free_irq(platform_get_irq(pdev, 0), ast);
+	rtc_device_unregister(ast->rtc);
+	clk_disable(ast->osc32);
+	iounmap(ast->regs);
+	clk_put(ast->pclk);
+	clk_put(ast->osc32);
+	kfree(ast);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct platform_driver rtc_ast_driver = {
+	.remove		= __exit_p(rtc_ast_remove),
+	.driver		= {
+		.name	= "rtc-ast",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init rtc_ast_init(void)
+{
+	return platform_driver_probe(&rtc_ast_driver, rtc_ast_probe);
+}
+module_init(rtc_ast_init);
+
+static void __exit rtc_ast_exit(void)
+{
+	platform_driver_unregister(&rtc_ast_driver);
+}
+module_exit(rtc_ast_exit);
+
+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
+MODULE_DESCRIPTION("AVR32 Asynchronous Timer RTC");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.28.2-0rig//drivers/spi/atmel_spi.c linux-2.6.28.2/drivers/spi/atmel_spi.c
--- linux-2.6.28.2-0rig//drivers/spi/atmel_spi.c	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/spi/atmel_spi.c	2009-01-29 09:29:00.000000000 +0100
@@ -1,306 +1,445 @@
 /*
  * Driver for Atmel AT32 and AT91 SPI Controllers
  *
- * Copyright (C) 2006 Atmel Corporation
+ * Copyright (C) 2006-2008 Atmel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
 #include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <linux/spi/atmel_spi.h>
 #include <linux/spi/spi.h>
 
-#include <asm/io.h>
-#include <mach/board.h>
-#include <mach/gpio.h>
 #include <mach/cpu.h>
 
 #include "atmel_spi.h"
 
-/*
- * The core SPI transfer engine just talks to a register bank to set up
- * DMA transfers; transfer queue progress is driven by IRQs.  The clock
- * framework provides the base clock, subdivided for each spi_device.
- *
- * Newer controllers, marked with "new_1" flag, have:
- *  - CR.LASTXFER
- *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
- *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
- *  - SPI_CSRx.CSAAT
- *  - SPI_CSRx.SBCR allows faster clocking
+#define BUFFER_SIZE		PAGE_SIZE
+#define INVALID_DMA_ADDRESS	0xffffffff
+#define MAX_SG_SEGS		8
+
+/**
+ * struct atmel_spi - SPI master controller state
+ * @lock: Spinlock protecting the @queue, @stay and @stopping fields
+ *	as well as the hardware registers.
+ * @regs: Base address of the hardware registers.
+ * @wait: Waitqueue used to wait for DMA completion or errors.
+ * @pending: Number of DMA transfers currently pending.
+ * @pending_bytes: Number of bytes submitted for DMA but not yet
+ *	accounted for.
+ * @error: Data transfer error detected by interrupt handler. When this
+ *	is set to a nonzero value, the DMA engine is stopped, @pending
+ *	is set to 0 and @wait is triggered.
+ * @buffer: Scratch buffer for use when the upper layers didn't provide
+ *	a TX or RX buffer.
+ * @buffer_dma: DMA address of @buffer.
+ * @buffer_size: Length of @buffer in bytes.
+ * @queue: SPI messages queued for transfer.
+ * @workqueue: Per-controller workqueue.
+ * @work: Queue processing work struct.
+ * @stay: If the last SPI message caused the SPI device to stay active,
+ *	this points to the SPI device associated with that message. NULL
+ *	otherwise.
+ * @clk: Bus clock connected to the controller.
+ * @base_hz: Base clock rate in Hz used for baud rate calculations.
+ * @stopping: Queue is being stopped. No new messages are started.
+ * @always_bounce: Always do transfers to/from bounce buffer.
+ * @pdev: Platform device associated with the controller.
  */
 struct atmel_spi {
 	spinlock_t		lock;
-
 	void __iomem		*regs;
-	int			irq;
-	struct clk		*clk;
-	struct platform_device	*pdev;
-	unsigned		new_1:1;
-	struct spi_device	*stay;
 
-	u8			stopping;
-	struct list_head	queue;
-	struct spi_transfer	*current_transfer;
-	unsigned long		current_remaining_bytes;
-	struct spi_transfer	*next_transfer;
-	unsigned long		next_remaining_bytes;
+	wait_queue_head_t	wait;
+	int			pending;
+	size_t			pending_bytes;
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+	struct scatterlist	tx_sg[MAX_SG_SEGS];
+	struct scatterlist	rx_sg[MAX_SG_SEGS];
+	unsigned int		sg_len;
+	struct dma_async_tx_descriptor *tx_desc;
+	struct dma_async_tx_descriptor *rx_desc;
+	struct dma_chan		*tx_chan;
+	struct dma_chan		*rx_chan;
+	struct dma_client	rx_client;
+	struct dma_client	tx_client;
+#endif
+	int			error;
 
 	void			*buffer;
 	dma_addr_t		buffer_dma;
+	size_t			buffer_size;
+
+	struct list_head	queue;
+	struct workqueue_struct	*workqueue;
+	struct work_struct	work;
+	struct spi_device	*stay;
+	struct clk		*clk;
+	unsigned long		base_hz;
+	bool			stopping;
+	bool			always_bounce;
+
+	struct platform_device	*pdev;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry		*debugfs_root;
+#endif
 };
 
-#define BUFFER_SIZE		PAGE_SIZE
-#define INVALID_DMA_ADDRESS	0xffffffff
+/**
+ * struct atmel_spi_device - Controller-specific per-slave state
+ * @npcs_pin: GPIO pin ID hooked up to this SPI slave.
+ * @csr: CSRn register value used when talking to this SPI slave.
+ */
+struct atmel_spi_device {
+	unsigned int		npcs_pin;
+	u32			csr;
+};
 
 /*
- * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
- * they assume that spi slave device state will not change on deselect, so
- * that automagic deselection is OK.  ("NPCSx rises if no data is to be
- * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
- * controllers have CSAAT and friends.
- *
- * Since the CSAAT functionality is a bit weird on newer controllers as
- * well, we use GPIO to control nCSx pins on all controllers, updating
- * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
- * support active-high chipselects despite the controller's belief that
- * only active-low devices/systems exists.
+ * Version 2 of the SPI controller has
+ *  - CR.LASTXFER
+ *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
+ *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
+ *  - SPI_CSRx.CSAAT
+ *  - SPI_CSRx.SBCR allows faster clocking
  *
- * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
- * right when driven with GPIO.  ("Mode Fault does not allow more than one
- * Master on Chip Select 0.")  No workaround exists for that ... so for
- * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
- * and (c) will trigger that first erratum in some cases.
+ * We can determine the controller version by reading the VERSION
+ * register, but I haven't checked that it exists on all chips, and
+ * this is cheaper anyway.
  */
+static bool atmel_spi_is_v2(void)
+{
+	return !cpu_is_at91rm9200();
+}
 
-static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
+static bool atmel_spi_xfer_is_last(struct spi_message *msg,
+		struct spi_transfer *xfer)
 {
-	unsigned gpio = (unsigned) spi->controller_data;
-	unsigned active = spi->mode & SPI_CS_HIGH;
-	u32 mr;
-	int i;
-	u32 csr;
-	u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-
-	/* Make sure clock polarity is correct */
-	for (i = 0; i < spi->master->num_chipselect; i++) {
-		csr = spi_readl(as, CSR0 + 4 * i);
-		if ((csr ^ cpol) & SPI_BIT(CPOL))
-			spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
-	}
+	return &xfer->transfer_list == msg->transfers.prev;
+}
 
-	mr = spi_readl(as, MR);
-	mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
+/*-------------------------------------------------------------------------*/
 
-	dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
-			gpio, active ? " (high)" : "",
-			mr);
+/*
+ * GCC doesn't eliminate _all_ the dead code, only some of it. In
+ * particular, the file operations appear to be difficult even if the
+ * file operations struct itself gets eliminated.
+ *
+ * So let's do the CPP dance.
+ */
+#ifdef CONFIG_DEBUG_FS
 
-	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
-		gpio_set_value(gpio, active);
-	spi_writel(as, MR, mr);
-}
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
 
-static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
+static int atmel_spi_queue_show(struct seq_file *s, void *v)
 {
-	unsigned gpio = (unsigned) spi->controller_data;
-	unsigned active = spi->mode & SPI_CS_HIGH;
-	u32 mr;
+	struct atmel_spi	*as = s->private;
+	struct spi_message	*msg;
+	struct spi_transfer	*xfer;
 
-	/* only deactivate *this* device; sometimes transfers to
-	 * another device may be active when this routine is called.
-	 */
-	mr = spi_readl(as, MR);
-	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
-		mr = SPI_BFINS(PCS, 0xf, mr);
-		spi_writel(as, MR, mr);
+	spin_lock_irq(&as->lock);
+	list_for_each_entry(msg, &as->queue, queue) {
+		seq_printf(s, "msg to %s:%s DMA mapped, status %d actual %u\n",
+				msg->spi->dev.bus_id,
+				msg->is_dma_mapped ? "" : " Not",
+				msg->status, msg->actual_length);
+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+			seq_printf(s, "  t%p r%p l%u%s %u bits %u us %u Hz\n",
+					xfer->tx_buf, xfer->rx_buf, xfer->len,
+					xfer->cs_change ? "cs_change" : "",
+					xfer->bits_per_word,
+					xfer->delay_usecs,
+					xfer->speed_hz);
+		}
 	}
+	spin_unlock_irq(&as->lock);
 
-	dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
-			gpio, active ? " (low)" : "",
-			mr);
-
-	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
-		gpio_set_value(gpio, !active);
+	return 0;
 }
 
-static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
-					struct spi_transfer *xfer)
+static int atmel_spi_queue_open(struct inode *inode, struct file *file)
 {
-	return msg->transfers.prev == &xfer->transfer_list;
+	return single_open(file, atmel_spi_queue_show, inode->i_private);
 }
 
-static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
+static const struct file_operations atmel_spi_queue_fops = {
+	.owner		= THIS_MODULE,
+	.open		= atmel_spi_queue_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static void atmel_spi_show_status_reg(struct seq_file *s,
+		const char *regname, u32 value)
 {
-	return xfer->delay_usecs == 0 && !xfer->cs_change;
+	static const char	*sr_bit[] = {
+		[0]	= "RDRF",
+		[1]	= "TDRE",
+		[2]	= "MODF",
+		[3]	= "OVRES",
+		[4]	= "ENDRX",
+		[5]	= "ENDTX",
+		[6]	= "RXBUFF",
+		[7]	= "TXBUFE",
+		[8]	= "NSSR",
+		[9]	= "TXEMPTY",
+		[16]	= "SPIENS",
+	};
+	unsigned int		i;
+
+	seq_printf(s, "%s:\t0x%08x", regname, value);
+	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
+		if (value & (1 << i)) {
+			if (sr_bit[i])
+				seq_printf(s, " %s", sr_bit[i]);
+			else
+				seq_printf(s, " UNKNOWN(%u)", i);
+		}
+	}
+	seq_putc(s, '\n');
 }
 
-static void atmel_spi_next_xfer_data(struct spi_master *master,
-				struct spi_transfer *xfer,
-				dma_addr_t *tx_dma,
-				dma_addr_t *rx_dma,
-				u32 *plen)
+static int atmel_spi_regs_show(struct seq_file *s, void *v)
 {
-	struct atmel_spi	*as = spi_master_get_devdata(master);
-	u32			len = *plen;
+	struct atmel_spi	*as = s->private;
+	unsigned int		i;
+	u32			value;
+	u32			*buf;
+
+	buf = kmalloc(0x200, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
 
-	/* use scratch buffer only when rx or tx data is unspecified */
-	if (xfer->rx_buf)
-		*rx_dma = xfer->rx_dma + xfer->len - len;
-	else {
-		*rx_dma = as->buffer_dma;
-		if (len > BUFFER_SIZE)
-			len = BUFFER_SIZE;
-	}
-	if (xfer->tx_buf)
-		*tx_dma = xfer->tx_dma + xfer->len - len;
-	else {
-		*tx_dma = as->buffer_dma;
-		if (len > BUFFER_SIZE)
-			len = BUFFER_SIZE;
-		memset(as->buffer, 0, len);
-		dma_sync_single_for_device(&as->pdev->dev,
-				as->buffer_dma, len, DMA_TO_DEVICE);
+	/* Grab a more or less consistent snapshot */
+	spin_lock_irq(&as->lock);
+	memcpy_fromio(buf, as->regs, 0x200);
+	spin_unlock_irq(&as->lock);
+
+	value = buf[SPI_MR / 4];
+	seq_printf(s, "MR:\t0x%08x%s%s%s%s%s%s PCS=%x DLYBCS=%u\n",
+			value,
+			(value & SPI_BIT(MSTR)) ? " MSTR" : "",
+			(value & SPI_BIT(PS)) ? " PS" : "",
+			(value & SPI_BIT(PCSDEC)) ? " PCSDEC" : "",
+			(value & SPI_BIT(FDIV)) ? " FDIV" : "",
+			(value & SPI_BIT(MODFDIS)) ? " MODFDIS" : "",
+			(value & SPI_BIT(LLB)) ? " LLB" : "",
+			SPI_BFEXT(PCS, value),
+			SPI_BFEXT(DLYBCS, value));
+
+	atmel_spi_show_status_reg(s, "SR", buf[SPI_SR / 4]);
+	atmel_spi_show_status_reg(s, "IMR", buf[SPI_IMR / 4]);
+
+	for (i = 0; i < 4; i++) {
+		value = buf[SPI_CSR0 / 4 + i];
+		seq_printf(s, "CSR%u:\t0x%08x%s%s%s\n",
+				i, value,
+				(value & SPI_BIT(CPOL)) ? " CPOL" : "",
+				(value & SPI_BIT(NCPHA)) ? " NCPHA" : "",
+				(value & SPI_BIT(CSAAT)) ? " CSAAT" : "");
+		seq_printf(s, "\t\tBITS=%u SCBR=%u DLYBS=%u DLYBCT=%u\n",
+				SPI_BFEXT(BITS, value) + 8,
+				SPI_BFEXT(SCBR, value),
+				SPI_BFEXT(DLYBS, value),
+				SPI_BFEXT(DLYBCT, value));
 	}
 
-	*plen = len;
+	seq_printf(s, "RPR:\t0x%08x\n", buf[SPI_RPR / 4]);
+	seq_printf(s, "RCR:\t0x%08x\n", buf[SPI_RCR / 4]);
+	seq_printf(s, "TPR:\t0x%08x\n", buf[SPI_TPR / 4]);
+	seq_printf(s, "TCR:\t0x%08x\n", buf[SPI_TCR / 4]);
+	seq_printf(s, "RNPR:\t0x%08x\n", buf[SPI_RNPR / 4]);
+	seq_printf(s, "RNCR:\t0x%08x\n", buf[SPI_RNCR / 4]);
+	seq_printf(s, "TNPR:\t0x%08x\n", buf[SPI_TNPR / 4]);
+	seq_printf(s, "TNCR:\t0x%08x\n", buf[SPI_TNCR / 4]);
+
+	value = buf[SPI_PTSR / 4];
+	seq_printf(s, "PTSR:\t0x%08x%s%s\n", value,
+			(value & SPI_BIT(RXTEN)) ? " RXTEN" : "",
+			(value & SPI_BIT(TXTEN)) ? " TXTEN" : "");
+
+	kfree(buf);
+
+	return 0;
 }
 
-/*
- * Submit next transfer for DMA.
- * lock is held, spi irq is blocked
- */
-static void atmel_spi_next_xfer(struct spi_master *master,
-				struct spi_message *msg)
+static int atmel_spi_regs_open(struct inode *inode, struct file *file)
 {
-	struct atmel_spi	*as = spi_master_get_devdata(master);
-	struct spi_transfer	*xfer;
-	u32			len, remaining;
-	u32			ieval;
-	dma_addr_t		tx_dma, rx_dma;
-
-	if (!as->current_transfer)
-		xfer = list_entry(msg->transfers.next,
-				struct spi_transfer, transfer_list);
-	else if (!as->next_transfer)
-		xfer = list_entry(as->current_transfer->transfer_list.next,
-				struct spi_transfer, transfer_list);
-	else
-		xfer = NULL;
-
-	if (xfer) {
-		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+	return single_open(file, atmel_spi_regs_show, inode->i_private);
+}
 
-		len = xfer->len;
-		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
-		remaining = xfer->len - len;
+static const struct file_operations atmel_spi_regs_fops = {
+	.owner		= THIS_MODULE,
+	.open		= atmel_spi_regs_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
 
-		spi_writel(as, RPR, rx_dma);
-		spi_writel(as, TPR, tx_dma);
+static void atmel_spi_init_debugfs(struct atmel_spi *as)
+{
+	struct dentry	*root;
+	struct dentry	*node;
 
-		if (msg->spi->bits_per_word > 8)
-			len >>= 1;
-		spi_writel(as, RCR, len);
-		spi_writel(as, TCR, len);
+	root = debugfs_create_dir(as->pdev->dev.bus_id, NULL);
+	if (IS_ERR(root))
+		/* Debugfs not enabled */
+		return;
+	if (!root)
+		/* Debugfs enabled, but failed to create directory */
+		goto err_root;
+
+	node = debugfs_create_file("regs", S_IRUSR, root, as,
+			&atmel_spi_regs_fops);
+	if (!node)
+		goto err;
+	node = debugfs_create_file("queue", S_IRUSR, root, as,
+			&atmel_spi_queue_fops);
+	if (!node)
+		goto err;
+
+	as->debugfs_root = root;
+	return;
+
+err:
+	debugfs_remove_recursive(root);
+err_root:
+	dev_err(&as->pdev->dev, "failed to initialize debugfs\n");
+}
 
-		dev_dbg(&msg->spi->dev,
-			"  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
-			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
-			xfer->rx_buf, xfer->rx_dma);
-	} else {
-		xfer = as->next_transfer;
-		remaining = as->next_remaining_bytes;
-	}
+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
+{
+	debugfs_remove_recursive(as->debugfs_root);
+}
 
-	as->current_transfer = xfer;
-	as->current_remaining_bytes = remaining;
+#else
+static void atmel_spi_init_debugfs(struct atmel_spi *as)
+{
 
-	if (remaining > 0)
-		len = remaining;
-	else if (!atmel_spi_xfer_is_last(msg, xfer)
-			&& atmel_spi_xfer_can_be_chained(xfer)) {
-		xfer = list_entry(xfer->transfer_list.next,
-				struct spi_transfer, transfer_list);
-		len = xfer->len;
-	} else
-		xfer = NULL;
+}
+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
+{
 
-	as->next_transfer = xfer;
+}
+#endif
 
-	if (xfer) {
-		u32	total;
+/*
+ * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
+ * they assume that spi slave device state will not change on deselect, so
+ * that automagic deselection is OK.  ("NPCSx rises if no data is to be
+ * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
+ * controllers have CSAAT and friends.
+ *
+ * Since the CSAAT functionality is a bit weird on newer controllers as
+ * well, we use GPIO to control nCSx pins on all controllers, updating
+ * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
+ * support active-high chipselects despite the controller's belief that
+ * only active-low devices/systems exists.
+ *
+ * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
+ * right when driven with GPIO.  ("Mode Fault does not allow more than one
+ * Master on Chip Select 0.")  No workaround exists for that ... so for
+ * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
+ * and (c) will trigger that first erratum in some cases.
+ *
+ * TODO: Test if the atmel_spi_is_v2() branch below works on
+ * AT91RM9200 if we use some other register than CSR0. However, don't
+ * do this unconditionally since AP7000 has an errata where the BITS
+ * field in CSR0 overrides all other CSRs.
+ */
 
-		total = len;
-		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
-		as->next_remaining_bytes = total - len;
+static void atmel_spi_set_csr(struct atmel_spi *as,
+		struct spi_device *spi, u32 csr)
+{
+	if (atmel_spi_is_v2())
+		spi_writel(as, CSR0, csr);
+	else
+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
+}
 
-		spi_writel(as, RNPR, rx_dma);
-		spi_writel(as, TNPR, tx_dma);
+static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
+{
+	struct atmel_spi_device *asd = spi->controller_state;
+	unsigned active = spi->mode & SPI_CS_HIGH;
 
-		if (msg->spi->bits_per_word > 8)
-			len >>= 1;
-		spi_writel(as, RNCR, len);
-		spi_writel(as, TNCR, len);
+	if (atmel_spi_is_v2()) {
+		/*
+		 * Always use CSR0. This ensures that the clock
+		 * switches to the correct idle polarity before we
+		 * toggle the CS.
+		 */
+		atmel_spi_set_csr(as, spi, asd->csr);
+		spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
+				| SPI_BIT(MSTR));
+		spi_readl(as, MR);
+		dev_vdbg(&spi->dev, "activate %u%s, csr0: %08x\n",
+				asd->npcs_pin, active ? " (low)" : "",
+				asd->csr);
 
-		dev_dbg(&msg->spi->dev,
-			"  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
-			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
-			xfer->rx_buf, xfer->rx_dma);
-		ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
+		gpio_set_value(asd->npcs_pin, active);
 	} else {
-		spi_writel(as, RNCR, 0);
-		spi_writel(as, TNCR, 0);
-		ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
-	}
+		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
+		int i;
+		u32 mr;
+		u32 csr;
+
+		/* Make sure clock polarity is correct */
+		for (i = 0; i < spi->master->num_chipselect; i++) {
+			csr = spi_readl(as, CSR0 + 4 * i);
+			if ((csr ^ cpol) & SPI_BIT(CPOL))
+				spi_writel(as, CSR0 + 4 * i,
+						csr ^ SPI_BIT(CPOL));
+		}
 
-	/* REVISIT: We're waiting for ENDRX before we start the next
-	 * transfer because we need to handle some difficult timing
-	 * issues otherwise. If we wait for ENDTX in one transfer and
-	 * then starts waiting for ENDRX in the next, it's difficult
-	 * to tell the difference between the ENDRX interrupt we're
-	 * actually waiting for and the ENDRX interrupt of the
-	 * previous transfer.
-	 *
-	 * It should be doable, though. Just not now...
-	 */
-	spi_writel(as, IER, ieval);
-	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
+		mr = spi_readl(as, MR);
+		mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
+		dev_vdbg(&spi->dev, "activate %u%s, mr: %08x csr: %08x\n",
+				asd->npcs_pin, active ? " (low)" : "",
+				mr, csr);
+		if (spi->chip_select != 0)
+			gpio_set_value(asd->npcs_pin, active);
+		spi_writel(as, MR, mr);
+	}
 }
 
-static void atmel_spi_next_message(struct spi_master *master)
+static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 {
-	struct atmel_spi	*as = spi_master_get_devdata(master);
-	struct spi_message	*msg;
-	struct spi_device	*spi;
-
-	BUG_ON(as->current_transfer);
-
-	msg = list_entry(as->queue.next, struct spi_message, queue);
-	spi = msg->spi;
+	struct atmel_spi_device *asd = spi->controller_state;
+	unsigned active = spi->mode & SPI_CS_HIGH;
+	u32 mr;
 
-	dev_dbg(master->dev.parent, "start message %p for %s\n",
-			msg, spi->dev.bus_id);
+	/* only deactivate *this* device; sometimes transfers to
+	 * another device may be active when this routine is called.
+	 */
+	mr = spi_readl(as, MR);
+	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
+		mr = SPI_BFINS(PCS, 0xf, mr);
+		spi_writel(as, MR, mr);
+	}
 
-	/* select chip if it's not still active */
-	if (as->stay) {
-		if (as->stay != spi) {
-			cs_deactivate(as, as->stay);
-			cs_activate(as, spi);
-		}
-		as->stay = NULL;
-	} else
-		cs_activate(as, spi);
+	dev_vdbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
+			asd->npcs_pin, active ? " (low)" : "",
+			mr);
 
-	atmel_spi_next_xfer(master, msg);
+	if (atmel_spi_is_v2() || spi->chip_select != 0)
+		gpio_set_value(asd->npcs_pin, !active);
 }
 
 /*
@@ -338,162 +477,460 @@
 	return 0;
 }
 
-static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
+static void atmel_spi_dma_unmap_xfer(struct atmel_spi *as,
 				     struct spi_transfer *xfer)
 {
 	if (xfer->tx_dma != INVALID_DMA_ADDRESS)
-		dma_unmap_single(master->dev.parent, xfer->tx_dma,
+		dma_unmap_single(&as->pdev->dev, xfer->tx_dma,
 				 xfer->len, DMA_TO_DEVICE);
 	if (xfer->rx_dma != INVALID_DMA_ADDRESS)
-		dma_unmap_single(master->dev.parent, xfer->rx_dma,
+		dma_unmap_single(&as->pdev->dev, xfer->rx_dma,
 				 xfer->len, DMA_FROM_DEVICE);
 }
 
-static void
-atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
-		struct spi_message *msg, int status, int stay)
+static void atmel_spi_dma_unmap_msg(struct atmel_spi *as, struct spi_message *msg)
 {
-	if (!stay || status < 0)
-		cs_deactivate(as, msg->spi);
-	else
-		as->stay = msg->spi;
+	struct spi_transfer	*xfer;
 
-	list_del(&msg->queue);
-	msg->status = status;
+	if (!msg->is_dma_mapped)
+		list_for_each_entry(xfer, &msg->transfers, transfer_list)
+			atmel_spi_dma_unmap_xfer(as, xfer);
+}
 
-	dev_dbg(master->dev.parent,
-		"xfer complete: %u bytes transferred\n",
-		msg->actual_length);
+static void atmel_spi_handle_error(struct atmel_spi *as,
+		struct spi_message *msg, int err)
+{
+	unsigned int timeout;
 
-	spin_unlock(&as->lock);
-	msg->complete(msg->context);
-	spin_lock(&as->lock);
+	/* Drain the buffers so that the hardware is ready for a new message */
+	for (timeout = 1000; timeout; timeout--)
+		if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
+			break;
+	if (!timeout)
+		dev_warn(&msg->spi->dev,
+			 "timeout waiting for TXEMPTY");
+	while (spi_readl(as, SR) & SPI_BIT(RDRF))
+		spi_readl(as, RDR);
 
-	as->current_transfer = NULL;
-	as->next_transfer = NULL;
+	/* Clear any overrun happening while cleaning up */
+	spi_readl(as, SR);
 
-	/* continue if needed */
-	if (list_empty(&as->queue) || as->stopping)
-		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-	else
-		atmel_spi_next_message(master);
+	msg->status = err;
+	as->error = 0;
 }
 
-static irqreturn_t
-atmel_spi_interrupt(int irq, void *dev_id)
+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
 {
-	struct spi_master	*master = dev_id;
-	struct atmel_spi	*as = spi_master_get_devdata(master);
-	struct spi_message	*msg;
-	struct spi_transfer	*xfer;
-	u32			status, pending, imr;
-	int			ret = IRQ_NONE;
+	int err;
 
-	spin_lock(&as->lock);
+	wait_event(as->wait, as->pending == 0);
+	err = as->error;
+	if (err) {
+		dev_warn(&msg->spi->dev,
+				"transfer error %d (%u/%u remaining)\n",
+				err, spi_readl(as, TCR), spi_readl(as, RCR));
 
-	xfer = as->current_transfer;
-	msg = list_entry(as->queue.next, struct spi_message, queue);
+		spi_writel(as, TNCR, 0);
+		spi_writel(as, RNCR, 0);
+		spi_writel(as, TCR, 0);
+		spi_writel(as, RCR, 0);
 
-	imr = spi_readl(as, IMR);
-	status = spi_readl(as, SR);
-	pending = status & imr;
+		atmel_spi_handle_error(as, msg, err);
 
-	if (pending & SPI_BIT(OVRES)) {
-		int timeout;
+		return err;
+	}
 
-		ret = IRQ_HANDLED;
+	msg->actual_length += as->pending_bytes;
+	as->pending_bytes = 0;
 
-		spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
-				     | SPI_BIT(OVRES)));
+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
+			msg->actual_length);
+
+	return 0;
+}
+
+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
+		struct spi_message *msg, struct spi_transfer *xfer)
+{
+	unsigned int	bits = xfer->bits_per_word;
+	unsigned int	speed_hz = xfer->speed_hz;
+	unsigned int	submitted = 0;
+	dma_addr_t	rx_dma;
+	dma_addr_t	tx_dma;
+
+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
+			xfer->len, xfer->rx_buf, xfer->tx_buf);
+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
+			xfer->cs_change, xfer->bits_per_word,
+			xfer->delay_usecs, xfer->speed_hz);
+
+	if (bits || speed_hz) {
+		struct atmel_spi_device *asd;
+		u32 csr;
+
+		if (atmel_spi_wait_idle(as, msg))
+			return 0;
+
+		asd = spi->controller_state;
+		csr = asd->csr;
+
+		if (bits)
+			csr = SPI_BFINS(BITS, csr, bits - 8);
+		if (speed_hz) {
+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
+			csr = SPI_BFINS(SCBR, csr, scbr);
+		}
+
+		atmel_spi_set_csr(as, spi, csr);
+	}
+
+	if (!bits)
+		bits = spi->bits_per_word;
+
+	/* PDC stuff starts here */
+	while (submitted < xfer->len) {
+		unsigned long len;
+
+		wait_event(as->wait, as->pending < 2);
 
 		/*
-		 * When we get an overrun, we disregard the current
-		 * transfer. Data will not be copied back from any
-		 * bounce buffer and msg->actual_len will not be
-		 * updated with the last xfer.
-		 *
-		 * We will also not process any remaning transfers in
-		 * the message.
-		 *
-		 * First, stop the transfer and unmap the DMA buffers.
+		 * This gives the RX side a slight advantage, making
+		 * overruns less likely.
 		 */
-		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-		if (!msg->is_dma_mapped)
-			atmel_spi_dma_unmap_xfer(master, xfer);
+		spi_writel(as, PTCR, SPI_BIT(TXTDIS));
+
+		len = xfer->len - submitted;
+		if (xfer->rx_buf) {
+			rx_dma = xfer->rx_dma + submitted;
+		} else {
+			rx_dma = as->buffer_dma;
+			len = min(len, BUFFER_SIZE);
+		}
+		if (xfer->tx_buf) {
+			tx_dma = xfer->tx_dma + submitted;
+		} else {
+			tx_dma = as->buffer_dma;
+			len = min(len, BUFFER_SIZE);
+			memset(as->buffer, 0, len);
+		}
+
+		submitted += len;
+		if (bits > 8)
+			len >>= 1;
+
+		spin_lock_irq(&as->lock);
+		if (as->error) {
+			spin_unlock_irq(&as->lock);
+			atmel_spi_wait_idle(as, msg);
+			return 0;
+		}
+
+		spi_writel(as, RNPR, rx_dma);
+		spi_writel(as, RNCR, len);
+		spi_writel(as, TNPR, tx_dma);
+		spi_writel(as, TNCR, len);
+		spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
+				| SPI_BIT(OVRES));
+		spi_writel(as, PTCR, SPI_BIT(RXTEN) | SPI_BIT(TXTEN));
+		as->pending++;
+		spin_unlock_irq(&as->lock);
+	}
 
-		/* REVISIT: udelay in irq is unfriendly */
+	as->pending_bytes += submitted;
+
+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
+			|| xfer->speed_hz) {
+		struct atmel_spi_device	*asd = spi->controller_state;
+		int			err;
+
+		err = atmel_spi_wait_idle(as, msg);
 		if (xfer->delay_usecs)
 			udelay(xfer->delay_usecs);
+		atmel_spi_set_csr(as, spi, asd->csr);
+		if (err)
+			return 0;
+
+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
+			cs_deactivate(as, spi);
+			udelay(1);
+			cs_activate(as, spi);
+		}
+	}
 
-		dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
-			 spi_readl(as, TCR), spi_readl(as, RCR));
+	return xfer->cs_change;
+}
 
-		/*
-		 * Clean up DMA registers and make sure the data
-		 * registers are empty.
-		 */
-		spi_writel(as, RNCR, 0);
-		spi_writel(as, TNCR, 0);
-		spi_writel(as, RCR, 0);
-		spi_writel(as, TCR, 0);
-		for (timeout = 1000; timeout; timeout--)
-			if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
-				break;
-		if (!timeout)
-			dev_warn(master->dev.parent,
-				 "timeout waiting for TXEMPTY");
-		while (spi_readl(as, SR) & SPI_BIT(RDRF))
-			spi_readl(as, RDR);
-
-		/* Clear any overrun happening while cleaning up */
-		spi_readl(as, SR);
-
-		atmel_spi_msg_done(master, as, msg, -EIO, 0);
-	} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
-		ret = IRQ_HANDLED;
+#else /* Use DMA engine framework, not PDC */
 
-		spi_writel(as, IDR, pending);
+static void atmel_spi_dma_complete(void *param)
+{
+	struct atmel_spi	*as = param;
 
-		if (as->current_remaining_bytes == 0) {
-			msg->actual_length += xfer->len;
+	as->pending = 0;
+	as->sg_len = 0;
+	wake_up(&as->wait);
+}
 
-			if (!msg->is_dma_mapped)
-				atmel_spi_dma_unmap_xfer(master, xfer);
+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
+{
+	struct dma_chan			*tx_chan = as->tx_chan;
+	struct dma_chan			*rx_chan = as->rx_chan;
+	struct dma_device		*dma = rx_chan->device;
+	struct dma_async_tx_descriptor	*tx_desc;
+	struct dma_async_tx_descriptor	*rx_desc;
+	int				err;
+
+	dev_vdbg(&msg->spi->dev, "wait_idle: sg_len=%u\n", as->sg_len);
+
+	if (!as->sg_len)
+		return 0;
+
+	sg_mark_end(as->tx_sg + (as->sg_len - 1));
+	sg_mark_end(as->rx_sg + (as->sg_len - 1));
+	as->pending = 1;
+	smp_wmb();
+
+	tx_desc = dma->device_prep_slave_sg(tx_chan,
+			as->tx_sg, as->sg_len, DMA_TO_DEVICE,
+			DMA_COMPL_SKIP_SRC_UNMAP | DMA_CTRL_ACK);
+	rx_desc = dma->device_prep_slave_sg(rx_chan,
+			as->rx_sg, as->sg_len, DMA_FROM_DEVICE,
+			DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP
+			| DMA_CTRL_ACK);
+	rx_desc->callback = atmel_spi_dma_complete;
+	rx_desc->callback_param = as;
+	rx_desc->tx_submit(rx_desc);
+	tx_desc->tx_submit(tx_desc);
+	dma->device_issue_pending(rx_chan);
+	dma->device_issue_pending(tx_chan);
+
+	spi_writel(as, IER, SPI_BIT(OVRES));
+	wait_event(as->wait, !as->pending);
+	spi_writel(as, IDR, SPI_BIT(OVRES));
+	err = as->error;
+	if (err) {
+		dev_warn(&msg->spi->dev, "transfer error %d\n", err);
 
-			/* REVISIT: udelay in irq is unfriendly */
-			if (xfer->delay_usecs)
-				udelay(xfer->delay_usecs);
-
-			if (atmel_spi_xfer_is_last(msg, xfer)) {
-				/* report completed message */
-				atmel_spi_msg_done(master, as, msg, 0,
-						xfer->cs_change);
-			} else {
-				if (xfer->cs_change) {
-					cs_deactivate(as, msg->spi);
-					udelay(1);
-					cs_activate(as, msg->spi);
-				}
+		dma->device_terminate_all(tx_chan);
+		dma->device_terminate_all(rx_chan);
+
+		atmel_spi_handle_error(as, msg, err);
+
+		return err;
+	}
+
+	msg->actual_length += as->pending_bytes;
+	as->pending_bytes = 0;
+	sg_init_table(as->rx_sg, MAX_SG_SEGS);
+	sg_init_table(as->tx_sg, MAX_SG_SEGS);
+
+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
+			msg->actual_length);
+
+	return 0;
+}
+
+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
+		struct spi_message *msg, struct spi_transfer *xfer)
+{
+	unsigned int	bits = xfer->bits_per_word;
+	unsigned int	speed_hz = xfer->speed_hz;
+	unsigned int	submitted = 0;
+	unsigned int	i;
+
+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
+			xfer->len, xfer->rx_buf, xfer->tx_buf);
+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
+			xfer->cs_change, xfer->bits_per_word,
+			xfer->delay_usecs, xfer->speed_hz);
+
+	if (bits || speed_hz) {
+		struct atmel_spi_device *asd;
+		u32 csr;
+
+		if (atmel_spi_wait_idle(as, msg))
+			return 0;
+
+		asd = spi->controller_state;
+		csr = asd->csr;
+
+		if (bits)
+			csr = SPI_BFINS(BITS, csr, bits - 8);
+		if (speed_hz) {
+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
+			csr = SPI_BFINS(SCBR, csr, scbr);
+		}
+
+		atmel_spi_set_csr(as, spi, csr);
+	}
+
+	if (!bits)
+		bits = spi->bits_per_word;
+
+	i = as->sg_len;
+	while (submitted < xfer->len) {
+		unsigned long len;
+
+		if (i == MAX_SG_SEGS) {
+			if (atmel_spi_wait_idle(as, msg))
+				return 0;
+			i = 0;
+		}
+
+		len = xfer->len - submitted;
+		if (!xfer->rx_buf || !xfer->tx_buf)
+			len = min(len, BUFFER_SIZE);
+
+		if (xfer->rx_buf) {
+			sg_set_buf(&as->rx_sg[i], xfer->rx_buf + submitted, len);
+			as->rx_sg[i].dma_address = xfer->rx_dma + submitted;
+		} else {
+			sg_set_buf(&as->rx_sg[i], as->buffer, len);
+			as->rx_sg[i].dma_address = as->buffer_dma;
+		}
+		if (xfer->tx_buf) {
+			sg_set_buf(&as->tx_sg[i], xfer->tx_buf + submitted, len);
+			as->tx_sg[i].dma_address = xfer->tx_dma + submitted;
+		} else {
+			sg_set_buf(&as->tx_sg[i], as->buffer, len);
+			as->tx_sg[i].dma_address = as->buffer_dma;
+			memset(as->buffer, 0, len);
+		}
+
+		submitted += len;
+		as->sg_len = ++i;
+	}
+
+	as->pending_bytes += submitted;
 
-				/*
-				 * Not done yet. Submit the next transfer.
-				 *
-				 * FIXME handle protocol options for xfer
-				 */
-				atmel_spi_next_xfer(master, msg);
+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
+			|| xfer->speed_hz) {
+		struct atmel_spi_device	*asd = spi->controller_state;
+		int			err;
+
+		err = atmel_spi_wait_idle(as, msg);
+		if (xfer->delay_usecs)
+			udelay(xfer->delay_usecs);
+		atmel_spi_set_csr(as, spi, asd->csr);
+		if (err)
+			return 0;
+
+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
+			cs_deactivate(as, spi);
+			udelay(1);
+			cs_activate(as, spi);
+		}
+	}
+
+	return xfer->cs_change;
+}
+
+#endif /* PDC vs. DMA engine */
+
+static void atmel_spi_work(struct work_struct *work)
+{
+	struct atmel_spi	*as;
+
+	as = container_of(work, struct atmel_spi, work);
+
+	spin_lock_irq(&as->lock);
+	while (!list_empty(&as->queue)) {
+		struct spi_message	*msg;
+		struct spi_transfer	*xfer;
+		struct spi_device	*spi;
+		int			cs_change = 0;
+
+		if (as->stopping)
+			break;
+
+		msg = list_entry(as->queue.next, struct spi_message, queue);
+		spin_unlock_irq(&as->lock);
+
+		spi = msg->spi;
+
+		if (as->stay) {
+			if (as->stay != spi) {
+				cs_deactivate(as, as->stay);
+				cs_activate(as, spi);
 			}
+			as->stay = NULL;
 		} else {
-			/*
-			 * Keep going, we still have data to send in
-			 * the current transfer.
-			 */
-			atmel_spi_next_xfer(master, msg);
+			cs_activate(as, spi);
+		}
+
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+		sg_init_table(as->rx_sg, MAX_SG_SEGS);
+		sg_init_table(as->tx_sg, MAX_SG_SEGS);
+#endif
+
+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+			if (msg->status != -EINPROGRESS)
+				break;
+			cs_change = atmel_spi_submit_xfer(as, spi, msg, xfer);
+		}
+
+		if (msg->status == -EINPROGRESS) {
+			if (atmel_spi_wait_idle(as, msg))
+				cs_change = 1;
+			else
+				msg->status = 0;
 		}
+		if (!cs_change)
+			cs_deactivate(as, spi);
+		else
+			as->stay = spi;
+
+		atmel_spi_dma_unmap_msg(as, msg);
+
+		msg->complete(msg->context);
+		spin_lock_irq(&as->lock);
+		list_del(&msg->queue);
 	}
+	spin_unlock_irq(&as->lock);
+}
+
+static irqreturn_t atmel_spi_interrupt(int irq, void *dev_id)
+{
+	struct atmel_spi	*as = dev_id;
+	u32			status;
+	u32			mask;
+	u32			pending;
+
+	spin_lock(&as->lock);
+
+	status = spi_readl(as, SR);
+	mask = spi_readl(as, IMR);
+	pending = status & mask;
+
+	if (pending & SPI_BIT(OVRES)) {
+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
+		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+#endif
+		spi_writel(as, IDR, ~0UL);
+		as->error = -EIO;
+		as->pending = 0;
+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
+	} else if (pending & SPI_BIT(RXBUFF)) {
+		spi_writel(as, IDR, ~0UL);
+		as->pending = 0;
+	} else if (pending & SPI_BIT(ENDRX)) {
+		spi_writel(as, IDR, SPI_BIT(ENDRX));
+		as->pending--;
+#endif
+	} else {
+		dev_err(&as->pdev->dev,
+			"unexpected interrupt: SR=0x%08x MR=0x%08x\n",
+				status, mask);
+		spi_writel(as, IDR, pending);
+	}
+
+	spi_readl(as, IMR);
+	wake_up(&as->wait);
 
 	spin_unlock(&as->lock);
 
-	return ret;
+	return IRQ_HANDLED;
 }
 
 /* the spi->mode bits understood by this driver: */
@@ -502,6 +939,7 @@
 static int atmel_spi_setup(struct spi_device *spi)
 {
 	struct atmel_spi	*as;
+	struct atmel_spi_device	*asd;
 	u32			scbr, csr;
 	unsigned int		bits = spi->bits_per_word;
 	unsigned long		bus_hz;
@@ -536,21 +974,14 @@
 	}
 
 	/* see notes above re chipselect */
-	if (cpu_is_at91rm9200()
+	if (!atmel_spi_is_v2()
 			&& spi->chip_select == 0
 			&& (spi->mode & SPI_CS_HIGH)) {
 		dev_dbg(&spi->dev, "setup: can't be active-high\n");
 		return -EINVAL;
 	}
 
-	/*
-	 * Pre-new_1 chips start out at half the peripheral
-	 * bus speed.
-	 */
-	bus_hz = clk_get_rate(as->clk);
-	if (!as->new_1)
-		bus_hz /= 2;
-
+	bus_hz = as->base_hz;
 	if (spi->max_speed_hz) {
 		/*
 		 * Calculate the lowest divider that satisfies the
@@ -589,11 +1020,20 @@
 
 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
 	npcs_pin = (unsigned int)spi->controller_data;
-	if (!spi->controller_state) {
+	asd = spi->controller_state;
+	if (!asd) {
+		asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
+		if (!asd)
+			return -ENOMEM;
+
 		ret = gpio_request(npcs_pin, spi->dev.bus_id);
-		if (ret)
+		if (ret) {
+			kfree(asd);
 			return ret;
-		spi->controller_state = (void *)npcs_pin;
+		}
+
+		asd->npcs_pin = npcs_pin;
+		spi->controller_state = asd;
 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 	} else {
 		unsigned long		flags;
@@ -605,11 +1045,14 @@
 		spin_unlock_irqrestore(&as->lock, flags);
 	}
 
+	asd->csr = csr;
+
 	dev_dbg(&spi->dev,
 		"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
 		bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
 
-	spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
+	if (!atmel_spi_is_v2())
+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 
 	return 0;
 }
@@ -620,74 +1063,81 @@
 	struct spi_transfer	*xfer;
 	unsigned long		flags;
 	struct device		*controller = spi->master->dev.parent;
+	int			ret;
 
 	as = spi_master_get_devdata(spi->master);
 
-	dev_dbg(controller, "new message %p submitted for %s\n",
+	dev_vdbg(controller, "new message %p submitted for %s\n",
 			msg, spi->dev.bus_id);
 
 	if (unlikely(list_empty(&msg->transfers)
 			|| !spi->max_speed_hz))
 		return -EINVAL;
 
-	if (as->stopping)
-		return -ESHUTDOWN;
-
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 		if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
 			dev_dbg(&spi->dev, "missing rx or tx buf\n");
 			return -EINVAL;
 		}
 
-		/* FIXME implement these protocol options!! */
-		if (xfer->bits_per_word || xfer->speed_hz) {
-			dev_dbg(&spi->dev, "no protocol options yet\n");
-			return -ENOPROTOOPT;
+		if (xfer->bits_per_word && (xfer->bits_per_word < 8
+					|| xfer->bits_per_word > 16)) {
+			dev_dbg(&spi->dev, "unsupported bits_per_word\n");
+			return -EINVAL;
+		}
+		if (xfer->speed_hz) {
+			unsigned long divider;
+			divider = DIV_ROUND_UP(as->base_hz, xfer->speed_hz);
+
+			if (divider > 255) {
+				dev_dbg(&spi->dev, "speed_hz too low\n");
+				return -EINVAL;
+			}
 		}
 
 		/*
 		 * DMA map early, for performance (empties dcache ASAP) and
 		 * better fault reporting.  This is a DMA-only driver.
-		 *
-		 * NOTE that if dma_unmap_single() ever starts to do work on
-		 * platforms supported by this driver, we would need to clean
-		 * up mappings for previously-mapped transfers.
 		 */
 		if (!msg->is_dma_mapped) {
-			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
+			if (atmel_spi_dma_map_xfer(as, xfer) < 0) {
+				/* Ick */
+				while (xfer->transfer_list.prev != &msg->transfers) {
+					xfer = list_entry(xfer->transfer_list.prev,
+							struct spi_transfer,
+							transfer_list);
+					atmel_spi_dma_unmap_xfer(as, xfer);
+				}
+
 				return -ENOMEM;
+			}
 		}
 	}
 
-#ifdef VERBOSE
-	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-		dev_dbg(controller,
-			"  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
-			xfer, xfer->len,
-			xfer->tx_buf, xfer->tx_dma,
-			xfer->rx_buf, xfer->rx_dma);
-	}
-#endif
-
 	msg->status = -EINPROGRESS;
 	msg->actual_length = 0;
 
 	spin_lock_irqsave(&as->lock, flags);
-	list_add_tail(&msg->queue, &as->queue);
-	if (!as->current_transfer)
-		atmel_spi_next_message(spi->master);
+	if (as->stopping) {
+		ret = -ESHUTDOWN;
+	} else {
+		list_add_tail(&msg->queue, &as->queue);
+		queue_work(as->workqueue, &as->work);
+		ret = 0;
+	}
 	spin_unlock_irqrestore(&as->lock, flags);
 
-	return 0;
+	return ret;
 }
 
 static void atmel_spi_cleanup(struct spi_device *spi)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
+	struct atmel_spi_device	*asd = spi->controller_state;
 	unsigned		gpio = (unsigned) spi->controller_data;
 	unsigned long		flags;
 
-	if (!spi->controller_state)
+	if (!asd)
 		return;
 
 	spin_lock_irqsave(&as->lock, flags);
@@ -697,14 +1147,131 @@
 	}
 	spin_unlock_irqrestore(&as->lock, flags);
 
+	spi->controller_state = NULL;
 	gpio_free(gpio);
+	kfree(asd);
+}
+
+static void atmel_spi_stop_queue(struct atmel_spi *as)
+{
+	struct spi_message	*msg;
+
+	/*
+	 * Prevent any new messages from being submitted, cancel any
+	 * submitted but not-yet-started messages, and wait for any
+	 * ongoing messages to complete.
+	 */
+	as->stopping = true;
+	smp_wmb();
+	cancel_work_sync(&as->work);
+
+	/* Terminate anything that was left over */
+	list_for_each_entry(msg, &as->queue, queue) {
+		atmel_spi_dma_unmap_msg(as, msg);
+		msg->status = -ESHUTDOWN;
+		msg->complete(msg->context);
+	}
+}
+
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+static enum dma_state_client atmel_spi_dma_chan_avail(struct atmel_spi *as,
+		struct dma_chan *chan, struct dma_chan **pchan)
+{
+	enum dma_state_client ret = DMA_NAK;
+
+	if (!*pchan) {
+		as->stopping = false;
+		*pchan = chan;
+		ret = DMA_ACK;
+	}
+
+	return ret;
+}
+
+static enum dma_state_client atmel_spi_dma_chan_removed(struct atmel_spi *as,
+		struct dma_chan *chan, struct dma_chan **pchan)
+{
+	enum dma_state_client ret = DMA_NAK;
+
+	if (chan == *pchan) {
+		atmel_spi_stop_queue(as);
+		*pchan = NULL;
+		ret = DMA_ACK;
+	}
+
+	return ret;
+}
+
+static enum dma_state_client atmel_spi_dma_rx_event(struct dma_client *client,
+		struct dma_chan *chan, enum dma_state state)
+{
+	struct atmel_spi	*as;
+	enum dma_state_client	ret = DMA_NAK;
+
+	as = container_of(client, struct atmel_spi, rx_client);
+
+	switch (state) {
+	case DMA_RESOURCE_AVAILABLE:
+		ret = atmel_spi_dma_chan_avail(as, chan, &as->rx_chan);
+		if (ret == DMA_ACK)
+			dev_info(&as->pdev->dev,
+					"Using %s for DMA RX transfers\n",
+					chan->dev.bus_id);
+		break;
+
+	case DMA_RESOURCE_REMOVED:
+		ret = atmel_spi_dma_chan_removed(as, chan, &as->rx_chan);
+		if (ret == DMA_ACK)
+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
+					chan->dev.bus_id);
+		break;
+
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static enum dma_state_client atmel_spi_dma_tx_event(struct dma_client *client,
+		struct dma_chan *chan, enum dma_state state)
+{
+	struct atmel_spi	*as;
+	enum dma_state_client	ret = DMA_NAK;
+
+	as = container_of(client, struct atmel_spi, tx_client);
+
+	switch (state) {
+	case DMA_RESOURCE_AVAILABLE:
+		ret = atmel_spi_dma_chan_avail(as, chan, &as->tx_chan);
+		if (ret == DMA_ACK)
+			dev_info(&as->pdev->dev,
+					"Using %s for DMA TX transfers\n",
+					chan->dev.bus_id);
+		break;
+
+	case DMA_RESOURCE_REMOVED:
+		ret = atmel_spi_dma_chan_removed(as, chan, &as->tx_chan);
+		if (ret == DMA_ACK)
+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
+					chan->dev.bus_id);
+		break;
+
+	default:
+		break;
+	}
+
+	return ret;
 }
+#endif
 
 /*-------------------------------------------------------------------------*/
 
 static int __init atmel_spi_probe(struct platform_device *pdev)
 {
 	struct resource		*regs;
+	struct resource		*buf;
+	struct atmel_spi_pdata	*pdata;
 	int			irq;
 	struct clk		*clk;
 	int			ret;
@@ -719,6 +1286,14 @@
 	if (irq < 0)
 		return irq;
 
+	pdata = pdev->dev.platform_data;
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+	if (!pdata) {
+		dev_dbg(&pdev->dev, "no platform data\n");
+		return -ENXIO;
+	}
+#endif
+
 	clk = clk_get(&pdev->dev, "spi_clk");
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
@@ -738,31 +1313,65 @@
 
 	as = spi_master_get_devdata(master);
 
-	/*
-	 * Scratch buffer is used for throwaway rx and tx data.
-	 * It's coherent to minimize dcache pollution.
-	 */
-	as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
-					&as->buffer_dma, GFP_KERNEL);
-	if (!as->buffer)
-		goto out_free;
+	buf = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (buf) {
+		as->buffer_dma = buf->start;
+		as->buffer_size
+			= rounddown_pow_of_two(buf->end - buf->start + 1);
+		if (as->buffer_size) {
+			as->buffer = (void __force *)ioremap(buf->start,
+					as->buffer_size);
+			if (as->buffer)
+				as->always_bounce = true;
+		}
+	}
+
+	if (!as->buffer) {
+		/*
+		 * Scratch buffer is used for throwaway rx and tx data.
+		 * It's coherent to minimize dcache pollution.
+		 */
+		as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
+						&as->buffer_dma, GFP_KERNEL);
+		if (!as->buffer)
+			goto out_free;
+	}
 
 	spin_lock_init(&as->lock);
+	init_waitqueue_head(&as->wait);
 	INIT_LIST_HEAD(&as->queue);
+	INIT_WORK(&as->work, atmel_spi_work);
 	as->pdev = pdev;
+	as->clk = clk;
 	as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 	if (!as->regs)
 		goto out_free_buffer;
-	as->irq = irq;
-	as->clk = clk;
-	if (!cpu_is_at91rm9200())
-		as->new_1 = 1;
 
-	ret = request_irq(irq, atmel_spi_interrupt, 0,
-			pdev->dev.bus_id, master);
+	ret = request_irq(irq, atmel_spi_interrupt, 0, pdev->dev.bus_id, as);
 	if (ret)
 		goto out_unmap_regs;
 
+	as->workqueue = create_singlethread_workqueue(pdev->dev.bus_id);
+	if (!as->workqueue)
+		goto out_free_irq;
+
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+	as->rx_client.event_callback = atmel_spi_dma_rx_event;
+	dma_cap_set(DMA_SLAVE, as->rx_client.cap_mask);
+	as->rx_client.slave = pdata->rx_dma_slave;
+	pdata->rx_dma_slave->rx_reg = regs->start + SPI_RDR + 3;
+
+	as->tx_client.event_callback = atmel_spi_dma_tx_event;
+	dma_cap_set(DMA_SLAVE, as->tx_client.cap_mask);
+	as->tx_client.slave = pdata->tx_dma_slave;
+	pdata->tx_dma_slave->tx_reg = regs->start + SPI_TDR + 3;
+
+	dma_async_client_register(&as->rx_client);
+	dma_async_client_register(&as->tx_client);
+	dma_async_client_chan_request(&as->rx_client);
+	dma_async_client_chan_request(&as->tx_client);
+#endif
+
 	/* Initialize the hardware */
 	clk_enable(clk);
 	spi_writel(as, CR, SPI_BIT(SWRST));
@@ -771,9 +1380,19 @@
 	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 	spi_writel(as, CR, SPI_BIT(SPIEN));
 
+	/* v1 chips start out at half the peripheral bus speed. */
+	as->base_hz = clk_get_rate(clk);
+	if (!atmel_spi_is_v2())
+		as->base_hz /= 2;
+
 	/* go! */
 	dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
 			(unsigned long)regs->start, irq);
+	if (as->always_bounce)
+		dev_info(&pdev->dev, "Using bounce buffer at 0x%08x len %zu\n",
+				as->buffer_dma, as->buffer_size);
+
+	atmel_spi_init_debugfs(as);
 
 	ret = spi_register_master(master);
 	if (ret)
@@ -782,10 +1401,17 @@
 	return 0;
 
 out_reset_hw:
+	atmel_spi_cleanup_debugfs(as);
 	spi_writel(as, CR, SPI_BIT(SWRST));
 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 	clk_disable(clk);
-	free_irq(irq, master);
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+	dma_async_client_unregister(&as->tx_client);
+	dma_async_client_unregister(&as->rx_client);
+#endif
+	destroy_workqueue(as->workqueue);
+out_free_irq:
+	free_irq(irq, as);
 out_unmap_regs:
 	iounmap(as->regs);
 out_free_buffer:
@@ -801,34 +1427,34 @@
 {
 	struct spi_master	*master = platform_get_drvdata(pdev);
 	struct atmel_spi	*as = spi_master_get_devdata(master);
-	struct spi_message	*msg;
 
-	/* reset the hardware and block queue progress */
-	spin_lock_irq(&as->lock);
-	as->stopping = 1;
-	spi_writel(as, CR, SPI_BIT(SWRST));
-	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
-	spi_readl(as, SR);
-	spin_unlock_irq(&as->lock);
+	/* Stop the queue */
+	atmel_spi_stop_queue(as);
 
-	/* Terminate remaining queued transfers */
-	list_for_each_entry(msg, &as->queue, queue) {
-		/* REVISIT unmapping the dma is a NOP on ARM and AVR32
-		 * but we shouldn't depend on that...
-		 */
-		msg->status = -ESHUTDOWN;
-		msg->complete(msg->context);
-	}
+	atmel_spi_cleanup_debugfs(as);
 
-	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
-			as->buffer_dma);
+	/* Shut down the hardware */
+	spi_writel(as, CR, SPI_BIT(SWRST));
+	spi_readl(as, SR);
 
+	/* Clean up */
+	spi_unregister_master(master);
+	free_irq(platform_get_irq(pdev, 0), as);
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+	dma_async_client_unregister(&as->tx_client);
+	dma_async_client_unregister(&as->rx_client);
+#endif
+	destroy_workqueue(as->workqueue);
+	if (as->always_bounce)
+		iounmap((void __iomem __force *)as->buffer);
+	else
+		dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
+				as->buffer_dma);
+	iounmap(as->regs);
 	clk_disable(as->clk);
 	clk_put(as->clk);
-	free_irq(as->irq, master);
-	iounmap(as->regs);
 
-	spi_unregister_master(master);
+	spi_master_put(master);
 
 	return 0;
 }
@@ -840,7 +1466,9 @@
 	struct spi_master	*master = platform_get_drvdata(pdev);
 	struct atmel_spi	*as = spi_master_get_devdata(master);
 
+	atmel_spi_stop_queue(as);
 	clk_disable(as->clk);
+
 	return 0;
 }
 
@@ -850,6 +1478,9 @@
 	struct atmel_spi	*as = spi_master_get_devdata(master);
 
 	clk_enable(as->clk);
+	as->stopping = false;
+	smp_wmb();
+
 	return 0;
 }
 
@@ -871,7 +1502,12 @@
 
 static int __init atmel_spi_init(void)
 {
-	return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
+	int ret;
+
+	ret = platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
+	if (ret)
+		pr_notice("atmel_spi probe failed: %d\n", ret);
+	return ret;
 }
 module_init(atmel_spi_init);
 
@@ -882,6 +1518,6 @@
 module_exit(atmel_spi_exit);
 
 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
-MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
-MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
+MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:atmel_spi");
diff -urN linux-2.6.28.2-0rig//drivers/spi/Kconfig linux-2.6.28.2/drivers/spi/Kconfig
--- linux-2.6.28.2-0rig//drivers/spi/Kconfig	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/spi/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -53,9 +53,14 @@
 
 comment "SPI Master Controller Drivers"
 
+config SPI_ATMEL_HAVE_PDC
+	def_bool y
+	depends on (ARCH_AT91 || CPU_AT32AP700X)
+
 config SPI_ATMEL
 	tristate "Atmel SPI Controller"
 	depends on (ARCH_AT91 || AVR32)
+	depends on SPI_ATMEL_HAVE_PDC || DMA_ENGINE
 	help
 	  This selects a driver for the Atmel SPI Controller, present on
 	  many AT32 (AVR32) and AT91 (ARM) chips.
diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ehci-avr32.c linux-2.6.28.2/drivers/usb/host/ehci-avr32.c
--- linux-2.6.28.2-0rig//drivers/usb/host/ehci-avr32.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/host/ehci-avr32.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,213 @@
+/*
+ * AVR32 EHCI bus and power management glue
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+static struct clk	*utmi_clk;
+static struct clk	*hclk;
+
+static void ehci_avr32_start_clocks(struct device *dev)
+{
+	dev_vdbg(dev, "starting clocks...\n");
+
+	clk_enable(utmi_clk);
+	clk_enable(hclk);
+}
+
+static void ehci_avr32_stop_clocks(struct device *dev)
+{
+	dev_vdbg(dev, "stopping clocks...\n");
+
+	clk_disable(hclk);
+	clk_disable(utmi_clk);
+}
+
+static int ehci_avr32_setup(struct usb_hcd *hcd)
+{
+	struct device	*dev = hcd->self.controller;
+	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
+	int		ret;
+
+	ehci_avr32_start_clocks(dev);
+
+	ehci->caps = hcd->regs;
+	ehci->regs = hcd->regs
+		+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+	dbg_hcs_params(ehci, "reset");
+	dbg_hcc_params(ehci, "reset");
+
+	/* cache this readonly data; minimize chip reads */
+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+	ret = ehci_halt(ehci);
+	if (ret)
+		goto err;
+
+	/* data structure init */
+	ret = ehci_init(hcd);
+	if (ret)
+		goto err;
+
+	ehci->sbrn = 0x20;
+	ehci_port_power(ehci, 0);
+
+	return 0;
+
+err:
+	ehci_avr32_stop_clocks(dev);
+	return ret;
+}
+
+static void ehci_avr32_shutdown(struct usb_hcd *hcd)
+{
+	ehci_shutdown(hcd);
+	ehci_avr32_stop_clocks(hcd->self.controller);
+}
+
+static const struct hc_driver ehci_avr32_hc_driver = {
+	.description		= hcd_name,
+	.product_desc		= "AVR32 USBH (EHCI)",
+	.hcd_priv_size		= sizeof(struct ehci_hcd),
+
+	.irq			= ehci_irq,
+	.flags			= HCD_MEMORY | HCD_USB2,
+
+	.reset			= ehci_avr32_setup,
+	.start			= ehci_run,
+	.stop			= ehci_stop,
+	.shutdown		= ehci_avr32_shutdown,
+
+	.urb_enqueue		= ehci_urb_enqueue,
+	.urb_dequeue		= ehci_urb_dequeue,
+	.endpoint_disable	= ehci_endpoint_disable,
+
+	.get_frame_number	= ehci_get_frame,
+
+	.hub_status_data	= ehci_hub_status_data,
+	.hub_control		= ehci_hub_control,
+	.bus_suspend		= ehci_bus_suspend,
+	.bus_resume		= ehci_bus_resume,
+	.relinquish_port	= ehci_relinquish_port,
+	.port_handed_over	= ehci_port_handed_over,
+};
+
+static int ehci_avr32_probe(struct platform_device *pdev)
+{
+	struct resource		*reg_res;
+	struct usb_hcd		*hcd;
+	struct ehci_hcd		*ehci;
+	int			irq;
+	int			ret;
+
+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!reg_res) {
+		dev_dbg(&pdev->dev, "no MMIO resource\n");
+		return -ENXIO;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_dbg(&pdev->dev, "no IRQ resource\n");
+		return -ENXIO;
+	}
+
+	hclk = clk_get(&pdev->dev, "hclk");
+	if (IS_ERR(hclk)) {
+		dev_dbg(&pdev->dev, "no HSB clock\n");
+		return -ENXIO;
+	}
+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
+	if (IS_ERR(utmi_clk)) {
+		dev_dbg(&pdev->dev, "no UTMI clock\n");
+		ret = -ENXIO;
+		goto err_utmi_clk;
+	}
+
+	if (!request_mem_region(reg_res->start,
+				reg_res->end - reg_res->start + 1,
+				hcd_name)) {
+		dev_dbg(&pdev->dev, "config regs busy\n");
+		ret = -EBUSY;
+		goto err_request_mmio;
+	}
+
+	ret = -ENOMEM;
+
+	hcd = usb_create_hcd(&ehci_avr32_hc_driver, &pdev->dev, "ehci-avr32");
+	if (!hcd) {
+		dev_dbg(&pdev->dev, "failed to create hcd\n");
+		goto err_create_hcd;
+	}
+
+	hcd->rsrc_start = reg_res->start;
+	hcd->rsrc_len = reg_res->end - reg_res->start + 1;
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs) {
+		dev_dbg(&pdev->dev, "failed to map registers\n");
+		goto err_ioremap;
+	}
+
+	ehci = hcd_to_ehci(hcd);
+	ehci->big_endian_mmio = 1;
+	ehci->big_endian_desc = 1;
+
+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+	if (ret)
+		goto err_add_hcd;
+
+	return 0;
+
+err_add_hcd:
+	iounmap(hcd->regs);
+err_ioremap:
+	usb_put_hcd(hcd);
+err_create_hcd:
+	release_mem_region(reg_res->start, reg_res->end - reg_res->start + 1);
+err_request_mmio:
+	clk_put(utmi_clk);
+err_utmi_clk:
+	clk_put(hclk);
+
+	return ret;
+}
+
+static int ehci_avr32_remove(struct platform_device *pdev)
+{
+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	clk_put(utmi_clk);
+	clk_put(hclk);
+
+	return 0;
+}
+
+/* FIXME */
+#define ehci_avr32_suspend	NULL
+#define ehci_avr32_resume	NULL
+
+static struct platform_driver ehci_hcd_avr32_driver = {
+	.probe		= ehci_avr32_probe,
+	.remove		= ehci_avr32_remove,
+	.suspend	= ehci_avr32_suspend,
+	.resume		= ehci_avr32_resume,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.driver		= {
+		.name	= "ehci",
+	},
+};
diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ehci-hcd.c linux-2.6.28.2/drivers/usb/host/ehci-hcd.c
--- linux-2.6.28.2-0rig//drivers/usb/host/ehci-hcd.c	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/host/ehci-hcd.c	2009-01-29 08:52:50.000000000 +0100
@@ -1014,6 +1014,11 @@
 #define	PLATFORM_DRIVER		ehci_hcd_au1xxx_driver
 #endif
 
+#ifdef CONFIG_AVR32
+#include "ehci-avr32.c"
+#define PLATFORM_DRIVER		ehci_hcd_avr32_driver
+#endif
+
 #ifdef CONFIG_PPC_PS3
 #include "ehci-ps3.c"
 #define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
diff -urN linux-2.6.28.2-0rig//drivers/usb/host/Kconfig linux-2.6.28.2/drivers/usb/host/Kconfig
--- linux-2.6.28.2-0rig//drivers/usb/host/Kconfig	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/host/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -73,12 +73,12 @@
 
 config USB_EHCI_BIG_ENDIAN_MMIO
 	bool
-	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX)
+	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || AVR32)
 	default y
 
 config USB_EHCI_BIG_ENDIAN_DESC
 	bool
-	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
+	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || AVR32)
 	default y
 
 config USB_EHCI_FSL
@@ -196,17 +196,19 @@
 config USB_OHCI_BIG_ENDIAN_DESC
 	bool
 	depends on USB_OHCI_HCD
+	default y if AVR32
 	default n
 
 config USB_OHCI_BIG_ENDIAN_MMIO
 	bool
 	depends on USB_OHCI_HCD
+	default y if AVR32
 	default n
 
 config USB_OHCI_LITTLE_ENDIAN
 	bool
 	depends on USB_OHCI_HCD
-	default n if STB03xxx || PPC_MPC52xx
+	default n if STB03xxx || PPC_MPC52xx || AVR32
 	default y
 
 config USB_UHCI_HCD
diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ohci-avr32.c linux-2.6.28.2/drivers/usb/host/ohci-avr32.c
--- linux-2.6.28.2-0rig//drivers/usb/host/ohci-avr32.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/host/ohci-avr32.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,208 @@
+/*
+ * AVR32 OHCI bus and power management glue
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+/* Grr! The core layer doesn't let us keep private data anywhere! */
+static struct clk	*ohci_clk;
+static struct clk	*utmi_clk;
+static struct clk	*hclk;
+
+static void ohci_avr32_start_clocks(struct device *dev)
+{
+	dev_vdbg(dev, "starting clocks...\n");
+
+	clk_enable(ohci_clk);
+	clk_enable(utmi_clk);
+	clk_enable(hclk);
+}
+
+static void ohci_avr32_stop_clocks(struct device *dev)
+{
+	dev_vdbg(dev, "stopping clocks...\n");
+
+	clk_disable(hclk);
+	clk_disable(utmi_clk);
+	clk_disable(ohci_clk);
+}
+
+static int ohci_avr32_start(struct usb_hcd *hcd)
+{
+	struct device	*dev = hcd->self.controller;
+	struct ohci_hcd	*ohci = hcd_to_ohci(hcd);
+	int		ret;
+
+	ohci_avr32_start_clocks(dev);
+
+	ret = ohci_init(ohci);
+	if (ret)
+		goto err_ohci_init;
+
+	ret = ohci_run(ohci);
+	if (likely(!ret))
+		return 0;
+
+	ohci_stop(hcd);
+
+err_ohci_init:
+	ohci_avr32_stop_clocks(dev);
+	return ret;
+}
+
+static void ohci_avr32_stop(struct usb_hcd *hcd)
+{
+	ohci_stop(hcd);
+	ohci_avr32_stop_clocks(hcd->self.controller);
+}
+
+static const struct hc_driver ohci_avr32_hc_driver = {
+	.description		= hcd_name,
+	.product_desc		= "AVR32 USBH (OHCI)",
+	.hcd_priv_size		= sizeof(struct ohci_hcd),
+
+	.irq			= ohci_irq,
+	.flags			= HCD_USB11 | HCD_MEMORY,
+
+	.start			= ohci_avr32_start,
+	.stop			= ohci_avr32_stop,
+	.shutdown		= ohci_shutdown,
+
+	.urb_enqueue		= ohci_urb_enqueue,
+	.urb_dequeue		= ohci_urb_dequeue,
+	.endpoint_disable	= ohci_endpoint_disable,
+	.get_frame_number	= ohci_get_frame,
+	.hub_status_data	= ohci_hub_status_data,
+	.hub_control		= ohci_hub_control,
+#ifdef CONFIG_PM
+	.bus_suspend		= ohci_bus_suspend,
+	.bus_resume		= ohci_bus_resume,
+#endif
+	.start_port_reset	= ohci_start_port_reset,
+};
+
+static int ohci_avr32_probe(struct platform_device *pdev)
+{
+	struct resource		*regs;
+	struct usb_hcd		*hcd;
+	int			irq;
+	int			ret;
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_dbg(&pdev->dev, "no MMIO resource\n");
+		return -ENXIO;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_dbg(&pdev->dev, "no IRQ resource\n");
+		return -ENXIO;
+	}
+
+	hclk = clk_get(&pdev->dev, "hclk");
+	if (IS_ERR(hclk)) {
+		dev_dbg(&pdev->dev, "no HSB clock\n");
+		return -ENXIO;
+	}
+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
+	if (IS_ERR(utmi_clk)) {
+		dev_dbg(&pdev->dev, "no UTMI clock\n");
+		ret = -ENXIO;
+		goto err_utmi_clk;
+	}
+	ohci_clk = clk_get(&pdev->dev, "ohci_clk");
+	if (IS_ERR(ohci_clk)) {
+		dev_dbg(&pdev->dev, "no OHCI clock\n");
+		ret = -ENXIO;
+		goto err_ohci_clk;
+	}
+
+	if (!request_mem_region(regs->start, regs->end - regs->start + 1,
+				hcd_name)) {
+		dev_dbg(&pdev->dev, "config regs busy\n");
+		ret = -EBUSY;
+		goto err_request_mmio;
+	}
+
+	ret = -ENOMEM;
+	hcd = usb_create_hcd(&ohci_avr32_hc_driver, &pdev->dev, "ohci-avr32");
+	if (!hcd) {
+		dev_dbg(&pdev->dev, "failed to create hcd\n");
+		goto err_create_hcd;
+	}
+
+	hcd->rsrc_start = regs->start;
+	hcd->rsrc_len = regs->end - regs->start + 1;
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs) {
+		dev_dbg(&pdev->dev, "failed to map registers\n");
+		goto err_ioremap;
+	}
+
+	ohci_hcd_init(hcd_to_ohci(hcd));
+
+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+	if (ret)
+		goto err_add_hcd;
+
+	return 0;
+
+err_add_hcd:
+	iounmap(hcd->regs);
+err_ioremap:
+	usb_put_hcd(hcd);
+err_create_hcd:
+	release_mem_region(regs->start, regs->end - regs->start + 1);
+err_request_mmio:
+	clk_put(ohci_clk);
+err_ohci_clk:
+	clk_put(utmi_clk);
+err_utmi_clk:
+	clk_put(hclk);
+
+	return ret;
+}
+
+static int ohci_avr32_remove(struct platform_device *pdev)
+{
+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+	usb_remove_hcd(hcd);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	clk_put(utmi_clk);
+	clk_put(ohci_clk);
+	clk_put(hclk);
+
+	return 0;
+}
+
+/* FIXME */
+#define ohci_avr32_suspend	NULL
+#define ohci_avr32_resume	NULL
+
+static struct platform_driver ohci_hcd_avr32_driver = {
+	.probe		= ohci_avr32_probe,
+	.remove		= ohci_avr32_remove,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.suspend	= ohci_avr32_suspend,
+	.resume		= ohci_avr32_resume,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ohci",
+	},
+};
+MODULE_ALIAS("platform:ohci");
diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ohci.h linux-2.6.28.2/drivers/usb/host/ohci.h
--- linux-2.6.28.2-0rig//drivers/usb/host/ohci.h	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/host/ohci.h	2009-01-29 08:52:50.000000000 +0100
@@ -646,8 +646,10 @@
  * some big-endian SOC implementations.  Same thing happens with PSW access.
  */
 
-#ifdef CONFIG_PPC_MPC52xx
+#if defined(CONFIG_PPC_MPC52xx)
 #define big_endian_frame_no_quirk(ohci)	(ohci->flags & OHCI_QUIRK_FRAME_NO)
+#elif defined(CONFIG_AVR32)
+#define big_endian_frame_no_quirk(ohci)	1
 #else
 #define big_endian_frame_no_quirk(ohci)	0
 #endif
diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ohci-hcd.c linux-2.6.28.2/drivers/usb/host/ohci-hcd.c
--- linux-2.6.28.2-0rig//drivers/usb/host/ohci-hcd.c	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/host/ohci-hcd.c	2009-01-29 08:52:50.000000000 +0100
@@ -1042,6 +1042,11 @@
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
+#ifdef CONFIG_AVR32
+#include "ohci-avr32.c"
+#define PLATFORM_DRIVER		ohci_hcd_avr32_driver
+#endif
+
 #ifdef CONFIG_ARCH_PNX4008
 #include "ohci-pnx4008.c"
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
diff -urN linux-2.6.28.2-0rig//drivers/usb/Kconfig linux-2.6.28.2/drivers/usb/Kconfig
--- linux-2.6.28.2-0rig//drivers/usb/Kconfig	2009-01-29 08:39:25.000000000 +0100
+++ linux-2.6.28.2/drivers/usb/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -56,6 +56,7 @@
 	default y if PPC_83xx
 	default y if SOC_AU1200
 	default y if ARCH_IXP4XX
+	default y if AVR32
 	default PCI
 
 # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
diff -urN linux-2.6.28.2-0rig//drivers/watchdog/at32ap700x_wdt.c linux-2.6.28.2/drivers/watchdog/at32ap700x_wdt.c
--- linux-2.6.28.2-0rig//drivers/watchdog/at32ap700x_wdt.c	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/watchdog/at32ap700x_wdt.c	1970-01-01 01:00:00.000000000 +0100
@@ -1,449 +0,0 @@
-/*
- * Watchdog driver for Atmel AT32AP700X devices
- *
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
- * Errata: WDT Clear is blocked after WDT Reset
- *
- * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
- * register, preventing the program to clear the next Watchdog Timer Reset.
- *
- * If you still want to use the WDT after a WDT reset a small code can be
- * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
- * and use a GPIO pin to reset the system. This method requires that one of the
- * GPIO pins are available and connected externally to the RESET_N pin. After
- * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
- * the pin tristated with pullup.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/miscdevice.h>
-#include <linux/fs.h>
-#include <linux/platform_device.h>
-#include <linux/watchdog.h>
-#include <linux/uaccess.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#define TIMEOUT_MIN		1
-#define TIMEOUT_MAX		2
-#define TIMEOUT_DEFAULT		TIMEOUT_MAX
-
-/* module parameters */
-static int timeout =  TIMEOUT_DEFAULT;
-module_param(timeout, int, 0);
-MODULE_PARM_DESC(timeout,
-		"Timeout value. Limited to be 1 or 2 seconds. (default="
-		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
-
-static int nowayout = WATCHDOG_NOWAYOUT;
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
-		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-
-/* Watchdog registers and write/read macro */
-#define WDT_CTRL		0x00
-#define WDT_CTRL_EN		   0
-#define WDT_CTRL_PSEL		   8
-#define WDT_CTRL_KEY		  24
-
-#define WDT_CLR			0x04
-
-#define WDT_RCAUSE		0x10
-#define WDT_RCAUSE_POR		   0
-#define WDT_RCAUSE_EXT		   2
-#define WDT_RCAUSE_WDT		   3
-#define WDT_RCAUSE_JTAG		   4
-#define WDT_RCAUSE_SERP		   5
-
-#define WDT_BIT(name)		(1 << WDT_##name)
-#define WDT_BF(name, value)	((value) << WDT_##name)
-
-#define wdt_readl(dev, reg)				\
-	__raw_readl((dev)->regs + WDT_##reg)
-#define wdt_writel(dev, reg, value)			\
-	__raw_writel((value), (dev)->regs + WDT_##reg)
-
-struct wdt_at32ap700x {
-	void __iomem		*regs;
-	spinlock_t		io_lock;
-	int			timeout;
-	int			boot_status;
-	unsigned long		users;
-	struct miscdevice	miscdev;
-};
-
-static struct wdt_at32ap700x *wdt;
-static char expect_release;
-
-/*
- * Disable the watchdog.
- */
-static inline void at32_wdt_stop(void)
-{
-	unsigned long psel;
-
-	spin_lock(&wdt->io_lock);
-	psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
-	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
-	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
-	spin_unlock(&wdt->io_lock);
-}
-
-/*
- * Enable and reset the watchdog.
- */
-static inline void at32_wdt_start(void)
-{
-	/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
-	unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
-
-	spin_lock(&wdt->io_lock);
-	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
-			| WDT_BF(CTRL_PSEL, psel)
-			| WDT_BF(CTRL_KEY, 0x55));
-	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
-			| WDT_BF(CTRL_PSEL, psel)
-			| WDT_BF(CTRL_KEY, 0xaa));
-	spin_unlock(&wdt->io_lock);
-}
-
-/*
- * Pat the watchdog timer.
- */
-static inline void at32_wdt_pat(void)
-{
-	spin_lock(&wdt->io_lock);
-	wdt_writel(wdt, CLR, 0x42);
-	spin_unlock(&wdt->io_lock);
-}
-
-/*
- * Watchdog device is opened, and watchdog starts running.
- */
-static int at32_wdt_open(struct inode *inode, struct file *file)
-{
-	if (test_and_set_bit(1, &wdt->users))
-		return -EBUSY;
-
-	at32_wdt_start();
-	return nonseekable_open(inode, file);
-}
-
-/*
- * Close the watchdog device.
- */
-static int at32_wdt_close(struct inode *inode, struct file *file)
-{
-	if (expect_release == 42) {
-		at32_wdt_stop();
-	} else {
-		dev_dbg(wdt->miscdev.parent,
-			"unexpected close, not stopping watchdog!\n");
-		at32_wdt_pat();
-	}
-	clear_bit(1, &wdt->users);
-	expect_release = 0;
-	return 0;
-}
-
-/*
- * Change the watchdog time interval.
- */
-static int at32_wdt_settimeout(int time)
-{
-	/*
-	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max prescaler is
-	 * 2 ^ 16 allowing up to 2 seconds timeout.
-	 */
-	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX))
-		return -EINVAL;
-
-	/*
-	 * Set new watchdog time. It will be used when at32_wdt_start() is
-	 * called.
-	 */
-	wdt->timeout = time;
-	return 0;
-}
-
-/*
- * Get the watchdog status.
- */
-static int at32_wdt_get_status(void)
-{
-	int rcause;
-	int status = 0;
-
-	rcause = wdt_readl(wdt, RCAUSE);
-
-	switch (rcause) {
-	case WDT_BIT(RCAUSE_EXT):
-		status = WDIOF_EXTERN1;
-		break;
-	case WDT_BIT(RCAUSE_WDT):
-		status = WDIOF_CARDRESET;
-		break;
-	case WDT_BIT(RCAUSE_POR):  /* fall through */
-	case WDT_BIT(RCAUSE_JTAG): /* fall through */
-	case WDT_BIT(RCAUSE_SERP): /* fall through */
-	default:
-		break;
-	}
-
-	return status;
-}
-
-static struct watchdog_info at32_wdt_info = {
-	.identity	= "at32ap700x watchdog",
-	.options	= WDIOF_SETTIMEOUT |
-			  WDIOF_KEEPALIVEPING |
-			  WDIOF_MAGICCLOSE,
-};
-
-/*
- * Handle commands from user-space.
- */
-static long at32_wdt_ioctl(struct file *file,
-				unsigned int cmd, unsigned long arg)
-{
-	int ret = -ENOTTY;
-	int time;
-	void __user *argp = (void __user *)arg;
-	int __user *p = argp;
-
-	switch (cmd) {
-	case WDIOC_GETSUPPORT:
-		ret = copy_to_user(argp, &at32_wdt_info,
-				sizeof(at32_wdt_info)) ? -EFAULT : 0;
-		break;
-	case WDIOC_GETSTATUS:
-		ret = put_user(0, p);
-		break;
-	case WDIOC_GETBOOTSTATUS:
-		ret = put_user(wdt->boot_status, p);
-		break;
-	case WDIOC_SETOPTIONS:
-		ret = get_user(time, p);
-		if (ret)
-			break;
-		if (time & WDIOS_DISABLECARD)
-			at32_wdt_stop();
-		if (time & WDIOS_ENABLECARD)
-			at32_wdt_start();
-		ret = 0;
-		break;
-	case WDIOC_KEEPALIVE:
-		at32_wdt_pat();
-		ret = 0;
-		break;
-	case WDIOC_SETTIMEOUT:
-		ret = get_user(time, p);
-		if (ret)
-			break;
-		ret = at32_wdt_settimeout(time);
-		if (ret)
-			break;
-		/* Enable new time value */
-		at32_wdt_start();
-		/* fall through */
-	case WDIOC_GETTIMEOUT:
-		ret = put_user(wdt->timeout, p);
-		break;
-	}
-
-	return ret;
-}
-
-static ssize_t at32_wdt_write(struct file *file, const char __user *data,
-				size_t len, loff_t *ppos)
-{
-	/* See if we got the magic character 'V' and reload the timer */
-	if (len) {
-		if (!nowayout) {
-			size_t i;
-
-			/*
-			 * note: just in case someone wrote the magic
-			 * character five months ago...
-			 */
-			expect_release = 0;
-
-			/*
-			 * scan to see whether or not we got the magic
-			 * character
-			 */
-			for (i = 0; i != len; i++) {
-				char c;
-				if (get_user(c, data + i))
-					return -EFAULT;
-				if (c == 'V')
-					expect_release = 42;
-			}
-		}
-		/* someone wrote to us, we should pat the watchdog */
-		at32_wdt_pat();
-	}
-	return len;
-}
-
-static const struct file_operations at32_wdt_fops = {
-	.owner		= THIS_MODULE,
-	.llseek		= no_llseek,
-	.unlocked_ioctl	= at32_wdt_ioctl,
-	.open		= at32_wdt_open,
-	.release	= at32_wdt_close,
-	.write		= at32_wdt_write,
-};
-
-static int __init at32_wdt_probe(struct platform_device *pdev)
-{
-	struct resource	*regs;
-	int ret;
-
-	if (wdt) {
-		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
-		return -EBUSY;
-	}
-
-	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!regs) {
-		dev_dbg(&pdev->dev, "missing mmio resource\n");
-		return -ENXIO;
-	}
-
-	wdt = kzalloc(sizeof(struct wdt_at32ap700x), GFP_KERNEL);
-	if (!wdt) {
-		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
-		return -ENOMEM;
-	}
-
-	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
-	if (!wdt->regs) {
-		ret = -ENOMEM;
-		dev_dbg(&pdev->dev, "could not map I/O memory\n");
-		goto err_free;
-	}
-
-	spin_lock_init(&wdt->io_lock);
-	wdt->boot_status = at32_wdt_get_status();
-
-	/* Work-around for watchdog silicon errata. */
-	if (wdt->boot_status & WDIOF_CARDRESET) {
-		dev_info(&pdev->dev, "CPU must be reset with external "
-				"reset or POR due to silicon errata.\n");
-		ret = -EIO;
-		goto err_iounmap;
-	} else {
-		wdt->users = 0;
-	}
-	wdt->miscdev.minor = WATCHDOG_MINOR;
-	wdt->miscdev.name = "watchdog";
-	wdt->miscdev.fops = &at32_wdt_fops;
-
-	if (at32_wdt_settimeout(timeout)) {
-		at32_wdt_settimeout(TIMEOUT_DEFAULT);
-		dev_dbg(&pdev->dev,
-			"default timeout invalid, set to %d sec.\n",
-			TIMEOUT_DEFAULT);
-	}
-
-	ret = misc_register(&wdt->miscdev);
-	if (ret) {
-		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
-		goto err_iounmap;
-	}
-
-	platform_set_drvdata(pdev, wdt);
-	wdt->miscdev.parent = &pdev->dev;
-	dev_info(&pdev->dev,
-		"AT32AP700X WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
-		wdt->regs, wdt->timeout, nowayout);
-
-	return 0;
-
-err_iounmap:
-	iounmap(wdt->regs);
-err_free:
-	kfree(wdt);
-	wdt = NULL;
-	return ret;
-}
-
-static int __exit at32_wdt_remove(struct platform_device *pdev)
-{
-	if (wdt && platform_get_drvdata(pdev) == wdt) {
-		/* Stop the timer before we leave */
-		if (!nowayout)
-			at32_wdt_stop();
-
-		misc_deregister(&wdt->miscdev);
-		iounmap(wdt->regs);
-		kfree(wdt);
-		wdt = NULL;
-		platform_set_drvdata(pdev, NULL);
-	}
-	return 0;
-}
-
-static void at32_wdt_shutdown(struct platform_device *pdev)
-{
-	at32_wdt_stop();
-}
-
-#ifdef CONFIG_PM
-static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-{
-	at32_wdt_stop();
-	return 0;
-}
-
-static int at32_wdt_resume(struct platform_device *pdev)
-{
-	if (wdt->users)
-		at32_wdt_start();
-	return 0;
-}
-#else
-#define at32_wdt_suspend NULL
-#define at32_wdt_resume NULL
-#endif
-
-/* work with hotplug and coldplug */
-MODULE_ALIAS("platform:at32_wdt");
-
-static struct platform_driver at32_wdt_driver = {
-	.remove		= __exit_p(at32_wdt_remove),
-	.suspend	= at32_wdt_suspend,
-	.resume		= at32_wdt_resume,
-	.driver		= {
-		.name	= "at32_wdt",
-		.owner	= THIS_MODULE,
-	},
-	.shutdown	= at32_wdt_shutdown,
-};
-
-static int __init at32_wdt_init(void)
-{
-	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
-}
-module_init(at32_wdt_init);
-
-static void __exit at32_wdt_exit(void)
-{
-	platform_driver_unregister(&at32_wdt_driver);
-}
-module_exit(at32_wdt_exit);
-
-MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
-MODULE_DESCRIPTION("Watchdog driver for Atmel AT32AP700X");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff -urN linux-2.6.28.2-0rig//drivers/watchdog/at32_wdt.c linux-2.6.28.2/drivers/watchdog/at32_wdt.c
--- linux-2.6.28.2-0rig//drivers/watchdog/at32_wdt.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/drivers/watchdog/at32_wdt.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,620 @@
+/*
+ * Watchdog driver for Atmel AVR32 devices
+ *
+ * Copyright (C) 2005-2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * AT32AP700x Errata: WDT Clear is blocked after WDT Reset
+ *
+ * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
+ * register, preventing the program to clear the next Watchdog Timer Reset.
+ *
+ * If you still want to use the WDT after a WDT reset a small code can be
+ * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
+ * and use a GPIO pin to reset the system. This method requires that one of the
+ * GPIO pins are available and connected externally to the RESET_N pin. After
+ * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
+ * the pin tristated with pullup.
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/platform_device.h>
+#include <linux/watchdog.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/log2.h>
+#include <linux/spinlock.h>
+
+#include <mach/cpu.h>
+#include <mach/pm.h>
+
+/*
+ * AT32AP700x uses a 16-bit prescaler. This limits the timeout range
+ * somewhat. Later chips use a 32-bit prescaler.
+ */
+#define TIMEOUT_MIN		1
+#ifdef CONFIG_CPU_AT32AP700X
+# define TIMEOUT_MAX		2
+# define TIMEOUT_DEFAULT	TIMEOUT_MAX
+#else
+# define TIMEOUT_MAX		131072
+# define TIMEOUT_DEFAULT	64
+#endif
+
+/* module parameters */
+static int timeout =  TIMEOUT_DEFAULT;
+module_param(timeout, int, 0);
+MODULE_PARM_DESC(timeout,
+		"Timeout value. Any power of two between 1 and "
+		__MODULE_STRING(TIMEOUT_MAX) " seconds. (default="
+		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
+		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+/* Watchdog registers and write/read macro */
+#define WDT_CTRL		0x00
+#define WDT_CTRL_EN		   0
+#define WDT_CTRL_PSEL		   8
+#define WDT_CTRL_CEN		  16
+#define WDT_CTRL_CSEL		  17
+#define WDT_CTRL_KEY		  24
+
+#define WDT_CLR			0x04
+
+#define WDT_BIT(name)		(1 << WDT_##name)
+#define WDT_BF(name, value)	((value) << WDT_##name)
+
+#define wdt_readl(dev, reg)				\
+	__raw_readl((dev)->regs + WDT_##reg)
+#define wdt_writel(dev, reg, value)			\
+	__raw_writel((value), (dev)->regs + WDT_##reg)
+
+struct wdt_at32 {
+	void __iomem		*regs;
+	struct clk		*pclk;
+	struct clk		*src_clk;
+	spinlock_t		io_lock;
+	int			timeout;
+	int			boot_status;
+	unsigned long		users;
+	struct miscdevice	miscdev;
+};
+
+static struct wdt_at32 *wdt;
+static char expect_release;
+
+static inline void wdt_clk_enable(struct wdt_at32 *w)
+{
+	if (!cpu_is_at32ap7000())
+		clk_enable(w->pclk);
+}
+
+static inline void wdt_clk_disable(struct wdt_at32 *w)
+{
+	if (!cpu_is_at32ap7000())
+		clk_disable(w->pclk);
+}
+
+static inline int at32_wdt_version(void)
+{
+	if (cpu_is_at32ap7000())
+		return 1;
+	if (cpu_is_at32ap7200())
+		return 3;
+
+	BUG();
+}
+
+static unsigned long at32_wdt_calc_psel(int timeout)
+{
+	if (at32_wdt_version() == 1)
+		/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
+		return (timeout > 1) ? 0xf : 0xe;
+
+	return order_base_2(timeout) + 14;
+}
+
+/*
+ * Disable the watchdog.
+ */
+static inline void at32_wdt_stop(void)
+{
+	unsigned long ctrl;
+	unsigned long ctrl_mask = 0;
+
+	switch (at32_wdt_version()) {
+	case 3:
+		ctrl_mask |= (1 << WDT_CTRL_CEN) | (1 << WDT_CTRL_CSEL);
+		/* fall through */
+	case 2:
+		ctrl_mask |= 0x1f << WDT_CTRL_PSEL;
+		break;
+	case 1:
+		ctrl_mask |= 0x0f << WDT_CTRL_PSEL;
+		break;
+	}
+
+	wdt_clk_enable(wdt);
+	spin_lock(&wdt->io_lock);
+	ctrl = wdt_readl(wdt, CTRL);
+	ctrl &= ctrl_mask;
+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
+	spin_unlock(&wdt->io_lock);
+	wdt_clk_disable(wdt);
+}
+
+/*
+ * Enable and reset the watchdog.
+ */
+static inline void at32_wdt_start(void)
+{
+	unsigned long psel;
+	unsigned long ctrl;
+
+	psel = at32_wdt_calc_psel(wdt->timeout);
+	ctrl = WDT_BIT(CTRL_EN) | WDT_BF(CTRL_PSEL, psel);
+
+	if (at32_wdt_version() >= 3)
+		ctrl |= wdt_readl(wdt, CTRL)
+			& (WDT_BIT(CTRL_CSEL) | WDT_BIT(CTRL_CEN));
+
+	wdt_clk_enable(wdt);
+	spin_lock(&wdt->io_lock);
+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
+	spin_unlock(&wdt->io_lock);
+	wdt_clk_disable(wdt);
+}
+
+/*
+ * Pat the watchdog timer.
+ */
+static inline void at32_wdt_pat(void)
+{
+	wdt_clk_enable(wdt);
+	spin_lock(&wdt->io_lock);
+	wdt_writel(wdt, CLR, 0x42);
+	spin_unlock(&wdt->io_lock);
+	wdt_clk_disable(wdt);
+}
+
+/*
+ * Watchdog device is opened, and watchdog starts running.
+ */
+static int at32_wdt_open(struct inode *inode, struct file *file)
+{
+	if (test_and_set_bit(1, &wdt->users))
+		return -EBUSY;
+
+	at32_wdt_start();
+	return nonseekable_open(inode, file);
+}
+
+/*
+ * Close the watchdog device.
+ */
+static int at32_wdt_close(struct inode *inode, struct file *file)
+{
+	if (expect_release == 42) {
+		at32_wdt_stop();
+	} else {
+		dev_dbg(wdt->miscdev.parent,
+			"unexpected close, not stopping watchdog!\n");
+		at32_wdt_pat();
+	}
+	clear_bit(1, &wdt->users);
+	expect_release = 0;
+	return 0;
+}
+
+/*
+ * Change the watchdog time interval.
+ */
+static int at32_wdt_settimeout(int time)
+{
+	/*
+	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max
+	 * prescaler is 2 ^ 16 (or 2 ^ 32) allowing up to TIMEOUT_MAX
+	 * seconds timeout.
+	 */
+	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX)
+			|| !is_power_of_2(time))
+		return -EINVAL;
+
+	/*
+	 * Set new watchdog time. It will be used when at32_wdt_start() is
+	 * called.
+	 */
+	wdt->timeout = time;
+	return 0;
+}
+
+/*
+ * Get the watchdog status.
+ */
+static int at32_wdt_get_status(void)
+{
+	int rcause;
+	int status = 0;
+
+	rcause = at32_get_reset_cause();
+
+	switch (rcause) {
+	case AT32_RCAUSE_BOD:
+		status = WDIOF_POWERUNDER;
+		break;
+	case AT32_RCAUSE_EXT:
+		status = WDIOF_EXTERN1;
+		break;
+	case AT32_RCAUSE_JTAG:
+	case AT32_RCAUSE_JTAGHARD:
+	case AT32_RCAUSE_OCDRST:
+		status = WDIOF_EXTERN2;
+		break;
+	case AT32_RCAUSE_WDT:
+		status = WDIOF_CARDRESET;
+		break;
+	case AT32_RCAUSE_POR:
+	case AT32_RCAUSE_NTAE:
+	case AT32_RCAUSE_SLEEP:
+	case AT32_RCAUSE_CPUERR:
+	default:
+		break;
+	}
+
+	return status;
+}
+
+static struct watchdog_info at32_wdt_info = {
+	.identity	= "at32 watchdog",
+	.options	= WDIOF_SETTIMEOUT |
+			  WDIOF_KEEPALIVEPING |
+			  WDIOF_MAGICCLOSE,
+};
+
+/*
+ * Handle commands from user-space.
+ */
+static long at32_wdt_ioctl(struct file *file,
+				unsigned int cmd, unsigned long arg)
+{
+	int ret = -ENOTTY;
+	int time;
+	void __user *argp = (void __user *)arg;
+	int __user *p = argp;
+
+	switch (cmd) {
+	case WDIOC_GETSUPPORT:
+		ret = copy_to_user(argp, &at32_wdt_info,
+				sizeof(at32_wdt_info)) ? -EFAULT : 0;
+		break;
+	case WDIOC_GETSTATUS:
+		ret = put_user(0, p);
+		break;
+	case WDIOC_GETBOOTSTATUS:
+		ret = put_user(wdt->boot_status, p);
+		break;
+	case WDIOC_SETOPTIONS:
+		ret = get_user(time, p);
+		if (ret)
+			break;
+		if (time & WDIOS_DISABLECARD)
+			at32_wdt_stop();
+		if (time & WDIOS_ENABLECARD)
+			at32_wdt_start();
+		ret = 0;
+		break;
+	case WDIOC_KEEPALIVE:
+		at32_wdt_pat();
+		ret = 0;
+		break;
+	case WDIOC_SETTIMEOUT:
+		ret = get_user(time, p);
+		if (ret)
+			break;
+		ret = at32_wdt_settimeout(time);
+		if (ret)
+			break;
+		/* Enable new time value */
+		at32_wdt_start();
+		/* fall through */
+	case WDIOC_GETTIMEOUT:
+		ret = put_user(wdt->timeout, p);
+		break;
+	}
+
+	return ret;
+}
+
+static ssize_t at32_wdt_write(struct file *file, const char __user *data,
+				size_t len, loff_t *ppos)
+{
+	/* See if we got the magic character 'V' and reload the timer */
+	if (len) {
+		if (!nowayout) {
+			size_t i;
+
+			/*
+			 * note: just in case someone wrote the magic
+			 * character five months ago...
+			 */
+			expect_release = 0;
+
+			/*
+			 * scan to see whether or not we got the magic
+			 * character
+			 */
+			for (i = 0; i != len; i++) {
+				char c;
+				if (get_user(c, data + i))
+					return -EFAULT;
+				if (c == 'V')
+					expect_release = 42;
+			}
+		}
+		/* someone wrote to us, we should pat the watchdog */
+		at32_wdt_pat();
+	}
+	return len;
+}
+
+static const struct file_operations at32_wdt_fops = {
+	.owner		= THIS_MODULE,
+	.llseek		= no_llseek,
+	.unlocked_ioctl	= at32_wdt_ioctl,
+	.open		= at32_wdt_open,
+	.release	= at32_wdt_close,
+	.write		= at32_wdt_write,
+};
+
+static int __init at32_wdt_enable_source_clock(struct platform_device *pdev)
+{
+	struct clk	*clk;
+	unsigned int	csel;
+	u32		ctrl;
+
+	/* Only v3+ have selectable source clock */
+	if (at32_wdt_version() < 3)
+		return 0;
+
+	csel = 1;
+
+	/*
+	 * Prefer the much more accurate crystal oscillator in favor
+	 * of the RC oscillator.
+	 */
+	clk = clk_get(NULL, "osc32");
+	if (IS_ERR(clk)) {
+		csel = 0;
+		clk = clk_get(NULL, "rcosc");
+	}
+	if (IS_ERR(clk)) {
+		dev_dbg(&pdev->dev, "No source clock\n");
+		return -ENXIO;
+	}
+
+	clk_enable(clk);
+
+	dev_info(&pdev->dev, "Using 32 kHz %s oscillator\n",
+			csel ? "crystal" : "RC");
+
+	wdt_clk_enable(wdt);
+	ctrl = (csel << WDT_CTRL_CSEL) | (1 << WDT_CTRL_CEN);
+
+	/*
+	 * Make sure the WDT is disabled, and disable any clocks that
+	 * may have been selected earlier.
+	 */
+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
+
+	/* Wait for the clock to become properly deselected */
+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
+		cpu_relax();
+
+	/* Select the new clock */
+	wdt_writel(wdt, CTRL, ctrl | (0x55 << WDT_CTRL_KEY));
+	wdt_writel(wdt, CTRL, ctrl | (0xaa << WDT_CTRL_KEY));
+
+	/* Wait for the new clock to become usable */
+	while (!(wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN)))
+		cpu_relax();
+
+	wdt_clk_disable(wdt);
+	return 0;
+}
+
+static void at32_wdt_disable_source_clock(void)
+{
+	wdt_clk_enable(wdt);
+
+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
+
+	/* Wait for the clock to become properly deselected */
+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
+		cpu_relax();
+
+	wdt_clk_disable(wdt);
+}
+
+static int __init at32_wdt_probe(struct platform_device *pdev)
+{
+	struct resource	*regs;
+	int ret;
+
+	if (wdt) {
+		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
+		return -EBUSY;
+	}
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_dbg(&pdev->dev, "missing mmio resource\n");
+		return -ENXIO;
+	}
+
+	wdt = kzalloc(sizeof(struct wdt_at32), GFP_KERNEL);
+	if (!wdt) {
+		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
+		return -ENOMEM;
+	}
+
+	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
+	if (!wdt->regs) {
+		ret = -ENOMEM;
+		dev_dbg(&pdev->dev, "could not map I/O memory\n");
+		goto err_free;
+	}
+
+	if (!cpu_is_at32ap7000()) {
+		wdt->pclk = clk_get(&pdev->dev, "pclk");
+		if (IS_ERR(wdt->pclk)) {
+			dev_dbg(&pdev->dev, "no peripheral clock\n");
+			ret = -ENXIO;
+			goto err_iounmap;
+		}
+	}
+
+	ret = at32_wdt_enable_source_clock(pdev);
+	if (ret)
+		goto err_put_clk;
+
+	spin_lock_init(&wdt->io_lock);
+	wdt->boot_status = at32_wdt_get_status();
+
+	/* Work-around for watchdog silicon errata. */
+	if (cpu_is_at32ap7000()
+			&& (wdt->boot_status & WDIOF_CARDRESET)) {
+		dev_info(&pdev->dev, "CPU must be reset with external "
+				"reset or POR due to silicon errata.\n");
+		ret = -EIO;
+		goto err_disable_source_clock;
+	} else {
+		wdt->users = 0;
+	}
+	wdt->miscdev.minor = WATCHDOG_MINOR;
+	wdt->miscdev.name = "watchdog";
+	wdt->miscdev.fops = &at32_wdt_fops;
+
+	if (at32_wdt_settimeout(timeout)) {
+		at32_wdt_settimeout(TIMEOUT_DEFAULT);
+		dev_dbg(&pdev->dev,
+			"default timeout invalid, set to %d sec.\n",
+			TIMEOUT_DEFAULT);
+	}
+
+	ret = misc_register(&wdt->miscdev);
+	if (ret) {
+		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
+		goto err_iounmap;
+	}
+
+	platform_set_drvdata(pdev, wdt);
+	wdt->miscdev.parent = &pdev->dev;
+	dev_info(&pdev->dev,
+		"AT32 WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
+		wdt->regs, wdt->timeout, nowayout);
+
+	return 0;
+
+err_disable_source_clock:
+	at32_wdt_disable_source_clock();
+err_put_clk:
+	if (!cpu_is_at32ap7000())
+		clk_put(wdt->pclk);
+err_iounmap:
+	iounmap(wdt->regs);
+err_free:
+	kfree(wdt);
+	wdt = NULL;
+	return ret;
+}
+
+static int __exit at32_wdt_remove(struct platform_device *pdev)
+{
+	if (wdt && platform_get_drvdata(pdev) == wdt) {
+		/* Stop the timer before we leave */
+		if (!nowayout) {
+			at32_wdt_stop();
+			at32_wdt_disable_source_clock();
+		}
+
+		misc_deregister(&wdt->miscdev);
+		if (!cpu_is_at32ap7000())
+			clk_put(wdt->pclk);
+		iounmap(wdt->regs);
+		kfree(wdt);
+		wdt = NULL;
+		platform_set_drvdata(pdev, NULL);
+	}
+	return 0;
+}
+
+static void at32_wdt_shutdown(struct platform_device *pdev)
+{
+	at32_wdt_stop();
+}
+
+#ifdef CONFIG_PM
+static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
+{
+	at32_wdt_stop();
+	return 0;
+}
+
+static int at32_wdt_resume(struct platform_device *pdev)
+{
+	if (wdt->users)
+		at32_wdt_start();
+	return 0;
+}
+#else
+#define at32_wdt_suspend NULL
+#define at32_wdt_resume NULL
+#endif
+
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:at32_wdt");
+
+static struct platform_driver at32_wdt_driver = {
+	.remove		= __exit_p(at32_wdt_remove),
+	.suspend	= at32_wdt_suspend,
+	.resume		= at32_wdt_resume,
+	.driver		= {
+		.name	= "at32_wdt",
+		.owner	= THIS_MODULE,
+	},
+	.shutdown	= at32_wdt_shutdown,
+};
+
+static int __init at32_wdt_init(void)
+{
+	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
+}
+module_init(at32_wdt_init);
+
+static void __exit at32_wdt_exit(void)
+{
+	platform_driver_unregister(&at32_wdt_driver);
+}
+module_exit(at32_wdt_exit);
+
+MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
+MODULE_DESCRIPTION("Watchdog driver for Atmel AVR32 devices");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff -urN linux-2.6.28.2-0rig//drivers/watchdog/Kconfig linux-2.6.28.2/drivers/watchdog/Kconfig
--- linux-2.6.28.2-0rig//drivers/watchdog/Kconfig	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/watchdog/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -237,12 +237,12 @@
 
 # AVR32 Architecture
 
-config AT32AP700X_WDT
-	tristate "AT32AP700x watchdog"
-	depends on CPU_AT32AP700X
+config AT32_WDT
+	tristate "AVR32 On-Chip Watchdog Timer"
+	depends on AVR32
 	help
-	  Watchdog timer embedded into AT32AP700x devices. This will reboot
-	  your system when the timeout is reached.
+	  Watchdog timer embedded into AT32AP700x and similar devices.
+	  This will reboot your system when the timeout is reached.
 
 # BLACKFIN Architecture
 
diff -urN linux-2.6.28.2-0rig//drivers/watchdog/Makefile linux-2.6.28.2/drivers/watchdog/Makefile
--- linux-2.6.28.2-0rig//drivers/watchdog/Makefile	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/watchdog/Makefile	2009-01-29 08:52:50.000000000 +0100
@@ -45,7 +45,7 @@
 # ARM26 Architecture
 
 # AVR32 Architecture
-obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
+obj-$(CONFIG_AT32_WDT) += at32_wdt.o
 
 # BLACKFIN Architecture
 obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
diff -urN linux-2.6.28.2-0rig//drivers/video/atmel_lcdfb.c linux-2.6.28.2/drivers/video/atmel_lcdfb.c
--- linux-2.6.28.2-0rig//drivers/video/atmel_lcdfb.c	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/video/atmel_lcdfb.c	2009-01-29 08:52:50.000000000 +0100
@@ -178,7 +178,7 @@
 static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
 	.type		= FB_TYPE_PACKED_PIXELS,
 	.visual		= FB_VISUAL_TRUECOLOR,
-	.xpanstep	= 0,
+	.xpanstep	= 1,
 	.ypanstep	= 1,
 	.ywrapstep	= 0,
 	.accel		= FB_ACCEL_NONE,
@@ -239,7 +239,7 @@
 }
 
 static void atmel_lcdfb_update_dma(struct fb_info *info,
-			       struct fb_var_screeninfo *var)
+                                   struct fb_var_screeninfo *var)
 {
 	struct atmel_lcdfb_info *sinfo = info->par;
 	struct fb_fix_screeninfo *fix = &info->fix;
@@ -251,6 +251,8 @@
 	dma_addr &= ~3UL;
 
 	/* Set framebuffer DMA base address and pixel offset */
+	dev_dbg(info->device, "%s:\n", __func__);
+        dev_dbg(info->device, "  *setting dma addr: 0x%lx \n", dma_addr); 
 	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
 
 	atmel_lcdfb_update_dma2d(sinfo, var);
@@ -493,6 +495,7 @@
 	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
 		 info->var.xres, info->var.yres,
 		 info->var.xres_virtual, info->var.yres_virtual);
+	dev_dbg(info->device, "  * bpp:        %u\n", info->var.bits_per_pixel);
 
 	atmel_lcdfb_stop_nowait(sinfo);
 
@@ -594,7 +597,12 @@
 	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
 	/* Enable FIFO & DMA errors */
 	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
-
+        
+        /* !!!HACK for logging end of frame and underruns 
+           when connected to MPOP. */
+        if( info->var.bits_per_pixel == 32 )
+          lcdc_writel(sinfo, ATMEL_LCDC_IER, 0x70);
+        
 	/* ...wait for DMA engine to become idle... */
 	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
 		msleep(10);
@@ -695,7 +703,7 @@
 }
 
 static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
-			       struct fb_info *info)
+                                   struct fb_info *info)
 {
 	dev_dbg(info->device, "%s\n", __func__);
 
@@ -827,7 +835,8 @@
 	info->fix = atmel_lcdfb_fix;
 
 	/* Enable LCDC Clocks */
-	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
+	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()
+			|| cpu_is_at32ap7200()) {
 		sinfo->bus_clk = clk_get(dev, "hck1");
 		if (IS_ERR(sinfo->bus_clk)) {
 			ret = PTR_ERR(sinfo->bus_clk);
diff -urN linux-2.6.28.2-0rig//drivers/video/atmel_mpopfb.c linux-2.6.28.2/drivers/video/atmel_mpopfb.c
--- linux-2.6.28.2-0rig//drivers/video/atmel_mpopfb.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/drivers/video/atmel_mpopfb.c	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,1127 @@
+/*
+ *  Driver for AT91/AT32 LCD Controller
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#define DEBUG
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+
+#include <mach/board.h>
+#include <mach/cpu.h>
+
+#include <video/atmel_lcdc.h>
+#include <video/atmel_mpop.h>
+
+#define mpop_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
+#define mpop_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
+
+#define	ATMEL_MPOPFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+                                         | FBINFO_PARTIAL_PAN_OK        \
+                                         | FBINFO_HWACCEL_XPAN          \
+                                         | FBINFO_HWACCEL_YPAN)
+
+static struct atmel_mpopfb_rgbconv_coeffs atmel_mpop_ycrcb2rgb_coeffs = {
+	.r1 = 298,
+	.r2 = 0,
+	.r3 = 409,
+	.r4 = -56992,
+	.g1 = 298,
+	.g2 = -100,
+	.g3 = -208,
+	.g4 = 34784,
+	.b1 = 298,
+	.b2 = 516,
+	.b3 = 0,
+	.b4 = -70688,
+};
+
+static struct fb_fix_screeninfo atmel_mpopfb_fix __initdata = {
+	.type		= FB_TYPE_PLANES,
+	.visual		= FB_VISUAL_TRUECOLOR,
+	.xpanstep	= 16,
+	.ypanstep	= 1,
+	.ywrapstep	= 1,
+	.accel		= FB_ACCEL_NONE,
+};
+
+static void atmel_mpopfb_update_sar(struct fb_info *info,
+		struct fb_var_screeninfo *var)
+{
+	struct atmel_mpopfb_info *sinfo = info->par;
+	struct fb_fix_screeninfo *fix = &info->fix;
+	u32 y_sar, u_sar, v_sar, o1_sar, o2_sar, cursor_sar, next_sar;
+
+	u32 chroma_xres_virtual;
+	u32 chroma_yres_virtual;
+	u32 chroma_xres;
+	u32 chroma_yres;
+	u32 chroma_xoffset;
+	u32 chroma_yoffset;
+
+	switch (var->bits_per_pixel) {
+	default:
+	case 12:
+		chroma_xres_virtual = var->xres_virtual / 2;
+		chroma_yres_virtual = var->yres_virtual / 2;
+		chroma_xres = var->xres / 2;
+		chroma_yres = var->yres / 2;
+		chroma_xoffset = var->xoffset / 2;
+		chroma_yoffset = var->yoffset / 2;
+		break;
+	case 16:
+		chroma_xres_virtual = var->xres_virtual / 2;
+		chroma_yres_virtual = var->yres_virtual;
+		chroma_xres = var->xres / 2;
+		chroma_yres = var->yres;
+		chroma_xoffset = var->xoffset / 2;
+		chroma_yoffset = var->yoffset;
+		break;
+	case 24:
+		chroma_xres_virtual = var->xres_virtual;
+		chroma_yres_virtual = var->yres_virtual;
+		chroma_xres = var->xres;
+		chroma_yres = var->yres;
+		chroma_xoffset = var->xoffset;
+		chroma_yoffset = var->yoffset;
+		break;
+	}
+
+	/* Setup pointer to YUV planes in YUV framebuffer. */
+	y_sar = fix->smem_start + var->xoffset
+		+ var->yoffset * var->xres_virtual;
+	u_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
+		+ chroma_xoffset + chroma_yoffset * chroma_xres_virtual;
+	v_sar = u_sar + chroma_xres_virtual * chroma_yres_virtual;
+	next_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
+		+ 2 * chroma_xres_virtual * chroma_yres_virtual;
+	o1_sar = next_sar;
+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize;
+	o2_sar = next_sar;
+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize
+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize;
+	cursor_sar = next_sar;
+
+	if (sinfo->baseimg_info.flip) {
+		/* If we flip we must start with the last line in the frame. */
+		y_sar += var->xres_virtual * (var->yres - 1);
+		u_sar += chroma_xres_virtual * (chroma_yres - 1);
+		v_sar += chroma_xres_virtual * (chroma_yres - 1);
+	}
+
+	dev_dbg(info->device, "%s:\n", __func__);
+	dev_dbg(info->device, "  * y_sar = 0x%x\n", y_sar);
+	dev_dbg(info->device, "  * u_sar = 0x%x\n", u_sar);
+	dev_dbg(info->device, "  * v_sar = 0x%x\n", v_sar);
+	dev_dbg(info->device, "  * o1_sar = 0x%x\n", o1_sar);
+	dev_dbg(info->device, "  * o2_sar = 0x%x\n", o2_sar);
+	dev_dbg(info->device, "  * cursor_sar = 0x%x\n", cursor_sar);
+
+	mpop_writel(sinfo, ATMEL_MPOP_Y_SAR, y_sar);
+	mpop_writel(sinfo, ATMEL_MPOP_U_SAR, u_sar);
+	mpop_writel(sinfo, ATMEL_MPOP_V_SAR, v_sar);
+	mpop_writel(sinfo, ATMEL_MPOP_O1_SAR, o1_sar);
+	mpop_writel(sinfo, ATMEL_MPOP_O2_SAR, o2_sar);
+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SAR, cursor_sar);
+}
+
+static void atmel_mpopfb_free_video_memory(struct atmel_mpopfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+
+	dma_free_writecombine(info->device, info->fix.smem_len,
+			(void __force *)info->screen_base,
+			info->fix.smem_start);
+}
+
+/**
+ *	atmel_mpopfb_alloc_video_memory - Allocate framebuffer memory
+ *	@sinfo: the frame buffer to allocate memory for
+ */
+static int atmel_mpopfb_alloc_video_memory(struct atmel_mpopfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+	struct fb_var_screeninfo *var = &info->var;
+
+	info->fix.smem_len = (var->xres_virtual * var->yres_virtual
+			* ((var->bits_per_pixel + 7) / 8));
+
+	info->screen_base
+		= (void __iomem __force *)dma_alloc_writecombine(info->device,
+				info->fix.smem_len,
+				(dma_addr_t *)&info->fix.smem_start,
+				GFP_KERNEL);
+
+	if (!info->screen_base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+/**
+ *      atmel_mpopfb_check_var - Validates a var passed in.
+ *      @var: frame buffer variable screen structure
+ *      @info: frame buffer structure that represents a single frame buffer
+ *
+ *	Checks to see if the hardware supports the state requested by
+ *	var passed in. This function does not alter the hardware
+ *	state!!!  This means the data stored in struct fb_info and
+ *	struct atmel_mpopfb_info do not change. This includes the var
+ *	inside of struct fb_info.  Do NOT change these. This function
+ *	can be called on its own if we intent to only test a mode and
+ *	not actually set it. The stuff in modedb.c is a example of
+ *	this. If the var passed in is slightly off by what the
+ *	hardware can support then we alter the var PASSED in to what
+ *	we can do. If the hardware doesn't support mode change a
+ *	-EINVAL will be returned by the upper layers. You don't need
+ *	to implement this function then. If you hardware doesn't
+ *	support changing the resolution then this function is not
+ *	needed. In this case the driver would just provide a var that
+ *	represents the static state the screen is in.
+ *
+ *	Returns negative errno on error, or zero on success.
+ */
+static int atmel_mpopfb_check_var(struct fb_var_screeninfo *var,
+		struct fb_info *info)
+{
+	struct device *dev = info->device;
+	struct atmel_mpopfb_info *sinfo = info->par;
+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
+
+	dev_dbg(dev, "%s:\n", __func__);
+	dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
+	dev_dbg(dev, "  offset: (%u,%u)\n", var->xoffset, var->yoffset);
+	dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
+
+	/*
+	 *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
+	 *  as FB_VMODE_SMOOTH_XPAN is only used internally
+	 */
+
+	if (var->vmode & FB_VMODE_CONUPDATE) {
+		var->vmode |= FB_VMODE_YWRAP;
+		var->xoffset = info->var.xoffset;
+		var->yoffset = info->var.yoffset;
+	}
+
+	/* Horizontal size must be a multiple of 16 pixels */
+
+	/*
+	 *  Some very basic checks
+	 */
+	if (!var->xres)
+		var->xres = 1;
+	if (!var->yres)
+		var->yres = 1;
+	if (var->xres > var->xres_virtual)
+		var->xres_virtual = var->xres;
+	if (var->yres > var->yres_virtual)
+		var->yres_virtual = var->yres;
+	if (var->bits_per_pixel > 16)
+		var->bits_per_pixel = 24;
+	else if (var->bits_per_pixel > 12)
+		var->bits_per_pixel = 16;
+	else
+		var->bits_per_pixel = 12;
+
+	/* Horizontal size and offset must be a multiple of 16 pixels */
+	var->xres = (var->xres + 15) & ~15UL;
+	var->xres_virtual = (var->xres_virtual + 15) & ~15UL;
+	var->xoffset = (var->xoffset + 15) & ~15UL;
+
+	if (var->xres_virtual < var->xoffset + var->xres)
+		var->xres_virtual = var->xoffset + var->xres;
+	if (var->yres_virtual < var->yoffset + var->yres)
+		var->yres_virtual = var->yoffset + var->yres;
+
+	/* Check that the scaled image will fit into the LCD display. */
+	if (sinfo->baseimg_info.xsize > lcdc_info->var.xres) {
+		dev_err(dev, "baseimage is wider than screen: %d > %d\n",
+			sinfo->baseimg_info.xsize, lcdc_info->var.xres);
+		return -EINVAL;
+	}
+
+	if (sinfo->baseimg_info.ysize > lcdc_info->var.yres) {
+		dev_err(dev, "baseimage is higher than screen: %d > %d\n",
+			sinfo->baseimg_info.ysize, lcdc_info->var.yres);
+		return -EINVAL;
+	}
+
+	/* Check that it is possible to scale to given size. */
+	if (ATMEL_MPOP_CALC_SCALE(var->xres, sinfo->baseimg_info.xsize) == 0
+			|| (ATMEL_MPOP_CALC_SCALE(var->xres,
+					sinfo->baseimg_info.xsize)
+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
+		dev_err(dev, "cannot scale from width %d to %d Max %s\n",
+			var->xres, sinfo->baseimg_info.xsize,
+			ATMEL_MPOP_CALC_SCALE(var->xres,
+					      sinfo->baseimg_info.xsize)
+			? "downscale factor is 4!"
+			: "upscale factor is 32");
+		return -EINVAL;
+	}
+
+	if (ATMEL_MPOP_CALC_SCALE(var->yres, sinfo->baseimg_info.ysize) == 0
+			|| (ATMEL_MPOP_CALC_SCALE(var->yres,
+					sinfo->baseimg_info.ysize)
+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
+		dev_err(dev, "cannot scale from height %d to %d Max %s\n",
+			var->yres, sinfo->baseimg_info.ysize,
+			ATMEL_MPOP_CALC_SCALE(var->yres,
+					      sinfo->baseimg_info.ysize)
+			? "downscale factor is 4!"
+			: "upscale factor is 32");
+		return -EINVAL;
+	}
+
+	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
+	var->transp.msb_right = 0;
+	var->transp.offset = var->transp.length = 0;
+
+	switch (var->bits_per_pixel) {
+	case 12:
+	case 16:
+	case 24:
+		var->red.offset = 0;
+		var->green.offset = 8;
+		var->blue.offset = 16;
+		var->red.length = var->green.length = var->blue.length = 8;
+		break;
+	default:
+		dev_err(dev, "color depth %d not supported\n",
+			var->bits_per_pixel);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
+{
+	if (!sinfo->running) {
+		dev_dbg(sinfo->info->device, "  * Starting MPOP.\n");
+
+		/* Enable all error interrupts. */
+		mpop_writel(sinfo, ATMEL_MPOP_INTEN, 0x7);
+
+		/*
+		 * Enable the MPOP. When the LCD controller starts
+		 * reading from the slave interface it will start
+		 * generating a frame.
+		 */
+		mpop_writel(sinfo, ATMEL_MPOP_CR,
+			    ATMEL_MPOP_CR_EN_MASK
+			    /*| ATMEL_MPOP_CR_OUT_BGR_MASK */ );
+
+		sinfo->running = 1;
+	}
+}
+
+static void atmel_mpopfb_stop(struct atmel_mpopfb_info *sinfo)
+{
+	if (!sinfo->running)
+		/* Not running. Already stopped. */
+		return;
+
+	dev_dbg(sinfo->info->device, "Stopping MPOP.\n");
+
+	/* Disable the MPOP. This will force the MPOP to be reset. */
+	mpop_writel(sinfo, ATMEL_MPOP_CR, 0);
+
+	/* Disable all interrupts. */
+	mpop_writel(sinfo, ATMEL_MPOP_INTDIS, ~0UL);
+
+	/* Looks like we stopped the MPOP... */
+	dev_dbg(sinfo->info->device, "MPOP stopped.\n");
+
+	sinfo->running = 0;
+}
+
+static void atmel_mpopfb_connect_to_lcdc(struct atmel_mpopfb_info *sinfo)
+{
+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
+
+	dev_dbg(sinfo->info->device, "Connecting MPOP to LCDC:\n");
+
+	/* Start the mpop if it is not running. */
+	atmel_mpopfb_start(sinfo);
+
+	if (sinfo->connected_to_lcdc)
+		/* Already connected. */
+		return;
+
+	/*
+	 * Set framebuffer pointer in LCDC to point to the slave
+	 * interface of the MPOP.
+	 */
+	dev_dbg(sinfo->info->device, "  * Attaching to LCDC.\n");
+	sinfo->lcdc_old_smem_start = lcdc_info->fix.smem_start;
+	lcdc_info->fix.smem_start = (unsigned long)sinfo->slave_base;
+	sinfo->lcdc_old_bits_per_pixel = lcdc_info->var.bits_per_pixel;
+	lcdc_info->var.bits_per_pixel = 32;
+
+	/* Force the LCDC to change the configuration. */
+	lcdc_info->fbops->fb_set_par(lcdc_info);
+
+	sinfo->connected_to_lcdc = 1;
+}
+
+static void atmel_mpopfb_disconnect_from_lcdc(struct atmel_mpopfb_info *sinfo)
+{
+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
+
+	dev_dbg(sinfo->info->device, "Disconnecting MPOP from LCDC:\n");
+
+	if (!sinfo->connected_to_lcdc)
+		/* Already disconnected. */
+		return;
+
+	/* Restore lcdc's old framebuffer pointer and pixel-format. */
+	lcdc_info->fix.smem_start = sinfo->lcdc_old_smem_start;
+	lcdc_info->var.bits_per_pixel = sinfo->lcdc_old_bits_per_pixel;
+
+	/* Force the LCDC to change the configuration. */
+	lcdc_info->fbops->fb_set_par(lcdc_info);
+
+	sinfo->connected_to_lcdc = 0;
+
+	/* We must stop the mpop to reset it. */
+	atmel_mpopfb_stop(sinfo);
+}
+
+static void atmel_mpopfb_put_overlay_palette(struct atmel_mpopfb_info *sinfo,
+		struct atmel_mpopfb_overlay_palette *palette)
+{
+	int i;
+
+	dev_dbg(sinfo->info->device, "Overlay palette = :\n");
+	for (i = 0; i < 256; i++) {
+		dev_dbg(sinfo->info->device, "%d -> 0x%x\n", i,
+			*((int *)&palette->entry[i]));
+		mpop_writel(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i,
+			    *((int *)&palette->entry[i]));
+	}
+}
+
+static void atmel_mpopfb_get_overlay_palette(struct atmel_mpopfb_info *sinfo,
+		struct atmel_mpopfb_overlay_palette *palette)
+{
+	int i;
+
+	for (i = 0; i < 256; i++)
+		*((int *)&palette->entry[i]) =
+		    mpop_readl(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i);
+}
+
+static void atmel_mpopfb_put_cursor_palette(struct atmel_mpopfb_info *sinfo,
+		struct atmel_mpopfb_cursor_palette *palette)
+{
+	int i;
+	for (i = 0; i < 4; i++)
+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i,
+				*((int *)&palette->entry[i]));
+}
+
+static void atmel_mpopfb_get_cursor_palette(struct atmel_mpopfb_info *sinfo,
+		struct atmel_mpopfb_cursor_palette *palette)
+{
+	int i;
+	for (i = 0; i < 4; i++)
+		*((int *)&palette->entry[i])
+			= mpop_readl(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i);
+}
+
+/**
+ *      atmel_mpopfb_set_par - Alters the hardware state.
+ *      @info: frame buffer structure that represents a single frame buffer
+ *
+ *	Using the fb_var_screeninfo in fb_info we set the resolution
+ *	of the this particular framebuffer. This function alters the
+ *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
+ *	not alter var in fb_info since we are using that data. This
+ *	means we depend on the data in var inside fb_info to be
+ *	supported by the hardware.  atmel_lcdfb_check_var is always called
+ *	before atmel_lcdfb_set_par to ensure this.  Again if you can't
+ *	change the resolution you don't need this function.
+ *
+ */
+static int atmel_mpopfb_set_par(struct fb_info *info)
+{
+	struct atmel_mpopfb_info *sinfo = info->par;
+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
+	struct fb_var_screeninfo *var = &info->var;
+
+	u32 yuv_format;
+	u32 xscale, yscale;
+
+	dev_dbg(info->device, "%s:\n", __func__);
+	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
+			info->var.xres, info->var.yres,
+			info->var.xres_virtual, info->var.yres_virtual);
+	dev_dbg(info->device, "  * offset: (%u,%u)\n",
+			info->var.xoffset, info->var.yoffset);
+	dev_dbg(info->device, "  * bpp: %u\n", info->var.bits_per_pixel);
+
+	/* Setup the output picture size. We must use the size of the lcdcfb. */
+	dev_dbg(info->device, "  * output frame resolution: %ux%u \n",
+			lcdc_info->var.xres, lcdc_info->var.yres);
+	mpop_writel(sinfo, ATMEL_MPOP_DISP_MAX_COORD,
+			((lcdc_info->var.xres - 1) << ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET)
+			| ((lcdc_info->var.yres - 1) << ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET));
+
+	/* Setup base picture. */
+
+	switch (var->bits_per_pixel) {
+	default:
+	case 12:
+		yuv_format = ATMEL_MPOP_YUVFORMAT_420;
+		break;
+	case 16:
+		yuv_format = ATMEL_MPOP_YUVFORMAT_422;
+		break;
+	case 24:
+		yuv_format = ATMEL_MPOP_YUVFORMAT_444;
+		break;
+	}
+
+	xscale = ATMEL_MPOP_CALC_SCALE(info->var.xres, sinfo->baseimg_info.xsize);
+	yscale = ATMEL_MPOP_CALC_SCALE(info->var.yres, sinfo->baseimg_info.ysize);
+
+	dev_dbg(info->device, "  * baseimg output size = %ux%u \n",
+			sinfo->baseimg_info.xsize, sinfo->baseimg_info.ysize);
+	dev_dbg(info->device, "  * resize scales = %ux%u \n", xscale, yscale);
+	dev_dbg(info->device, "  * yuv format = %u \n", yuv_format);
+	mpop_writel(sinfo, ATMEL_MPOP_YCR,
+			yuv_format << ATMEL_MPOP_YCR_YUVFORMAT_OFFSET
+			| xscale << ATMEL_MPOP_YCR_XRESIZE_OFFSET
+			| yscale << ATMEL_MPOP_YCR_YRESIZE_OFFSET);
+
+	/* Setup conversion coefficients. */
+	mpop_writel(sinfo, ATMEL_MPOP_R2R1,
+			((sinfo->rgbconv_coeffs.r1 << ATMEL_MPOP_R1_OFFSET) & ATMEL_MPOP_R1_MASK)
+			| ((sinfo->rgbconv_coeffs.r2 << ATMEL_MPOP_R2_OFFSET) & ATMEL_MPOP_R2_MASK));
+	mpop_writel(sinfo, ATMEL_MPOP_R4R3,
+			((sinfo->rgbconv_coeffs.r3 << ATMEL_MPOP_R3_OFFSET) & ATMEL_MPOP_R3_MASK)
+			| ((sinfo->rgbconv_coeffs.r4 << ATMEL_MPOP_R4_OFFSET) & ATMEL_MPOP_R4_MASK));
+	mpop_writel(sinfo, ATMEL_MPOP_G2G1,
+			((sinfo->rgbconv_coeffs.g1 << ATMEL_MPOP_G1_OFFSET) & ATMEL_MPOP_G1_MASK)
+			| ((sinfo->rgbconv_coeffs.g2 << ATMEL_MPOP_G2_OFFSET) & ATMEL_MPOP_G2_MASK));
+	mpop_writel(sinfo, ATMEL_MPOP_G4G3,
+			((sinfo->rgbconv_coeffs.g3 << ATMEL_MPOP_G3_OFFSET) & ATMEL_MPOP_G3_MASK)
+			| ((sinfo->rgbconv_coeffs.g4 << ATMEL_MPOP_G4_OFFSET) & ATMEL_MPOP_G4_MASK));
+	mpop_writel(sinfo, ATMEL_MPOP_B2B1,
+			((sinfo->rgbconv_coeffs.b1 << ATMEL_MPOP_B1_OFFSET) & ATMEL_MPOP_B1_MASK)
+			| ((sinfo->rgbconv_coeffs.b2 << ATMEL_MPOP_B2_OFFSET) & ATMEL_MPOP_B2_MASK));
+	mpop_writel(sinfo, ATMEL_MPOP_B4B3,
+			((sinfo->rgbconv_coeffs.b3 << ATMEL_MPOP_B3_OFFSET) & ATMEL_MPOP_B3_MASK)
+			| ((sinfo->rgbconv_coeffs.b4 << ATMEL_MPOP_B4_OFFSET) & ATMEL_MPOP_B4_MASK));
+
+	info->fix.line_length = info->var.xres_virtual;
+	info->fix.visual = FB_VISUAL_TRUECOLOR;
+
+	/* Setup stride. We can flip the image by negating the 
+	   stride, but we must then set the SAR registers to point
+	   to the last line in the image. */
+	if (sinfo->baseimg_info.flip) {
+		dev_dbg(info->device, "  * flip \n");
+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, -info->var.xres_virtual);
+	} else
+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, info->var.xres_virtual);
+
+	/* Setup input image size. */
+	mpop_writel(sinfo, ATMEL_MPOP_YUV_MAX_COORD,
+			((info->var.xres - 1) << ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET)
+			| ((info->var.yres - 1) << ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET));
+
+	/* Setup size and position of output base image after scaling. */
+	mpop_writel(sinfo, ATMEL_MPOP_RGB_SIZE,
+			sinfo->baseimg_info.xsize << ATMEL_MPOP_RGB_SIZE_X_OFFSET
+			| sinfo->baseimg_info.ysize << ATMEL_MPOP_RGB_SIZE_Y_OFFSET);
+
+	mpop_writel(sinfo, ATMEL_MPOP_RGB_POS,
+			(sinfo->baseimg_info.xpos << ATMEL_MPOP_RGB_POS_X_OFFSET)
+			| (sinfo->baseimg_info.ypos << ATMEL_MPOP_RGB_POS_Y_OFFSET));
+
+	dev_dbg(info->device, "  * baseimg pos: (%u,%u) \n",
+			sinfo->baseimg_info.xpos, sinfo->baseimg_info.ypos);
+
+	/* Setup Word Transfer Count. */
+	mpop_writel(sinfo, ATMEL_MPOP_RGB_WTC,
+			DIV_ROUND_UP(info->var.xres * info->var.yres
+				* var->bits_per_pixel, 32));
+
+	/* Set overlay parameters. */
+	mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
+	mpop_writel(sinfo, ATMEL_MPOP_O1_SIZE,
+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize << ATMEL_MPOP_O1_SIZE_O1_SIZE_X)
+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize << ATMEL_MPOP_O1_SIZE_O1_SIZE_Y));
+	mpop_writel(sinfo, ATMEL_MPOP_O1_WTC,
+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
+			 * sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize, 4));
+
+	mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
+	mpop_writel(sinfo, ATMEL_MPOP_O2_SIZE,
+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize << ATMEL_MPOP_O2_SIZE_O2_SIZE_X)
+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize << ATMEL_MPOP_O2_SIZE_O2_SIZE_Y));
+	mpop_writel(sinfo, ATMEL_MPOP_O2_WTC,
+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize *
+				sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize, 4));
+
+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SIZE,
+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X)
+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y));
+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_WTC,
+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize
+				* sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize, 16));
+
+	/* Enable base overlay + any other enabled overlays. */
+	mpop_writel(sinfo, ATMEL_MPOP_OCR, ATMEL_MPOP_OCR_RGBEN_MASK);
+
+	if (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled)
+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
+				| ATMEL_MPOP_OCR_CURSOREN_MASK);
+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
+				| ATMEL_MPOP_OCR_O1EN_MASK);
+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
+				| ATMEL_MPOP_OCR_O2EN_MASK);
+
+	/* Set background to black. */
+	mpop_writel(sinfo, ATMEL_MPOP_BGCOLOR, 0);
+
+	/* Setup source address registers */
+	atmel_mpopfb_update_sar(info, &info->var);
+
+	dev_dbg(info->device, "  * DONE\n");
+
+	return 0;
+}
+
+static int atmel_mpopfb_pan_display(struct fb_var_screeninfo *var,
+		struct fb_info *info)
+{
+	dev_dbg(info->device, "%s\n", __func__);
+
+	/* Change source address registers to reflect the panning. */
+	atmel_mpopfb_update_sar(info, var);
+
+	return 0;
+}
+
+static void atmel_mpopfb_put_overlay_info(struct fb_info *info,
+		struct atmel_mpopfb_overlay_info overlay_info)
+{
+	struct atmel_mpopfb_info *sinfo = info->par;
+
+	/* We can update the position now since it is double buffered. */
+	switch (overlay_info.overlay) {
+	case ATMEL_MPOPFB_OVERLAY1:
+		mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
+			(overlay_info.xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
+			| (overlay_info.ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
+		break;
+	case ATMEL_MPOPFB_OVERLAY2:
+		mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
+			(overlay_info.xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
+			| (overlay_info.ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
+		break;
+	case ATMEL_MPOPFB_CURSOR:
+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
+			(overlay_info.xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
+			| (overlay_info.ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
+		break;
+	default:
+		dev_warn(info->device, "Unknown overlay type: %d\n",
+				overlay_info.overlay);
+		return;
+	}
+
+	/* Copy the overlay info to the mpopfb info structure. */
+	sinfo->overlay_info[overlay_info.overlay] = overlay_info;
+}
+
+static int atmel_mpopfb_ioctl(struct fb_info *info,
+		unsigned int cmd, unsigned long arg)
+{
+	void __user *argp = (void __user *)arg;
+	struct atmel_mpopfb_info *sinfo = info->par;
+	struct atmel_mpopfb_overlay_info overlay_info;
+
+	switch (cmd) {
+	case ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE:{
+			struct atmel_mpopfb_overlay_palette palette;
+			if (copy_from_user(&palette, argp, sizeof(palette)))
+				return -EFAULT;
+			atmel_mpopfb_put_overlay_palette(sinfo, &palette);
+			return 0;
+		}
+	case ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE:{
+			struct atmel_mpopfb_overlay_palette palette;
+			atmel_mpopfb_get_overlay_palette(sinfo, &palette);
+			if (copy_to_user(argp, &palette, sizeof(palette)))
+				return -EFAULT;
+			return 0;
+		}
+	case ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE:{
+			struct atmel_mpopfb_cursor_palette palette;
+			if (copy_from_user(&palette, argp, sizeof(palette)))
+				return -EFAULT;
+			atmel_mpopfb_put_cursor_palette(sinfo, &palette);
+			return 0;
+		}
+	case ATMEL_MPOP_FBIOGET_CURSOR_PALETTE:{
+			struct atmel_mpopfb_cursor_palette palette;
+			atmel_mpopfb_get_cursor_palette(sinfo, &palette);
+			if (copy_to_user(argp, &palette, sizeof(palette)))
+				return -EFAULT;
+			return 0;
+		}
+	case ATMEL_MPOP_FBIOPUT_OVERLAY_INFO:
+		if (copy_from_user(&overlay_info, argp, sizeof(overlay_info)))
+			return -EFAULT;
+		atmel_mpopfb_put_overlay_info(info, overlay_info);
+		return 0;
+	case ATMEL_MPOP_FBIOPUT_BASEIMG_INFO:
+		if (copy_from_user(&sinfo->baseimg_info, argp,
+					sizeof(sinfo->baseimg_info)))
+			return -EFAULT;
+
+		/* Check that new baseimg parameters are sane. */
+		if (atmel_mpopfb_check_var(&info->var, info))
+			return -EFAULT;
+
+		/* Update hardware configuration. */
+		atmel_mpopfb_set_par(info);
+		return 0;
+	case ATMEL_MPOP_FBIOGET_BASEIMG_INFO:
+		return copy_to_user(argp, &sinfo->baseimg_info,
+				sizeof(sinfo->baseimg_info)) ? -EFAULT : 0;
+	case ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS:
+		if (copy_from_user(&sinfo->rgbconv_coeffs, argp,
+					sizeof(sinfo->rgbconv_coeffs)))
+			return -EFAULT;
+
+		/* Update hardware configuration. */
+		if (atmel_mpopfb_set_par(info))
+			return -EFAULT;
+
+		return 0;
+	case ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS:
+		return copy_to_user(argp, &sinfo->rgbconv_coeffs,
+				sizeof(sinfo->rgbconv_coeffs)) ? -EFAULT : 0;
+	case ATMEL_MPOP_FBIO_CONNECT_TO_LCDC:
+		atmel_mpopfb_connect_to_lcdc(sinfo);
+		return 0;
+	case ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC:
+		atmel_mpopfb_disconnect_from_lcdc(sinfo);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+
+	/* Force MPOP to be updated with any new parameters. */
+	atmel_mpopfb_set_par(info);
+}
+
+static int atmel_mpopfb_setcolreg(unsigned int regno, unsigned int red,
+				  unsigned int green, unsigned int blue,
+				  unsigned int transp, struct fb_info *info)
+{
+	return 0;
+}
+
+static struct fb_ops atmel_mpopfb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_check_var	= atmel_mpopfb_check_var,
+	.fb_set_par	= atmel_mpopfb_set_par,
+	.fb_setcolreg	= atmel_mpopfb_setcolreg,
+	.fb_pan_display	= atmel_mpopfb_pan_display,
+	.fb_imageblit	= cfb_imageblit,
+	.fb_ioctl	= atmel_mpopfb_ioctl,
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+};
+
+static irqreturn_t atmel_mpopfb_interrupt(int irq, void *dev_id)
+{
+	struct fb_info *info = dev_id;
+	struct atmel_mpopfb_info *sinfo = info->par;
+	u32 status;
+
+	/* Check which interrupt we have. */
+	status = mpop_readl(sinfo, ATMEL_MPOP_INTSTATUS);
+
+	/* Clear interrupts. */
+	mpop_writel(sinfo, ATMEL_MPOP_INTCLEAR, status);
+
+	if (status & ATMEL_MPOP_EOP) {
+		/* End Of Picture. Start new picture. */
+		mpop_writel(sinfo, ATMEL_MPOP_CR,
+				ATMEL_MPOP_CR_START_MASK
+				| mpop_readl(sinfo, ATMEL_MPOP_CR));
+	} else if (status & ATMEL_MPOP_OUT) {
+		dev_err(info->dev,
+			"MPOP Output DMA interface Bus Error (address=0x%x)!\n",
+			mpop_readl(sinfo, ATMEL_MPOP_OUT_BEAR));
+	} else if (status & ATMEL_MPOP_YUV) {
+		dev_err(info->dev,
+			"MPOP YUV Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
+			mpop_readl(sinfo, ATMEL_MPOP_YUV_BEAR));
+	} else if (status & ATMEL_MPOP_OVERLAY) {
+		dev_err(info->dev,
+			"MPOP Overlay Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
+			mpop_readl(sinfo, ATMEL_MPOP_OVERLAY_BEAR));
+	}
+
+	dev_dbg(info->device, "%s\n", __func__);
+	dev_dbg(info->device, "  * status: 0x%x \n", status);
+
+	return IRQ_HANDLED;
+}
+
+static int __init atmel_mpopfb_init_fbinfo(struct atmel_mpopfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+	int ret = 0;
+
+	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
+
+	dev_info(info->device,
+			"%luKiB frame buffer at %08lx (mapped at %p)\n",
+			(unsigned long)info->fix.smem_len / 1024,
+			(unsigned long)info->fix.smem_start, info->screen_base);
+
+	return ret;
+}
+
+static void atmel_mpopfb_start_clock(struct atmel_mpopfb_info *sinfo)
+{
+	clk_enable(sinfo->mpop_hclk);
+	clk_enable(sinfo->mpop_pclk);
+}
+
+static void atmel_mpopfb_stop_clock(struct atmel_mpopfb_info *sinfo)
+{
+	clk_disable(sinfo->mpop_hclk);
+	clk_disable(sinfo->mpop_pclk);
+}
+
+static int __init atmel_mpopfb_probe(struct platform_device *pdev)
+{
+	struct device			*dev = &pdev->dev;
+	struct fb_info			*info;
+	struct fb_info			*lcdc_info;
+	struct atmel_mpopfb_info	*sinfo;
+	struct atmel_mpopfb_info	*pdata_sinfo;
+	struct resource			*regs = NULL;
+	struct resource			*slave = NULL;
+	struct resource			*map = NULL;
+	int				ret;
+
+	dev_dbg(dev, "%s BEGIN\n", __func__);
+
+	ret = -ENOMEM;
+	info = framebuffer_alloc(sizeof(struct atmel_mpopfb_info), dev);
+	if (!info) {
+		dev_err(dev, "cannot allocate memory\n");
+		goto out;
+	}
+
+	sinfo = info->par;
+
+	if (dev->platform_data) {
+		pdata_sinfo = dev->platform_data;
+		sinfo->lcdc_pdev = pdata_sinfo->lcdc_pdev;
+		if (!sinfo->lcdc_pdev) {
+			dev_err(dev, "cannot get hold of lcdcfb device\n");
+			goto free_info;
+		}
+	} else {
+		dev_err(dev, "cannot get default configuration\n");
+		goto free_info;
+	}
+
+	sinfo->info = info;
+	sinfo->pdev = pdev;
+	sinfo->running = 0;
+	sinfo->connected_to_lcdc = 0;
+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled = 0;
+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled = 0;
+	sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled = 0;
+
+	/* Setup default info */
+
+	/* Set fb_var_screeninfo equal to that of the lcdcfb driver. */
+	lcdc_info = (struct fb_info *)platform_get_drvdata(sinfo->lcdc_pdev);
+	memcpy(&info->var, &lcdc_info->var, sizeof(struct fb_var_screeninfo));
+
+	/* Set default position of the image on the screen to (0,0) and
+	   no scaling */
+	sinfo->baseimg_info.xpos = 0;
+	sinfo->baseimg_info.ypos = 0;
+	sinfo->baseimg_info.xsize = info->var.xres;
+	sinfo->baseimg_info.ysize = info->var.yres;
+
+	/* Use YCbCr --> RGB converion per default. */
+	memcpy(&sinfo->rgbconv_coeffs, &atmel_mpop_ycrcb2rgb_coeffs,
+	       sizeof(struct atmel_mpopfb_rgbconv_coeffs));
+
+	strcpy(info->fix.id, sinfo->pdev->name);
+	info->flags = ATMEL_MPOPFB_FBINFO_DEFAULT;
+	info->fbops = &atmel_mpopfb_ops;
+
+	//memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
+	info->fix = atmel_mpopfb_fix;
+
+	/* Enable MPOP Clocks */
+	sinfo->mpop_hclk = clk_get(dev, "hclk");
+	sinfo->mpop_pclk = clk_get(dev, "pclk");
+	if (IS_ERR(sinfo->mpop_hclk)) {
+		ret = PTR_ERR(sinfo->mpop_hclk);
+		goto put_bus_clk;
+	}
+	if (IS_ERR(sinfo->mpop_pclk)) {
+		ret = PTR_ERR(sinfo->mpop_pclk);
+		goto stop_clk;
+	}
+	atmel_mpopfb_start_clock(sinfo);
+
+	//ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
+	//                   info->monspecs.modedb_len, info->monspecs.modedb,
+	//                   sinfo->default_bpp);
+	//if (!ret) {
+	//      dev_err(dev, "no suitable video mode found\n");
+	//      goto stop_clk;
+	//}
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "resources unusable\n");
+		ret = -ENXIO;
+		goto stop_clk;
+	}
+
+	slave = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!slave) {
+		dev_err(dev, "slave interface memory resource unusable\n");
+		ret = -ENXIO;
+		goto stop_clk;
+	}
+	sinfo->slave_base = (void *)slave->start;
+
+	sinfo->irq_base = platform_get_irq(pdev, 0);
+	if (sinfo->irq_base < 0) {
+		dev_err(dev, "unable to get irq\n");
+		ret = sinfo->irq_base;
+		goto stop_clk;
+	}
+
+	/* Initialize video memory */
+	map = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	if (map) {
+		/* use a pre-allocated memory buffer */
+		info->fix.smem_start = map->start;
+		info->fix.smem_len = map->end - map->start + 1;
+		if (!request_mem_region(info->fix.smem_start,
+					info->fix.smem_len, pdev->name)) {
+			//ret = -EBUSY;
+			//goto stop_clk;
+			/* Probably in use by LCD controller. */
+			info->screen_base = lcdc_info->screen_base;
+		} else {
+			info->screen_base =
+			    ioremap(info->fix.smem_start, info->fix.smem_len);
+			if (!info->screen_base)
+				goto release_intmem;
+		}
+	} else {
+		/* alocate memory buffer */
+		ret = atmel_mpopfb_alloc_video_memory(sinfo);
+		if (ret < 0) {
+			dev_err(dev, "cannot allocate mpop framebuffer: %d\n",
+				ret);
+			goto stop_clk;
+		}
+	}
+
+	/* MPOP registers */
+	info->fix.mmio_start = regs->start;
+	info->fix.mmio_len = regs->end - regs->start + 1;
+
+	if (!request_mem_region(info->fix.mmio_start,
+				info->fix.mmio_len, pdev->name)) {
+		ret = -EBUSY;
+		goto free_fb;
+	}
+
+	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
+	if (!sinfo->mmio) {
+		dev_err(dev, "cannot map MPOP registers\n");
+		goto release_mem;
+	}
+
+	/* MPOP slave interface */
+	if (!request_mem_region(slave->start,
+				slave->end - slave->start + 1, pdev->name)) {
+		dev_err(dev,
+			"error requesting memory region for MPOP slave interface\n");
+		ret = -EBUSY;
+		goto unmap_mmio;
+	}
+
+	/* interrupt */
+	ret =
+	    request_irq(sinfo->irq_base, atmel_mpopfb_interrupt, 0, pdev->name,
+			info);
+	if (ret) {
+		dev_err(dev, "request_irq failed: %d\n", ret);
+		goto release_mem_slave;
+	}
+
+	ret = atmel_mpopfb_init_fbinfo(sinfo);
+	if (ret < 0) {
+		dev_err(dev, "init fbinfo failed: %d\n", ret);
+		goto unregister_irqs;
+	}
+
+	/*
+	 * This makes sure that our colour bitfield
+	 * descriptors are correctly initialised.
+	 */
+	atmel_mpopfb_check_var(&info->var, info);
+
+	ret = fb_set_var(info, &info->var);
+	if (ret) {
+		dev_warn(dev, "unable to set display parameters\n");
+		goto free_cmap;
+	}
+
+	dev_set_drvdata(dev, info);
+
+	/*
+	 * Tell the world that we're ready to go
+	 */
+	ret = register_framebuffer(info);
+	if (ret < 0) {
+		dev_err(dev, "failed to register framebuffer device: %d\n",
+			ret);
+		goto free_cmap;
+	}
+
+	dev_info(dev, "fb%d: Atmel MPOP at 0x%08lx (mapped at %p), irq %lu\n",
+		 info->node, info->fix.mmio_start, sinfo->mmio,
+		 sinfo->irq_base);
+
+	return 0;
+
+free_cmap:
+	fb_dealloc_cmap(&info->cmap);
+unregister_irqs:
+	free_irq(sinfo->irq_base, info);
+release_mem_slave:
+	release_mem_region(slave->start, slave->end - slave->start + 1);
+unmap_mmio:
+	iounmap(sinfo->mmio);
+release_mem:
+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+free_fb:
+	if (map)
+		iounmap(info->screen_base);
+	else
+		atmel_mpopfb_free_video_memory(sinfo);
+
+release_intmem:
+	if (map)
+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+stop_clk:
+	atmel_mpopfb_stop_clock(sinfo);
+	clk_put(sinfo->mpop_hclk);
+put_bus_clk:
+	if (sinfo->mpop_pclk)
+		clk_put(sinfo->mpop_pclk);
+free_info:
+	framebuffer_release(info);
+out:
+	dev_dbg(dev, "%s FAILED\n", __func__);
+	return ret;
+}
+
+static int __exit atmel_mpopfb_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fb_info *info = dev_get_drvdata(dev);
+	struct atmel_mpopfb_info *sinfo = info->par;
+
+	if (!sinfo)
+		return 0;
+
+	unregister_framebuffer(info);
+	atmel_mpopfb_stop_clock(sinfo);
+	clk_put(sinfo->mpop_hclk);
+	clk_put(sinfo->mpop_pclk);
+	fb_dealloc_cmap(&info->cmap);
+	free_irq(sinfo->irq_base, info);
+	iounmap(sinfo->mmio);
+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
+		iounmap(info->screen_base);
+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+	} else {
+		atmel_mpopfb_free_video_memory(sinfo);
+	}
+
+	dev_set_drvdata(dev, NULL);
+	framebuffer_release(info);
+
+	return 0;
+}
+
+static struct platform_driver atmel_mpopfb_driver = {
+	.remove = __exit_p(atmel_mpopfb_remove),
+	.driver.name = "atmel_mpopfb",
+	.driver.owner = THIS_MODULE,
+};
+
+static int __init atmel_mpopfb_init(void)
+{
+	return platform_driver_probe(&atmel_mpopfb_driver, atmel_mpopfb_probe);
+}
+
+static void __exit atmel_mpopfb_exit(void)
+{
+	platform_driver_unregister(&atmel_mpopfb_driver);
+}
+
+module_init(atmel_mpopfb_init);
+module_exit(atmel_mpopfb_exit);
+
+MODULE_DESCRIPTION("AT32 MPOP framebuffer driver");
+MODULE_AUTHOR("Ronny Pedersen <rpedersen@atmel.com>");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.28.2-0rig//drivers/video/Kconfig linux-2.6.28.2/drivers/video/Kconfig
--- linux-2.6.28.2-0rig//drivers/video/Kconfig	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/video/Kconfig	2009-01-29 08:52:50.000000000 +0100
@@ -940,6 +940,15 @@
 	help
 	  This enables support for the AT91/AT32 LCD Controller.
 
+config FB_ATMEL_MPOP
+	tristate "AT32 MPOP support"
+	depends on FB && AVR32 && FB_ATMEL
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	help
+	  This enables support for the AT32 MPOP module.
+
 config FB_INTSRAM
 	bool "Frame Buffer in internal SRAM"
 	depends on FB_ATMEL && ARCH_AT91SAM9261
diff -urN linux-2.6.28.2-0rig//drivers/video/Makefile linux-2.6.28.2/drivers/video/Makefile
--- linux-2.6.28.2-0rig//drivers/video/Makefile	2009-01-29 08:39:31.000000000 +0100
+++ linux-2.6.28.2/drivers/video/Makefile	2009-01-29 08:52:50.000000000 +0100
@@ -89,6 +89,7 @@
 obj-$(CONFIG_FB_HIT)              += hitfb.o
 obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
 obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
+obj-$(CONFIG_FB_ATMEL_MPOP)	  += atmel_mpopfb.o
 obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
 obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
 obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
diff -urN linux-2.6.28.2-0rig//include/linux/atmel_mpopfb.h linux-2.6.28.2/include/linux/atmel_mpopfb.h
--- linux-2.6.28.2-0rig//include/linux/atmel_mpopfb.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/include/linux/atmel_mpopfb.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,112 @@
+/*
+ *  Header file for AT32 MPOP FB Driver
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ATMEL_MPOPFB_H__
+#define __ATMEL_MPOPFB_H__
+
+#include <linux/fb.h>
+#include <linux/ioctl.h>
+
+/* Coefficients for conversion to rgb. */
+struct atmel_mpopfb_rgbconv_coeffs {
+	int r1, r2, r3, r4;
+	int g1, g2, g3, g4;
+	int b1, b2, b3, b4;
+};
+
+struct atmel_mpopfb_baseimg_info {
+	/* Position of the mpop base image
+	   in the image sent to the LCD. */
+	unsigned xpos;
+	unsigned ypos;
+
+	/* The size of the base image after scaling. */
+	unsigned xsize;
+	unsigned ysize;
+
+	/* Signal that we should flip the video. */
+	int flip;
+
+};
+
+enum atmel_mpopfb_overlay_type {
+	ATMEL_MPOPFB_OVERLAY1 = 0,
+	ATMEL_MPOPFB_OVERLAY2 = 1,
+	ATMEL_MPOPFB_CURSOR = 2
+};
+
+struct atmel_mpopfb_overlay_info {
+	/* Position of the mpop overlay image
+	   in the image sent to the LCD. */
+	unsigned xpos;
+	unsigned ypos;
+	/* The size of the overlay image. */
+	unsigned xsize;
+	unsigned ysize;
+	/* Signal which overlay this info is for. */
+	enum atmel_mpopfb_overlay_type overlay;
+	/* Signal if the overlay is enabled. */
+	unsigned enabled;
+};
+
+struct atmel_mpopfb_overlay_palette_entry {
+	unsigned char alpha;
+	unsigned char red;
+	unsigned char green;
+	unsigned char blue;
+};
+
+struct atmel_mpopfb_cursor_palette_entry {
+	unsigned char:6;
+	unsigned char invert:1;
+	unsigned char visible:1;
+	unsigned char red;
+	unsigned char green;
+	unsigned char blue;
+};
+
+struct atmel_mpopfb_overlay_palette {
+	struct atmel_mpopfb_overlay_palette_entry entry[256];
+};
+
+struct atmel_mpopfb_cursor_palette {
+	struct atmel_mpopfb_cursor_palette_entry entry[4];
+};
+
+#define ATMEL_MPOP_FBIOPUT_BASEIMG_INFO        _IOW('x',0,struct atmel_mpopfb_baseimg_info)
+#define ATMEL_MPOP_FBIOGET_BASEIMG_INFO        _IOR('x',1,struct atmel_mpopfb_baseimg_info)
+#define ATMEL_MPOP_FBIOPUT_OVERLAY_INFO        _IOW('x',2,struct atmel_mpopfb_overlay_info)
+#define ATMEL_MPOP_FBIO_CONNECT_TO_LCDC        _IO( 'x',4)
+#define ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC   _IO( 'x',5)
+#define ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS      _IOW('x',6,struct atmel_mpopfb_rgbconv_coeffs)
+#define ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS      _IOR('x',7,struct atmel_mpopfb_rgbconv_coeffs)
+#define ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE     _IOW('x',8,struct atmel_mpopfb_overlay_palette)
+#define ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE     _IOR('x',9,struct atmel_mpopfb_overlay_palette)
+#define ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE      _IOW('x',10,struct atmel_mpopfb_cursor_palette)
+#define ATMEL_MPOP_FBIOGET_CURSOR_PALETTE      _IOR('x',11,struct atmel_mpopfb_cursor_palette)
+
+#define ATMEL_MPOP_RESIZE_FRAC_BITS 5
+#define ATMEL_MPOP_SCALE_FRAC_DIV(a,b)  ((((a) << ATMEL_MPOP_RESIZE_FRAC_BITS))/(b))
+#define ATMEL_MPOP_CALC_SCALE(from_res,to_res)  ATMEL_MPOP_SCALE_FRAC_DIV(from_res, to_res)
+
+#define ATMEL_MPOP_COEFF_FRAC_BITS 8
+
+#endif
diff -urN linux-2.6.28.2-0rig//include/linux/atmel_pdca.h linux-2.6.28.2/include/linux/atmel_pdca.h
--- linux-2.6.28.2-0rig//include/linux/atmel_pdca.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/include/linux/atmel_pdca.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,120 @@
+/*
+ * Driver for the Atmel PDCA Peripheral DMA Controller
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ATMEL_PDCA_H
+#define __ATMEL_PDCA_H
+
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+
+struct pdca_pdata {
+	unsigned int		nr_channels;
+};
+
+struct pdca_slave {
+	struct dma_slave	slave;
+	u8			tx_periph_id;
+	u8			rx_periph_id;
+};
+
+struct pdca_desc {
+	/* This controller does not support hardware descriptors */
+	struct scatterlist	*sg;
+	int			sg_len;
+	u8			reg_width;
+	u8			periph_id;
+
+	struct list_head	desc_node;
+	struct dma_async_tx_descriptor txd;
+};
+
+struct pdca_chan {
+	struct list_head	freelist;
+	struct list_head	queue;
+
+	spinlock_t		lock;
+	void __iomem		*regs;
+
+	struct scatterlist	*cur_sg;
+	struct scatterlist	*next_sg;
+
+	struct tasklet_struct	tasklet;
+
+	dma_cookie_t		completed;
+	struct dma_chan		chan;
+	struct pdca_slave	*pslave;
+	unsigned int		descs_allocated;
+	bool			enabled;
+};
+
+struct pdca_dev {
+	struct clk		*hclk;
+	struct clk		*pclk;
+	struct dma_device	dma;
+	void __iomem		*regs;
+
+	struct pdca_chan	chan[];
+};
+
+static inline struct pdca_slave *dma_to_pdca_slave(struct dma_slave *slave)
+{
+	return container_of(slave, struct pdca_slave, slave);
+}
+
+static inline struct pdca_desc *txd_to_pdca_desc(
+		struct dma_async_tx_descriptor *txd)
+{
+	return container_of(txd, struct pdca_desc, txd);
+}
+
+static inline struct pdca_chan *dma_to_pdca_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct pdca_chan, chan);
+}
+
+static inline struct pdca_dev *dma_to_pdca_dev(struct dma_device *dma)
+{
+	return container_of(dma, struct pdca_dev, dma);
+}
+
+/* PDCA per-channel register definitions */
+#define PDCA_MAR		0x0000	/* Memory Address */
+#define PDCA_PSR		0x0004	/* Peripheral Select */
+#define PDCA_TCR		0x0008	/* Transfer Counter */
+#define PDCA_MARR		0x000c	/* Memory Address Reload */
+#define PDCA_TCRR		0x0010	/* Transfer Counter Reload */
+#define PDCA_CR			0x0014	/* Control */
+# define PDCA_CR_TEN		(  1 <<  0)	/* Transfer Enable */
+# define PDCA_CR_TDIS		(  1 <<  1)	/* Transfer Disable */
+# define PDCA_CR_ECLR		(  1 <<  8)	/* Error Clear */
+#define PDCA_MR			0x0018	/* Mode */
+# define PDCA_SIZE_BYTE		(  0 <<  0)	/* 8 bits per transfer */
+# define PDCA_SIZE_HWORD	(  1 <<  0)	/* 16 bits per transfer */
+# define PDCA_SIZE_WORD		(  2 <<  0)	/* 32 bits per transfer */
+#define PDCA_SR			0x001c	/* Status */
+# define PDCA_SR_TEN		(  1 <<  0)	/* Transfer Enabled */
+#define PDCA_IER		0x0020	/* Interrupt Enable */
+#define PDCA_IDR		0x0024	/* Interrupt Disable */
+#define PDCA_IMR		0x0028	/* Interrupt Mask */
+#define PDCA_ISR		0x002c	/* Interrupt Status */
+# define PDCA_RCZ		(  1 <<  0)	/* Reload Counter Zero */
+# define PDCA_TRC		(  1 <<  1)	/* Transfer Complete */
+# define PDCA_TERR		(  1 <<  2)	/* Transfer Error */
+
+/* Address space occupied by one channel */
+#define PDCA_CHAN_SIZE		0x40
+
+#define pdca_readl(base, reg)				\
+	__raw_readl((base) + PDCA_##reg)
+#define pdca_writel(base, reg, value)			\
+	__raw_writel((value), (base) + PDCA_##reg)
+
+#endif /* __ATMEL_PDCA_H */
diff -urN linux-2.6.28.2-0rig//include/linux/Kbuild linux-2.6.28.2/include/linux/Kbuild
--- linux-2.6.28.2-0rig//include/linux/Kbuild	2009-01-29 08:39:39.000000000 +0100
+++ linux-2.6.28.2/include/linux/Kbuild	2009-01-29 08:52:50.000000000 +0100
@@ -23,6 +23,7 @@
 header-y += atmarp.h
 header-y += atmbr2684.h
 header-y += atmclip.h
+header-y += atmel_mpopfb.h
 header-y += atm_eni.h
 header-y += atm_he.h
 header-y += atm_idt77105.h
diff -urN linux-2.6.28.2-0rig//include/linux/spi/atmel_spi.h linux-2.6.28.2/include/linux/spi/atmel_spi.h
--- linux-2.6.28.2-0rig//include/linux/spi/atmel_spi.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/include/linux/spi/atmel_spi.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,20 @@
+/*
+ * Driver for Atmel AT32 and AT91 SPI Controllers
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SPI_ATMEL_SPI_H
+#define __LINUX_SPI_ATMEL_SPI_H
+
+struct atmel_spi_pdata {
+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
+	struct dma_slave	*rx_dma_slave;
+	struct dma_slave	*tx_dma_slave;
+#endif
+};
+
+#endif /* __LINUX_SPI_ATMEL_SPI_H */
diff -urN linux-2.6.28.2-0rig//include/video/atmel_mpop.h linux-2.6.28.2/include/video/atmel_mpop.h
--- linux-2.6.28.2-0rig//include/video/atmel_mpop.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.28.2/include/video/atmel_mpop.h	2009-01-29 08:52:50.000000000 +0100
@@ -0,0 +1,820 @@
+/*
+ *  Header file for AT32 MPOP Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ATMEL_MPOP_H__
+#define __ATMEL_MPOP_H__
+
+#include <linux/atmel_mpopfb.h>
+
+/* MPOP Controller info data structure */
+struct atmel_mpopfb_info {
+	spinlock_t lock;
+	struct fb_info *info;
+	void __iomem *mmio;
+	unsigned long irq_base;
+	void *slave_base;
+
+	struct platform_device *pdev;
+	struct platform_device *lcdc_pdev;
+	struct clk *mpop_hclk;
+	struct clk *mpop_pclk;
+	unsigned int running;
+	unsigned int connected_to_lcdc;
+	unsigned long lcdc_old_smem_start;
+	unsigned long lcdc_old_bits_per_pixel;
+	struct atmel_mpopfb_baseimg_info baseimg_info;
+	struct atmel_mpopfb_overlay_info overlay_info[3];
+	struct atmel_mpopfb_rgbconv_coeffs rgbconv_coeffs;
+};
+
+/* TODO! Clean up these defines.... */
+#define ATMEL_MPOP_B                                                 0
+#define ATMEL_MPOP_B1                                                0
+#define ATMEL_MPOP_B1_MASK                                  0x00000fff
+#define ATMEL_MPOP_B1_OFFSET                                         0
+#define ATMEL_MPOP_B1_SIZE                                          12
+#define ATMEL_MPOP_B2                                               12
+#define ATMEL_MPOP_B2B1                                     0x00000024
+#define ATMEL_MPOP_B2B1_B1                                           0
+#define ATMEL_MPOP_B2B1_B1_MASK                             0x00000fff
+#define ATMEL_MPOP_B2B1_B1_OFFSET                                    0
+#define ATMEL_MPOP_B2B1_B1_SIZE                                     12
+#define ATMEL_MPOP_B2B1_B2                                          12
+#define ATMEL_MPOP_B2B1_B2_MASK                             0x00fff000
+#define ATMEL_MPOP_B2B1_B2_OFFSET                                   12
+#define ATMEL_MPOP_B2B1_B2_SIZE                                     12
+#define ATMEL_MPOP_B2_MASK                                  0x00fff000
+#define ATMEL_MPOP_B2_OFFSET                                        12
+#define ATMEL_MPOP_B2_SIZE                                          12
+#define ATMEL_MPOP_B3                                                0
+#define ATMEL_MPOP_B3_MASK                                  0x00000fff
+#define ATMEL_MPOP_B3_OFFSET                                         0
+#define ATMEL_MPOP_B3_SIZE                                          12
+#define ATMEL_MPOP_B4                                               12
+#define ATMEL_MPOP_B4B3                                     0x00000028
+#define ATMEL_MPOP_B4B3_B3                                           0
+#define ATMEL_MPOP_B4B3_B3_MASK                             0x00000fff
+#define ATMEL_MPOP_B4B3_B3_OFFSET                                    0
+#define ATMEL_MPOP_B4B3_B3_SIZE                                     12
+#define ATMEL_MPOP_B4B3_B4                                          12
+#define ATMEL_MPOP_B4B3_B4_MASK                             0xfffff000
+#define ATMEL_MPOP_B4B3_B4_OFFSET                                   12
+#define ATMEL_MPOP_B4B3_B4_SIZE                                     20
+#define ATMEL_MPOP_B4_MASK                                  0xfffff000
+#define ATMEL_MPOP_B4_OFFSET                                        12
+#define ATMEL_MPOP_B4_SIZE                                          20
+#define ATMEL_MPOP_BGCOLOR                                  0x00000090
+#define ATMEL_MPOP_BGCOLOR_BGCOLOR                                   0
+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_MASK                     0xffffffff
+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_OFFSET                            0
+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_SIZE                             32
+#define ATMEL_MPOP_BGCOLOR_MASK                             0xffffffff
+#define ATMEL_MPOP_BGCOLOR_OFFSET                                    0
+#define ATMEL_MPOP_BGCOLOR_SIZE                                     32
+#define ATMEL_MPOP_BGR                                               6
+#define ATMEL_MPOP_BGR_MASK                                 0x00000040
+#define ATMEL_MPOP_BGR_OFFSET                                        6
+#define ATMEL_MPOP_BGR_SIZE                                          1
+#define ATMEL_MPOP_B_MASK                                   0x000000ff
+#define ATMEL_MPOP_B_OFFSET                                          0
+#define ATMEL_MPOP_B_SIZE                                            8
+#define ATMEL_MPOP_CACHEDIS                                          8
+#define ATMEL_MPOP_CACHEDIS_MASK                            0x00000100
+#define ATMEL_MPOP_CACHEDIS_OFFSET                                   8
+#define ATMEL_MPOP_CACHEDIS_SIZE                                     1
+#define ATMEL_MPOP_CR                                       0x00000000
+#define ATMEL_MPOP_CR_CACHEDIS                                       8
+#define ATMEL_MPOP_CR_CACHEDIS_MASK                         0x00000100
+#define ATMEL_MPOP_CR_CACHEDIS_OFFSET                                8
+#define ATMEL_MPOP_CR_CACHEDIS_SIZE                                  1
+#define ATMEL_MPOP_CR_EN                                             0
+#define ATMEL_MPOP_CR_EN_MASK                               0x00000001
+#define ATMEL_MPOP_CR_EN_OFFSET                                      0
+#define ATMEL_MPOP_CR_EN_SIZE                                        1
+#define ATMEL_MPOP_CR_OUT_BGR                                        3
+#define ATMEL_MPOP_CR_OUT_BGR_MASK                          0x00000008
+#define ATMEL_MPOP_CR_OUT_BGR_OFFSET                                 3
+#define ATMEL_MPOP_CR_OUT_BGR_SIZE                                   1
+#define ATMEL_MPOP_CR_OUT_CTRL                                       2
+#define ATMEL_MPOP_CR_OUT_CTRL_MASK                         0x00000004
+#define ATMEL_MPOP_CR_OUT_CTRL_OFFSET                                2
+#define ATMEL_MPOP_CR_OUT_CTRL_SIZE                                  1
+#define ATMEL_MPOP_CR_START                                          1
+#define ATMEL_MPOP_CR_START_MASK                            0x00000002
+#define ATMEL_MPOP_CR_START_OFFSET                                   1
+#define ATMEL_MPOP_CR_START_SIZE                                     1
+#define ATMEL_MPOP_CURSOREN                                          0
+#define ATMEL_MPOP_CURSOREN_MASK                            0x00000001
+#define ATMEL_MPOP_CURSOREN_OFFSET                                   0
+#define ATMEL_MPOP_CURSOREN_SIZE                                     1
+#define ATMEL_MPOP_CURSOR_P0                                0x00000080
+#define ATMEL_MPOP_CURSOR_P0_B                                       0
+#define ATMEL_MPOP_CURSOR_P0_B_MASK                         0x000000ff
+#define ATMEL_MPOP_CURSOR_P0_B_OFFSET                                0
+#define ATMEL_MPOP_CURSOR_P0_B_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P0_G                                       8
+#define ATMEL_MPOP_CURSOR_P0_G_MASK                         0x0000ff00
+#define ATMEL_MPOP_CURSOR_P0_G_OFFSET                                8
+#define ATMEL_MPOP_CURSOR_P0_G_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P0_INVERT                                 25
+#define ATMEL_MPOP_CURSOR_P0_INVERT_MASK                    0x02000000
+#define ATMEL_MPOP_CURSOR_P0_INVERT_OFFSET                          25
+#define ATMEL_MPOP_CURSOR_P0_INVERT_SIZE                             1
+#define ATMEL_MPOP_CURSOR_P0_R                                      16
+#define ATMEL_MPOP_CURSOR_P0_R_MASK                         0x00ff0000
+#define ATMEL_MPOP_CURSOR_P0_R_OFFSET                               16
+#define ATMEL_MPOP_CURSOR_P0_R_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P0_VISIBLE                                24
+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_MASK                   0x01000000
+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_OFFSET                         24
+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_SIZE                            1
+#define ATMEL_MPOP_CURSOR_P1                                0x00000084
+#define ATMEL_MPOP_CURSOR_P1_B                                       0
+#define ATMEL_MPOP_CURSOR_P1_B_MASK                         0x000000ff
+#define ATMEL_MPOP_CURSOR_P1_B_OFFSET                                0
+#define ATMEL_MPOP_CURSOR_P1_B_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P1_G                                       8
+#define ATMEL_MPOP_CURSOR_P1_G_MASK                         0x0000ff00
+#define ATMEL_MPOP_CURSOR_P1_G_OFFSET                                8
+#define ATMEL_MPOP_CURSOR_P1_G_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P1_INVERT                                 25
+#define ATMEL_MPOP_CURSOR_P1_INVERT_MASK                    0x02000000
+#define ATMEL_MPOP_CURSOR_P1_INVERT_OFFSET                          25
+#define ATMEL_MPOP_CURSOR_P1_INVERT_SIZE                             1
+#define ATMEL_MPOP_CURSOR_P1_R                                      16
+#define ATMEL_MPOP_CURSOR_P1_R_MASK                         0x00ff0000
+#define ATMEL_MPOP_CURSOR_P1_R_OFFSET                               16
+#define ATMEL_MPOP_CURSOR_P1_R_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P1_VISIBLE                                24
+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_MASK                   0x01000000
+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_OFFSET                         24
+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_SIZE                            1
+#define ATMEL_MPOP_CURSOR_P2                                0x00000088
+#define ATMEL_MPOP_CURSOR_P2_B                                       0
+#define ATMEL_MPOP_CURSOR_P2_B_MASK                         0x000000ff
+#define ATMEL_MPOP_CURSOR_P2_B_OFFSET                                0
+#define ATMEL_MPOP_CURSOR_P2_B_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P2_G                                       8
+#define ATMEL_MPOP_CURSOR_P2_G_MASK                         0x0000ff00
+#define ATMEL_MPOP_CURSOR_P2_G_OFFSET                                8
+#define ATMEL_MPOP_CURSOR_P2_G_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P2_INVERT                                 25
+#define ATMEL_MPOP_CURSOR_P2_INVERT_MASK                    0x02000000
+#define ATMEL_MPOP_CURSOR_P2_INVERT_OFFSET                          25
+#define ATMEL_MPOP_CURSOR_P2_INVERT_SIZE                             1
+#define ATMEL_MPOP_CURSOR_P2_R                                      16
+#define ATMEL_MPOP_CURSOR_P2_R_MASK                         0x00ff0000
+#define ATMEL_MPOP_CURSOR_P2_R_OFFSET                               16
+#define ATMEL_MPOP_CURSOR_P2_R_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P2_VISIBLE                                24
+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_MASK                   0x01000000
+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_OFFSET                         24
+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_SIZE                            1
+#define ATMEL_MPOP_CURSOR_P3                                0x0000008c
+#define ATMEL_MPOP_CURSOR_P3_B                                       0
+#define ATMEL_MPOP_CURSOR_P3_B_MASK                         0x000000ff
+#define ATMEL_MPOP_CURSOR_P3_B_OFFSET                                0
+#define ATMEL_MPOP_CURSOR_P3_B_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P3_G                                       8
+#define ATMEL_MPOP_CURSOR_P3_G_MASK                         0x0000ff00
+#define ATMEL_MPOP_CURSOR_P3_G_OFFSET                                8
+#define ATMEL_MPOP_CURSOR_P3_G_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P3_INVERT                                 25
+#define ATMEL_MPOP_CURSOR_P3_INVERT_MASK                    0x02000000
+#define ATMEL_MPOP_CURSOR_P3_INVERT_OFFSET                          25
+#define ATMEL_MPOP_CURSOR_P3_INVERT_SIZE                             1
+#define ATMEL_MPOP_CURSOR_P3_R                                      16
+#define ATMEL_MPOP_CURSOR_P3_R_MASK                         0x00ff0000
+#define ATMEL_MPOP_CURSOR_P3_R_OFFSET                               16
+#define ATMEL_MPOP_CURSOR_P3_R_SIZE                                  8
+#define ATMEL_MPOP_CURSOR_P3_VISIBLE                                24
+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_MASK                   0x01000000
+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_OFFSET                         24
+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_SIZE                            1
+#define ATMEL_MPOP_CURSOR_POS                               0x00000058
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X                          11
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_MASK             0x003ff800
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_OFFSET                   11
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_SIZE                     11
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y                           0
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_MASK             0x000007ff
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_OFFSET                    0
+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_SIZE                     11
+#define ATMEL_MPOP_CURSOR_POS_X                                     11
+#define ATMEL_MPOP_CURSOR_POS_X_MASK                        0x003ff800
+#define ATMEL_MPOP_CURSOR_POS_X_OFFSET                              11
+#define ATMEL_MPOP_CURSOR_POS_X_SIZE                                11
+#define ATMEL_MPOP_CURSOR_POS_Y                                      0
+#define ATMEL_MPOP_CURSOR_POS_Y_MASK                        0x000007ff
+#define ATMEL_MPOP_CURSOR_POS_Y_OFFSET                               0
+#define ATMEL_MPOP_CURSOR_POS_Y_SIZE                                11
+#define ATMEL_MPOP_CURSOR_SAR                               0x00000048
+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR                             0
+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_MASK               0xffffffff
+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_OFFSET                      0
+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_SIZE                       32
+#define ATMEL_MPOP_CURSOR_SAR_MASK                          0xffffffff
+#define ATMEL_MPOP_CURSOR_SAR_OFFSET                                 0
+#define ATMEL_MPOP_CURSOR_SAR_SIZE                                  32
+#define ATMEL_MPOP_CURSOR_SIZE                              0x0000006c
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X                        11
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_MASK           0x003ff800
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_OFFSET                 11
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_SIZE                   11
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y                         0
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_MASK           0x000007ff
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_OFFSET                  0
+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_SIZE                   11
+#define ATMEL_MPOP_CURSOR_SIZE_X                                    11
+#define ATMEL_MPOP_CURSOR_SIZE_X_MASK                       0x003ff800
+#define ATMEL_MPOP_CURSOR_SIZE_X_OFFSET                             11
+#define ATMEL_MPOP_CURSOR_SIZE_X_SIZE                               11
+#define ATMEL_MPOP_CURSOR_SIZE_Y                                     0
+#define ATMEL_MPOP_CURSOR_SIZE_Y_MASK                       0x000007ff
+#define ATMEL_MPOP_CURSOR_SIZE_Y_OFFSET                              0
+#define ATMEL_MPOP_CURSOR_SIZE_Y_SIZE                               11
+#define ATMEL_MPOP_CURSOR_WTC                               0x0000007c
+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC                             0
+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_MASK               0xffffffff
+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_OFFSET                      0
+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_SIZE                       32
+#define ATMEL_MPOP_CURSOR_WTC_MASK                          0xffffffff
+#define ATMEL_MPOP_CURSOR_WTC_OFFSET                                 0
+#define ATMEL_MPOP_CURSOR_WTC_SIZE                                  32
+#define ATMEL_MPOP_DISP_MAX_COORD                           0x00000010
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X                  11
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_MASK     0x003ff800
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_OFFSET           11
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_SIZE             11
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y                   0
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_MASK     0x000007ff
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_OFFSET            0
+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_SIZE             11
+#define ATMEL_MPOP_DISP_MAX_COORD_X                                 11
+#define ATMEL_MPOP_DISP_MAX_COORD_X_MASK                    0x003ff800
+#define ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET                          11
+#define ATMEL_MPOP_DISP_MAX_COORD_X_SIZE                            11
+#define ATMEL_MPOP_DISP_MAX_COORD_Y                                  0
+#define ATMEL_MPOP_DISP_MAX_COORD_Y_MASK                    0x000007ff
+#define ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET                           0
+#define ATMEL_MPOP_DISP_MAX_COORD_Y_SIZE                            11
+#define ATMEL_MPOP_EN                                                0
+#define ATMEL_MPOP_EN_MASK                                  0x00000001
+#define ATMEL_MPOP_EN_OFFSET                                         0
+#define ATMEL_MPOP_EN_SIZE                                           1
+#define ATMEL_MPOP_EOP                                               3
+#define ATMEL_MPOP_EOP_MASK                                 0x00000008
+#define ATMEL_MPOP_EOP_OFFSET                                        3
+#define ATMEL_MPOP_EOP_SIZE                                          1
+#define ATMEL_MPOP_G                                                 8
+#define ATMEL_MPOP_G1                                                0
+#define ATMEL_MPOP_G1_MASK                                  0x00000fff
+#define ATMEL_MPOP_G1_OFFSET                                         0
+#define ATMEL_MPOP_G1_SIZE                                          12
+#define ATMEL_MPOP_G2                                               12
+#define ATMEL_MPOP_G2G1                                     0x0000001c
+#define ATMEL_MPOP_G2G1_G1                                           0
+#define ATMEL_MPOP_G2G1_G1_MASK                             0x00000fff
+#define ATMEL_MPOP_G2G1_G1_OFFSET                                    0
+#define ATMEL_MPOP_G2G1_G1_SIZE                                     12
+#define ATMEL_MPOP_G2G1_G2                                          12
+#define ATMEL_MPOP_G2G1_G2_MASK                             0x00fff000
+#define ATMEL_MPOP_G2G1_G2_OFFSET                                   12
+#define ATMEL_MPOP_G2G1_G2_SIZE                                     12
+#define ATMEL_MPOP_G2_MASK                                  0x00fff000
+#define ATMEL_MPOP_G2_OFFSET                                        12
+#define ATMEL_MPOP_G2_SIZE                                          12
+#define ATMEL_MPOP_G3                                                0
+#define ATMEL_MPOP_G3_MASK                                  0x00000fff
+#define ATMEL_MPOP_G3_OFFSET                                         0
+#define ATMEL_MPOP_G3_SIZE                                          12
+#define ATMEL_MPOP_G4                                               12
+#define ATMEL_MPOP_G4G3                                     0x00000020
+#define ATMEL_MPOP_G4G3_G3                                           0
+#define ATMEL_MPOP_G4G3_G3_MASK                             0x00000fff
+#define ATMEL_MPOP_G4G3_G3_OFFSET                                    0
+#define ATMEL_MPOP_G4G3_G3_SIZE                                     12
+#define ATMEL_MPOP_G4G3_G4                                          12
+#define ATMEL_MPOP_G4G3_G4_MASK                             0xfffff000
+#define ATMEL_MPOP_G4G3_G4_OFFSET                                   12
+#define ATMEL_MPOP_G4G3_G4_SIZE                                     20
+#define ATMEL_MPOP_G4_MASK                                  0xfffff000
+#define ATMEL_MPOP_G4_OFFSET                                        12
+#define ATMEL_MPOP_G4_SIZE                                          20
+#define ATMEL_MPOP_G_MASK                                   0x0000ff00
+#define ATMEL_MPOP_G_OFFSET                                          8
+#define ATMEL_MPOP_G_SIZE                                            8
+#define ATMEL_MPOP_INTCLEAR                                 0x000000b0
+#define ATMEL_MPOP_INTCLEAR_EOP                                      3
+#define ATMEL_MPOP_INTCLEAR_EOP_MASK                        0x00000008
+#define ATMEL_MPOP_INTCLEAR_EOP_OFFSET                               3
+#define ATMEL_MPOP_INTCLEAR_EOP_SIZE                                 1
+#define ATMEL_MPOP_INTCLEAR_OUT                                      2
+#define ATMEL_MPOP_INTCLEAR_OUT_MASK                        0x00000004
+#define ATMEL_MPOP_INTCLEAR_OUT_OFFSET                               2
+#define ATMEL_MPOP_INTCLEAR_OUT_SIZE                                 1
+#define ATMEL_MPOP_INTCLEAR_OVERLAY                                  1
+#define ATMEL_MPOP_INTCLEAR_OVERLAY_MASK                    0x00000002
+#define ATMEL_MPOP_INTCLEAR_OVERLAY_OFFSET                           1
+#define ATMEL_MPOP_INTCLEAR_OVERLAY_SIZE                             1
+#define ATMEL_MPOP_INTCLEAR_SOP                                      4
+#define ATMEL_MPOP_INTCLEAR_SOP_MASK                        0x00000010
+#define ATMEL_MPOP_INTCLEAR_SOP_OFFSET                               4
+#define ATMEL_MPOP_INTCLEAR_SOP_SIZE                                 1
+#define ATMEL_MPOP_INTCLEAR_YUV                                      0
+#define ATMEL_MPOP_INTCLEAR_YUV_MASK                        0x00000001
+#define ATMEL_MPOP_INTCLEAR_YUV_OFFSET                               0
+#define ATMEL_MPOP_INTCLEAR_YUV_SIZE                                 1
+#define ATMEL_MPOP_INTDIS                                   0x000000a4
+#define ATMEL_MPOP_INTDIS_EOP                                        3
+#define ATMEL_MPOP_INTDIS_EOP_MASK                          0x00000008
+#define ATMEL_MPOP_INTDIS_EOP_OFFSET                                 3
+#define ATMEL_MPOP_INTDIS_EOP_SIZE                                   1
+#define ATMEL_MPOP_INTDIS_OUT                                        2
+#define ATMEL_MPOP_INTDIS_OUT_MASK                          0x00000004
+#define ATMEL_MPOP_INTDIS_OUT_OFFSET                                 2
+#define ATMEL_MPOP_INTDIS_OUT_SIZE                                   1
+#define ATMEL_MPOP_INTDIS_OVERLAY                                    1
+#define ATMEL_MPOP_INTDIS_OVERLAY_MASK                      0x00000002
+#define ATMEL_MPOP_INTDIS_OVERLAY_OFFSET                             1
+#define ATMEL_MPOP_INTDIS_OVERLAY_SIZE                               1
+#define ATMEL_MPOP_INTDIS_SOP                                        4
+#define ATMEL_MPOP_INTDIS_SOP_MASK                          0x00000010
+#define ATMEL_MPOP_INTDIS_SOP_OFFSET                                 4
+#define ATMEL_MPOP_INTDIS_SOP_SIZE                                   1
+#define ATMEL_MPOP_INTDIS_YUV                                        0
+#define ATMEL_MPOP_INTDIS_YUV_MASK                          0x00000001
+#define ATMEL_MPOP_INTDIS_YUV_OFFSET                                 0
+#define ATMEL_MPOP_INTDIS_YUV_SIZE                                   1
+#define ATMEL_MPOP_INTEN                                    0x000000a0
+#define ATMEL_MPOP_INTEN_EOP                                         3
+#define ATMEL_MPOP_INTEN_EOP_MASK                           0x00000008
+#define ATMEL_MPOP_INTEN_EOP_OFFSET                                  3
+#define ATMEL_MPOP_INTEN_EOP_SIZE                                    1
+#define ATMEL_MPOP_INTEN_OUT                                         2
+#define ATMEL_MPOP_INTEN_OUT_MASK                           0x00000004
+#define ATMEL_MPOP_INTEN_OUT_OFFSET                                  2
+#define ATMEL_MPOP_INTEN_OUT_SIZE                                    1
+#define ATMEL_MPOP_INTEN_OVERLAY                                     1
+#define ATMEL_MPOP_INTEN_OVERLAY_MASK                       0x00000002
+#define ATMEL_MPOP_INTEN_OVERLAY_OFFSET                              1
+#define ATMEL_MPOP_INTEN_OVERLAY_SIZE                                1
+#define ATMEL_MPOP_INTEN_SOP                                         4
+#define ATMEL_MPOP_INTEN_SOP_MASK                           0x00000010
+#define ATMEL_MPOP_INTEN_SOP_OFFSET                                  4
+#define ATMEL_MPOP_INTEN_SOP_SIZE                                    1
+#define ATMEL_MPOP_INTEN_YUV                                         0
+#define ATMEL_MPOP_INTEN_YUV_MASK                           0x00000001
+#define ATMEL_MPOP_INTEN_YUV_OFFSET                                  0
+#define ATMEL_MPOP_INTEN_YUV_SIZE                                    1
+#define ATMEL_MPOP_INTMASK                                  0x000000a8
+#define ATMEL_MPOP_INTMASK_EOP                                       3
+#define ATMEL_MPOP_INTMASK_EOP_MASK                         0x00000008
+#define ATMEL_MPOP_INTMASK_EOP_OFFSET                                3
+#define ATMEL_MPOP_INTMASK_EOP_SIZE                                  1
+#define ATMEL_MPOP_INTMASK_OUT                                       2
+#define ATMEL_MPOP_INTMASK_OUT_MASK                         0x00000004
+#define ATMEL_MPOP_INTMASK_OUT_OFFSET                                2
+#define ATMEL_MPOP_INTMASK_OUT_SIZE                                  1
+#define ATMEL_MPOP_INTMASK_OVERLAY                                   1
+#define ATMEL_MPOP_INTMASK_OVERLAY_MASK                     0x00000002
+#define ATMEL_MPOP_INTMASK_OVERLAY_OFFSET                            1
+#define ATMEL_MPOP_INTMASK_OVERLAY_SIZE                              1
+#define ATMEL_MPOP_INTMASK_SOP                                       4
+#define ATMEL_MPOP_INTMASK_SOP_MASK                         0x00000010
+#define ATMEL_MPOP_INTMASK_SOP_OFFSET                                4
+#define ATMEL_MPOP_INTMASK_SOP_SIZE                                  1
+#define ATMEL_MPOP_INTMASK_YUV                                       0
+#define ATMEL_MPOP_INTMASK_YUV_MASK                         0x00000001
+#define ATMEL_MPOP_INTMASK_YUV_OFFSET                                0
+#define ATMEL_MPOP_INTMASK_YUV_SIZE                                  1
+#define ATMEL_MPOP_INTSTATUS                                0x000000ac
+#define ATMEL_MPOP_INTSTATUS_EOP                                     3
+#define ATMEL_MPOP_INTSTATUS_EOP_MASK                       0x00000008
+#define ATMEL_MPOP_INTSTATUS_EOP_OFFSET                              3
+#define ATMEL_MPOP_INTSTATUS_EOP_SIZE                                1
+#define ATMEL_MPOP_INTSTATUS_OUT                                     2
+#define ATMEL_MPOP_INTSTATUS_OUT_MASK                       0x00000004
+#define ATMEL_MPOP_INTSTATUS_OUT_OFFSET                              2
+#define ATMEL_MPOP_INTSTATUS_OUT_SIZE                                1
+#define ATMEL_MPOP_INTSTATUS_OVERLAY                                 1
+#define ATMEL_MPOP_INTSTATUS_OVERLAY_MASK                   0x00000002
+#define ATMEL_MPOP_INTSTATUS_OVERLAY_OFFSET                          1
+#define ATMEL_MPOP_INTSTATUS_OVERLAY_SIZE                            1
+#define ATMEL_MPOP_INTSTATUS_SOP                                     4
+#define ATMEL_MPOP_INTSTATUS_SOP_MASK                       0x00000010
+#define ATMEL_MPOP_INTSTATUS_SOP_OFFSET                              4
+#define ATMEL_MPOP_INTSTATUS_SOP_SIZE                                1
+#define ATMEL_MPOP_INTSTATUS_YUV                                     0
+#define ATMEL_MPOP_INTSTATUS_YUV_MASK                       0x00000001
+#define ATMEL_MPOP_INTSTATUS_YUV_OFFSET                              0
+#define ATMEL_MPOP_INTSTATUS_YUV_SIZE                                1
+#define ATMEL_MPOP_INVERT                                           25
+#define ATMEL_MPOP_INVERT_MASK                              0x02000000
+#define ATMEL_MPOP_INVERT_OFFSET                                    25
+#define ATMEL_MPOP_INVERT_SIZE                                       1
+#define ATMEL_MPOP_MSTR_PTR                                 0x0000000c
+#define ATMEL_MPOP_MSTR_PTR_MASK                            0xffffffff
+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR                                 0
+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_MASK                   0xffffffff
+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_OFFSET                          0
+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_SIZE                           32
+#define ATMEL_MPOP_MSTR_PTR_OFFSET                                   0
+#define ATMEL_MPOP_MSTR_PTR_SIZE                                    32
+#define ATMEL_MPOP_O1EN                                              1
+#define ATMEL_MPOP_O1EN_MASK                                0x00000002
+#define ATMEL_MPOP_O1EN_OFFSET                                       1
+#define ATMEL_MPOP_O1EN_SIZE                                         1
+#define ATMEL_MPOP_O1_POS                                   0x00000050
+#define ATMEL_MPOP_O1_POS_O1_POS_X                                  11
+#define ATMEL_MPOP_O1_POS_O1_POS_X_MASK                     0x003ff800
+#define ATMEL_MPOP_O1_POS_O1_POS_X_OFFSET                           11
+#define ATMEL_MPOP_O1_POS_O1_POS_X_SIZE                             11
+#define ATMEL_MPOP_O1_POS_O1_POS_Y                                   0
+#define ATMEL_MPOP_O1_POS_O1_POS_Y_MASK                     0x000007ff
+#define ATMEL_MPOP_O1_POS_O1_POS_Y_OFFSET                            0
+#define ATMEL_MPOP_O1_POS_O1_POS_Y_SIZE                             11
+#define ATMEL_MPOP_O1_POS_X                                         11
+#define ATMEL_MPOP_O1_POS_X_MASK                            0x003ff800
+#define ATMEL_MPOP_O1_POS_X_OFFSET                                  11
+#define ATMEL_MPOP_O1_POS_X_SIZE                                    11
+#define ATMEL_MPOP_O1_POS_Y                                          0
+#define ATMEL_MPOP_O1_POS_Y_MASK                            0x000007ff
+#define ATMEL_MPOP_O1_POS_Y_OFFSET                                   0
+#define ATMEL_MPOP_O1_POS_Y_SIZE                                    11
+#define ATMEL_MPOP_O1_SAR                                   0x00000040
+#define ATMEL_MPOP_O1_SAR_MASK                              0xffffffff
+#define ATMEL_MPOP_O1_SAR_O1_SAR                                     0
+#define ATMEL_MPOP_O1_SAR_O1_SAR_MASK                       0xffffffff
+#define ATMEL_MPOP_O1_SAR_O1_SAR_OFFSET                              0
+#define ATMEL_MPOP_O1_SAR_O1_SAR_SIZE                               32
+#define ATMEL_MPOP_O1_SAR_OFFSET                                     0
+#define ATMEL_MPOP_O1_SAR_SIZE                                      32
+#define ATMEL_MPOP_O1_SIZE                                  0x00000064
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X                                11
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_MASK                   0x003ff800
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_OFFSET                         11
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_SIZE                           11
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y                                 0
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_MASK                   0x000007ff
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_OFFSET                          0
+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_SIZE                           11
+#define ATMEL_MPOP_O1_SIZE_X                                        11
+#define ATMEL_MPOP_O1_SIZE_X_MASK                           0x003ff800
+#define ATMEL_MPOP_O1_SIZE_X_OFFSET                                 11
+#define ATMEL_MPOP_O1_SIZE_X_SIZE                                   11
+#define ATMEL_MPOP_O1_SIZE_Y                                         0
+#define ATMEL_MPOP_O1_SIZE_Y_MASK                           0x000007ff
+#define ATMEL_MPOP_O1_SIZE_Y_OFFSET                                  0
+#define ATMEL_MPOP_O1_SIZE_Y_SIZE                                   11
+#define ATMEL_MPOP_O1_WTC                                   0x00000074
+#define ATMEL_MPOP_O1_WTC_MASK                              0xffffffff
+#define ATMEL_MPOP_O1_WTC_O1_WTC                                     0
+#define ATMEL_MPOP_O1_WTC_O1_WTC_MASK                       0xffffffff
+#define ATMEL_MPOP_O1_WTC_O1_WTC_OFFSET                              0
+#define ATMEL_MPOP_O1_WTC_O1_WTC_SIZE                               32
+#define ATMEL_MPOP_O1_WTC_OFFSET                                     0
+#define ATMEL_MPOP_O1_WTC_SIZE                                      32
+#define ATMEL_MPOP_O2EN                                              2
+#define ATMEL_MPOP_O2EN_MASK                                0x00000004
+#define ATMEL_MPOP_O2EN_OFFSET                                       2
+#define ATMEL_MPOP_O2EN_SIZE                                         1
+#define ATMEL_MPOP_O2_POS                                   0x00000054
+#define ATMEL_MPOP_O2_POS_O2_POS_X                                  11
+#define ATMEL_MPOP_O2_POS_O2_POS_X_MASK                     0x003ff800
+#define ATMEL_MPOP_O2_POS_O2_POS_X_OFFSET                           11
+#define ATMEL_MPOP_O2_POS_O2_POS_X_SIZE                             11
+#define ATMEL_MPOP_O2_POS_O2_POS_Y                                   0
+#define ATMEL_MPOP_O2_POS_O2_POS_Y_MASK                     0x000007ff
+#define ATMEL_MPOP_O2_POS_O2_POS_Y_OFFSET                            0
+#define ATMEL_MPOP_O2_POS_O2_POS_Y_SIZE                             11
+#define ATMEL_MPOP_O2_POS_X                                         11
+#define ATMEL_MPOP_O2_POS_X_MASK                            0x003ff800
+#define ATMEL_MPOP_O2_POS_X_OFFSET                                  11
+#define ATMEL_MPOP_O2_POS_X_SIZE                                    11
+#define ATMEL_MPOP_O2_POS_Y                                          0
+#define ATMEL_MPOP_O2_POS_Y_MASK                            0x000007ff
+#define ATMEL_MPOP_O2_POS_Y_OFFSET                                   0
+#define ATMEL_MPOP_O2_POS_Y_SIZE                                    11
+#define ATMEL_MPOP_O2_SAR                                   0x00000044
+#define ATMEL_MPOP_O2_SAR_MASK                              0xffffffff
+#define ATMEL_MPOP_O2_SAR_O2_SAR                                     0
+#define ATMEL_MPOP_O2_SAR_O2_SAR_MASK                       0xffffffff
+#define ATMEL_MPOP_O2_SAR_O2_SAR_OFFSET                              0
+#define ATMEL_MPOP_O2_SAR_O2_SAR_SIZE                               32
+#define ATMEL_MPOP_O2_SAR_OFFSET                                     0
+#define ATMEL_MPOP_O2_SAR_SIZE                                      32
+#define ATMEL_MPOP_O2_SIZE                                  0x00000068
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X                                11
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_MASK                   0x003ff800
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_OFFSET                         11
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_SIZE                           11
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y                                 0
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_MASK                   0x000007ff
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_OFFSET                          0
+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_SIZE                           11
+#define ATMEL_MPOP_O2_SIZE_X                                        11
+#define ATMEL_MPOP_O2_SIZE_X_MASK                           0x003ff800
+#define ATMEL_MPOP_O2_SIZE_X_OFFSET                                 11
+#define ATMEL_MPOP_O2_SIZE_X_SIZE                                   11
+#define ATMEL_MPOP_O2_SIZE_Y                                         0
+#define ATMEL_MPOP_O2_SIZE_Y_MASK                           0x000007ff
+#define ATMEL_MPOP_O2_SIZE_Y_OFFSET                                  0
+#define ATMEL_MPOP_O2_SIZE_Y_SIZE                                   11
+#define ATMEL_MPOP_O2_WTC                                   0x00000078
+#define ATMEL_MPOP_O2_WTC_MASK                              0xffffffff
+#define ATMEL_MPOP_O2_WTC_O2_WTC                                     0
+#define ATMEL_MPOP_O2_WTC_O2_WTC_MASK                       0xffffffff
+#define ATMEL_MPOP_O2_WTC_O2_WTC_OFFSET                              0
+#define ATMEL_MPOP_O2_WTC_O2_WTC_SIZE                               32
+#define ATMEL_MPOP_O2_WTC_OFFSET                                     0
+#define ATMEL_MPOP_O2_WTC_SIZE                                      32
+#define ATMEL_MPOP_OCR                                      0x00000008
+#define ATMEL_MPOP_OCR_BGR                                           6
+#define ATMEL_MPOP_OCR_BGR_MASK                             0x00000040
+#define ATMEL_MPOP_OCR_BGR_OFFSET                                    6
+#define ATMEL_MPOP_OCR_BGR_SIZE                                      1
+#define ATMEL_MPOP_OCR_CURSOREN                                      0
+#define ATMEL_MPOP_OCR_CURSOREN_MASK                        0x00000001
+#define ATMEL_MPOP_OCR_CURSOREN_OFFSET                               0
+#define ATMEL_MPOP_OCR_CURSOREN_SIZE                                 1
+#define ATMEL_MPOP_OCR_O1EN                                          1
+#define ATMEL_MPOP_OCR_O1EN_MASK                            0x00000002
+#define ATMEL_MPOP_OCR_O1EN_OFFSET                                   1
+#define ATMEL_MPOP_OCR_O1EN_SIZE                                     1
+#define ATMEL_MPOP_OCR_O2EN                                          2
+#define ATMEL_MPOP_OCR_O2EN_MASK                            0x00000004
+#define ATMEL_MPOP_OCR_O2EN_OFFSET                                   2
+#define ATMEL_MPOP_OCR_O2EN_SIZE                                     1
+#define ATMEL_MPOP_OCR_RGBEN                                         3
+#define ATMEL_MPOP_OCR_RGBEN_MASK                           0x00000008
+#define ATMEL_MPOP_OCR_RGBEN_OFFSET                                  3
+#define ATMEL_MPOP_OCR_RGBEN_SIZE                                    1
+#define ATMEL_MPOP_OCR_RGBFORM                                       5
+#define ATMEL_MPOP_OCR_RGBFORM_MASK                         0x00000020
+#define ATMEL_MPOP_OCR_RGBFORM_OFFSET                                5
+#define ATMEL_MPOP_OCR_RGBFORM_SIZE                                  1
+#define ATMEL_MPOP_OCR_RGBSRC                                        4
+#define ATMEL_MPOP_OCR_RGBSRC_MASK                          0x00000010
+#define ATMEL_MPOP_OCR_RGBSRC_OFFSET                                 4
+#define ATMEL_MPOP_OCR_RGBSRC_SIZE                                   1
+#define ATMEL_MPOP_OUT                                               2
+#define ATMEL_MPOP_OUT_BEAR                                 0x0000009c
+#define ATMEL_MPOP_OUT_BEAR_MASK                            0xffffffff
+#define ATMEL_MPOP_OUT_BEAR_OFFSET                                   0
+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR                                 0
+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_MASK                   0xffffffff
+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_OFFSET                          0
+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_SIZE                           32
+#define ATMEL_MPOP_OUT_BEAR_SIZE                                    32
+#define ATMEL_MPOP_OUT_BGR                                           3
+#define ATMEL_MPOP_OUT_BGR_MASK                             0x00000008
+#define ATMEL_MPOP_OUT_BGR_OFFSET                                    3
+#define ATMEL_MPOP_OUT_BGR_SIZE                                      1
+#define ATMEL_MPOP_OUT_CTRL                                          2
+#define ATMEL_MPOP_OUT_CTRL_MASK                            0x00000004
+#define ATMEL_MPOP_OUT_CTRL_OFFSET                                   2
+#define ATMEL_MPOP_OUT_CTRL_SIZE                                     1
+#define ATMEL_MPOP_OUT_MASK                                 0x00000004
+#define ATMEL_MPOP_OUT_OFFSET                                        2
+#define ATMEL_MPOP_OUT_SIZE                                          1
+#define ATMEL_MPOP_OVERLAY                                           1
+#define ATMEL_MPOP_OVERLAY_BEAR                             0x00000098
+#define ATMEL_MPOP_OVERLAY_BEAR_MASK                        0xffffffff
+#define ATMEL_MPOP_OVERLAY_BEAR_OFFSET                               0
+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR                         0
+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_MASK           0xffffffff
+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_OFFSET                  0
+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_SIZE                   32
+#define ATMEL_MPOP_OVERLAY_BEAR_SIZE                                32
+#define ATMEL_MPOP_OVERLAY_MASK                             0x00000002
+#define ATMEL_MPOP_OVERLAY_OFFSET                                    1
+#define ATMEL_MPOP_OVERLAY_SIZE                                      1
+#define ATMEL_MPOP_PALETTEDATA                              0x00000400
+#define ATMEL_MPOP_R                                                16
+#define ATMEL_MPOP_R1                                                0
+#define ATMEL_MPOP_R1_MASK                                  0x00000fff
+#define ATMEL_MPOP_R1_OFFSET                                         0
+#define ATMEL_MPOP_R1_SIZE                                          12
+#define ATMEL_MPOP_R2                                               12
+#define ATMEL_MPOP_R2R1                                     0x00000014
+#define ATMEL_MPOP_R2R1_R1                                           0
+#define ATMEL_MPOP_R2R1_R1_MASK                             0x00000fff
+#define ATMEL_MPOP_R2R1_R1_OFFSET                                    0
+#define ATMEL_MPOP_R2R1_R1_SIZE                                     12
+#define ATMEL_MPOP_R2R1_R2                                          12
+#define ATMEL_MPOP_R2R1_R2_MASK                             0x00fff000
+#define ATMEL_MPOP_R2R1_R2_OFFSET                                   12
+#define ATMEL_MPOP_R2R1_R2_SIZE                                     12
+#define ATMEL_MPOP_R2_MASK                                  0x00fff000
+#define ATMEL_MPOP_R2_OFFSET                                        12
+#define ATMEL_MPOP_R2_SIZE                                          12
+#define ATMEL_MPOP_R3                                                0
+#define ATMEL_MPOP_R3_MASK                                  0x00000fff
+#define ATMEL_MPOP_R3_OFFSET                                         0
+#define ATMEL_MPOP_R3_SIZE                                          12
+#define ATMEL_MPOP_R4                                               12
+#define ATMEL_MPOP_R4R3                                     0x00000018
+#define ATMEL_MPOP_R4R3_R3                                           0
+#define ATMEL_MPOP_R4R3_R3_MASK                             0x00000fff
+#define ATMEL_MPOP_R4R3_R3_OFFSET                                    0
+#define ATMEL_MPOP_R4R3_R3_SIZE                                     12
+#define ATMEL_MPOP_R4R3_R4                                          12
+#define ATMEL_MPOP_R4R3_R4_MASK                             0xfffff000
+#define ATMEL_MPOP_R4R3_R4_OFFSET                                   12
+#define ATMEL_MPOP_R4R3_R4_SIZE                                     20
+#define ATMEL_MPOP_R4_MASK                                  0xfffff000
+#define ATMEL_MPOP_R4_OFFSET                                        12
+#define ATMEL_MPOP_R4_SIZE                                          20
+#define ATMEL_MPOP_RGBEN                                             3
+#define ATMEL_MPOP_RGBEN_MASK                               0x00000008
+#define ATMEL_MPOP_RGBEN_OFFSET                                      3
+#define ATMEL_MPOP_RGBEN_SIZE                                        1
+#define ATMEL_MPOP_RGBFORM                                           5
+#define ATMEL_MPOP_RGBFORM_MASK                             0x00000020
+#define ATMEL_MPOP_RGBFORM_OFFSET                                    5
+#define ATMEL_MPOP_RGBFORM_SIZE                                      1
+#define ATMEL_MPOP_RGBSRC                                            4
+#define ATMEL_MPOP_RGBSRC_MASK                              0x00000010
+#define ATMEL_MPOP_RGBSRC_OFFSET                                     4
+#define ATMEL_MPOP_RGBSRC_SIZE                                       1
+#define ATMEL_MPOP_RGB_POS                                  0x0000004c
+#define ATMEL_MPOP_RGB_POS_RGB_POS_X                                11
+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_MASK                   0x003ff800
+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_OFFSET                         11
+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_SIZE                           11
+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y                                 0
+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_MASK                   0x000007ff
+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_OFFSET                          0
+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_SIZE                           11
+#define ATMEL_MPOP_RGB_POS_X                                        11
+#define ATMEL_MPOP_RGB_POS_X_MASK                           0x003ff800
+#define ATMEL_MPOP_RGB_POS_X_OFFSET                                 11
+#define ATMEL_MPOP_RGB_POS_X_SIZE                                   11
+#define ATMEL_MPOP_RGB_POS_Y                                         0
+#define ATMEL_MPOP_RGB_POS_Y_MASK                           0x000007ff
+#define ATMEL_MPOP_RGB_POS_Y_OFFSET                                  0
+#define ATMEL_MPOP_RGB_POS_Y_SIZE                                   11
+#define ATMEL_MPOP_RGB_SAR                                  0x0000003c
+#define ATMEL_MPOP_RGB_SAR_MASK                             0xffffffff
+#define ATMEL_MPOP_RGB_SAR_OFFSET                                    0
+#define ATMEL_MPOP_RGB_SAR_RGB_SAR                                   0
+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_MASK                     0xffffffff
+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_OFFSET                            0
+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_SIZE                             32
+#define ATMEL_MPOP_RGB_SAR_SIZE                                     32
+#define ATMEL_MPOP_RGB_SIZE                                 0x00000060
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X                              11
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_MASK                 0x003ff800
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_OFFSET                       11
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_SIZE                         11
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y                               0
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_MASK                 0x000007ff
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_OFFSET                        0
+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_SIZE                         11
+#define ATMEL_MPOP_RGB_SIZE_X                                       11
+#define ATMEL_MPOP_RGB_SIZE_X_MASK                          0x003ff800
+#define ATMEL_MPOP_RGB_SIZE_X_OFFSET                                11
+#define ATMEL_MPOP_RGB_SIZE_X_SIZE                                  11
+#define ATMEL_MPOP_RGB_SIZE_Y                                        0
+#define ATMEL_MPOP_RGB_SIZE_Y_MASK                          0x000007ff
+#define ATMEL_MPOP_RGB_SIZE_Y_OFFSET                                 0
+#define ATMEL_MPOP_RGB_SIZE_Y_SIZE                                  11
+#define ATMEL_MPOP_RGB_WTC                                  0x00000070
+#define ATMEL_MPOP_RGB_WTC_MASK                             0xffffffff
+#define ATMEL_MPOP_RGB_WTC_OFFSET                                    0
+#define ATMEL_MPOP_RGB_WTC_RGB_WTC                                   0
+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_MASK                     0xffffffff
+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_OFFSET                            0
+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_SIZE                             32
+#define ATMEL_MPOP_RGB_WTC_SIZE                                     32
+#define ATMEL_MPOP_R_MASK                                   0x00ff0000
+#define ATMEL_MPOP_R_OFFSET                                         16
+#define ATMEL_MPOP_R_SIZE                                            8
+#define ATMEL_MPOP_SOP                                               4
+#define ATMEL_MPOP_SOP_MASK                                 0x00000010
+#define ATMEL_MPOP_SOP_OFFSET                                        4
+#define ATMEL_MPOP_SOP_SIZE                                          1
+#define ATMEL_MPOP_START                                             1
+#define ATMEL_MPOP_START_MASK                               0x00000002
+#define ATMEL_MPOP_START_OFFSET                                      1
+#define ATMEL_MPOP_START_SIZE                                        1
+#define ATMEL_MPOP_STRIDE                                   0x0000002c
+#define ATMEL_MPOP_STRIDE_MASK                              0xffffffff
+#define ATMEL_MPOP_STRIDE_OFFSET                                     0
+#define ATMEL_MPOP_STRIDE_SIZE                                      32
+#define ATMEL_MPOP_STRIDE_STRIDE                                     0
+#define ATMEL_MPOP_STRIDE_STRIDE_MASK                       0xffffffff
+#define ATMEL_MPOP_STRIDE_STRIDE_OFFSET                              0
+#define ATMEL_MPOP_STRIDE_STRIDE_SIZE                               32
+#define ATMEL_MPOP_U_SAR                                    0x00000034
+#define ATMEL_MPOP_U_SAR_MASK                               0xffffffff
+#define ATMEL_MPOP_U_SAR_OFFSET                                      0
+#define ATMEL_MPOP_U_SAR_SIZE                                       32
+#define ATMEL_MPOP_U_SAR_U_SAR                                       0
+#define ATMEL_MPOP_U_SAR_U_SAR_MASK                         0xffffffff
+#define ATMEL_MPOP_U_SAR_U_SAR_OFFSET                                0
+#define ATMEL_MPOP_U_SAR_U_SAR_SIZE                                 32
+#define ATMEL_MPOP_VISIBLE                                          24
+#define ATMEL_MPOP_VISIBLE_MASK                             0x01000000
+#define ATMEL_MPOP_VISIBLE_OFFSET                                   24
+#define ATMEL_MPOP_VISIBLE_SIZE                                      1
+#define ATMEL_MPOP_V_SAR                                    0x00000038
+#define ATMEL_MPOP_V_SAR_MASK                               0xffffffff
+#define ATMEL_MPOP_V_SAR_OFFSET                                      0
+#define ATMEL_MPOP_V_SAR_SIZE                                       32
+#define ATMEL_MPOP_V_SAR_V_SAR                                       0
+#define ATMEL_MPOP_V_SAR_V_SAR_MASK                         0xffffffff
+#define ATMEL_MPOP_V_SAR_V_SAR_OFFSET                                0
+#define ATMEL_MPOP_V_SAR_V_SAR_SIZE                                 32
+#define ATMEL_MPOP_XRESIZE                                          16
+#define ATMEL_MPOP_XRESIZE_MASK                             0x00ff0000
+#define ATMEL_MPOP_XRESIZE_OFFSET                                   16
+#define ATMEL_MPOP_XRESIZE_SIZE                                      8
+#define ATMEL_MPOP_YCR                                      0x00000004
+#define ATMEL_MPOP_YCR_XRESIZE                                      16
+#define ATMEL_MPOP_YCR_XRESIZE_MASK                         0x00ff0000
+#define ATMEL_MPOP_YCR_XRESIZE_OFFSET                               16
+#define ATMEL_MPOP_YCR_XRESIZE_SIZE                                  8
+#define ATMEL_MPOP_YCR_YRESIZE                                       8
+#define ATMEL_MPOP_YCR_YRESIZE_MASK                         0x0000ff00
+#define ATMEL_MPOP_YCR_YRESIZE_OFFSET                                8
+#define ATMEL_MPOP_YCR_YRESIZE_SIZE                                  8
+#define ATMEL_MPOP_YCR_YUVFORMAT                                     0
+#define ATMEL_MPOP_YCR_YUVFORMAT_MASK                       0x00000003
+#define ATMEL_MPOP_YCR_YUVFORMAT_OFFSET                              0
+#define ATMEL_MPOP_YCR_YUVFORMAT_SIZE                                2
+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_420              0x00000002
+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_422              0x00000001
+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_444              0x00000000
+#define ATMEL_MPOP_YRESIZE                                           8
+#define ATMEL_MPOP_YRESIZE_MASK                             0x0000ff00
+#define ATMEL_MPOP_YRESIZE_OFFSET                                    8
+#define ATMEL_MPOP_YRESIZE_SIZE                                      8
+#define ATMEL_MPOP_YUV                                               0
+#define ATMEL_MPOP_YUVFORMAT                                         0
+#define ATMEL_MPOP_YUVFORMAT_420                            0x00000002
+#define ATMEL_MPOP_YUVFORMAT_422                            0x00000001
+#define ATMEL_MPOP_YUVFORMAT_444                            0x00000000
+#define ATMEL_MPOP_YUVFORMAT_MASK                           0x00000003
+#define ATMEL_MPOP_YUVFORMAT_OFFSET                                  0
+#define ATMEL_MPOP_YUVFORMAT_SIZE                                    2
+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_420                  0x00000002
+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_422                  0x00000001
+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_444                  0x00000000
+#define ATMEL_MPOP_YUV_BEAR                                 0x00000094
+#define ATMEL_MPOP_YUV_BEAR_MASK                            0xffffffff
+#define ATMEL_MPOP_YUV_BEAR_OFFSET                                   0
+#define ATMEL_MPOP_YUV_BEAR_SIZE                                    32
+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR                                 0
+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_MASK                   0xffffffff
+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_OFFSET                          0
+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_SIZE                           32
+#define ATMEL_MPOP_YUV_MASK                                 0x00000001
+#define ATMEL_MPOP_YUV_MAX_COORD                            0x0000005c
+#define ATMEL_MPOP_YUV_MAX_COORD_X                                  11
+#define ATMEL_MPOP_YUV_MAX_COORD_X_MASK                     0x003ff800
+#define ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET                           11
+#define ATMEL_MPOP_YUV_MAX_COORD_X_SIZE                             11
+#define ATMEL_MPOP_YUV_MAX_COORD_Y                                   0
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X                    11
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_MASK       0x003ff800
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_OFFSET             11
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_SIZE               11
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y                     0
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_MASK       0x000007ff
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_OFFSET              0
+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_SIZE               11
+#define ATMEL_MPOP_YUV_MAX_COORD_Y_MASK                     0x000007ff
+#define ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET                            0
+#define ATMEL_MPOP_YUV_MAX_COORD_Y_SIZE                             11
+#define ATMEL_MPOP_YUV_OFFSET                                        0
+#define ATMEL_MPOP_YUV_SIZE                                          1
+#define ATMEL_MPOP_Y_SAR                                    0x00000030
+#define ATMEL_MPOP_Y_SAR_MASK                               0xffffffff
+#define ATMEL_MPOP_Y_SAR_OFFSET                                      0
+#define ATMEL_MPOP_Y_SAR_SIZE                                       32
+#define ATMEL_MPOP_Y_SAR_Y_SAR                                       0
+#define ATMEL_MPOP_Y_SAR_Y_SAR_MASK                         0xffffffff
+#define ATMEL_MPOP_Y_SAR_Y_SAR_OFFSET                                0
+#define ATMEL_MPOP_Y_SAR_Y_SAR_SIZE                                 32
+
+#endif /* __ATMEL_MPOP_H__ */
diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/clock.c linux-2.6.28.2/arch/avr32/mach-at32ap/clock.c
--- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/clock.c	2009-01-29 08:39:35.000000000 +0100
+++ linux-2.6.28.2/arch/avr32/mach-at32ap/clock.c	2009-01-29 10:16:11.000000000 +0100
@@ -178,7 +178,11 @@
 #include <linux/io.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
-#include "pm.h"
+#if defined(CONFIG_CPU_AT32AP700X)
+# include "pm-v1.h"
+#elif defined(CONFIG_CPU_AT32AP720X)
+# include "pm-v3.h"
+#endif
 
 
 #define	NEST_DELTA	2
@@ -234,19 +238,40 @@
 	struct clk 	*clk;
 
 	/* show all the power manager registers */
-	seq_printf(s, "MCCTRL  = %8x\n", pm_readl(MCCTRL));
-	seq_printf(s, "CKSEL   = %8x\n", pm_readl(CKSEL));
-	seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK));
-	seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK));
-	seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK));
-	seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK));
-	seq_printf(s, "PLL0    = %8x\n", pm_readl(PLL0));
-	seq_printf(s, "PLL1    = %8x\n", pm_readl(PLL1));
-	seq_printf(s, "IMR     = %8x\n", pm_readl(IMR));
+	seq_printf(s, "MCCTRL     = %8x\n", pm_readl(MCCTRL));
+	seq_printf(s, "CKSEL      = %8x\n", pm_readl(CKSEL));
+#ifdef CONFIG_CPU_AT32AP700X
+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPU_MASK));
+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSB_MASK));
+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBA_MASK));
+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBB_MASK));
+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL0));
+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL1));
+#else
+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPUMASK));
+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSBMASK));
+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBAMASK));
+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBBMASK));
+	seq_printf(s, "PBADIVMASK = %8x\n", pm_readl(PBADIVMASK));
+	seq_printf(s, "PBBDIVMASK = %8x\n", pm_readl(PBBDIVMASK));
+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL[0]));
+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL[1]));
+	seq_printf(s, "PLL2       = %8x\n", pm_readl(PLL[2]));
+	seq_printf(s, "OSCCTRL0   = %8x\n", pm_readl(OSCCTRL[0]));
+	seq_printf(s, "OSCCTRL1   = %8x\n", pm_readl(OSCCTRL[1]));
+	seq_printf(s, "OSCCTRL2   = %8x\n", pm_readl(OSCCTRL[2]));
+	seq_printf(s, "POSCSR     = %8x\n", pm_readl(POSCSR));
+	seq_printf(s, "PPCR       = %8x\n", pm_readl(PPCR));
+#endif
+	seq_printf(s, "IMR        = %8x\n", pm_readl(IMR));
 	for (i = 0; i < 8; i++) {
 		if (i == 5)
 			continue;
-		seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
+#ifdef CONFIG_CPU_AT32AP700X
+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL(i)));
+#else
+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL[i]));
+#endif
 	}
 
 	seq_printf(s, "\n");
@@ -269,6 +294,16 @@
 	dump_clock(clk, &r);
 	clk_put(clk);
 
+#ifdef CONFIG_CPU_AT32AP720X
+	clk = clk_get(NULL, "osc2");
+	dump_clock(clk, &r);
+	clk_put(clk);
+
+	clk = clk_get(NULL, "rcosc");
+	dump_clock(clk, &r);
+	clk_put(clk);
+#endif
+
 	spin_unlock(&clk_list_lock);
 
 	return 0;