From 8356bda519796432ec6965fe95371a2c9e1305cc Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Sun, 5 Dec 2010 21:53:09 +0100
Subject: Remove the few remaining unused Atmel-specific bits

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
---
 .../linux-2.6.27.6-100-avr32-atmel.1.patch         | 26786 -------------------
 1 file changed, 26786 deletions(-)
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch

(limited to 'target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch')

diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch
deleted file mode 100644
index 11bcdae04..000000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch
+++ /dev/null
@@ -1,26786 +0,0 @@
-diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
-index dbfd9f7..b2a96fe 100644
---- a/arch/arm/mach-at91/include/mach/cpu.h
-+++ b/arch/arm/mach-at91/include/mach/cpu.h
-@@ -99,5 +99,6 @@ static inline unsigned long at91_arch_identify(void)
-  * definitions may reduce clutter in common drivers.
-  */
- #define cpu_is_at32ap7000()	(0)
-+#define cpu_is_at32ap7200()	(0)
- 
- #endif
-diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
-index 7c239a9..6cef643 100644
---- a/arch/avr32/Kconfig
-+++ b/arch/avr32/Kconfig
-@@ -83,6 +83,18 @@ config MMU
- config PERFORMANCE_COUNTERS
- 	bool
- 
-+# The old "PIO" portmux/GPIO module used on AT32AP700x
-+config PORTMUX_PIO
-+	bool
-+
-+# The new "GPIO" portmux/GPIO module, version 2
-+config PORTMUX_GPIO_V2
-+	bool
-+
-+# Asynchronous Timer clocksource/clockevent driver
-+config TIMER_AST
-+	bool
-+
- config PLATFORM_AT32AP
- 	bool
- 	select SUBARCH_AVR32B
-@@ -99,6 +111,7 @@ config PLATFORM_AT32AP
- config CPU_AT32AP700X
- 	bool
- 	select PLATFORM_AT32AP
-+	select PORTMUX_PIO
- config CPU_AT32AP7000
- 	bool
- 	select CPU_AT32AP700X
-@@ -109,6 +122,16 @@ config CPU_AT32AP7002
- 	bool
- 	select CPU_AT32AP700X
- 
-+# AP7200 derivatives
-+config CPU_AT32AP720X
-+	bool
-+	select PLATFORM_AT32AP
-+	select TIMER_AST
-+	select PORTMUX_GPIO_V2
-+config CPU_AT32AP7200
-+	bool
-+	select CPU_AT32AP720X
-+
- choice
- 	prompt "AVR32 board type"
- 	default BOARD_ATSTK1000
-@@ -119,11 +142,19 @@ config BOARD_ATSTK1000
- config BOARD_ATNGW100
- 	bool "ATNGW100 Network Gateway"
- 	select CPU_AT32AP7000
-+
-+config BOARD_FAVR_32
-+	bool "Favr-32 LCD-board"
-+	select CPU_AT32AP7000
-+
-+config BOARD_MIMC200
-+	bool "MIMC200 CPU board"
-+	select CPU_AT32AP7000
- endchoice
- 
--if BOARD_ATSTK1000
- source "arch/avr32/boards/atstk1000/Kconfig"
--endif
-+source "arch/avr32/boards/atngw100/Kconfig"
-+source "arch/avr32/boards/favr-32/Kconfig"
- 
- choice
- 	prompt "Boot loader type"
-@@ -138,14 +169,17 @@ source "arch/avr32/mach-at32ap/Kconfig"
- config LOAD_ADDRESS
- 	hex
- 	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-+	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
- 
- config ENTRY_ADDRESS
- 	hex
- 	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-+	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
- 
- config PHYS_OFFSET
- 	hex
- 	default 0x10000000 if CPU_AT32AP700X=y
-+	default 0x10000000 if CPU_AT32AP720X=y
- 
- source "kernel/Kconfig.preempt"
- 
-diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
-index c9e1f0b..b088e10 100644
---- a/arch/avr32/Makefile
-+++ b/arch/avr32/Makefile
-@@ -33,6 +33,8 @@ head-y					+= arch/avr32/kernel/head.o
- core-y					+= $(machdirs)
- core-$(CONFIG_BOARD_ATSTK1000)		+= arch/avr32/boards/atstk1000/
- core-$(CONFIG_BOARD_ATNGW100)		+= arch/avr32/boards/atngw100/
-+core-$(CONFIG_BOARD_FAVR_32)		+= arch/avr32/boards/favr-32/
-+core-$(CONFIG_BOARD_MIMC200)		+= arch/avr32/boards/mimc200/
- core-$(CONFIG_LOADER_U_BOOT)		+= arch/avr32/boot/u-boot/
- core-y					+= arch/avr32/kernel/
- core-y					+= arch/avr32/mm/
-diff --git a/arch/avr32/boards/atngw100/Kconfig b/arch/avr32/boards/atngw100/Kconfig
-new file mode 100644
-index 0000000..b3f9947
---- /dev/null
-+++ b/arch/avr32/boards/atngw100/Kconfig
-@@ -0,0 +1,35 @@
-+# NGW100 customization
-+
-+if BOARD_ATNGW100
-+
-+config BOARD_ATNGW100_EVKLCD10X
-+	bool "Add support for EVKLCD10X addon board"
-+	help
-+	  This enables support for the EVKLCD100 (QVGA) or EVKLCD101 (VGA)
-+	  addon board for the NGW100. By enabling this the LCD controller and
-+	  AC97 controller is added as platform devices.
-+
-+	  This choice disables the detect pin and the write-protect pin for the
-+	  MCI platform device, since it conflicts with the LCD platform device.
-+	  The MCI pins can be reenabled by editing the "add device function" but
-+	  this may break the setup for other displays that use these pins.
-+
-+	  Choose 'Y' here if you have a EVKLCD100/101 connected to the NGW100.
-+
-+choice
-+	prompt "LCD panel resolution on EVKLCD10X"
-+	depends on BOARD_ATNGW100_EVKLCD10X
-+	default BOARD_ATNGW100_EVKLCD10X_VGA
-+
-+config BOARD_ATNGW100_EVKLCD10X_QVGA
-+	bool "QVGA (320x240)"
-+
-+config BOARD_ATNGW100_EVKLCD10X_VGA
-+	bool "VGA (640x480)"
-+
-+config BOARD_ATNGW100_EVKLCD10X_POW_QVGA
-+	bool "Powertip QVGA (320x240)"
-+
-+endchoice
-+
-+endif	# BOARD_ATNGW100
-diff --git a/arch/avr32/boards/atngw100/Makefile b/arch/avr32/boards/atngw100/Makefile
-index c740aa1..6376f53 100644
---- a/arch/avr32/boards/atngw100/Makefile
-+++ b/arch/avr32/boards/atngw100/Makefile
-@@ -1 +1,2 @@
--obj-y				+= setup.o flash.o
-+obj-y					+= setup.o flash.o
-+obj-$(CONFIG_BOARD_ATNGW100_EVKLCD10X)	+= evklcd10x.o
-diff --git a/arch/avr32/boards/atngw100/evklcd10x.c b/arch/avr32/boards/atngw100/evklcd10x.c
-new file mode 100644
-index 0000000..8140b22
---- /dev/null
-+++ b/arch/avr32/boards/atngw100/evklcd10x.c
-@@ -0,0 +1,155 @@
-+/*
-+ * Board-specific setup code for the ATEVKLCD10X addon board to the ATNGW100
-+ * Network Gateway
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/linkage.h>
-+#include <linux/fb.h>
-+#include <linux/platform_device.h>
-+
-+#include <video/atmel_lcdc.h>
-+
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap700x.h>
-+#include <mach/board.h>
-+
-+static struct ac97c_platform_data __initdata ac97c0_data = {
-+	.dma_rx_periph_id	= 3,
-+	.dma_tx_periph_id	= 4,
-+	.dma_controller_id	= 0,
-+	.reset_pin		= GPIO_PIN_PB(19),
-+};
-+
-+#ifdef CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA
-+static struct fb_videomode __initdata tcg057vglad_modes[] = {
-+	{
-+		.name		= "640x480 @ 60",
-+		.refresh	= 60,
-+		.xres		= 640,		.yres		= 480,
-+		.pixclock	= KHZ2PICOS(25180),
-+
-+		.left_margin	= 64,		.right_margin	= 31,
-+		.upper_margin	= 34,		.lower_margin	= 2,
-+		.hsync_len	= 96,		.vsync_len	= 4,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata atevklcd10x_default_monspecs = {
-+	.manufacturer		= "KYO",
-+	.monitor		= "TCG057VGLAD",
-+	.modedb			= tcg057vglad_modes,
-+	.modedb_len		= ARRAY_SIZE(tcg057vglad_modes),
-+	.hfmin			= 19948,
-+	.hfmax			= 31478,
-+	.vfmin			= 50,
-+	.vfmax			= 67,
-+	.dclkmax		= 28330000,
-+};
-+
-+static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &atevklcd10x_default_monspecs,
-+	.guard_time		= 2,
-+};
-+#elif CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA
-+static struct fb_videomode __initdata tcg057qvlad_modes[] = {
-+	{
-+		.name		= "320x240 @ 60",
-+		.refresh	= 60,
-+		.xres		= 320,		.yres		= 240,
-+		.pixclock	= KHZ2PICOS(6300),
-+
-+		.left_margin	= 52,		.right_margin	= 28,
-+		.upper_margin	= 7,		.lower_margin	= 2,
-+		.hsync_len	= 96,		.vsync_len	= 4,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata atevklcd10x_default_monspecs = {
-+	.manufacturer		= "KYO",
-+	.monitor		= "TCG057QVLAD",
-+	.modedb			= tcg057qvlad_modes,
-+	.modedb_len		= ARRAY_SIZE(tcg057qvlad_modes),
-+	.hfmin			= 19948,
-+	.hfmax			= 31478,
-+	.vfmin			= 50,
-+	.vfmax			= 67,
-+	.dclkmax		= 7000000,
-+};
-+
-+static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &atevklcd10x_default_monspecs,
-+	.guard_time		= 2,
-+};
-+#elif CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA
-+static struct fb_videomode __initdata ph320240t_modes[] = {
-+	{
-+		.name		= "320x240 @ 60",
-+		.refresh	= 60,
-+		.xres		= 320,		.yres		= 240,
-+		.pixclock	= KHZ2PICOS(6300),
-+
-+		.left_margin	= 38,		.right_margin	= 20,
-+		.upper_margin	= 15,		.lower_margin	= 5,
-+		.hsync_len	= 30,		.vsync_len	= 3,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata atevklcd10x_default_monspecs = {
-+	.manufacturer		= "POW",
-+	.monitor		= "PH320240T",
-+	.modedb			= ph320240t_modes,
-+	.modedb_len		= ARRAY_SIZE(ph320240t_modes),
-+	.hfmin			= 14400,
-+	.hfmax			= 21600,
-+	.vfmin			= 50,
-+	.vfmax			= 90,
-+	.dclkmax		= 6400000,
-+};
-+
-+static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &atevklcd10x_default_monspecs,
-+	.guard_time		= 2,
-+};
-+#endif
-+
-+static int __init atevklcd10x_init(void)
-+{
-+	at32_add_device_ac97c(0, &ac97c0_data);
-+
-+	at32_add_device_lcdc(0, &atevklcd10x_lcdc_data,
-+			fbmem_start, fbmem_size, 1);
-+	return 0;
-+}
-+postcore_initcall(atevklcd10x_init);
-diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
-index b8286f1..32fb9ba 100644
---- a/arch/avr32/boards/atngw100/setup.c
-+++ b/arch/avr32/boards/atngw100/setup.c
-@@ -9,6 +9,7 @@
-  */
- #include <linux/clk.h>
- #include <linux/etherdevice.h>
-+#include <linux/gpio.h>
- #include <linux/irq.h>
- #include <linux/i2c.h>
- #include <linux/i2c-gpio.h>
-@@ -53,8 +54,16 @@ static struct spi_board_info spi0_board_info[] __initdata = {
- };
- 
- static struct mci_platform_data __initdata mci0_data = {
--	.detect_pin	= GPIO_PIN_PC(25),
--	.wp_pin		= GPIO_PIN_PE(0),
-+	.slot[0] = {
-+		.bus_width	= 4,
-+#ifndef CONFIG_BOARD_ATNGW100_EVKLCD10X
-+		.detect_pin	= GPIO_PIN_PC(25),
-+		.wp_pin		= GPIO_PIN_PE(0),
-+#else
-+		.detect_pin	= GPIO_PIN_NONE,
-+		.wp_pin		= GPIO_PIN_NONE,
-+#endif
-+	},
- };
- 
- /*
-@@ -168,8 +177,6 @@ static int __init atngw100_init(void)
- 	 * reserve any pins for it.
- 	 */
- 
--	at32_add_system_devices();
--
- 	at32_add_device_usart(0);
- 
- 	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
-@@ -190,7 +197,7 @@ static int __init atngw100_init(void)
- 	 * PB28/EXTINT3 doesn't; it should be SMBALERT# (for PMBus),
- 	 * but it's not available off-board.
- 	 */
--	at32_select_periph(GPIO_PIN_PB(28), 0, AT32_GPIOF_PULLUP);
-+	at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
- 	at32_select_gpio(i2c_gpio_data.sda_pin,
- 		AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
- 	at32_select_gpio(i2c_gpio_data.scl_pin,
-@@ -204,6 +211,15 @@ postcore_initcall(atngw100_init);
- 
- static int __init atngw100_arch_init(void)
- {
-+	/* PB30 is the otherwise unused jumper on the mainboard, with an
-+	 * external pullup; the jumper grounds it.  Use it however you
-+	 * like, including letting U-Boot or Linux tweak boot sequences.
-+	 */
-+	at32_select_gpio(GPIO_PIN_PB(30), 0);
-+	gpio_request(GPIO_PIN_PB(30), "j15");
-+	gpio_direction_input(GPIO_PIN_PB(30));
-+	gpio_export(GPIO_PIN_PB(30), false);
-+
- 	/* set_irq_type() after the arch_initcall for EIC has run, and
- 	 * before the I2C subsystem could try using this IRQ.
- 	 */
-diff --git a/arch/avr32/boards/atstk1000/Kconfig b/arch/avr32/boards/atstk1000/Kconfig
-index 8dc4821..0884884 100644
---- a/arch/avr32/boards/atstk1000/Kconfig
-+++ b/arch/avr32/boards/atstk1000/Kconfig
-@@ -18,6 +18,10 @@ config BOARD_ATSTK1004
- 	bool "ATSTK1004"
- 	select CPU_AT32AP7002
- 
-+config BOARD_ATSTK1005
-+	bool "ATSTK1005"
-+	select CPU_AT32AP7200
-+
- config BOARD_ATSTK1006
- 	bool "ATSTK1006"
- 	select CPU_AT32AP7000
-diff --git a/arch/avr32/boards/atstk1000/Makefile b/arch/avr32/boards/atstk1000/Makefile
-index edecee0..d0f248d 100644
---- a/arch/avr32/boards/atstk1000/Makefile
-+++ b/arch/avr32/boards/atstk1000/Makefile
-@@ -2,4 +2,5 @@ obj-y				+= setup.o flash.o
- obj-$(CONFIG_BOARD_ATSTK1002)	+= atstk1002.o
- obj-$(CONFIG_BOARD_ATSTK1003)	+= atstk1003.o
- obj-$(CONFIG_BOARD_ATSTK1004)	+= atstk1004.o
-+obj-$(CONFIG_BOARD_ATSTK1005)	+= atstk1005.o
- obj-$(CONFIG_BOARD_ATSTK1006)	+= atstk1002.o
-diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
-index dfc3443..11e7800 100644
---- a/arch/avr32/boards/atstk1000/atstk1002.c
-+++ b/arch/avr32/boards/atstk1000/atstk1002.c
-@@ -232,7 +232,7 @@ static void __init atstk1002_setup_extdac(void)
- 		goto err_set_clk;
- 	}
- 
--	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
- 	at73c213_data.dac_clk = gclk;
- 
- err_set_clk:
-@@ -264,16 +264,20 @@ void __init setup_board(void)
- 
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- 
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+
- /* MMC card detect requires MACB0 *NOT* be used */
- #ifdef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
--static struct mci_platform_data __initdata mci0_data = {
--	.detect_pin	= GPIO_PIN_PC(14),	/* gpio30/sdcd */
--	.wp_pin		= GPIO_PIN_PC(15),	/* gpio31/sdwp */
--};
--#define MCI_PDATA	&mci0_data
-+		.detect_pin	= GPIO_PIN_PC(14), /* gpio30/sdcd */
-+		.wp_pin		= GPIO_PIN_PC(15), /* gpio31/sdwp */
- #else
--#define MCI_PDATA	NULL
-+		.detect_pin	= -ENODEV,
-+		.wp_pin		= -ENODEV,
- #endif	/* SW6 for sd{cd,wp} routing */
-+	},
-+};
- 
- #endif	/* SW2 for MMC signal routing */
- 
-@@ -283,25 +287,7 @@ static int __init atstk1002_init(void)
- 	 * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
- 	 * SDRAM-specific pins so that nobody messes with them.
- 	 */
--	at32_reserve_pin(GPIO_PIN_PE(0));	/* DATA[16]	*/
--	at32_reserve_pin(GPIO_PIN_PE(1));	/* DATA[17]	*/
--	at32_reserve_pin(GPIO_PIN_PE(2));	/* DATA[18]	*/
--	at32_reserve_pin(GPIO_PIN_PE(3));	/* DATA[19]	*/
--	at32_reserve_pin(GPIO_PIN_PE(4));	/* DATA[20]	*/
--	at32_reserve_pin(GPIO_PIN_PE(5));	/* DATA[21]	*/
--	at32_reserve_pin(GPIO_PIN_PE(6));	/* DATA[22]	*/
--	at32_reserve_pin(GPIO_PIN_PE(7));	/* DATA[23]	*/
--	at32_reserve_pin(GPIO_PIN_PE(8));	/* DATA[24]	*/
--	at32_reserve_pin(GPIO_PIN_PE(9));	/* DATA[25]	*/
--	at32_reserve_pin(GPIO_PIN_PE(10));	/* DATA[26]	*/
--	at32_reserve_pin(GPIO_PIN_PE(11));	/* DATA[27]	*/
--	at32_reserve_pin(GPIO_PIN_PE(12));	/* DATA[28]	*/
--	at32_reserve_pin(GPIO_PIN_PE(13));	/* DATA[29]	*/
--	at32_reserve_pin(GPIO_PIN_PE(14));	/* DATA[30]	*/
--	at32_reserve_pin(GPIO_PIN_PE(15));	/* DATA[31]	*/
--	at32_reserve_pin(GPIO_PIN_PE(26));	/* SDCS		*/
--
--	at32_add_system_devices();
-+	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
- 
- #ifdef CONFIG_BOARD_ATSTK1006
- 	smc_set_timing(&nand_config, &nand_timing);
-@@ -326,13 +312,14 @@ static int __init atstk1002_init(void)
- 	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
- #endif
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
--	at32_add_device_mci(0, MCI_PDATA);
-+	at32_add_device_mci(0, &mci0_data);
- #endif
- #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
- 	set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
- #else
- 	at32_add_device_lcdc(0, &atstk1000_lcdc_data,
--			     fbmem_start, fbmem_size, 0);
-+			     fbmem_start, fbmem_size,
-+			     ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
- #endif
- 	at32_add_device_usba(0, NULL);
- #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-diff --git a/arch/avr32/boards/atstk1000/atstk1003.c b/arch/avr32/boards/atstk1000/atstk1003.c
-index 0cf6641..ac31666 100644
---- a/arch/avr32/boards/atstk1000/atstk1003.c
-+++ b/arch/avr32/boards/atstk1000/atstk1003.c
-@@ -19,6 +19,7 @@
- #include <linux/spi/spi.h>
- 
- #include <asm/setup.h>
-+#include <asm/atmel-mci.h>
- 
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
-@@ -66,6 +67,16 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
- } };
- #endif
- 
-+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+		.detect_pin	= -ENODEV,
-+		.wp_pin		= -ENODEV,
-+	},
-+};
-+#endif
-+
- #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
- static void __init atstk1003_setup_extdac(void)
- {
-@@ -84,7 +95,7 @@ static void __init atstk1003_setup_extdac(void)
- 		goto err_set_clk;
- 	}
- 
--	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
- 	at73c213_data.dac_clk = gclk;
- 
- err_set_clk:
-@@ -120,25 +131,7 @@ static int __init atstk1003_init(void)
- 	 * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
- 	 * SDRAM-specific pins so that nobody messes with them.
- 	 */
--	at32_reserve_pin(GPIO_PIN_PE(0));	/* DATA[16]	*/
--	at32_reserve_pin(GPIO_PIN_PE(1));	/* DATA[17]	*/
--	at32_reserve_pin(GPIO_PIN_PE(2));	/* DATA[18]	*/
--	at32_reserve_pin(GPIO_PIN_PE(3));	/* DATA[19]	*/
--	at32_reserve_pin(GPIO_PIN_PE(4));	/* DATA[20]	*/
--	at32_reserve_pin(GPIO_PIN_PE(5));	/* DATA[21]	*/
--	at32_reserve_pin(GPIO_PIN_PE(6));	/* DATA[22]	*/
--	at32_reserve_pin(GPIO_PIN_PE(7));	/* DATA[23]	*/
--	at32_reserve_pin(GPIO_PIN_PE(8));	/* DATA[24]	*/
--	at32_reserve_pin(GPIO_PIN_PE(9));	/* DATA[25]	*/
--	at32_reserve_pin(GPIO_PIN_PE(10));	/* DATA[26]	*/
--	at32_reserve_pin(GPIO_PIN_PE(11));	/* DATA[27]	*/
--	at32_reserve_pin(GPIO_PIN_PE(12));	/* DATA[28]	*/
--	at32_reserve_pin(GPIO_PIN_PE(13));	/* DATA[29]	*/
--	at32_reserve_pin(GPIO_PIN_PE(14));	/* DATA[30]	*/
--	at32_reserve_pin(GPIO_PIN_PE(15));	/* DATA[31]	*/
--	at32_reserve_pin(GPIO_PIN_PE(26));	/* SDCS		*/
--
--	at32_add_system_devices();
-+	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
- 
- #ifdef	CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- 	at32_add_device_usart(1);
-@@ -154,7 +147,7 @@ static int __init atstk1003_init(void)
- 	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
- #endif
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
--	at32_add_device_mci(0, NULL);
-+	at32_add_device_mci(0, &mci0_data);
- #endif
- 	at32_add_device_usba(0, NULL);
- #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-diff --git a/arch/avr32/boards/atstk1000/atstk1004.c b/arch/avr32/boards/atstk1000/atstk1004.c
-index 50a5273..cb32eb8 100644
---- a/arch/avr32/boards/atstk1000/atstk1004.c
-+++ b/arch/avr32/boards/atstk1000/atstk1004.c
-@@ -21,6 +21,7 @@
- #include <video/atmel_lcdc.h>
- 
- #include <asm/setup.h>
-+#include <asm/atmel-mci.h>
- 
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
-@@ -71,6 +72,16 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
- } };
- #endif
- 
-+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+		.detect_pin	= -ENODEV,
-+		.wp_pin		= -ENODEV,
-+	},
-+};
-+#endif
-+
- #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
- static void __init atstk1004_setup_extdac(void)
- {
-@@ -89,7 +100,7 @@ static void __init atstk1004_setup_extdac(void)
- 		goto err_set_clk;
- 	}
- 
--	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
- 	at73c213_data.dac_clk = gclk;
- 
- err_set_clk:
-@@ -121,8 +132,6 @@ void __init setup_board(void)
- 
- static int __init atstk1004_init(void)
- {
--	at32_add_system_devices();
--
- #ifdef	CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- 	at32_add_device_usart(1);
- #else
-@@ -137,10 +146,11 @@ static int __init atstk1004_init(void)
- 	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
- #endif
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
--	at32_add_device_mci(0, NULL);
-+	at32_add_device_mci(0, &mci0_data);
- #endif
- 	at32_add_device_lcdc(0, &atstk1000_lcdc_data,
--			     fbmem_start, fbmem_size, 0);
-+			     fbmem_start, fbmem_size,
-+			     ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
- 	at32_add_device_usba(0, NULL);
- #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
- 	at32_add_device_ssc(0, ATMEL_SSC_TX);
-diff --git a/arch/avr32/boards/atstk1000/atstk1005.c b/arch/avr32/boards/atstk1000/atstk1005.c
-new file mode 100644
-index 0000000..f5a9baa
---- /dev/null
-+++ b/arch/avr32/boards/atstk1000/atstk1005.c
-@@ -0,0 +1,225 @@
-+/*
-+ * ATSTK1005 daughterboard-specific init code
-+ *
-+ * Copyright (C) 2005-2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/string.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/spi/spi.h>
-+
-+#include <asm/atmel-mci.h>
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap720x.h>
-+#include <mach/board.h>
-+#include <mach/init.h>
-+#include <mach/portmux.h>
-+#include <mach/smc.h>
-+
-+#include "atstk1000.h"
-+
-+/* Oscillator frequencies. These are board specific */
-+unsigned long at32_board_osc_rates[4] = {
-+	[0] = 20000000,	/* 20 MHz on osc0 */
-+	[1] = 0,	/* Nothing on osc1 */
-+	[2] = 12000000,	/* 12 MHz on osc2 */
-+	[3] = 32768,	/* 32.768 kHz on RTC osc */
-+};
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+
-+static struct eth_addr __initdata hw_addr;
-+static struct eth_platform_data __initdata eth_data;
-+
-+static struct mci_platform_data mci_data __initdata = {
-+	.slot[0]	= {
-+		.detect_pin		= GPIO_PIN_NONE,
-+		.wp_pin			= GPIO_PIN_NONE,
-+		.bus_width		= 4,
-+	},
-+	.slot[1]	= {
-+		.detect_pin		= GPIO_PIN_PA(30),
-+		.wp_pin			= GPIO_PIN_PA(31),
-+		.bus_width		= 8,
-+	},
-+};
-+
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+	{
-+		/* AT45DB642D: 8MB DataFlash */
-+		.modalias	= "mtd_dataflash",
-+		.max_speed_hz	= 8000000,
-+		.chip_select	= 0,
-+		.mode		= SPI_MODE_0,
-+	}, {
-+		/* QVGA display */
-+		.modalias	= "ltv350qv",
-+		.max_speed_hz	= 8000000,
-+		.chip_select	= 2,
-+		.mode		= SPI_MODE_3,
-+	},
-+};
-+
-+static struct smc_timing nand_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 10,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 10,
-+
-+	.ncs_read_pulse		= 30,
-+	.nrd_pulse		= 15,
-+	.ncs_write_pulse	= 30,
-+	.nwe_pulse		= 15,
-+
-+	.read_cycle		= 30,
-+	.write_cycle		= 30,
-+
-+	.ncs_read_recover	= 0,
-+	.nrd_recover		= 15,
-+	.ncs_write_recover	= 0,
-+	.nwe_recover		= 50,
-+};
-+
-+static struct smc_config nand_config __initdata = {
-+	.bus_width		= 1,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.nwait_mode		= 0,
-+	.byte_write		= 0,
-+	.tdf_cycles		= 3,
-+	.tdf_mode		= 0,
-+};
-+
-+static struct mtd_partition nand_partitions[] = {
-+	{
-+		.name	= "u-boot",
-+		.offset	= 0,
-+		.size	= 131072,
-+	}, {
-+		.name	= "kernel",
-+		.offset	= 262144,
-+		.size	= 2097152,
-+	}, {
-+		.name	= "user",
-+		.offset	= 2359296,
-+		.size	= MTDPART_SIZ_FULL,
-+	},
-+};
-+
-+/* Isn't this rather more complicated than necessary? */
-+static struct mtd_partition *nand_part_info(int size, int *num_partitions)
-+{
-+	*num_partitions = ARRAY_SIZE(nand_partitions);
-+	return nand_partitions;
-+}
-+
-+static struct atmel_nand_data nand_data __initdata = {
-+	.cle		= 21,
-+	.ale		= 22,
-+	.rdy_pin	= GPIO_PIN_PE(31),
-+	.enable_pin	= GPIO_PIN_PF(2),
-+	.det_pin	= GPIO_PIN_NONE,
-+	.partition_info	= nand_part_info,
-+};
-+
-+
-+/*
-+ * Grab ethernet address and PHY address provided by the boot loader.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	struct tag_ethernet *etag = &tag->u.ethernet;
-+
-+	if (etag->mac_index == 0) {
-+		eth_data.phy_mask = ~(1U << etag->mii_phy_addr);
-+		memcpy(&hw_addr.addr, etag->hw_address, sizeof(hw_addr.addr));
-+	}
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+/*
-+ * We need to get rid of this crap and pass the mac address to the
-+ * driver explicitly.
-+ */
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id != 0)
-+		return;
-+
-+	addr = hw_addr.addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(4, 0);	/* USART4: /dev/ttyS0, DB9 */
-+	at32_setup_serial_console(0);
-+}
-+
-+static int __init atstk1005_init(void)
-+{
-+	struct platform_device	*lcdc_pdev;
-+
-+	at32_add_device_usart(0);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data));
-+	lcdc_pdev = at32_add_device_lcdc(0, &atstk1000_lcdc_data,
-+			fbmem_start, fbmem_size, 0);
-+	at32_add_device_mpop(0, lcdc_pdev, fbmem_start, fbmem_size);
-+	at32_add_device_mci(0, &mci_data);
-+	at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+
-+	/* NAND Flash */
-+	smc_set_timing(&nand_config, &nand_timing);
-+	smc_set_configuration(3, &nand_config);
-+	at32_add_device_nand(0, &nand_data);
-+
-+	/* USB OHCI/EHCI host */
-+	at32_add_device_ohci(0);
-+	at32_add_device_ehci(0);
-+
-+	return 0;
-+}
-+postcore_initcall(atstk1005_init);
-diff --git a/arch/avr32/boards/favr-32/Kconfig b/arch/avr32/boards/favr-32/Kconfig
-new file mode 100644
-index 0000000..2c83d1d
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/Kconfig
-@@ -0,0 +1,22 @@
-+# Favr-32 customization
-+
-+if BOARD_FAVR_32
-+
-+config BOARD_FAVR32_ABDAC_RATE
-+	int "DAC target rate"
-+	default 44100
-+	range 32000 50000
-+	help
-+	  Specify the target rate the internal DAC should try to match. This
-+	  will use PLL1 to generate a frequency as close as possible to this
-+	  rate.
-+
-+	  Must be within the range 32000 to 50000, which should be suitable to
-+	  generate most other frequencies in power of 2 steps.
-+
-+	  Ex:
-+		48000 will also suit 24000 and 12000
-+		44100 will also suit 22050 and 11025
-+		32000 will also suit 16000 and 8000
-+
-+endif # BOARD_FAVR_32
-diff --git a/arch/avr32/boards/favr-32/Makefile b/arch/avr32/boards/favr-32/Makefile
-new file mode 100644
-index 0000000..234f215
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/Makefile
-@@ -0,0 +1 @@
-+obj-y	+= setup.o flash.o
-diff --git a/arch/avr32/boards/favr-32/flash.c b/arch/avr32/boards/favr-32/flash.c
-new file mode 100644
-index 0000000..604bbd5
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/flash.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Favr-32 board-specific flash initialization
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include <mach/smc.h>
-+
-+static struct smc_timing flash_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 40,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 10,
-+
-+	.ncs_read_pulse		= 80,
-+	.nrd_pulse		= 40,
-+	.ncs_write_pulse	= 65,
-+	.nwe_pulse		= 55,
-+
-+	.read_cycle		= 120,
-+	.write_cycle		= 120,
-+};
-+
-+static struct smc_config flash_config __initdata = {
-+	.bus_width		= 2,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.byte_write		= 1,
-+};
-+
-+static struct mtd_partition flash_parts[] = {
-+	{
-+		.name           = "u-boot",
-+		.offset         = 0x00000000,
-+		.size           = 0x00020000,           /* 128 KiB */
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+	{
-+		.name           = "root",
-+		.offset         = 0x00020000,
-+		.size           = 0x007d0000,
-+	},
-+	{
-+		.name           = "env",
-+		.offset         = 0x007f0000,
-+		.size           = 0x00010000,
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+};
-+
-+static struct physmap_flash_data flash_data = {
-+	.width		= 2,
-+	.nr_parts	= ARRAY_SIZE(flash_parts),
-+	.parts		= flash_parts,
-+};
-+
-+static struct resource flash_resource = {
-+	.start		= 0x00000000,
-+	.end		= 0x007fffff,
-+	.flags		= IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device = {
-+	.name		= "physmap-flash",
-+	.id		= 0,
-+	.resource	= &flash_resource,
-+	.num_resources	= 1,
-+	.dev		= {
-+		.platform_data = &flash_data,
-+	},
-+};
-+
-+/* This needs to be called after the SMC has been initialized */
-+static int __init favr32_flash_init(void)
-+{
-+	int ret;
-+
-+	smc_set_timing(&flash_config, &flash_timing);
-+	ret = smc_set_configuration(0, &flash_config);
-+	if (ret < 0) {
-+		printk(KERN_ERR "Favr-32: failed to set NOR flash timing\n");
-+		return ret;
-+	}
-+
-+	platform_device_register(&flash_device);
-+
-+	return 0;
-+}
-+device_initcall(favr32_flash_init);
-diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c
-new file mode 100644
-index 0000000..1a12930
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/setup.c
-@@ -0,0 +1,334 @@
-+/*
-+ * Favr-32 board-specific setup code.
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/bootmem.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/types.h>
-+#include <linux/linkage.h>
-+#include <linux/gpio.h>
-+#include <linux/leds.h>
-+#include <linux/atmel-pwm-bl.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/ads7846.h>
-+
-+#include <video/atmel_lcdc.h>
-+
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap700x.h>
-+#include <mach/init.h>
-+#include <mach/board.h>
-+#include <mach/portmux.h>
-+
-+/* Oscillator frequencies. These are board-specific */
-+unsigned long at32_board_osc_rates[3] = {
-+	[0] = 32768,	/* 32.768 kHz on RTC osc */
-+	[1] = 20000000,	/* 20 MHz on osc0 */
-+	[2] = 12000000,	/* 12 MHz on osc1 */
-+};
-+
-+/* Initialized by bootloader-specific startup code. */
-+struct tag *bootloader_tags __initdata;
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+static struct eth_addr __initdata hw_addr[1];
-+static struct eth_platform_data __initdata eth_data[1] = {
-+	{
-+		.phy_mask	= ~(1U << 1),
-+	},
-+};
-+
-+static int ads7843_get_pendown_state(void)
-+{
-+	return !gpio_get_value(GPIO_PIN_PB(3));
-+}
-+
-+static struct ads7846_platform_data ads7843_data = {
-+	.model			= 7843,
-+	.get_pendown_state	= ads7843_get_pendown_state,
-+	.pressure_max		= 255,
-+	/*
-+	 * Values below are for debounce filtering, these can be experimented
-+	 * with further.
-+	 */
-+	.debounce_max		= 20,
-+	.debounce_rep		= 4,
-+	.debounce_tol		= 5,
-+};
-+
-+static struct spi_board_info __initdata spi1_board_info[] = {
-+	{
-+		/* ADS7843 touch controller */
-+		.modalias	= "ads7846",
-+		.max_speed_hz	= 2000000,
-+		.chip_select	= 0,
-+		.bus_num	= 1,
-+		.platform_data	= &ads7843_data,
-+	},
-+};
-+
-+static struct fb_videomode __initdata lb104v03_modes[] = {
-+	{
-+		.name		= "640x480 @ 50",
-+		.refresh	= 50,
-+		.xres		= 640,		.yres		= 480,
-+		.pixclock	= KHZ2PICOS(25100),
-+
-+		.left_margin	= 90,		.right_margin	= 70,
-+		.upper_margin	= 30,		.lower_margin	= 15,
-+		.hsync_len	= 12,		.vsync_len	= 2,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata favr32_default_monspecs = {
-+	.manufacturer		= "LG",
-+	.monitor		= "LB104V03",
-+	.modedb			= lb104v03_modes,
-+	.modedb_len		= ARRAY_SIZE(lb104v03_modes),
-+	.hfmin			= 27273,
-+	.hfmax			= 31111,
-+	.vfmin			= 45,
-+	.vfmax			= 60,
-+	.dclkmax		= 28000000,
-+};
-+
-+struct atmel_lcdfb_info __initdata favr32_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &favr32_default_monspecs,
-+	.guard_time		= 2,
-+};
-+
-+static struct gpio_led favr32_leds[] = {
-+	{
-+		.name		 = "green",
-+		.gpio		 = GPIO_PIN_PE(19),
-+		.default_trigger = "heartbeat",
-+		.active_low	 = 1,
-+	},
-+	{
-+		.name		 = "red",
-+		.gpio		 = GPIO_PIN_PE(20),
-+		.active_low	 = 1,
-+	},
-+};
-+
-+static struct gpio_led_platform_data favr32_led_data = {
-+	.num_leds	= ARRAY_SIZE(favr32_leds),
-+	.leds		= favr32_leds,
-+};
-+
-+static struct platform_device favr32_led_dev = {
-+	.name		= "leds-gpio",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data	= &favr32_led_data,
-+	},
-+};
-+
-+/*
-+ * The next two functions should go away as the boot loader is
-+ * supposed to initialize the macb address registers with a valid
-+ * ethernet address. But we need to keep it around for a while until
-+ * we can be reasonably sure the boot loader does this.
-+ *
-+ * The phy_id is ignored as the driver will probe for it.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	int i;
-+
-+	i = tag->u.ethernet.mac_index;
-+	if (i < ARRAY_SIZE(hw_addr))
-+		memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
-+		       sizeof(hw_addr[i].addr));
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id >= ARRAY_SIZE(hw_addr))
-+		return;
-+
-+	addr = hw_addr[pdev->id].addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init favr32_setup_leds(void)
-+{
-+	unsigned i;
-+
-+	for (i = 0; i < ARRAY_SIZE(favr32_leds); i++)
-+		at32_select_gpio(favr32_leds[i].gpio, AT32_GPIOF_OUTPUT);
-+
-+	platform_device_register(&favr32_led_dev);
-+}
-+
-+static struct atmel_pwm_bl_platform_data atmel_pwm_bl_pdata = {
-+	.pwm_channel		= 2,
-+	.pwm_frequency		= 200000,
-+	.pwm_compare_max	= 345,
-+	.pwm_duty_max		= 345,
-+	.pwm_duty_min		= 90,
-+	.pwm_active_low		= 1,
-+	.gpio_on		= GPIO_PIN_PA(28),
-+	.on_active_low		= 0,
-+};
-+
-+static struct platform_device atmel_pwm_bl_dev = {
-+	.name		= "atmel-pwm-bl",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data = &atmel_pwm_bl_pdata,
-+	},
-+};
-+
-+static void __init favr32_setup_atmel_pwm_bl(void)
-+{
-+	platform_device_register(&atmel_pwm_bl_dev);
-+	at32_select_gpio(atmel_pwm_bl_pdata.gpio_on, 0);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(3, 0);	/* USART 3 => /dev/ttyS0 */
-+	at32_setup_serial_console(0);
-+}
-+
-+static int __init set_abdac_rate(struct platform_device *pdev)
-+{
-+	int retval;
-+	struct clk *osc1;
-+	struct clk *pll1;
-+	struct clk *abdac;
-+
-+	if (pdev == NULL)
-+		return -ENXIO;
-+
-+	osc1 = clk_get(NULL, "osc1");
-+	if (IS_ERR(osc1)) {
-+		retval = PTR_ERR(osc1);
-+		goto out;
-+	}
-+
-+	pll1 = clk_get(NULL, "pll1");
-+	if (IS_ERR(pll1)) {
-+		retval = PTR_ERR(pll1);
-+		goto out_osc1;
-+	}
-+
-+	abdac = clk_get(&pdev->dev, "sample_clk");
-+	if (IS_ERR(abdac)) {
-+		retval = PTR_ERR(abdac);
-+		goto out_pll1;
-+	}
-+
-+	retval = clk_set_parent(pll1, osc1);
-+	if (retval != 0)
-+		goto out_abdac;
-+
-+	/*
-+	 * Rate is 32000 to 50000 and ABDAC oversamples 256x. Multiply, in
-+	 * power of 2, to a value above 80 MHz. Power of 2 so it is possible
-+	 * for the generic clock to divide it down again and 80 MHz is the
-+	 * lowest frequency for the PLL.
-+	 */
-+	retval = clk_round_rate(pll1,
-+			CONFIG_BOARD_FAVR32_ABDAC_RATE * 256 * 16);
-+	if (retval < 0)
-+		goto out_abdac;
-+
-+	retval = clk_set_rate(pll1, retval);
-+	if (retval != 0)
-+		goto out_abdac;
-+
-+	retval = clk_set_parent(abdac, pll1);
-+	if (retval != 0)
-+		goto out_abdac;
-+
-+out_abdac:
-+	clk_put(abdac);
-+out_pll1:
-+	clk_put(pll1);
-+out_osc1:
-+	clk_put(osc1);
-+out:
-+	return retval;
-+}
-+
-+static int __init favr32_init(void)
-+{
-+	/*
-+	 * Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific
-+	 * pins so that nobody messes with them.
-+	 */
-+	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
-+
-+	at32_select_gpio(GPIO_PIN_PB(3), 0);	/* IRQ from ADS7843 */
-+
-+	at32_add_device_usart(0);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
-+
-+	spi1_board_info[0].irq = gpio_to_irq(GPIO_PIN_PB(3));
-+
-+	set_abdac_rate(at32_add_device_abdac(0));
-+
-+	at32_add_device_pwm(1 << atmel_pwm_bl_pdata.pwm_channel);
-+	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
-+	at32_add_device_mci(0, NULL);
-+	at32_add_device_usba(0, NULL);
-+	at32_add_device_lcdc(0, &favr32_lcdc_data, fbmem_start, fbmem_size, 0);
-+
-+	favr32_setup_leds();
-+
-+	favr32_setup_atmel_pwm_bl();
-+
-+	return 0;
-+}
-+postcore_initcall(favr32_init);
-diff --git a/arch/avr32/boards/mimc200/Makefile b/arch/avr32/boards/mimc200/Makefile
-new file mode 100644
-index 0000000..79c076e
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/Makefile
-@@ -0,0 +1 @@
-+obj-y				+= setup.o flash.o fram.o
-diff --git a/arch/avr32/boards/mimc200/flash.c b/arch/avr32/boards/mimc200/flash.c
-new file mode 100644
-index 0000000..d83d650
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/flash.c
-@@ -0,0 +1,143 @@
-+/*
-+ * MIMC200 board-specific flash initialization
-+ *
-+ * Copyright (C) 2008 Mercury IMC Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include <mach/smc.h>
-+
-+static struct smc_timing flash_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 15,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 0,
-+
-+	.ncs_read_pulse		= 115,
-+	.nrd_pulse		= 110,
-+	.ncs_write_pulse	= 60,
-+	.nwe_pulse		= 60,
-+
-+	.read_cycle		= 115,
-+	.write_cycle		= 100,
-+};
-+
-+static struct smc_config flash_config __initdata = {
-+	.bus_width		= 2,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.byte_write		= 1,
-+};
-+
-+/* system flash definition */
-+
-+static struct mtd_partition flash_parts_system[] = {
-+	{
-+		.name           = "u-boot",
-+		.offset         = 0x00000000,
-+		.size           = 0x00020000,           /* 128 KiB */
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+	{
-+		.name           = "root",
-+		.offset         = 0x00020000,
-+		.size           = 0x007c0000,
-+	},
-+	{
-+		.name		= "splash",
-+		.offset		= 0x007e0000,
-+		.size		= 0x00010000,		/* 64KiB */
-+	},
-+	{
-+		.name           = "env",
-+		.offset         = 0x007f0000,
-+		.size           = 0x00010000,
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+};
-+
-+static struct physmap_flash_data flash_system = {
-+	.width		= 2,
-+	.nr_parts	= ARRAY_SIZE(flash_parts_system),
-+	.parts		= flash_parts_system,
-+};
-+
-+static struct resource flash_resource_system = {
-+	.start		= 0x00000000,
-+	.end		= 0x007fffff,
-+	.flags		= IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device_system = {
-+	.name		= "physmap-flash",
-+	.id		= 0,
-+	.resource	= &flash_resource_system,
-+	.num_resources	= 1,
-+	.dev		= {
-+		.platform_data = &flash_system,
-+	},
-+};
-+
-+/* data flash definition */
-+
-+static struct mtd_partition flash_parts_data[] = {
-+	{
-+		.name		= "data",
-+		.offset		= 0x00000000,
-+		.size		= 0x00800000,
-+	},
-+};
-+
-+static struct physmap_flash_data flash_data = {
-+	.width		= 2,
-+	.nr_parts	= ARRAY_SIZE(flash_parts_data),
-+	.parts		= flash_parts_data,
-+};
-+
-+static struct resource flash_resource_data = {
-+	.start		= 0x08000000,
-+	.end		= 0x087fffff,
-+	.flags		= IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device_data = {
-+	.name		= "physmap-flash",
-+	.id		= 1,
-+	.resource	= &flash_resource_data,
-+	.num_resources	= 1,
-+	.dev		= {
-+		.platform_data = &flash_data,
-+	},
-+};
-+
-+/* This needs to be called after the SMC has been initialized */
-+static int __init mimc200_flash_init(void)
-+{
-+	int ret;
-+
-+	smc_set_timing(&flash_config, &flash_timing);
-+	ret = smc_set_configuration(0, &flash_config);
-+	if (ret < 0) {
-+		printk(KERN_ERR "mimc200: failed to set 'System' NOR flash timing\n");
-+		return ret;
-+	}
-+	ret = smc_set_configuration(1, &flash_config);
-+	if (ret < 0) {
-+		printk(KERN_ERR "mimc200: failed to set 'Data' NOR flash timing\n");
-+		return ret;
-+	}
-+
-+	platform_device_register(&flash_device_system);
-+	platform_device_register(&flash_device_data);
-+
-+	return 0;
-+}
-+device_initcall(mimc200_flash_init);
-diff --git a/arch/avr32/boards/mimc200/fram.c b/arch/avr32/boards/mimc200/fram.c
-new file mode 100644
-index 0000000..54fbd95
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/fram.c
-@@ -0,0 +1,80 @@
-+/*
-+ * FRAM driver for MIMC200 board
-+ *
-+ * Copyright 2008 Mark Jackson <mpfj@mimc.co.uk>
-+ *
-+ * This module adds *very* simply support for the system's FRAM device.
-+ * At the moment, this is hard-coded to the MIMC200 platform, and only
-+ * supports mmap().
-+ */
-+
-+#define FRAM_VERSION	"1.0"
-+
-+#include <linux/miscdevice.h>
-+#include <linux/proc_fs.h>
-+#include <linux/mm.h>
-+#include <linux/io.h>
-+
-+#define FRAM_BASE	0xac000000
-+#define FRAM_SIZE	0x20000
-+
-+/*
-+ * The are the file operation function for user access to /dev/fram
-+ */
-+
-+static int fram_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+	int ret;
-+
-+	ret = remap_pfn_range(vma,
-+		vma->vm_start,
-+		virt_to_phys((void *)((unsigned long)FRAM_BASE)) >> PAGE_SHIFT,
-+		vma->vm_end-vma->vm_start,
-+		PAGE_SHARED);
-+
-+	if (ret != 0)
-+		return -EAGAIN;
-+
-+	return 0;
-+}
-+
-+static const struct file_operations fram_fops = {
-+	.owner			= THIS_MODULE,
-+	.mmap			= fram_mmap,
-+};
-+
-+#define FRAM_MINOR	0
-+
-+static struct miscdevice fram_dev = {
-+	FRAM_MINOR,
-+	"fram",
-+	&fram_fops
-+};
-+
-+static int __init
-+fram_init(void)
-+{
-+	int ret;
-+
-+	ret = misc_register(&fram_dev);
-+	if (ret) {
-+		printk(KERN_ERR "fram: can't misc_register on minor=%d\n",
-+		    FRAM_MINOR);
-+		return ret;
-+	}
-+	printk(KERN_INFO "FRAM memory driver v" FRAM_VERSION "\n");
-+	return 0;
-+}
-+
-+static void __exit
-+fram_cleanup_module(void)
-+{
-+	misc_deregister(&fram_dev);
-+}
-+
-+module_init(fram_init);
-+module_exit(fram_cleanup_module);
-+
-+MODULE_LICENSE("GPL");
-+
-+MODULE_ALIAS_MISCDEV(FRAM_MINOR);
-diff --git a/arch/avr32/boards/mimc200/setup.c b/arch/avr32/boards/mimc200/setup.c
-new file mode 100644
-index 0000000..c060d4d
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/setup.c
-@@ -0,0 +1,235 @@
-+/*
-+ * Board-specific setup code for the MIMC200
-+ *
-+ * Copyright (C) 2008 Mercury IMC Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+extern struct atmel_lcdfb_info mimc200_lcdc_data;
-+
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/i2c-gpio.h>
-+#include <linux/init.h>
-+#include <linux/linkage.h>
-+#include <linux/platform_device.h>
-+#include <linux/types.h>
-+#include <linux/leds.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/eeprom.h>
-+
-+#include <video/atmel_lcdc.h>
-+#include <linux/fb.h>
-+
-+#include <asm/atmel-mci.h>
-+#include <linux/io.h>
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap700x.h>
-+#include <mach/board.h>
-+#include <mach/init.h>
-+#include <mach/portmux.h>
-+
-+/* Oscillator frequencies. These are board-specific */
-+unsigned long at32_board_osc_rates[3] = {
-+	[0] = 32768,	/* 32.768 kHz on RTC osc */
-+	[1] = 10000000,	/* 10 MHz on osc0 */
-+	[2] = 12000000,	/* 12 MHz on osc1 */
-+};
-+
-+/* Initialized by bootloader-specific startup code. */
-+struct tag *bootloader_tags __initdata;
-+
-+static struct fb_videomode __initdata tx14d14_modes[] = {
-+	{
-+		.name		= "640x480 @ 60",
-+		.refresh	= 60,
-+		.xres		= 640,		.yres		= 480,
-+		.pixclock	= KHZ2PICOS(11666),
-+
-+		.left_margin	= 80,		.right_margin	= 1,
-+		.upper_margin	= 13,		.lower_margin	= 2,
-+		.hsync_len	= 64,		.vsync_len	= 1,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata mimc200_default_monspecs = {
-+	.manufacturer		= "HIT",
-+	.monitor		= "TX14D14VM1BAB",
-+	.modedb			= tx14d14_modes,
-+	.modedb_len		= ARRAY_SIZE(tx14d14_modes),
-+	.hfmin			= 14820,
-+	.hfmax			= 22230,
-+	.vfmin			= 60,
-+	.vfmax			= 73.3,
-+	.dclkmax		= 25200000,
-+};
-+
-+struct atmel_lcdfb_info __initdata mimc200_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_INVCLK
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &mimc200_default_monspecs,
-+	.guard_time		= 2,
-+};
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+static struct eth_addr __initdata hw_addr[2];
-+static struct eth_platform_data __initdata eth_data[2];
-+
-+static struct spi_eeprom eeprom_25lc010 = {
-+		.name = "25lc010",
-+		.byte_len = 128,
-+		.page_size = 16,
-+		.flags = EE_ADDR1,
-+};
-+
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+	{
-+		.modalias	= "rtc-ds1390",
-+		.max_speed_hz	= 4000000,
-+		.chip_select	= 2,
-+	},
-+	{
-+		.modalias	= "at25",
-+		.max_speed_hz	= 1000000,
-+		.chip_select	= 1,
-+		.mode		= SPI_MODE_3,
-+		.platform_data	= &eeprom_25lc010,
-+	},
-+};
-+
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+		.detect_pin	= GPIO_PIN_PA(26),
-+		.wp_pin		= GPIO_PIN_PA(27),
-+	},
-+};
-+
-+/*
-+ * The next two functions should go away as the boot loader is
-+ * supposed to initialize the macb address registers with a valid
-+ * ethernet address. But we need to keep it around for a while until
-+ * we can be reasonably sure the boot loader does this.
-+ *
-+ * The phy_id is ignored as the driver will probe for it.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	int i;
-+
-+	i = tag->u.ethernet.mac_index;
-+	if (i < ARRAY_SIZE(hw_addr))
-+		memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
-+		       sizeof(hw_addr[i].addr));
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id >= ARRAY_SIZE(hw_addr))
-+		return;
-+
-+	addr = hw_addr[pdev->id].addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(0, 0);	/* USART 0: /dev/ttyS0 (TTL --> Altera) */
-+	at32_map_usart(1, 1);	/* USART 1: /dev/ttyS1 (RS232) */
-+	at32_map_usart(2, 2);	/* USART 2: /dev/ttyS2 (RS485) */
-+	at32_map_usart(3, 3);	/* USART 3: /dev/ttyS3 (RS422 Multidrop) */
-+}
-+
-+static struct i2c_gpio_platform_data i2c_gpio_data = {
-+	.sda_pin		= GPIO_PIN_PA(6),
-+	.scl_pin		= GPIO_PIN_PA(7),
-+	.sda_is_open_drain	= 1,
-+	.scl_is_open_drain	= 1,
-+	.udelay			= 2,	/* close to 100 kHz */
-+};
-+
-+static struct platform_device i2c_gpio_device = {
-+	.name		= "i2c-gpio",
-+	.id		= 0,
-+	.dev		= {
-+	.platform_data	= &i2c_gpio_data,
-+	},
-+};
-+
-+static struct i2c_board_info __initdata i2c_info[] = {
-+};
-+
-+static int __init mimc200_init(void)
-+{
-+	/*
-+	 * MIMC200 uses 16-bit SDRAM interface, so we don't need to
-+	 * reserve any pins for it.
-+	 */
-+
-+	at32_add_device_usart(0);
-+	at32_add_device_usart(1);
-+	at32_add_device_usart(2);
-+	at32_add_device_usart(3);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
-+	set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
-+
-+	at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+	at32_add_device_mci(0, &mci0_data);
-+	at32_add_device_usba(0, NULL);
-+
-+	at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
-+	at32_select_gpio(i2c_gpio_data.sda_pin,
-+		AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	at32_select_gpio(i2c_gpio_data.scl_pin,
-+		AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	platform_device_register(&i2c_gpio_device);
-+	i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
-+
-+	at32_add_device_lcdc(0, &mimc200_lcdc_data,
-+			     fbmem_start, fbmem_size, 1);
-+
-+	return 0;
-+}
-+postcore_initcall(mimc200_init);
-diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
-index 5415209..58fe9f3 100644
---- a/arch/avr32/configs/atngw100_defconfig
-+++ b/arch/avr32/configs/atngw100_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 16:00:47 2008
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:33:33 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -130,11 +130,15 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- # CONFIG_BOARD_ATSTK1000 is not set
- CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X is not set
- CONFIG_LOADER_U_BOOT=y
- 
- #
-@@ -177,7 +181,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -615,6 +619,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -664,6 +669,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -706,7 +712,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -720,6 +726,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -751,11 +758,14 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_DISPLAY_SUPPORT is not set
- # CONFIG_SOUND is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -806,6 +816,7 @@ CONFIG_MMC_TEST=m
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -880,11 +891,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -898,13 +911,13 @@ CONFIG_DMATEST=m
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- # CONFIG_FS_POSIX_ACL is not set
-@@ -944,7 +957,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--CONFIG_CONFIGFS_FS=m
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig
-new file mode 100644
-index 0000000..24f57fa
---- /dev/null
-+++ b/arch/avr32/configs/atngw100_evklcd100_defconfig
-@@ -0,0 +1,1323 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:10:50 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+CONFIG_BOARD_ATNGW100_EVKLCD10X=y
-+CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA=y
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA is not set
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=y
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=y
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_MULTIPLE_TABLES is not set
-+# CONFIG_IP_ROUTE_MULTIPATH is not set
-+# CONFIG_IP_ROUTE_VERBOSE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_PIMSM_V1=y
-+# CONFIG_IP_PIMSM_V2 is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=y
-+CONFIG_INET_ESP=y
-+CONFIG_INET_IPCOMP=y
-+CONFIG_INET_XFRM_TUNNEL=y
-+CONFIG_INET_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IP_VS is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=y
-+CONFIG_INET6_ESP=y
-+CONFIG_INET6_IPCOMP=y
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=y
-+CONFIG_INET6_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET6_XFRM_MODE_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_BEET=y
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=y
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+CONFIG_NETFILTER=y
-+# CONFIG_NETFILTER_DEBUG is not set
-+# CONFIG_NETFILTER_ADVANCED is not set
-+
-+#
-+# Core Netfilter Configuration
-+#
-+CONFIG_NETFILTER_NETLINK=m
-+CONFIG_NETFILTER_NETLINK_LOG=m
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XTABLES=y
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+
-+#
-+# IP: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_TARGET_LOG=m
-+# CONFIG_IP_NF_TARGET_ULOG is not set
-+CONFIG_NF_NAT=m
-+CONFIG_NF_NAT_NEEDED=y
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_NF_NAT_FTP=m
-+CONFIG_NF_NAT_IRC=m
-+# CONFIG_NF_NAT_TFTP is not set
-+# CONFIG_NF_NAT_AMANDA is not set
-+# CONFIG_NF_NAT_PPTP is not set
-+# CONFIG_NF_NAT_H323 is not set
-+CONFIG_NF_NAT_SIP=m
-+CONFIG_IP_NF_MANGLE=m
-+
-+#
-+# IPv6: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_LOG=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+# CONFIG_VLAN_8021Q_GVRP is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x80000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=y
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPPOE=m
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_UCB1400 is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_SPI=y
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+# CONFIG_DMADEVICES is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=850
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+# CONFIG_PROC_KCORE is not set
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3=y
-+# CONFIG_NFSD_V3_ACL is not set
-+# CONFIG_NFSD_V4 is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+CONFIG_SMB_FS=m
-+# CONFIG_SMB_NLS_DEFAULT is not set
-+CONFIG_CIFS=m
-+# CONFIG_CIFS_STATS is not set
-+# CONFIG_CIFS_WEAK_PW_HASH is not set
-+# CONFIG_CIFS_XATTR is not set
-+# CONFIG_CIFS_DEBUG2 is not set
-+# CONFIG_CIFS_EXPERIMENTAL is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=m
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_MANAGER=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=y
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=m
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=y
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=m
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig
-new file mode 100644
-index 0000000..253b4b9
---- /dev/null
-+++ b/arch/avr32/configs/atngw100_evklcd101_defconfig
-@@ -0,0 +1,1323 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:11:19 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+CONFIG_BOARD_ATNGW100_EVKLCD10X=y
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA is not set
-+CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA=y
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=y
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=y
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_MULTIPLE_TABLES is not set
-+# CONFIG_IP_ROUTE_MULTIPATH is not set
-+# CONFIG_IP_ROUTE_VERBOSE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_PIMSM_V1=y
-+# CONFIG_IP_PIMSM_V2 is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=y
-+CONFIG_INET_ESP=y
-+CONFIG_INET_IPCOMP=y
-+CONFIG_INET_XFRM_TUNNEL=y
-+CONFIG_INET_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IP_VS is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=y
-+CONFIG_INET6_ESP=y
-+CONFIG_INET6_IPCOMP=y
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=y
-+CONFIG_INET6_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET6_XFRM_MODE_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_BEET=y
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=y
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+CONFIG_NETFILTER=y
-+# CONFIG_NETFILTER_DEBUG is not set
-+# CONFIG_NETFILTER_ADVANCED is not set
-+
-+#
-+# Core Netfilter Configuration
-+#
-+CONFIG_NETFILTER_NETLINK=m
-+CONFIG_NETFILTER_NETLINK_LOG=m
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XTABLES=y
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+
-+#
-+# IP: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_TARGET_LOG=m
-+# CONFIG_IP_NF_TARGET_ULOG is not set
-+CONFIG_NF_NAT=m
-+CONFIG_NF_NAT_NEEDED=y
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_NF_NAT_FTP=m
-+CONFIG_NF_NAT_IRC=m
-+# CONFIG_NF_NAT_TFTP is not set
-+# CONFIG_NF_NAT_AMANDA is not set
-+# CONFIG_NF_NAT_PPTP is not set
-+# CONFIG_NF_NAT_H323 is not set
-+CONFIG_NF_NAT_SIP=m
-+CONFIG_IP_NF_MANGLE=m
-+
-+#
-+# IPv6: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_LOG=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+# CONFIG_VLAN_8021Q_GVRP is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x80000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=y
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPPOE=m
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_UCB1400 is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_SPI=y
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+# CONFIG_DMADEVICES is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=850
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+# CONFIG_PROC_KCORE is not set
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3=y
-+# CONFIG_NFSD_V3_ACL is not set
-+# CONFIG_NFSD_V4 is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+CONFIG_SMB_FS=m
-+# CONFIG_SMB_NLS_DEFAULT is not set
-+CONFIG_CIFS=m
-+# CONFIG_CIFS_STATS is not set
-+# CONFIG_CIFS_WEAK_PW_HASH is not set
-+# CONFIG_CIFS_XATTR is not set
-+# CONFIG_CIFS_DEBUG2 is not set
-+# CONFIG_CIFS_EXPERIMENTAL is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=m
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_MANAGER=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=y
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=m
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=y
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=m
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
-index 69fce6b..42829bb 100644
---- a/arch/avr32/configs/atstk1002_defconfig
-+++ b/arch/avr32/configs/atstk1002_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Mon Aug  4 16:02:27 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:28:45 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -129,20 +129,24 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- CONFIG_BOARD_ATSTK1002=y
- # CONFIG_BOARD_ATSTK1003 is not set
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -186,7 +190,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -360,7 +364,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -421,12 +426,23 @@ CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_DOC2001 is not set
- # CONFIG_MTD_DOC2001PLUS is not set
- # CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
- # CONFIG_MTD_ONENAND is not set
- 
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
- CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
-@@ -502,7 +518,7 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
--CONFIG_TUN=m
-+# CONFIG_TUN is not set
- # CONFIG_VETH is not set
- CONFIG_PHYLIB=y
- 
-@@ -561,7 +577,7 @@ CONFIG_SLHC=m
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -590,6 +606,8 @@ CONFIG_KEYBOARD_GPIO=m
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -606,8 +624,12 @@ CONFIG_MOUSE_GPIO=m
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -634,6 +656,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -663,7 +686,7 @@ CONFIG_I2C_GPIO=m
- # Miscellaneous I2C Chip support
- #
- # CONFIG_DS1682 is not set
--CONFIG_AT24=m
-+# CONFIG_AT24 is not set
- # CONFIG_SENSORS_EEPROM is not set
- # CONFIG_SENSORS_PCF8574 is not set
- # CONFIG_PCF8575 is not set
-@@ -683,6 +706,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -725,7 +749,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -739,6 +763,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -784,6 +809,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -797,6 +823,12 @@ CONFIG_LCD_LTV350QV=y
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
- CONFIG_SOUND=m
- CONFIG_SND=m
-@@ -820,11 +852,14 @@ CONFIG_SND_AT73C213_TARGET_BITRATE=48000
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -876,6 +911,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -952,11 +988,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -1017,7 +1055,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -1031,7 +1069,8 @@ CONFIG_TMPFS=y
- # CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-@@ -1039,6 +1078,12 @@ CONFIG_JFFS2_ZLIB=y
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
- # CONFIG_CRAMFS is not set
- # CONFIG_VXFS_FS is not set
- CONFIG_MINIX_FS=m
-@@ -1173,7 +1218,7 @@ CONFIG_CRYPTO=y
- #
- # Crypto core or helper
- #
--CONFIG_CRYPTO_ALGAPI=m
-+CONFIG_CRYPTO_ALGAPI=y
- CONFIG_CRYPTO_AEAD=m
- CONFIG_CRYPTO_BLKCIPHER=m
- CONFIG_CRYPTO_HASH=m
-@@ -1247,8 +1292,8 @@ CONFIG_CRYPTO_DES=m
- #
- # Compression
- #
--CONFIG_CRYPTO_DEFLATE=m
--# CONFIG_CRYPTO_LZO is not set
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
- # CONFIG_CRYPTO_HW is not set
- 
- #
-@@ -1258,7 +1303,7 @@ CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
- CONFIG_CRC_CCITT=m
--# CONFIG_CRC16 is not set
-+CONFIG_CRC16=y
- CONFIG_CRC_T10DIF=m
- CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
-@@ -1266,6 +1311,8 @@ CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
- CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
-diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig
-index 5477ed3..9eb129b 100644
---- a/arch/avr32/configs/atstk1003_defconfig
-+++ b/arch/avr32/configs/atstk1003_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:34:44 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:33:33 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -34,12 +34,9 @@ CONFIG_SWAP=y
- CONFIG_SYSVIPC=y
- CONFIG_SYSVIPC_SYSCTL=y
- CONFIG_POSIX_MQUEUE=y
--CONFIG_BSD_PROCESS_ACCT=y
--CONFIG_BSD_PROCESS_ACCT_V3=y
--CONFIG_TASKSTATS=y
--CONFIG_TASK_DELAY_ACCT=y
--# CONFIG_TASK_XACCT is not set
--CONFIG_AUDIT=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
- # CONFIG_IKCONFIG is not set
- CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_CGROUPS is not set
-@@ -71,7 +68,7 @@ CONFIG_TIMERFD=y
- CONFIG_EVENTFD=y
- CONFIG_SHMEM=y
- CONFIG_VM_EVENT_COUNTERS=y
--# CONFIG_SLUB_DEBUG is not set
-+CONFIG_SLUB_DEBUG=y
- # CONFIG_SLAB is not set
- CONFIG_SLUB=y
- # CONFIG_SLOB is not set
-@@ -90,6 +87,7 @@ CONFIG_HAVE_KPROBES=y
- CONFIG_HAVE_CLK=y
- CONFIG_PROC_PAGE_MONITOR=y
- # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
- CONFIG_RT_MUTEXES=y
- # CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
-@@ -131,20 +129,24 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7001=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- CONFIG_BOARD_ATSTK1003=y
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -188,7 +190,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -239,40 +241,71 @@ CONFIG_NET=y
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
- CONFIG_IP_FIB_HASH=y
--# CONFIG_IP_PNP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
- # CONFIG_INET_LRO is not set
--# CONFIG_INET_DIAG is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -331,7 +364,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -397,7 +431,15 @@ CONFIG_M25PXX_USE_FAST_READ=y
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
- CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
-@@ -458,9 +500,7 @@ CONFIG_SCSI_WAIT_SCAN=m
- # CONFIG_SCSI_ISCSI_ATTRS is not set
- # CONFIG_SCSI_SAS_LIBSAS is not set
- # CONFIG_SCSI_SRP_ATTRS is not set
--CONFIG_SCSI_LOWLEVEL=y
--# CONFIG_ISCSI_TCP is not set
--# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
- # CONFIG_SCSI_DH is not set
- CONFIG_ATA=m
- # CONFIG_ATA_NONSTANDARD is not set
-@@ -477,7 +517,32 @@ CONFIG_NETDEVICES=y
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
- # CONFIG_VETH is not set
--# CONFIG_NET_ETHERNET is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
- # CONFIG_NETDEV_1000 is not set
- # CONFIG_NETDEV_10000 is not set
- 
-@@ -509,7 +574,7 @@ CONFIG_SLHC=m
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -521,7 +586,7 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
- CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
- CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_JOYDEV is not set
--# CONFIG_INPUT_EVDEV is not set
-+CONFIG_INPUT_EVDEV=m
- # CONFIG_INPUT_EVBUG is not set
- 
- #
-@@ -538,6 +603,8 @@ CONFIG_KEYBOARD_GPIO=m
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -555,7 +622,7 @@ CONFIG_MOUSE_GPIO=m
- # Character devices
- #
- # CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -582,6 +649,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -611,7 +679,7 @@ CONFIG_I2C_GPIO=m
- # Miscellaneous I2C Chip support
- #
- # CONFIG_DS1682 is not set
--CONFIG_AT24=m
-+# CONFIG_AT24 is not set
- # CONFIG_SENSORS_EEPROM is not set
- # CONFIG_SENSORS_PCF8574 is not set
- # CONFIG_PCF8575 is not set
-@@ -631,6 +699,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -673,7 +742,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -687,6 +756,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -726,8 +796,8 @@ CONFIG_SND_MIXER_OSS=m
- CONFIG_SND_PCM_OSS=m
- CONFIG_SND_PCM_OSS_PLUGINS=y
- # CONFIG_SND_DYNAMIC_MINORS is not set
--CONFIG_SND_SUPPORT_OLD_API=y
--CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
- # CONFIG_SND_VERBOSE_PRINTK is not set
- # CONFIG_SND_DEBUG is not set
- # CONFIG_SND_DRIVERS is not set
-@@ -738,11 +808,14 @@ CONFIG_SND_AT73C213_TARGET_BITRATE=48000
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -750,7 +823,7 @@ CONFIG_USB_SUPPORT=y
- CONFIG_USB_GADGET=y
- # CONFIG_USB_GADGET_DEBUG is not set
- # CONFIG_USB_GADGET_DEBUG_FILES is not set
--CONFIG_USB_GADGET_DEBUG_FS=y
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
- CONFIG_USB_GADGET_SELECTED=y
- # CONFIG_USB_GADGET_AMD5536UDC is not set
- CONFIG_USB_GADGET_ATMEL_USBA=y
-@@ -787,33 +860,34 @@ CONFIG_MMC=y
- CONFIG_MMC_BLOCK=y
- CONFIG_MMC_BLOCK_BOUNCE=y
- # CONFIG_SDIO_UART is not set
--CONFIG_MMC_TEST=m
-+# CONFIG_MMC_TEST is not set
- 
- #
- # MMC/SD Host Controller Drivers
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
--CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_CLASS=m
- 
- #
- # LED drivers
- #
- CONFIG_LEDS_ATMEL_PWM=m
- # CONFIG_LEDS_PCA9532 is not set
--CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_GPIO=m
- # CONFIG_LEDS_PCA955X is not set
- 
- #
- # LED Triggers
- #
- CONFIG_LEDS_TRIGGERS=y
--CONFIG_LEDS_TRIGGER_TIMER=y
--CONFIG_LEDS_TRIGGER_HEARTBEAT=y
--CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
- # CONFIG_ACCESSIBILITY is not set
- CONFIG_RTC_LIB=y
- CONFIG_RTC_CLASS=y
-@@ -870,11 +944,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -888,13 +964,13 @@ CONFIG_DMATEST=m
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_JBD_DEBUG is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-@@ -935,7 +1011,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--CONFIG_CONFIGFS_FS=m
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -958,16 +1034,39 @@ CONFIG_JFFS2_ZLIB=y
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
- # CONFIG_CRAMFS is not set
- # CONFIG_VXFS_FS is not set
--# CONFIG_MINIX_FS is not set
-+CONFIG_MINIX_FS=m
- # CONFIG_OMFS_FS is not set
- # CONFIG_HPFS_FS is not set
- # CONFIG_QNX4FS_FS is not set
- # CONFIG_ROMFS_FS is not set
- # CONFIG_SYSV_FS is not set
- # CONFIG_UFS_FS is not set
--# CONFIG_NETWORK_FILESYSTEMS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
- 
- #
- # Partition Types
-@@ -1036,6 +1135,8 @@ CONFIG_SCHED_DEBUG=y
- # CONFIG_SCHEDSTATS is not set
- # CONFIG_TIMER_STATS is not set
- # CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
- # CONFIG_DEBUG_RT_MUTEXES is not set
- # CONFIG_RT_MUTEX_TESTER is not set
- # CONFIG_DEBUG_SPINLOCK is not set
-@@ -1068,7 +1169,88 @@ CONFIG_FRAME_POINTER=y
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
- # CONFIG_SECURITY_FILE_CAPABILITIES is not set
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
- 
- #
- # Library routines
-@@ -1077,15 +1259,16 @@ CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
- CONFIG_CRC_CCITT=m
--# CONFIG_CRC16 is not set
-+CONFIG_CRC16=y
- CONFIG_CRC_T10DIF=m
- CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
- CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
--CONFIG_AUDIT_GENERIC=y
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
- CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
-diff --git a/arch/avr32/configs/atstk1004_defconfig b/arch/avr32/configs/atstk1004_defconfig
-index 69e6c0d..9f76e2a 100644
---- a/arch/avr32/configs/atstk1004_defconfig
-+++ b/arch/avr32/configs/atstk1004_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:38:56 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:35:14 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -30,8 +30,10 @@ CONFIG_BROKEN_ON_SMP=y
- CONFIG_INIT_ENV_ARG_LIMIT=32
- CONFIG_LOCALVERSION=""
- # CONFIG_LOCALVERSION_AUTO is not set
--# CONFIG_SYSVIPC is not set
--# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- # CONFIG_TASKSTATS is not set
- # CONFIG_AUDIT is not set
-@@ -41,14 +43,16 @@ CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_GROUP_SCHED is not set
- CONFIG_SYSFS_DEPRECATED=y
- CONFIG_SYSFS_DEPRECATED_V2=y
--# CONFIG_RELAY is not set
-+CONFIG_RELAY=y
- # CONFIG_NAMESPACES is not set
--# CONFIG_BLK_DEV_INITRD is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
- CONFIG_CC_OPTIMIZE_FOR_SIZE=y
- CONFIG_SYSCTL=y
- CONFIG_EMBEDDED=y
- # CONFIG_SYSCTL_SYSCALL is not set
- CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
- CONFIG_HOTPLUG=y
- CONFIG_PRINTK=y
-@@ -56,19 +60,23 @@ CONFIG_BUG=y
- CONFIG_ELF_CORE=y
- # CONFIG_COMPAT_BRK is not set
- # CONFIG_BASE_FULL is not set
--# CONFIG_FUTEX is not set
--# CONFIG_EPOLL is not set
--# CONFIG_SIGNALFD is not set
--# CONFIG_TIMERFD is not set
--# CONFIG_EVENTFD is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
- CONFIG_SHMEM=y
- CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
- # CONFIG_SLAB is not set
--# CONFIG_SLUB is not set
--CONFIG_SLOB=y
--# CONFIG_PROFILING is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
- # CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
- CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
- # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
- # CONFIG_HAVE_IOREMAP_PROT is not set
- CONFIG_HAVE_KPROBES=y
-@@ -77,36 +85,68 @@ CONFIG_HAVE_KPROBES=y
- # CONFIG_HAVE_DMA_ATTRS is not set
- # CONFIG_USE_GENERIC_SMP_HELPERS is not set
- CONFIG_HAVE_CLK=y
--# CONFIG_PROC_PAGE_MONITOR is not set
-+CONFIG_PROC_PAGE_MONITOR=y
- # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
- # CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
--# CONFIG_MODULES is not set
--# CONFIG_BLOCK is not set
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
- CONFIG_CLASSIC_RCU=y
- 
- #
- # System Type and features
- #
--# CONFIG_TICK_ONESHOT is not set
--# CONFIG_NO_HZ is not set
--# CONFIG_HIGH_RES_TIMERS is not set
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
- CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7002=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- # CONFIG_BOARD_ATSTK1003 is not set
- CONFIG_BOARD_ATSTK1004=y
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -144,25 +184,43 @@ CONFIG_ZONE_DMA_FLAG=0
- CONFIG_NR_QUICK=2
- CONFIG_VIRT_TO_BUS=y
- # CONFIG_OWNERSHIP_TRACE is not set
--# CONFIG_NMI_DEBUGGING is not set
-+CONFIG_NMI_DEBUGGING=y
- # CONFIG_HZ_100 is not set
- CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
- # Power management options
- #
--# CONFIG_PM is not set
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
- CONFIG_ARCH_SUSPEND_POSSIBLE=y
- 
- #
- # CPU Frequency scaling
- #
--# CONFIG_CPU_FREQ is not set
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
- 
- #
- # Bus options
-@@ -183,40 +241,71 @@ CONFIG_NET=y
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
- CONFIG_IP_FIB_HASH=y
--# CONFIG_IP_PNP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
- # CONFIG_INET_LRO is not set
--# CONFIG_INET_DIAG is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -230,6 +319,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
- # Network testing
- #
- # CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
- # CONFIG_HAMRADIO is not set
- # CONFIG_CAN is not set
- # CONFIG_IRDA is not set
-@@ -257,6 +347,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
- CONFIG_STANDALONE=y
- # CONFIG_PREVENT_FIRMWARE_BUILD is not set
- # CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
- # CONFIG_SYS_HYPERVISOR is not set
- # CONFIG_CONNECTOR is not set
- CONFIG_MTD=y
-@@ -271,6 +363,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
- # User Modules And Translation Layers
- #
- CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
- # CONFIG_MTD_OOPS is not set
- 
- #
-@@ -311,11 +411,13 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- # Self-contained MTD device drivers
- #
--# CONFIG_MTD_DATAFLASH is not set
--# CONFIG_MTD_M25P80 is not set
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_SLRAM is not set
- # CONFIG_MTD_PHRAM is not set
- # CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
- 
- #
- # Disk-On-Chip Device Drivers
-@@ -329,24 +431,186 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
--# CONFIG_MISC_DEVICES is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
- # CONFIG_HAVE_IDE is not set
- 
- #
- # SCSI device support
- #
--# CONFIG_SCSI_DMA is not set
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
- # CONFIG_SCSI_NETLINK is not set
--# CONFIG_NETDEVICES is not set
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+# CONFIG_SCSI_DH is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+# CONFIG_SATA_PMP is not set
-+CONFIG_ATA_SFF=y
-+# CONFIG_SATA_MV is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
- # CONFIG_ISDN is not set
- # CONFIG_PHONE is not set
- 
- #
- # Input device support
- #
--# CONFIG_INPUT is not set
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
- 
- #
- # Hardware I/O ports
-@@ -357,8 +621,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -371,7 +639,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- CONFIG_SERIAL_ATMEL=y
- CONFIG_SERIAL_ATMEL_CONSOLE=y
--# CONFIG_SERIAL_ATMEL_PDC is not set
-+CONFIG_SERIAL_ATMEL_PDC=y
- # CONFIG_SERIAL_ATMEL_TTYAT is not set
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-@@ -380,14 +648,62 @@ CONFIG_UNIX98_PTYS=y
- # CONFIG_IPMI_HANDLER is not set
- # CONFIG_HW_RANDOM is not set
- # CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
- # CONFIG_TCG_TPM is not set
--# CONFIG_I2C is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
- CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
- CONFIG_SPI_MASTER=y
- 
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -395,15 +711,19 @@ CONFIG_SPI_ATMEL=y
- # SPI Protocol Masters
- #
- # CONFIG_SPI_AT25 is not set
--# CONFIG_SPI_SPIDEV is not set
-+CONFIG_SPI_SPIDEV=m
- # CONFIG_SPI_TLE62X0 is not set
- CONFIG_ARCH_REQUIRE_GPIOLIB=y
- CONFIG_GPIOLIB=y
--# CONFIG_GPIO_SYSFS is not set
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
- 
- #
- # I2C GPIO expanders:
- #
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
- 
- #
- # PCI GPIO expanders:
-@@ -426,7 +746,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -440,6 +760,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -485,6 +806,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -498,20 +820,51 @@ CONFIG_LCD_LTV350QV=y
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
--# CONFIG_SOUND is not set
-+CONFIG_SOUND=m
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_DRIVERS is not set
-+CONFIG_SND_SPI=y
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+# CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
- #
- CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
- # CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
- CONFIG_USB_GADGET_SELECTED=y
- # CONFIG_USB_GADGET_AMD5536UDC is not set
- CONFIG_USB_GADGET_ATMEL_USBA=y
-@@ -528,18 +881,54 @@ CONFIG_USB_ATMEL_USBA=y
- # CONFIG_USB_GADGET_AT91 is not set
- # CONFIG_USB_GADGET_DUMMY_HCD is not set
- CONFIG_USB_GADGET_DUALSPEED=y
--# CONFIG_USB_ZERO is not set
--CONFIG_USB_ETH=y
--# CONFIG_USB_ETH_RNDIS is not set
--# CONFIG_USB_GADGETFS is not set
--# CONFIG_USB_FILE_STORAGE is not set
--# CONFIG_USB_G_SERIAL is not set
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
- # CONFIG_USB_MIDI_GADGET is not set
- # CONFIG_USB_G_PRINTER is not set
--# CONFIG_USB_CDC_COMPOSITE is not set
--# CONFIG_MMC is not set
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
--# CONFIG_NEW_LEDS is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=m
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
- # CONFIG_ACCESSIBILITY is not set
- CONFIG_RTC_LIB=y
- CONFIG_RTC_CLASS=y
-@@ -551,12 +940,28 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
- # RTC interfaces
- #
- CONFIG_RTC_INTF_SYSFS=y
--# CONFIG_RTC_INTF_PROC is not set
-+CONFIG_RTC_INTF_PROC=y
- CONFIG_RTC_INTF_DEV=y
- # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
- # CONFIG_RTC_DRV_TEST is not set
- 
- #
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
- # SPI RTC drivers
- #
- # CONFIG_RTC_DRV_M41T94 is not set
-@@ -580,18 +985,62 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
--# CONFIG_DMADEVICES is not set
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+# CONFIG_ATMEL_PDCA is not set
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+CONFIG_DMATEST=m
- # CONFIG_UIO is not set
- 
- #
- # File systems
- #
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
- # CONFIG_DNOTIFY is not set
--# CONFIG_INOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
- # CONFIG_QUOTA is not set
- # CONFIG_AUTOFS_FS is not set
- # CONFIG_AUTOFS4_FS is not set
--# CONFIG_FUSE_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
- 
- #
- # Pseudo filesystems
-@@ -603,14 +1052,22 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
- #
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-@@ -618,8 +1075,85 @@ CONFIG_JFFS2_ZLIB=y
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
--# CONFIG_NETWORK_FILESYSTEMS is not set
--# CONFIG_NLS is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+CONFIG_MINIX_FS=m
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
- # CONFIG_DLM is not set
- 
- #
-@@ -631,11 +1165,43 @@ CONFIG_ENABLE_MUST_CHECK=y
- CONFIG_FRAME_WARN=1024
- CONFIG_MAGIC_SYSRQ=y
- # CONFIG_UNUSED_SYMBOLS is not set
--# CONFIG_DEBUG_FS is not set
-+CONFIG_DEBUG_FS=y
- # CONFIG_HEADERS_CHECK is not set
--# CONFIG_DEBUG_KERNEL is not set
--# CONFIG_DEBUG_BUGVERBOSE is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
- # CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
- # CONFIG_SAMPLES is not set
- 
- #
-@@ -644,7 +1210,88 @@ CONFIG_MAGIC_SYSRQ=y
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
- # CONFIG_SECURITY_FILE_CAPABILITIES is not set
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
- 
- #
- # Library routines
-@@ -652,16 +1299,19 @@ CONFIG_MAGIC_SYSRQ=y
- CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
--# CONFIG_CRC_CCITT is not set
--# CONFIG_CRC16 is not set
--# CONFIG_CRC_T10DIF is not set
--# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+CONFIG_CRC_T10DIF=m
-+CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
--# CONFIG_CRC7 is not set
-+CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
- CONFIG_HAS_IOPORT=y
- CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atstk1005_defconfig b/arch/avr32/configs/atstk1005_defconfig
-new file mode 100644
-index 0000000..e36b73d
---- /dev/null
-+++ b/arch/avr32/configs/atstk1005_defconfig
-@@ -0,0 +1,1505 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Fri Nov  7 10:22:27 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+CONFIG_RELAY=y
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_GPIO_V2=y
-+CONFIG_TIMER_AST=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP720X=y
-+CONFIG_CPU_AT32AP7200=y
-+CONFIG_BOARD_ATSTK1000=y
-+# CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+# CONFIG_BOARD_ATSTK1002 is not set
-+# CONFIG_BOARD_ATSTK1003 is not set
-+# CONFIG_BOARD_ATSTK1004 is not set
-+CONFIG_BOARD_ATSTK1005=y
-+# CONFIG_BOARD_ATSTK1006 is not set
-+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
-+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
-+CONFIG_BOARD_ATSTK1000_EXTDAC=y
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x8000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_M25PXX_USE_FAST_READ=y
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+CONFIG_MTD_NAND_ATMEL=y
-+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
-+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+# CONFIG_BLK_DEV_UB is not set
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+# CONFIG_ATMEL_TCLIB is not set
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+# CONFIG_SCSI_DH is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+# CONFIG_SATA_PMP is not set
-+CONFIG_ATA_SFF=y
-+# CONFIG_SATA_MV is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+CONFIG_MII=m
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+
-+#
-+# USB Network Adapters
-+#
-+CONFIG_USB_CATC=m
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+CONFIG_USB_USBNET=m
-+# CONFIG_USB_NET_AX8817X is not set
-+CONFIG_USB_NET_CDCETHER=m
-+# CONFIG_USB_NET_DM9601 is not set
-+# CONFIG_USB_NET_GL620A is not set
-+# CONFIG_USB_NET_NET1080 is not set
-+# CONFIG_USB_NET_PLUSB is not set
-+# CONFIG_USB_NET_MCS7830 is not set
-+# CONFIG_USB_NET_RNDIS_HOST is not set
-+CONFIG_USB_NET_CDC_SUBSET=m
-+# CONFIG_USB_ALI_M5632 is not set
-+# CONFIG_USB_AN2720 is not set
-+CONFIG_USB_BELKIN=y
-+CONFIG_USB_ARMLINUX=y
-+# CONFIG_USB_EPSON2888 is not set
-+# CONFIG_USB_KC2190 is not set
-+# CONFIG_USB_NET_ZAURUS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+CONFIG_I2C_TINY_USB=m
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+CONFIG_LCD_CLASS_DEVICE=y
-+CONFIG_LCD_LTV350QV=y
-+# CONFIG_LCD_ILI9320 is not set
-+# CONFIG_LCD_VGG2432A4 is not set
-+# CONFIG_LCD_PLATFORM is not set
-+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=m
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+CONFIG_SND_HWDEP=m
-+CONFIG_SND_RAWMIDI=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_DRIVERS is not set
-+CONFIG_SND_SPI=y
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+CONFIG_SND_USB=y
-+CONFIG_SND_USB_AUDIO=m
-+# CONFIG_SND_USB_CAIAQ is not set
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-+# CONFIG_HID_FF is not set
-+# CONFIG_USB_HIDDEV is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+
-+#
-+# Miscellaneous USB options
-+#
-+CONFIG_USB_DEVICEFS=y
-+# CONFIG_USB_DEVICE_CLASS is not set
-+CONFIG_USB_DYNAMIC_MINORS=y
-+CONFIG_USB_SUSPEND=y
-+# CONFIG_USB_OTG is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+CONFIG_USB_MON=y
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+CONFIG_USB_EHCI_HCD=y
-+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_ISP1760_HCD is not set
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
-+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
-+# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+CONFIG_USB_ACM=m
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_WDM=m
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+
-+#
-+# may also be needed; see USB_STORAGE Help for more information
-+#
-+CONFIG_USB_STORAGE=m
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_DPCM is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+CONFIG_USB_SERIAL=m
-+# CONFIG_USB_EZUSB is not set
-+CONFIG_USB_SERIAL_GENERIC=y
-+# CONFIG_USB_SERIAL_AIRCABLE is not set
-+# CONFIG_USB_SERIAL_ARK3116 is not set
-+# CONFIG_USB_SERIAL_BELKIN is not set
-+# CONFIG_USB_SERIAL_CH341 is not set
-+# CONFIG_USB_SERIAL_WHITEHEAT is not set
-+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-+# CONFIG_USB_SERIAL_CP2101 is not set
-+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-+# CONFIG_USB_SERIAL_EMPEG is not set
-+# CONFIG_USB_SERIAL_FTDI_SIO is not set
-+# CONFIG_USB_SERIAL_FUNSOFT is not set
-+# CONFIG_USB_SERIAL_VISOR is not set
-+# CONFIG_USB_SERIAL_IPAQ is not set
-+# CONFIG_USB_SERIAL_IR is not set
-+# CONFIG_USB_SERIAL_EDGEPORT is not set
-+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-+# CONFIG_USB_SERIAL_GARMIN is not set
-+# CONFIG_USB_SERIAL_IPW is not set
-+# CONFIG_USB_SERIAL_IUU is not set
-+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-+# CONFIG_USB_SERIAL_KEYSPAN is not set
-+# CONFIG_USB_SERIAL_KLSI is not set
-+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-+# CONFIG_USB_SERIAL_MCT_U232 is not set
-+# CONFIG_USB_SERIAL_MOS7720 is not set
-+# CONFIG_USB_SERIAL_MOS7840 is not set
-+# CONFIG_USB_SERIAL_MOTOROLA is not set
-+# CONFIG_USB_SERIAL_NAVMAN is not set
-+CONFIG_USB_SERIAL_PL2303=m
-+# CONFIG_USB_SERIAL_OTI6858 is not set
-+# CONFIG_USB_SERIAL_SPCP8X5 is not set
-+# CONFIG_USB_SERIAL_HP4X is not set
-+# CONFIG_USB_SERIAL_SAFE is not set
-+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-+# CONFIG_USB_SERIAL_TI is not set
-+# CONFIG_USB_SERIAL_CYBERJACK is not set
-+# CONFIG_USB_SERIAL_XIRCOM is not set
-+# CONFIG_USB_SERIAL_OPTION is not set
-+# CONFIG_USB_SERIAL_OMNINET is not set
-+# CONFIG_USB_SERIAL_DEBUG is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_BERRY_CHARGE is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_PHIDGET is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+CONFIG_USB_TEST=m
-+# CONFIG_USB_ISIGHTFW is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+CONFIG_MMC_TEST=m
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=m
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=m
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_RTC_DRV_AT32AP700X is not set
-+CONFIG_RTC_DRV_AVR32_AST=y
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_ATMEL_PDCA=y
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+CONFIG_DMATEST=m
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+CONFIG_MINIX_FS=m
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+CONFIG_CRC_ITU_T=m
-+CONFIG_CRC32=y
-+CONFIG_CRC7=m
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
-index 8b6e54c..cee2884 100644
---- a/arch/avr32/configs/atstk1006_defconfig
-+++ b/arch/avr32/configs/atstk1006_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:40:26 2008
-+# Linux kernel version: 2.6.27.4
-+# Fri Nov  7 10:25:15 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -129,20 +129,24 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- # CONFIG_BOARD_ATSTK1003 is not set
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- CONFIG_BOARD_ATSTK1006=y
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -186,7 +190,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -360,7 +364,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -422,7 +427,7 @@ CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_DOC2001PLUS is not set
- CONFIG_MTD_NAND=y
- # CONFIG_MTD_NAND_VERIFY_WRITE is not set
--# CONFIG_MTD_NAND_ECC_SMC is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
- # CONFIG_MTD_NAND_MUSEUM_IDS is not set
- CONFIG_MTD_NAND_IDS=y
- # CONFIG_MTD_NAND_DISKONCHIP is not set
-@@ -521,7 +526,7 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
--CONFIG_TUN=m
-+# CONFIG_TUN is not set
- # CONFIG_VETH is not set
- CONFIG_PHYLIB=y
- 
-@@ -580,7 +585,7 @@ CONFIG_SLHC=m
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -609,6 +614,8 @@ CONFIG_KEYBOARD_GPIO=m
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -625,8 +632,12 @@ CONFIG_MOUSE_GPIO=m
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -653,6 +664,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -702,6 +714,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -744,7 +757,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -758,6 +771,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -803,6 +817,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -816,6 +831,12 @@ CONFIG_LCD_LTV350QV=y
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
- CONFIG_SOUND=m
- CONFIG_SND=m
-@@ -831,11 +852,7 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
- # CONFIG_SND_VERBOSE_PROCFS is not set
- # CONFIG_SND_VERBOSE_PRINTK is not set
- # CONFIG_SND_DEBUG is not set
--CONFIG_SND_DRIVERS=y
--# CONFIG_SND_DUMMY is not set
--# CONFIG_SND_MTPAV is not set
--# CONFIG_SND_SERIAL_U16550 is not set
--# CONFIG_SND_MPU401 is not set
-+# CONFIG_SND_DRIVERS is not set
- CONFIG_SND_SPI=y
- CONFIG_SND_AT73C213=m
- CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-@@ -843,11 +860,14 @@ CONFIG_SND_AT73C213_TARGET_BITRATE=48000
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -881,7 +901,7 @@ CONFIG_USB_FILE_STORAGE=m
- CONFIG_USB_G_SERIAL=m
- # CONFIG_USB_MIDI_GADGET is not set
- # CONFIG_USB_G_PRINTER is not set
--# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_USB_CDC_COMPOSITE=m
- CONFIG_MMC=y
- # CONFIG_MMC_DEBUG is not set
- # CONFIG_MMC_UNSAFE_RESUME is not set
-@@ -899,6 +919,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -975,11 +996,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -993,13 +1016,13 @@ CONFIG_DMATEST=m
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_JBD_DEBUG is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-@@ -1040,7 +1063,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -1054,7 +1077,8 @@ CONFIG_TMPFS=y
- # CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-diff --git a/arch/avr32/configs/favr-32_defconfig b/arch/avr32/configs/favr-32_defconfig
-new file mode 100644
-index 0000000..e2bd998
---- /dev/null
-+++ b/arch/avr32/configs/favr-32_defconfig
-@@ -0,0 +1,1235 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27-rc8
-+# Tue Oct 14 13:20:41 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+CONFIG_RELAY=y
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+# CONFIG_BOARD_ATNGW100 is not set
-+CONFIG_BOARD_FAVR_32=y
-+# CONFIG_BOARD_MIMC200 is not set
-+CONFIG_BOARD_FAVR32_ABDAC_RATE=44100
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x8000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_UCB1400 is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+# CONFIG_CONSOLE_TRANSLATIONS is not set
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+# CONFIG_DEVKMEM is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+# CONFIG_LCD_CLASS_DEVICE is not set
-+CONFIG_BACKLIGHT_CLASS_DEVICE=m
-+# CONFIG_BACKLIGHT_ATMEL_LCDC is not set
-+CONFIG_BACKLIGHT_ATMEL_PWM=m
-+# CONFIG_BACKLIGHT_CORGI is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=m
-+# CONFIG_SND is not set
-+CONFIG_SOUND_PRIME=m
-+# CONFIG_HID_SUPPORT is not set
-+CONFIG_USB_SUPPORT=y
-+# CONFIG_USB_ARCH_HAS_HCD is not set
-+# CONFIG_USB_ARCH_HAS_OHCI is not set
-+# CONFIG_USB_ARCH_HAS_EHCI is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+CONFIG_MMC_ATMELMCI_DMA=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+# CONFIG_DMATEST is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=m
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=m
-+# CONFIG_CRYPTO_LZO is not set
-+# CONFIG_CRYPTO_HW is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/mimc200_defconfig b/arch/avr32/configs/mimc200_defconfig
-new file mode 100644
-index 0000000..981e4f8
---- /dev/null
-+++ b/arch/avr32/configs/mimc200_defconfig
-@@ -0,0 +1,1109 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27-rc8
-+# Mon Oct 13 15:46:53 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+# CONFIG_OPROFILE is not set
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+# CONFIG_MODULES is not set
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+# CONFIG_BOARD_ATNGW100 is not set
-+CONFIG_BOARD_MIMC200=y
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=y
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=y
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_MULTIPLE_TABLES is not set
-+# CONFIG_IP_ROUTE_MULTIPATH is not set
-+# CONFIG_IP_ROUTE_VERBOSE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_PIMSM_V1=y
-+# CONFIG_IP_PIMSM_V2 is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=y
-+CONFIG_INET_ESP=y
-+CONFIG_INET_IPCOMP=y
-+CONFIG_INET_XFRM_TUNNEL=y
-+CONFIG_INET_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=y
-+CONFIG_INET6_ESP=y
-+CONFIG_INET6_IPCOMP=y
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=y
-+CONFIG_INET6_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET6_XFRM_MODE_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_BEET=y
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=y
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x80000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=y
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+# CONFIG_BLK_DEV_LOOP is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_RAM is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+# CONFIG_INPUT is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+# CONFIG_VT is not set
-+# CONFIG_DEVKMEM is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=y
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=y
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+CONFIG_AT24=y
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_DS28CM00 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+CONFIG_SPI_AT25=y
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+# CONFIG_LOGO is not set
-+# CONFIG_SOUND is not set
-+# CONFIG_USB_SUPPORT is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+CONFIG_MMC_TEST=y
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=y
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+CONFIG_RTC_DRV_DS1390=y
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_RTC_DRV_AT32AP700X is not set
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+# CONFIG_DMATEST is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=850
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+# CONFIG_PROC_KCORE is not set
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=y
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=y
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_MANAGER=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=y
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=y
-+# CONFIG_CRYPTO_LRW is not set
-+CONFIG_CRYPTO_PCBC=y
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=y
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=y
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+# CONFIG_CRYPTO_LZO is not set
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=y
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_T10DIF is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_CRC32=y
-+CONFIG_CRC7=y
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/include/asm/ast_regs.h b/arch/avr32/include/asm/ast_regs.h
-new file mode 100644
-index 0000000..2e2cfb9
---- /dev/null
-+++ b/arch/avr32/include/asm/ast_regs.h
-@@ -0,0 +1,88 @@
-+/*
-+ * Register definitions for the Asynchronous Timer (AST)
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __AST_REGS_H__
-+#define __AST_REGS_H__
-+
-+/* Control Register */
-+#define AST_CR				0x0000
-+# define AST_CR_EN_BIT			0	/* Enable */
-+# define AST_CR_PCLR_BIT		1	/* Prescaler Clear */
-+# define AST_CR_CA0_BIT			8	/* Clear on Alarm */
-+# define AST_CR_CA1_BIT			9
-+# define AST_CR_PSEL_START		16	/* Prescale Select */
-+# define AST_CR_PSEL_SIZE		4
-+
-+/* Counter Value */
-+#define AST_CV				0x0004
-+
-+/* Status, Status Clear, Interrupt Enable/Disable/Mask, Wake Enable */
-+#define AST_SR				0x0008
-+#define AST_SCR				0x000c
-+#define AST_IER				0x0010
-+#define AST_IDR				0x0014
-+#define AST_IMR				0x0018
-+#define AST_WER				0x001c
-+# define AST_OVF_BIT			0	/* Overflow */
-+# define AST_ALARM0_BIT			8	/* Alarm event */
-+# define AST_ALARM1_BIT			9
-+# define AST_PER0_BIT			16	/* Periodic event */
-+# define AST_PER1_BIT			17
-+# define AST_BUSY_BIT			24	/* AST busy */
-+# define AST_READY_BIT			25	/* BUSY 1 -> 0 event */
-+# define AST_CLK_BUSY_BIT		28	/* CLOCK busy */
-+# define AST_CLK_READY_BIT		29	/* CKL_BUSY 1 -> 0 event */
-+
-+/* Alarm registers */
-+#define AST_AR0				0x0020
-+#define AST_AR1				0x0024
-+
-+/* Periodic Interval registers */
-+#define AST_PIR0			0x0030
-+#define AST_PIR1			0x0034
-+# define AST_PIRx_INSEL_START		0	/* Interval select */
-+# define AST_PIRx_INSEL_SIZE		4
-+
-+/* Clock Select register */
-+#define AST_CLOCK			0x0040
-+# define AST_CLOCK_CEN_BIT		0	/* Clock Enable */
-+# define AST_CLOCK_CSSEL_START		8	/* Clock Source */
-+# define AST_CLOCK_CSSEL_SIZE		2
-+#  define AST_CLOCK_SLOW		0	/* RC oscillator */
-+#  define AST_CLOCK_OSC32		1	/* 32 kHz oscillator */
-+#  define AST_CLOCK_PB			2	/* Peripheral Bus clock */
-+#  define AST_CLOCK_GC			3	/* Generic clock */
-+
-+/* Version register */
-+#define AST_VERSION			0x00fc
-+
-+/* Bit manipulation macros */
-+#define AST_BIT(name)						\
-+	(1 << AST_##name##_BIT)
-+#define AST_BF(name,value)					\
-+	(((value) & ((1 << AST_##name##_SIZE) - 1))		\
-+	 << AST_##name##_START)
-+#define AST_BFEXT(name,value)					\
-+	(((value) >> AST_##name##_START)			\
-+	 & ((1 << AST_##name##_SIZE) - 1))
-+#define AST_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << AST_##name##_SIZE) - 1)		\
-+		    << AST_##name##_START))			\
-+	 | AST_BF(name,value))
-+
-+/* Register access macros */
-+#define ast_readl(base, reg)					\
-+	__raw_readl(base + AST_##reg)
-+#define ast_writel(base, reg, value)				\
-+	__raw_writel(value, base + AST_##reg)
-+
-+struct platform_device;
-+void ast_time_init(struct platform_device *pdev, unsigned int clksel);
-+
-+#endif /* __AST_REGS_H__ */
-diff --git a/arch/avr32/include/asm/atmel-mci.h b/arch/avr32/include/asm/atmel-mci.h
-index c2ea6e1..59f3fad 100644
---- a/arch/avr32/include/asm/atmel-mci.h
-+++ b/arch/avr32/include/asm/atmel-mci.h
-@@ -1,9 +1,39 @@
- #ifndef __ASM_AVR32_ATMEL_MCI_H
- #define __ASM_AVR32_ATMEL_MCI_H
- 
--struct mci_platform_data {
-+#define ATMEL_MCI_MAX_NR_SLOTS	2
-+
-+struct dma_slave;
-+
-+/**
-+ * struct mci_slot_pdata - board-specific per-slot configuration
-+ * @bus_width: Number of data lines wired up the slot
-+ * @detect_pin: GPIO pin wired to the card detect switch
-+ * @wp_pin: GPIO pin wired to the write protect sensor
-+ *
-+ * If a given slot is not present on the board, @bus_width should be
-+ * set to 0. The other fields are ignored in this case.
-+ *
-+ * Any pins that aren't available should be set to a negative value.
-+ *
-+ * Note that support for multiple slots is experimental -- some cards
-+ * might get upset if we don't get the clock management exactly right.
-+ * But in most cases, it should work just fine.
-+ */
-+struct mci_slot_pdata {
-+	unsigned int		bus_width;
- 	int			detect_pin;
- 	int			wp_pin;
- };
- 
-+/**
-+ * struct mci_platform_data - board-specific MMC/SDcard configuration
-+ * @dma_slave: DMA slave interface to use in data transfers, or NULL.
-+ * @slot: Per-slot configuration data.
-+ */
-+struct mci_platform_data {
-+	struct dma_slave	*dma_slave;
-+	struct mci_slot_pdata	slot[ATMEL_MCI_MAX_NR_SLOTS];
-+};
-+
- #endif /* __ASM_AVR32_ATMEL_MCI_H */
-diff --git a/arch/avr32/include/asm/byteorder.h b/arch/avr32/include/asm/byteorder.h
-index d77b48b..8e3af02 100644
---- a/arch/avr32/include/asm/byteorder.h
-+++ b/arch/avr32/include/asm/byteorder.h
-@@ -7,6 +7,9 @@
- #include <asm/types.h>
- #include <linux/compiler.h>
- 
-+#define __BIG_ENDIAN
-+#define __SWAB_64_THRU_32__
-+
- #ifdef __CHECKER__
- extern unsigned long __builtin_bswap_32(unsigned long x);
- extern unsigned short __builtin_bswap_16(unsigned short x);
-@@ -17,15 +20,18 @@ extern unsigned short __builtin_bswap_16(unsigned short x);
-  * the result.
-  */
- #if !(__GNUC__ == 4 && __GNUC_MINOR__ < 2)
--#define __arch__swab32(x) __builtin_bswap_32(x)
--#define __arch__swab16(x) __builtin_bswap_16(x)
--#endif
-+static inline __attribute_const__ __u16 __arch_swab16(__u16 val)
-+{
-+	return __builtin_bswap_16(val);
-+}
-+#define __arch_swab16 __arch_swab16
- 
--#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
--# define __BYTEORDER_HAS_U64__
--# define __SWAB_64_THRU_32__
-+static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
-+{
-+	return __builtin_bswap_32(val);
-+}
-+#define __arch_swab32 __arch_swab32
- #endif
- 
--#include <linux/byteorder/big_endian.h>
--
-+#include <linux/byteorder.h>
- #endif /* __ASM_AVR32_BYTEORDER_H */
-diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
-index a520f77..22c97ef 100644
---- a/arch/avr32/include/asm/io.h
-+++ b/arch/avr32/include/asm/io.h
-@@ -160,6 +160,14 @@ BUILDIO_IOPORT(l, u32)
- #define readw_relaxed			readw
- #define readl_relaxed			readl
- 
-+#define readb_be			__raw_readb
-+#define readw_be			__raw_readw
-+#define readl_be			__raw_readl
-+
-+#define writeb_be			__raw_writeb
-+#define writew_be			__raw_writew
-+#define writel_be			__raw_writel
-+
- #define __BUILD_MEMORY_STRING(bwl, type)				\
- static inline void writes##bwl(volatile void __iomem *addr,		\
- 			       const void *data, unsigned int count)	\
-diff --git a/arch/avr32/kernel/cpu.c b/arch/avr32/kernel/cpu.c
-index e84faff..f2c0cb1 100644
---- a/arch/avr32/kernel/cpu.c
-+++ b/arch/avr32/kernel/cpu.c
-@@ -208,6 +208,7 @@ struct chip_id_map {
- 
- static const struct chip_id_map chip_names[] = {
- 	{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
-+	{ .mid = 0x1f, .pn = 0x1e83, .name = "AT32AP720x" },
- };
- #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
- 
-diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
-index 33d4937..921da60 100644
---- a/arch/avr32/kernel/entry-avr32b.S
-+++ b/arch/avr32/kernel/entry-avr32b.S
-@@ -112,7 +112,9 @@ pgtbl_lookup:
- 
- 	/* Second level lookup */
- 	ld.w	r2, r3[r1 << 2]
-+#ifdef CONFIG_CPU_AT32AP700X
- 	mfsr	r0, SYSREG_TLBARLO
-+#endif
- 	bld	r2, _PAGE_BIT_PRESENT
- 	brcc	page_not_present
- 
-@@ -124,6 +126,8 @@ pgtbl_lookup:
- 	andl	r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
- 	mtsr	SYSREG_TLBELO, r2
- 
-+	/* Later CPUs do this algorithm in hardware */
-+#ifdef CONFIG_CPU_AT32AP700X
- 	/* Figure out which entry we want to replace */
- 	mfsr	r1, SYSREG_MMUCR
- 	clz	r2, r0
-@@ -134,6 +138,7 @@ pgtbl_lookup:
- 
- 1:	bfins	r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
- 	mtsr	SYSREG_MMUCR, r1
-+#endif /* CONFIG_CPU_AT32AP700X */
- 	tlbw
- 
- 	tlbmiss_restore
-@@ -751,8 +756,10 @@ irq_level\level:
- 
- 	lddsp	r4, sp[REG_SR]
- 	bfextu	r4, r4, SYSREG_M0_OFFSET, 3
-+#ifdef CONFIG_CPU_AT32AP700X
- 	cp.w	r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
- 	breq	2f
-+#endif
- 	cp.w	r4, MODE_USER >> SYSREG_M0_OFFSET
- #ifdef CONFIG_PREEMPT
- 	brne	3f
-@@ -786,6 +793,7 @@ irq_level\level:
- 	rete
- #endif
- 
-+#ifdef CONFIG_CPU_AT32AP700X
- 2:	get_thread_info	r0
- 	ld.w	r1, r0[TI_flags]
- 	bld	r1, TIF_CPU_GOING_TO_SLEEP
-@@ -796,6 +804,7 @@ irq_level\level:
- #endif
- 	sub	r1, pc, . - cpu_idle_skip_sleep
- 	stdsp	sp[REG_PC], r1
-+#endif
- #ifdef CONFIG_PREEMPT
- 3:	get_thread_info r0
- 	ld.w	r2, r0[TI_preempt_count]
-diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
-index 2c08ac9..134d530 100644
---- a/arch/avr32/kernel/process.c
-+++ b/arch/avr32/kernel/process.c
-@@ -9,6 +9,7 @@
- #include <linux/module.h>
- #include <linux/kallsyms.h>
- #include <linux/fs.h>
-+#include <linux/pm.h>
- #include <linux/ptrace.h>
- #include <linux/reboot.h>
- #include <linux/tick.h>
-@@ -20,7 +21,7 @@
- 
- #include <mach/pm.h>
- 
--void (*pm_power_off)(void) = NULL;
-+void (*pm_power_off)(void);
- EXPORT_SYMBOL(pm_power_off);
- 
- /*
-diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
-index d8e623c..5c70839 100644
---- a/arch/avr32/kernel/setup.c
-+++ b/arch/avr32/kernel/setup.c
-@@ -283,6 +283,25 @@ static int __init early_parse_fbmem(char *p)
- }
- early_param("fbmem", early_parse_fbmem);
- 
-+/*
-+ * Pick out the memory size.  We look for mem=size@start,
-+ * where start and size are "size[KkMmGg]"
-+ */
-+static int __init early_mem(char *p)
-+{
-+	resource_size_t size, start;
-+
-+	start = system_ram->start;
-+	size  = memparse(p, &p);
-+	if (*p == '@')
-+		start = memparse(p + 1, &p);
-+
-+	system_ram->start = start;
-+	system_ram->end = system_ram->start + size - 1;
-+	return 0;
-+}
-+early_param("mem", early_mem);
-+
- static int __init parse_tag_core(struct tag *tag)
- {
- 	if (tag->hdr.size > 2) {
-diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
-index 283481d..09dfab9 100644
---- a/arch/avr32/kernel/time.c
-+++ b/arch/avr32/kernel/time.c
-@@ -15,6 +15,8 @@
- 
- #include <asm/sysreg.h>
- 
-+#include <mach/cpu.h>
-+#include <mach/init.h>
- #include <mach/pm.h>
- 
- 
-@@ -116,6 +118,9 @@ void __init time_init(void)
- 	unsigned long counter_hz;
- 	int ret;
- 
-+	/* Make sure we don't get any interrupts until we ask for it. */
-+	sysreg_write(COMPARE, 0);
-+
- 	xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
- 	xtime.tv_nsec = 0;
- 
-@@ -130,12 +135,16 @@ void __init time_init(void)
- 	if (ret)
- 		pr_debug("timer: could not register clocksource: %d\n", ret);
- 
-+	if (!cpu_has_working_compare()) {
-+		platform_time_init();
-+		return;
-+	}
-+
- 	/* setup COMPARE clockevent */
- 	comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
- 	comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
- 	comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
- 
--	sysreg_write(COMPARE, 0);
- 	timer_irqaction.dev_id = &comparator;
- 
- 	ret = setup_irq(0, &timer_irqaction);
-diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
-index 514c9a9..79ef59b 100644
---- a/arch/avr32/mach-at32ap/Makefile
-+++ b/arch/avr32/mach-at32ap/Makefile
-@@ -1,9 +1,14 @@
--obj-y				+= pdc.o clock.o intc.o extint.o pio.o hsmc.o
-+obj-y				+= pdc.o clock.o intc.o extint.o hsmc.o
- obj-y				+= hmatrix.o
--obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
-+obj-$(CONFIG_PORTMUX_PIO)	+= pio.o
-+obj-$(CONFIG_PORTMUX_GPIO_V2)	+= gpio-v2.o
-+obj-$(CONFIG_TIMER_AST)		+= timer-ast.o
- obj-$(CONFIG_CPU_FREQ_AT32AP)	+= cpufreq.o
- obj-$(CONFIG_PM)		+= pm.o
- 
-+obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
-+obj-$(CONFIG_CPU_AT32AP720X)	+= at32ap720x.o pm-at32ap720x.o
-+
- ifeq ($(CONFIG_PM_DEBUG),y)
- CFLAGS_pm.o	+= -DDEBUG
- endif
-diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
-index e01dbe4..7e83326 100644
---- a/arch/avr32/mach-at32ap/at32ap700x.c
-+++ b/arch/avr32/mach-at32ap/at32ap700x.c
-@@ -23,6 +23,7 @@
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
- #include <mach/hmatrix.h>
-+#include <mach/pm.h>
- #include <mach/portmux.h>
- #include <mach/sram.h>
- 
-@@ -30,7 +31,7 @@
- 
- #include "clock.h"
- #include "pio.h"
--#include "pm.h"
-+#include "pm-v1.h"
- 
- 
- #define PBMEM(base)					\
-@@ -82,8 +83,9 @@ static struct platform_device _name##_id##_device = {		\
- 	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
- }
- 
--#define select_peripheral(pin, periph, flags)			\
--	at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
-+#define select_peripheral(port, pin_mask, periph, flags)	\
-+	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
-+			   GPIO_##periph, flags)
- 
- #define DEV_CLK(_name, devname, bus, _index)			\
- static struct clk devname##_##_name = {				\
-@@ -812,7 +814,7 @@ static struct resource pio4_resource[] = {
- DEFINE_DEV(pio, 4);
- DEV_CLK(mck, pio4, pba, 14);
- 
--void __init at32_add_system_devices(void)
-+static int __init system_device_init(void)
- {
- 	platform_device_register(&at32_pm0_device);
- 	platform_device_register(&at32_intc0_device);
-@@ -831,7 +833,10 @@ void __init at32_add_system_devices(void)
- 	platform_device_register(&pio2_device);
- 	platform_device_register(&pio3_device);
- 	platform_device_register(&pio4_device);
-+
-+	return 0;
- }
-+core_initcall(system_device_init);
- 
- /* --------------------------------------------------------------------
-  *  PSIF
-@@ -871,6 +876,7 @@ static struct clk atmel_psif1_pclk = {
- struct platform_device *__init at32_add_device_psif(unsigned int id)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (!(id == 0 || id == 1))
- 		return NULL;
-@@ -881,20 +887,22 @@ struct platform_device *__init at32_add_device_psif(unsigned int id)
- 
- 	switch (id) {
- 	case 0:
-+		pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
-+
- 		if (platform_device_add_resources(pdev, atmel_psif0_resource,
- 					ARRAY_SIZE(atmel_psif0_resource)))
- 			goto err_add_resources;
- 		atmel_psif0_pclk.dev = &pdev->dev;
--		select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
--		select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
-+		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
- 		break;
- 	case 1:
-+		pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
-+
- 		if (platform_device_add_resources(pdev, atmel_psif1_resource,
- 					ARRAY_SIZE(atmel_psif1_resource)))
- 			goto err_add_resources;
- 		atmel_psif1_pclk.dev = &pdev->dev;
--		select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
--		select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
-+		select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
- 		break;
- 	default:
- 		return NULL;
-@@ -958,26 +966,30 @@ DEV_CLK(usart, atmel_usart3, pba, 6);
- 
- static inline void configure_usart0_pins(void)
- {
--	select_peripheral(PA(8),  PERIPH_B, 0);	/* RXD	*/
--	select_peripheral(PA(9),  PERIPH_B, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
-+
-+	select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
- }
- 
- static inline void configure_usart1_pins(void)
- {
--	select_peripheral(PA(17), PERIPH_A, 0);	/* RXD	*/
--	select_peripheral(PA(18), PERIPH_A, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
-+
-+	select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
- }
- 
- static inline void configure_usart2_pins(void)
- {
--	select_peripheral(PB(26), PERIPH_B, 0);	/* RXD	*/
--	select_peripheral(PB(27), PERIPH_B, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
- }
- 
- static inline void configure_usart3_pins(void)
- {
--	select_peripheral(PB(18), PERIPH_B, 0);	/* RXD	*/
--	select_peripheral(PB(17), PERIPH_B, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
- }
- 
- static struct platform_device *__initdata at32_usarts[4];
-@@ -1057,59 +1069,73 @@ struct platform_device *__init
- at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	switch (id) {
- 	case 0:
- 		pdev = &macb0_device;
- 
--		select_peripheral(PC(3),  PERIPH_A, 0);	/* TXD0	*/
--		select_peripheral(PC(4),  PERIPH_A, 0);	/* TXD1	*/
--		select_peripheral(PC(7),  PERIPH_A, 0);	/* TXEN	*/
--		select_peripheral(PC(8),  PERIPH_A, 0);	/* TXCK */
--		select_peripheral(PC(9),  PERIPH_A, 0);	/* RXD0	*/
--		select_peripheral(PC(10), PERIPH_A, 0);	/* RXD1	*/
--		select_peripheral(PC(13), PERIPH_A, 0);	/* RXER	*/
--		select_peripheral(PC(15), PERIPH_A, 0);	/* RXDV	*/
--		select_peripheral(PC(16), PERIPH_A, 0);	/* MDC	*/
--		select_peripheral(PC(17), PERIPH_A, 0);	/* MDIO	*/
-+		pin_mask  = (1 << 3);	/* TXD0 */
-+		pin_mask |= (1 << 4);	/* TXD1 */
-+		pin_mask |= (1 << 7);	/* TXEN */
-+		pin_mask |= (1 << 8);	/* TXCK */
-+		pin_mask |= (1 << 9);	/* RXD0 */
-+		pin_mask |= (1 << 10);	/* RXD1 */
-+		pin_mask |= (1 << 13);	/* RXER */
-+		pin_mask |= (1 << 15);	/* RXDV */
-+		pin_mask |= (1 << 16);	/* MDC  */
-+		pin_mask |= (1 << 17);	/* MDIO */
- 
- 		if (!data->is_rmii) {
--			select_peripheral(PC(0),  PERIPH_A, 0);	/* COL	*/
--			select_peripheral(PC(1),  PERIPH_A, 0);	/* CRS	*/
--			select_peripheral(PC(2),  PERIPH_A, 0);	/* TXER	*/
--			select_peripheral(PC(5),  PERIPH_A, 0);	/* TXD2	*/
--			select_peripheral(PC(6),  PERIPH_A, 0);	/* TXD3 */
--			select_peripheral(PC(11), PERIPH_A, 0);	/* RXD2	*/
--			select_peripheral(PC(12), PERIPH_A, 0);	/* RXD3	*/
--			select_peripheral(PC(14), PERIPH_A, 0);	/* RXCK	*/
--			select_peripheral(PC(18), PERIPH_A, 0);	/* SPD	*/
-+			pin_mask |= (1 << 0);	/* COL  */
-+			pin_mask |= (1 << 1);	/* CRS  */
-+			pin_mask |= (1 << 2);	/* TXER */
-+			pin_mask |= (1 << 5);	/* TXD2 */
-+			pin_mask |= (1 << 6);	/* TXD3 */
-+			pin_mask |= (1 << 11);	/* RXD2 */
-+			pin_mask |= (1 << 12);	/* RXD3 */
-+			pin_mask |= (1 << 14);	/* RXCK */
-+#ifndef CONFIG_BOARD_MIMC200
-+			pin_mask |= (1 << 18);	/* SPD  */
-+#endif
- 		}
-+
-+		select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
-+
- 		break;
- 
- 	case 1:
- 		pdev = &macb1_device;
- 
--		select_peripheral(PD(13), PERIPH_B, 0);		/* TXD0	*/
--		select_peripheral(PD(14), PERIPH_B, 0);		/* TXD1	*/
--		select_peripheral(PD(11), PERIPH_B, 0);		/* TXEN	*/
--		select_peripheral(PD(12), PERIPH_B, 0);		/* TXCK */
--		select_peripheral(PD(10), PERIPH_B, 0);		/* RXD0	*/
--		select_peripheral(PD(6),  PERIPH_B, 0);		/* RXD1	*/
--		select_peripheral(PD(5),  PERIPH_B, 0);		/* RXER	*/
--		select_peripheral(PD(4),  PERIPH_B, 0);		/* RXDV	*/
--		select_peripheral(PD(3),  PERIPH_B, 0);		/* MDC	*/
--		select_peripheral(PD(2),  PERIPH_B, 0);		/* MDIO	*/
-+		pin_mask  = (1 << 13);	/* TXD0 */
-+		pin_mask |= (1 << 14);	/* TXD1 */
-+		pin_mask |= (1 << 11);	/* TXEN */
-+		pin_mask |= (1 << 12);	/* TXCK */
-+		pin_mask |= (1 << 10);	/* RXD0 */
-+		pin_mask |= (1 << 6);	/* RXD1 */
-+		pin_mask |= (1 << 5);	/* RXER */
-+		pin_mask |= (1 << 4);	/* RXDV */
-+		pin_mask |= (1 << 3);	/* MDC  */
-+		pin_mask |= (1 << 2);	/* MDIO */
-+
-+#ifndef CONFIG_BOARD_MIMC200
-+		if (!data->is_rmii)
-+			pin_mask |= (1 << 15);	/* SPD  */
-+#endif
-+
-+		select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
- 
- 		if (!data->is_rmii) {
--			select_peripheral(PC(19), PERIPH_B, 0);	/* COL	*/
--			select_peripheral(PC(23), PERIPH_B, 0);	/* CRS	*/
--			select_peripheral(PC(26), PERIPH_B, 0);	/* TXER	*/
--			select_peripheral(PC(27), PERIPH_B, 0);	/* TXD2	*/
--			select_peripheral(PC(28), PERIPH_B, 0);	/* TXD3 */
--			select_peripheral(PC(29), PERIPH_B, 0);	/* RXD2	*/
--			select_peripheral(PC(30), PERIPH_B, 0);	/* RXD3	*/
--			select_peripheral(PC(24), PERIPH_B, 0);	/* RXCK	*/
--			select_peripheral(PD(15), PERIPH_B, 0);	/* SPD	*/
-+			pin_mask  = (1 << 19);	/* COL  */
-+			pin_mask |= (1 << 23);	/* CRS  */
-+			pin_mask |= (1 << 26);	/* TXER */
-+			pin_mask |= (1 << 27);	/* TXD2 */
-+			pin_mask |= (1 << 28);	/* TXD3 */
-+			pin_mask |= (1 << 29);	/* RXD2 */
-+			pin_mask |= (1 << 30);	/* RXD3 */
-+			pin_mask |= (1 << 24);	/* RXCK */
-+
-+			select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
- 		}
- 		break;
- 
-@@ -1130,6 +1156,7 @@ at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
- static struct resource atmel_spi0_resource[] = {
- 	PBMEM(0xffe00000),
- 	IRQ(3),
-+	{ 0 },	/* SRAM buffer, if available */
- };
- DEFINE_DEV(atmel_spi, 0);
- DEV_CLK(spi_clk, atmel_spi0, pba, 0);
-@@ -1137,6 +1164,7 @@ DEV_CLK(spi_clk, atmel_spi0, pba, 0);
- static struct resource atmel_spi1_resource[] = {
- 	PBMEM(0xffe00400),
- 	IRQ(4),
-+	{ 0 },	/* SRAM buffer, if available */
- };
- DEFINE_DEV(atmel_spi, 1);
- DEV_CLK(spi_clk, atmel_spi1, pba, 1);
-@@ -1166,6 +1194,8 @@ at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
- struct platform_device *__init
- at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- {
-+	unsigned long sram_buf;
-+
- 	/*
- 	 * Manage the chipselects as GPIOs, normally using the same pins
- 	 * the SPI controller expects; but boards can use other pins.
-@@ -1177,23 +1207,28 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- 		{ GPIO_PIN_PB(2), GPIO_PIN_PB(3),
- 		  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	switch (id) {
- 	case 0:
- 		pdev = &atmel_spi0_device;
-+		pin_mask  = (1 << 1) | (1 << 2);	/* MOSI & SCK */
-+
- 		/* pullup MISO so a level is always defined */
--		select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
--		select_peripheral(PA(1),  PERIPH_A, 0);	/* MOSI	 */
--		select_peripheral(PA(2),  PERIPH_A, 0);	/* SCK	 */
-+		select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-+
- 		at32_spi_setup_slaves(0, b, n, spi0_pins);
- 		break;
- 
- 	case 1:
- 		pdev = &atmel_spi1_device;
-+		pin_mask  = (1 << 1) | (1 << 5);	/* MOSI */
-+
- 		/* pullup MISO so a level is always defined */
--		select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
--		select_peripheral(PB(1),  PERIPH_B, 0);	/* MOSI  */
--		select_peripheral(PB(5),  PERIPH_B, 0);	/* SCK   */
-+		select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
-+		select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
-+
- 		at32_spi_setup_slaves(1, b, n, spi1_pins);
- 		break;
- 
-@@ -1201,6 +1236,13 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- 		return NULL;
- 	}
- 
-+	sram_buf = sram_alloc(4096);
-+	if (sram_buf) {
-+		pdev->resource[2].start = sram_buf;
-+		pdev->resource[2].end = sram_buf + 4096 - 1;
-+		pdev->resource[2].flags = IORESOURCE_MEM;
-+	}
-+
- 	spi_register_board_info(b, n);
- 	platform_device_register(pdev);
- 	return pdev;
-@@ -1226,6 +1268,7 @@ struct platform_device *__init at32_add_device_twi(unsigned int id,
- 						    unsigned int n)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -1238,8 +1281,9 @@ struct platform_device *__init at32_add_device_twi(unsigned int id,
- 				ARRAY_SIZE(atmel_twi0_resource)))
- 		goto err_add_resources;
- 
--	select_peripheral(PA(6),  PERIPH_A, 0);	/* SDA	*/
--	select_peripheral(PA(7),  PERIPH_A, 0);	/* SDL	*/
-+	pin_mask  = (1 << 6) | (1 << 7);	/* SDA & SDL */
-+
-+	select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
- 
- 	atmel_twi0_pclk.dev = &pdev->dev;
- 
-@@ -1272,10 +1316,16 @@ static struct clk atmel_mci0_pclk = {
- struct platform_device *__init
- at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
- {
--	struct mci_platform_data	_data;
- 	struct platform_device		*pdev;
-+	struct dw_dma_slave		*dws;
-+	u32				pioa_mask;
-+	u32				piob_mask;
- 
--	if (id != 0)
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	/* Must have at least one usable slot */
-+	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
- 		return NULL;
- 
- 	pdev = platform_device_alloc("atmel_mci", id);
-@@ -1286,28 +1336,80 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
- 				ARRAY_SIZE(atmel_mci0_resource)))
- 		goto fail;
- 
--	if (!data) {
--		data = &_data;
--		memset(data, -1, sizeof(struct mci_platform_data));
--		data->detect_pin = GPIO_PIN_NONE;
--		data->wp_pin = GPIO_PIN_NONE;
--	}
-+	if (data->dma_slave)
-+		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	dws->slave.dev = &pdev->dev;
-+	dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
-+	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
-+				| DWC_CFGH_DST_PER(1));
-+	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	data->dma_slave = &dws->slave;
- 
- 	if (platform_device_add_data(pdev, data,
- 				sizeof(struct mci_platform_data)))
- 		goto fail;
- 
--	select_peripheral(PA(10), PERIPH_A, 0);	/* CLK	 */
--	select_peripheral(PA(11), PERIPH_A, 0);	/* CMD	 */
--	select_peripheral(PA(12), PERIPH_A, 0);	/* DATA0 */
--	select_peripheral(PA(13), PERIPH_A, 0);	/* DATA1 */
--	select_peripheral(PA(14), PERIPH_A, 0);	/* DATA2 */
--	select_peripheral(PA(15), PERIPH_A, 0);	/* DATA3 */
-+	/* CLK line is common to both slots */
-+	pioa_mask = 1 << 10;
- 
--	if (gpio_is_valid(data->detect_pin))
--		at32_select_gpio(data->detect_pin, 0);
--	if (gpio_is_valid(data->wp_pin))
--		at32_select_gpio(data->wp_pin, 0);
-+	switch (data->slot[0].bus_width) {
-+	case 4:
-+		pioa_mask |= 1 << 13;		/* DATA1 */
-+		pioa_mask |= 1 << 14;		/* DATA2 */
-+		pioa_mask |= 1 << 15;		/* DATA3 */
-+		/* fall through */
-+	case 1:
-+		pioa_mask |= 1 << 11;		/* CMD	 */
-+		pioa_mask |= 1 << 12;		/* DATA0 */
-+
-+		if (gpio_is_valid(data->slot[0].detect_pin))
-+			at32_select_gpio(data->slot[0].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[0].wp_pin))
-+			at32_select_gpio(data->slot[0].wp_pin, 0);
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
-+	piob_mask = 0;
-+
-+	switch (data->slot[1].bus_width) {
-+	case 4:
-+		piob_mask |= 1 <<  8;		/* DATA1 */
-+		piob_mask |= 1 <<  9;		/* DATA2 */
-+		piob_mask |= 1 << 10;		/* DATA3 */
-+		/* fall through */
-+	case 1:
-+		piob_mask |= 1 <<  6;		/* CMD	 */
-+		piob_mask |= 1 <<  7;		/* DATA0 */
-+		select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
-+
-+		if (gpio_is_valid(data->slot[1].detect_pin))
-+			at32_select_gpio(data->slot[1].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[1].wp_pin))
-+			at32_select_gpio(data->slot[1].wp_pin, 0);
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		if (!data->slot[0].bus_width)
-+			goto fail;
-+
-+		data->slot[1].bus_width = 0;
-+		break;
-+	}
- 
- 	atmel_mci0_pclk.dev = &pdev->dev;
- 
-@@ -1353,13 +1455,14 @@ static struct clk atmel_lcdfb0_pixclk = {
- struct platform_device *__init
- at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- 		     unsigned long fbmem_start, unsigned long fbmem_len,
--		     unsigned int pin_config)
-+		     u64 pin_mask)
- {
- 	struct platform_device *pdev;
- 	struct atmel_lcdfb_info *info;
- 	struct fb_monspecs *monspecs;
- 	struct fb_videomode *modedb;
- 	unsigned int modedb_size;
-+	u32 portc_mask, portd_mask, porte_mask;
- 
- 	/*
- 	 * Do a deep copy of the fb data, monspecs and modedb. Make
-@@ -1381,76 +1484,21 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- 	case 0:
- 		pdev = &atmel_lcdfb0_device;
- 
--		switch (pin_config) {
--		case 0:
--			select_peripheral(PC(19), PERIPH_A, 0);	/* CC	  */
--			select_peripheral(PC(20), PERIPH_A, 0);	/* HSYNC  */
--			select_peripheral(PC(21), PERIPH_A, 0);	/* PCLK	  */
--			select_peripheral(PC(22), PERIPH_A, 0);	/* VSYNC  */
--			select_peripheral(PC(23), PERIPH_A, 0);	/* DVAL	  */
--			select_peripheral(PC(24), PERIPH_A, 0);	/* MODE	  */
--			select_peripheral(PC(25), PERIPH_A, 0);	/* PWR	  */
--			select_peripheral(PC(26), PERIPH_A, 0);	/* DATA0  */
--			select_peripheral(PC(27), PERIPH_A, 0);	/* DATA1  */
--			select_peripheral(PC(28), PERIPH_A, 0);	/* DATA2  */
--			select_peripheral(PC(29), PERIPH_A, 0);	/* DATA3  */
--			select_peripheral(PC(30), PERIPH_A, 0);	/* DATA4  */
--			select_peripheral(PC(31), PERIPH_A, 0);	/* DATA5  */
--			select_peripheral(PD(0),  PERIPH_A, 0);	/* DATA6  */
--			select_peripheral(PD(1),  PERIPH_A, 0);	/* DATA7  */
--			select_peripheral(PD(2),  PERIPH_A, 0);	/* DATA8  */
--			select_peripheral(PD(3),  PERIPH_A, 0);	/* DATA9  */
--			select_peripheral(PD(4),  PERIPH_A, 0);	/* DATA10 */
--			select_peripheral(PD(5),  PERIPH_A, 0);	/* DATA11 */
--			select_peripheral(PD(6),  PERIPH_A, 0);	/* DATA12 */
--			select_peripheral(PD(7),  PERIPH_A, 0);	/* DATA13 */
--			select_peripheral(PD(8),  PERIPH_A, 0);	/* DATA14 */
--			select_peripheral(PD(9),  PERIPH_A, 0);	/* DATA15 */
--			select_peripheral(PD(10), PERIPH_A, 0);	/* DATA16 */
--			select_peripheral(PD(11), PERIPH_A, 0);	/* DATA17 */
--			select_peripheral(PD(12), PERIPH_A, 0);	/* DATA18 */
--			select_peripheral(PD(13), PERIPH_A, 0);	/* DATA19 */
--			select_peripheral(PD(14), PERIPH_A, 0);	/* DATA20 */
--			select_peripheral(PD(15), PERIPH_A, 0);	/* DATA21 */
--			select_peripheral(PD(16), PERIPH_A, 0);	/* DATA22 */
--			select_peripheral(PD(17), PERIPH_A, 0);	/* DATA23 */
--			break;
--		case 1:
--			select_peripheral(PE(0),  PERIPH_B, 0);	/* CC	  */
--			select_peripheral(PC(20), PERIPH_A, 0);	/* HSYNC  */
--			select_peripheral(PC(21), PERIPH_A, 0);	/* PCLK	  */
--			select_peripheral(PC(22), PERIPH_A, 0);	/* VSYNC  */
--			select_peripheral(PE(1),  PERIPH_B, 0);	/* DVAL	  */
--			select_peripheral(PE(2),  PERIPH_B, 0);	/* MODE	  */
--			select_peripheral(PC(25), PERIPH_A, 0);	/* PWR	  */
--			select_peripheral(PE(3),  PERIPH_B, 0);	/* DATA0  */
--			select_peripheral(PE(4),  PERIPH_B, 0);	/* DATA1  */
--			select_peripheral(PE(5),  PERIPH_B, 0);	/* DATA2  */
--			select_peripheral(PE(6),  PERIPH_B, 0);	/* DATA3  */
--			select_peripheral(PE(7),  PERIPH_B, 0);	/* DATA4  */
--			select_peripheral(PC(31), PERIPH_A, 0);	/* DATA5  */
--			select_peripheral(PD(0),  PERIPH_A, 0);	/* DATA6  */
--			select_peripheral(PD(1),  PERIPH_A, 0);	/* DATA7  */
--			select_peripheral(PE(8),  PERIPH_B, 0);	/* DATA8  */
--			select_peripheral(PE(9),  PERIPH_B, 0);	/* DATA9  */
--			select_peripheral(PE(10), PERIPH_B, 0);	/* DATA10 */
--			select_peripheral(PE(11), PERIPH_B, 0);	/* DATA11 */
--			select_peripheral(PE(12), PERIPH_B, 0);	/* DATA12 */
--			select_peripheral(PD(7),  PERIPH_A, 0);	/* DATA13 */
--			select_peripheral(PD(8),  PERIPH_A, 0);	/* DATA14 */
--			select_peripheral(PD(9),  PERIPH_A, 0);	/* DATA15 */
--			select_peripheral(PE(13), PERIPH_B, 0);	/* DATA16 */
--			select_peripheral(PE(14), PERIPH_B, 0);	/* DATA17 */
--			select_peripheral(PE(15), PERIPH_B, 0);	/* DATA18 */
--			select_peripheral(PE(16), PERIPH_B, 0);	/* DATA19 */
--			select_peripheral(PE(17), PERIPH_B, 0);	/* DATA20 */
--			select_peripheral(PE(18), PERIPH_B, 0);	/* DATA21 */
--			select_peripheral(PD(16), PERIPH_A, 0);	/* DATA22 */
--			select_peripheral(PD(17), PERIPH_A, 0);	/* DATA23 */
--			break;
--		default:
--			goto err_invalid_id;
--		}
-+		if (pin_mask == 0ULL)
-+			/* Default to "full" lcdc control signals and 24bit */
-+			pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
-+
-+		/* LCDC on port C */
-+		portc_mask = pin_mask & 0xfff80000;
-+		select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
-+
-+		/* LCDC on port D */
-+		portd_mask = pin_mask & 0x0003ffff;
-+		select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
-+
-+		/* LCDC on port E */
-+		porte_mask = (pin_mask >> 32) & 0x0007ffff;
-+		select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
- 
- 		clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
- 		clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-@@ -1499,6 +1547,7 @@ static struct clk atmel_pwm0_mck = {
- struct platform_device *__init at32_add_device_pwm(u32 mask)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (!mask)
- 		return NULL;
-@@ -1514,14 +1563,21 @@ struct platform_device *__init at32_add_device_pwm(u32 mask)
- 	if (platform_device_add_data(pdev, &mask, sizeof(mask)))
- 		goto out_free_pdev;
- 
-+	pin_mask = 0;
- 	if (mask & (1 << 0))
--		select_peripheral(PA(28), PERIPH_A, 0);
-+		pin_mask |= (1 << 28);
- 	if (mask & (1 << 1))
--		select_peripheral(PA(29), PERIPH_A, 0);
-+		pin_mask |= (1 << 29);
-+	if (pin_mask > 0)
-+		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-+
-+	pin_mask = 0;
- 	if (mask & (1 << 2))
--		select_peripheral(PA(21), PERIPH_B, 0);
-+		pin_mask |= (1 << 21);
- 	if (mask & (1 << 3))
--		select_peripheral(PA(22), PERIPH_B, 0);
-+		pin_mask |= (1 << 22);
-+	if (pin_mask > 0)
-+		select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
- 
- 	atmel_pwm0_mck.dev = &pdev->dev;
- 
-@@ -1562,52 +1618,65 @@ struct platform_device *__init
- at32_add_device_ssc(unsigned int id, unsigned int flags)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask = 0;
- 
- 	switch (id) {
- 	case 0:
- 		pdev = &ssc0_device;
- 		if (flags & ATMEL_SSC_RF)
--			select_peripheral(PA(21), PERIPH_A, 0);	/* RF */
-+			pin_mask |= (1 << 21);	/* RF */
- 		if (flags & ATMEL_SSC_RK)
--			select_peripheral(PA(22), PERIPH_A, 0);	/* RK */
-+			pin_mask |= (1 << 22);	/* RK */
- 		if (flags & ATMEL_SSC_TK)
--			select_peripheral(PA(23), PERIPH_A, 0);	/* TK */
-+			pin_mask |= (1 << 23);	/* TK */
- 		if (flags & ATMEL_SSC_TF)
--			select_peripheral(PA(24), PERIPH_A, 0);	/* TF */
-+			pin_mask |= (1 << 24);	/* TF */
- 		if (flags & ATMEL_SSC_TD)
--			select_peripheral(PA(25), PERIPH_A, 0);	/* TD */
-+			pin_mask |= (1 << 25);	/* TD */
- 		if (flags & ATMEL_SSC_RD)
--			select_peripheral(PA(26), PERIPH_A, 0);	/* RD */
-+			pin_mask |= (1 << 26);	/* RD */
-+
-+		if (pin_mask > 0)
-+			select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-+
- 		break;
- 	case 1:
- 		pdev = &ssc1_device;
- 		if (flags & ATMEL_SSC_RF)
--			select_peripheral(PA(0), PERIPH_B, 0);	/* RF */
-+			pin_mask |= (1 << 0);	/* RF */
- 		if (flags & ATMEL_SSC_RK)
--			select_peripheral(PA(1), PERIPH_B, 0);	/* RK */
-+			pin_mask |= (1 << 1);	/* RK */
- 		if (flags & ATMEL_SSC_TK)
--			select_peripheral(PA(2), PERIPH_B, 0);	/* TK */
-+			pin_mask |= (1 << 2);	/* TK */
- 		if (flags & ATMEL_SSC_TF)
--			select_peripheral(PA(3), PERIPH_B, 0);	/* TF */
-+			pin_mask |= (1 << 3);	/* TF */
- 		if (flags & ATMEL_SSC_TD)
--			select_peripheral(PA(4), PERIPH_B, 0);	/* TD */
-+			pin_mask |= (1 << 4);	/* TD */
- 		if (flags & ATMEL_SSC_RD)
--			select_peripheral(PA(5), PERIPH_B, 0);	/* RD */
-+			pin_mask |= (1 << 5);	/* RD */
-+
-+		if (pin_mask > 0)
-+			select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
-+
- 		break;
- 	case 2:
- 		pdev = &ssc2_device;
- 		if (flags & ATMEL_SSC_TD)
--			select_peripheral(PB(13), PERIPH_A, 0);	/* TD */
-+			pin_mask |= (1 << 13);	/* TD */
- 		if (flags & ATMEL_SSC_RD)
--			select_peripheral(PB(14), PERIPH_A, 0);	/* RD */
-+			pin_mask |= (1 << 14);	/* RD */
- 		if (flags & ATMEL_SSC_TK)
--			select_peripheral(PB(15), PERIPH_A, 0);	/* TK */
-+			pin_mask |= (1 << 15);	/* TK */
- 		if (flags & ATMEL_SSC_TF)
--			select_peripheral(PB(16), PERIPH_A, 0);	/* TF */
-+			pin_mask |= (1 << 16);	/* TF */
- 		if (flags & ATMEL_SSC_RF)
--			select_peripheral(PB(17), PERIPH_A, 0);	/* RF */
-+			pin_mask |= (1 << 17);	/* RF */
- 		if (flags & ATMEL_SSC_RK)
--			select_peripheral(PB(18), PERIPH_A, 0);	/* RK */
-+			pin_mask |= (1 << 18);	/* RK */
-+
-+		if (pin_mask > 0)
-+			select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
-+
- 		break;
- 	default:
- 		return NULL;
-@@ -1745,14 +1814,15 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 		unsigned int cs, unsigned int extint)
- {
- 	static unsigned int extint_pin_map[4] __initdata = {
--		GPIO_PIN_PB(25),
--		GPIO_PIN_PB(26),
--		GPIO_PIN_PB(27),
--		GPIO_PIN_PB(28),
-+		(1 << 25),
-+		(1 << 26),
-+		(1 << 27),
-+		(1 << 28),
- 	};
- 	static bool common_pins_initialized __initdata = false;
- 	unsigned int extint_pin;
- 	int ret;
-+	u32 pin_mask;
- 
- 	if (extint >= ARRAY_SIZE(extint_pin_map))
- 		return -EINVAL;
-@@ -1766,7 +1836,8 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 		if (ret)
- 			return ret;
- 
--		select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
-+		/* NCS4   -> OE_N  */
-+		select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
- 		hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
- 		break;
- 	case 5:
-@@ -1776,7 +1847,8 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 		if (ret)
- 			return ret;
- 
--		select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
-+		/* NCS5   -> OE_N  */
-+		select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
- 		hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
- 		break;
- 	default:
-@@ -1784,14 +1856,17 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 	}
- 
- 	if (!common_pins_initialized) {
--		select_peripheral(PE(19), PERIPH_A, 0);	/* CFCE1  -> CS0_N */
--		select_peripheral(PE(20), PERIPH_A, 0);	/* CFCE2  -> CS1_N */
--		select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
--		select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
-+		pin_mask  = (1 << 19);	/* CFCE1  -> CS0_N */
-+		pin_mask |= (1 << 20);	/* CFCE2  -> CS1_N */
-+		pin_mask |= (1 << 23);	/* CFRNW  -> DIR   */
-+		pin_mask |= (1 << 24);	/* NWAIT  <- IORDY */
-+
-+		select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
-+
- 		common_pins_initialized = true;
- 	}
- 
--	at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
-+	select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
- 
- 	pdev->resource[1].start = EIM_IRQ_BASE + extint;
- 	pdev->resource[1].end = pdev->resource[1].start;
-@@ -1930,6 +2005,7 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
- {
- 	struct platform_device *pdev;
- 	struct ac97c_platform_data _data;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -1956,10 +2032,10 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
- 				sizeof(struct ac97c_platform_data)))
- 		goto fail;
- 
--	select_peripheral(PB(20), PERIPH_B, 0);	/* SDO	*/
--	select_peripheral(PB(21), PERIPH_B, 0);	/* SYNC	*/
--	select_peripheral(PB(22), PERIPH_B, 0);	/* SCLK	*/
--	select_peripheral(PB(23), PERIPH_B, 0);	/* SDI	*/
-+	pin_mask  = (1 << 20) | (1 << 21);	/* SDO & SYNC */
-+	pin_mask |= (1 << 22) | (1 << 23);	/* SCLK & SDI */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
- 
- 	/* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
- 	if (data->reset_pin != GPIO_PIN_NONE)
-@@ -2001,6 +2077,7 @@ static struct clk abdac0_sample_clk = {
- struct platform_device *__init at32_add_device_abdac(unsigned int id)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -2013,10 +2090,10 @@ struct platform_device *__init at32_add_device_abdac(unsigned int id)
- 				ARRAY_SIZE(abdac0_resource)))
- 		goto err_add_resources;
- 
--	select_peripheral(PB(20), PERIPH_A, 0);	/* DATA1	*/
--	select_peripheral(PB(21), PERIPH_A, 0);	/* DATA0	*/
--	select_peripheral(PB(22), PERIPH_A, 0);	/* DATAN1	*/
--	select_peripheral(PB(23), PERIPH_A, 0);	/* DATAN0	*/
-+	pin_mask  = (1 << 20) | (1 << 22);	/* DATA1 & DATAN1 */
-+	pin_mask |= (1 << 21) | (1 << 23);	/* DATA0 & DATAN0 */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
- 
- 	abdac0_pclk.dev = &pdev->dev;
- 	abdac0_sample_clk.dev = &pdev->dev;
-@@ -2073,7 +2150,7 @@ static struct clk gclk4 = {
- 	.index		= 4,
- };
- 
--struct clk *at32_clock_list[] = {
-+static __initdata struct clk *init_clocks[] = {
- 	&osc32k,
- 	&osc0,
- 	&osc1,
-@@ -2137,7 +2214,6 @@ struct clk *at32_clock_list[] = {
- 	&gclk3,
- 	&gclk4,
- };
--unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
- 
- void __init setup_platform(void)
- {
-@@ -2168,14 +2244,19 @@ void __init setup_platform(void)
- 	genclk_init_parent(&abdac0_sample_clk);
- 
- 	/*
--	 * Turn on all clocks that have at least one user already, and
--	 * turn off everything else. We only do this for module
--	 * clocks, and even though it isn't particularly pretty to
--	 * check the address of the mode function, it should do the
--	 * trick...
-+	 * Build initial dynamic clock list by registering all clocks
-+	 * from the array.
-+	 * At the same time, turn on all clocks that have at least one
-+	 * user already, and turn off everything else. We only do this
-+	 * for module clocks, and even though it isn't particularly
-+	 * pretty to  check the address of the mode function, it should
-+	 * do the trick...
- 	 */
--	for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
--		struct clk *clk = at32_clock_list[i];
-+	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
-+		struct clk *clk = init_clocks[i];
-+
-+		/* first, register clock */
-+		at32_clk_register(clk);
- 
- 		if (clk->users == 0)
- 			continue;
-@@ -2203,6 +2284,11 @@ void __init setup_platform(void)
- 	at32_init_pio(&pio4_device);
- }
- 
-+unsigned long at32_get_reset_cause(void)
-+{
-+	return pm_readl(RCAUSE);
-+}
-+
- struct gen_pool *sram_pool;
- 
- static int __init sram_init(void)
-diff --git a/arch/avr32/mach-at32ap/at32ap720x.c b/arch/avr32/mach-at32ap/at32ap720x.c
-new file mode 100644
-index 0000000..0cb675a
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/at32ap720x.c
-@@ -0,0 +1,2303 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/atmel_pdca.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dw_dmac.h>
-+#include <linux/errno.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm.h>
-+#include <linux/spinlock.h>
-+#include <linux/spi/atmel_spi.h>
-+#include <linux/spi/spi.h>
-+#include <video/atmel_lcdc.h>
-+#include <video/atmel_mpop.h>
-+
-+#include <asm/ast_regs.h>
-+#include <asm/atmel-mci.h>
-+
-+#include <mach/at32ap720x.h>
-+#include <mach/board.h>
-+#include <mach/hmatrix.h>
-+#include <mach/init.h>
-+#include <mach/pm.h>
-+#include <mach/portmux.h>
-+#include <mach/sram.h>
-+
-+#include "clock.h"
-+#include "gpio-v2.h"
-+#include "pm-v3.h"
-+#include "sdc.h"
-+
-+#define PBMEM(base)					\
-+	{						\
-+		.start		= base,			\
-+		.end		= base + 0x3ff,		\
-+		.flags		= IORESOURCE_MEM,	\
-+	}
-+#define IRQ(num)					\
-+	{						\
-+		.start		= num,			\
-+		.end		= num,			\
-+		.flags		= IORESOURCE_IRQ,	\
-+	}
-+
-+#define select_peripheral(port, pin_mask, periph, flags)	\
-+	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
-+			   GPIO_##periph, flags)
-+
-+#define DEV_CLK(_name, devname, bus, _index)			\
-+static struct clk devname##_##_name = {				\
-+	.name		= #_name,				\
-+	.dev		= &devname##_device.dev,		\
-+	.parent		= &bus##_clk,				\
-+	.mode		= bus##_clk_mode,			\
-+	.get_rate	= bus##_clk_get_rate,			\
-+	.index		= _index,				\
-+}
-+
-+static DEFINE_SPINLOCK(pm_lock);
-+
-+static unsigned long rcosc_get_rate(struct clk *clk)
-+{
-+	return 32768;
-+}
-+
-+static unsigned long osc_get_rate(struct clk *clk)
-+{
-+	return at32_board_osc_rates[clk->index];
-+}
-+
-+static void osc32_mode(struct clk *clk, int enabled)
-+{
-+	/* We never disable the 32 kHz oscillator */
-+	if (!enabled)
-+		return;
-+
-+	/* If it's already running, we're done. */
-+	if (pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY))
-+		return;
-+
-+	/* Enable it, unless someone did it for us already */
-+	if (!(sdc_readl(OSCCTRL32) & SDC_BIT(OSCCTRL32_OSC32EN))) {
-+		u32 value;
-+
-+		value = SDC_BF(OSCCTRL32_STARTUP, 5)
-+			| SDC_BF(OSCCTRL32_MODE, 0xd)
-+			| SDC_BIT(OSCCTRL32_OSC32EN);
-+
-+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0x55));
-+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0xaa));
-+	}
-+
-+	pr_info("Waiting for 32 kHz crystal oscillator to start...\n");
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY)))
-+		cpu_relax();
-+}
-+
-+static void oscn_mode(struct clk *clk, int enabled)
-+{
-+	unsigned int	i = clk->index;
-+	u32		mcctrl;
-+
-+	BUG_ON(i > 2);
-+
-+	/* Let's keep oscillators running for now... */
-+	if (!enabled)
-+		goto out;
-+
-+	/* If it's already running, we're done */
-+	if (pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i))
-+		goto out;
-+
-+	/* Enable it, unless someone did it for us already */
-+	mcctrl = pm_readl(MCCTRL);
-+	if (!(mcctrl & (PM_BIT(MCCTRL_OSC0EN) << i))) {
-+		/* TODO: Make OSC startup parameters configurable */
-+		pm_writel(OSCCTRL[i], PM_BF(OSCCTRLx_STARTUP, 5)
-+				| PM_BF(OSCCTRLx_MODE, 0xa));
-+		pm_writel(MCCTRL, mcctrl | (PM_BIT(MCCTRL_OSC0EN) << i));
-+	}
-+
-+	pr_debug("clk %s: waiting for clock to become ready...\n", clk->name);
-+	pr_debug("clk %s: MCCTRL=%08x OSCCTRL%u=%08x\n", clk->name,
-+			pm_readl(MCCTRL), i, pm_readl(OSCCTRL[i]));
-+
-+	while (!(pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i)))
-+		cpu_relax();
-+
-+out:
-+	pr_debug("clk %s: running\n", clk->name);
-+}
-+
-+static struct clk rcosc = {
-+	.name		= "rcosc",
-+	.get_rate	= rcosc_get_rate,
-+	.users		= 1,
-+};
-+static struct clk osc0 = {
-+	.name		= "osc0",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.users		= 1,
-+	.index		= 0,
-+};
-+static struct clk osc1 = {
-+	.name		= "osc1",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.index		= 1,
-+};
-+static struct clk osc2 = {
-+	.name		= "osc2",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.index		= 2,
-+};
-+static struct clk osc32 = {
-+	.name		= "osc32k",
-+	.get_rate	= osc_get_rate,
-+	.mode		= osc32_mode,
-+	.index		= 3,
-+};
-+
-+static void pll_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long timeout;
-+	unsigned int index = clk->index;
-+	u32 status;
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[index]);
-+
-+	if (enabled) {
-+		if (PM_BFEXT(PLLx_PLLMUL, ctrl) <= 1) {
-+			pr_debug("clk %s: failed to enable, rate not set\n",
-+					clk->name);
-+			return;
-+		}
-+
-+		ctrl |= PM_BIT(PLLx_PLLEN);
-+		pm_writel(PLL[index], ctrl);
-+
-+		pr_debug("clk %s: waiting for lock...\n", clk->name);
-+		for (timeout = 10000; timeout; timeout--) {
-+			status = pm_readl(POSCSR);
-+			if (status & (PM_BIT(POSCSR_LOCK0) << index))
-+				break;
-+			udelay(10);
-+		}
-+
-+		if (!(status & (PM_BIT(POSCSR_LOCK0) << index)))
-+			pr_err("clk %s: timeout waiting for lock\n",
-+					clk->name);
-+		else
-+			pr_debug("clk %s: running\n", clk->name);
-+	} else {
-+		ctrl &= ~PM_BIT(PLLx_PLLEN);
-+		pm_writel(PLL[index], ctrl);
-+		pr_debug("clk %s: stopped\n", clk->name);
-+	}
-+}
-+
-+
-+static unsigned long pll_get_rate(struct clk *clk)
-+{
-+	unsigned long rate;
-+	unsigned int div;
-+	unsigned int mul;
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[clk->index]);
-+
-+	div = PM_BFEXT(PLLx_PLLDIV, ctrl);
-+	mul = PM_BFEXT(PLLx_PLLMUL, ctrl);
-+
-+	rate = clk->parent->get_rate(clk->parent);
-+	if (div != 0)
-+		rate = (rate + div / 2) / div;
-+	else
-+		rate = rate * 2;
-+	rate *= mul;
-+
-+	if (ctrl & PM_BF(PLLx_PLLOPT, 4))
-+		rate = (rate + 1) / 2;
-+
-+	return rate;
-+}
-+
-+static long pll_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	unsigned long mul_best_fit = 0;
-+	unsigned long div;
-+	unsigned long div_min;
-+	unsigned long div_max;
-+	unsigned long div_best_fit = 0;
-+	unsigned long base;
-+	unsigned long fvco;
-+	unsigned long actual = 0;
-+	unsigned long rate_error_prev = ~0UL;
-+	u32 ctrl;
-+
-+	/* Rate must be between 25 MHz and 400 Mhz. */
-+	if (rate < 25000000UL || rate > 400000000UL)
-+		return -EINVAL;
-+
-+	base = clk->parent->get_rate(clk->parent);
-+
-+	/* PLL input frequency must be between 10 MHz and 200 MHz. */
-+	div_min = DIV_ROUND_UP(base, 200000000UL);
-+	div_max = base / 10000000UL;
-+
-+	if (div_max < div_min)
-+		return -EINVAL;
-+
-+	for (div = div_min; div <= div_max; div++) {
-+		unsigned long mul;
-+		unsigned long pll_in;
-+		unsigned long rate_error;
-+
-+		pll_in = (base + div / 2) / div;
-+		mul = (rate + pll_in / 2) / pll_in;
-+
-+		if (mul < 1)
-+			continue;
-+
-+		actual = pll_in * mul;
-+		rate_error = abs(actual - rate);
-+
-+		if (rate_error < rate_error_prev) {
-+			mul_best_fit = mul;
-+			div_best_fit = div;
-+			rate_error_prev = rate_error;
-+		}
-+
-+		if (rate_error == 0)
-+			break;
-+	}
-+
-+	if (div_best_fit == 0)
-+		return -EINVAL;
-+
-+	ctrl = 0;
-+	fvco = actual;
-+
-+	/*
-+	 * MUL=1 is not allowed. So we must double it and set the
-+	 * divide-by-two bit.
-+	 */
-+	if (mul_best_fit == 1) {
-+		ctrl |= PM_BF(PLLx_PLLOPT, 4);
-+		mul_best_fit *= 2;
-+		fvco = actual * 2;
-+	}
-+
-+	if (fvco > 200000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 3);
-+	else if (fvco > 100000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 2);
-+	else if (fvco > 50000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 1);
-+
-+	ctrl |= PM_BF(PLLx_PLLCOUNT, 31);
-+	ctrl |= PM_BF(PLLx_PLLMUL, mul_best_fit);
-+	ctrl |= PM_BF(PLLx_PLLDIV, div_best_fit);
-+	ctrl |= PM_BF(PLLx_PLLOSC, clk->parent->index);
-+
-+	if (apply) {
-+		if (actual != rate)
-+			return -EINVAL;
-+		if (clk->users > 0)
-+			return -EBUSY;
-+		pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
-+				clk->name, rate, actual);
-+		pm_writel(PLL[clk->index], ctrl);
-+	}
-+
-+	return actual;
-+}
-+
-+static int pll_set_parent(struct clk *clk, struct clk *parent)
-+{
-+	unsigned int index = clk->index;
-+	u32 ctrl;
-+
-+	if (clk->users > 0)
-+		return -EBUSY;
-+
-+	ctrl = pm_readl(PLL[index]);
-+	BUG_ON(ctrl & PM_BIT(PLLx_PLLEN));
-+
-+	ctrl = PM_BFINS(PLLx_PLLOSC, parent->index, ctrl);
-+	pm_writel(PLL[index], ctrl);
-+
-+	clk->parent = parent;
-+
-+	return 0;
-+}
-+
-+static struct clk pll0 = {
-+	.name		= "pll0",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 1,
-+	.index		= 0,
-+};
-+static struct clk pll1 = {
-+	.name		= "pll1",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 0,
-+	.index		= 1,
-+};
-+static struct clk pll2 = {
-+	.name		= "pll2",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 0,
-+	.index		= 2,
-+};
-+
-+/*
-+ * The main clock can be either rcosc, osc0 or pll0.  The boot loader
-+ * may have chosen one for us, so we don't really know which one until
-+ * we have a look at the PM registers.
-+ */
-+static struct clk *main_clock;
-+
-+/*
-+ * Synchronous clocks are generated from the main clock. The clocks
-+ * must satisfy the constraint
-+ *   fCPU >= fHSB >= fPB
-+ * i.e. each clock must not be faster than its parent.
-+ */
-+static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
-+{
-+	return main_clock->get_rate(main_clock) >> shift;
-+};
-+
-+static void cpu_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(CPUMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(CPUMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long cpu_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_CPUDIV))
-+		shift = PM_BFEXT(CKSEL_CPUSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	u32 control;
-+	unsigned long parent_rate, child_div, actual_rate, div;
-+
-+	parent_rate = clk->parent->get_rate(clk->parent);
-+	control = pm_readl(CKSEL);
-+
-+	if (control & PM_BIT(CKSEL_HSBDIV))
-+		child_div = 1 << (PM_BFEXT(CKSEL_HSBSEL, control) + 1);
-+	else
-+		child_div = 1;
-+
-+	if (rate > 3 * (parent_rate / 4) || child_div == 1) {
-+		actual_rate = parent_rate;
-+		control &= ~PM_BIT(CKSEL_CPUDIV);
-+	} else {
-+		unsigned int cpusel;
-+		div = (parent_rate + rate / 2) / rate;
-+		if (div > child_div)
-+			div = child_div;
-+		cpusel = (div > 1) ? (fls(div) - 2) : 0;
-+		control = PM_BIT(CKSEL_CPUDIV)
-+			| PM_BFINS(CKSEL_CPUSEL, cpusel, control);
-+		actual_rate = parent_rate / (1 << (cpusel + 1));
-+	}
-+
-+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+			clk->name, rate, actual_rate);
-+
-+	if (apply) {
-+		while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_CKRDY)))
-+			cpu_relax();
-+
-+		pm_writel(CKSEL, control);
-+	}
-+
-+	return actual_rate;
-+}
-+
-+static void hsb_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(HSBMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(HSBMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long hsb_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_HSBDIV))
-+		shift = PM_BFEXT(CKSEL_HSBSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pba_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(PBAMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(PBAMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pba_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_PBADIV))
-+		shift = PM_BFEXT(CKSEL_PBASEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pbb_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(PBBMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(PBBMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pbb_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_PBBDIV))
-+		shift = PM_BFEXT(CKSEL_PBBSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static struct clk cpu_clk = {
-+	.name		= "cpu",
-+	.get_rate	= cpu_clk_get_rate,
-+	.set_rate	= cpu_clk_set_rate,
-+	.users		= 1,
-+};
-+static struct clk hsb_clk = {
-+	.name		= "hsb",
-+	.parent		= &cpu_clk,
-+	.get_rate	= hsb_clk_get_rate,
-+};
-+static struct clk pba_clk = {
-+	.name		= "pba",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pba_clk_get_rate,
-+	.users		= 1,
-+	.index		= 1,
-+};
-+static struct clk pbb_clk = {
-+	.name		= "pbb",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 2,
-+};
-+static struct clk pbc_clk = {
-+	.name		= "pbc",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 3,
-+};
-+
-+/* --------------------------------------------------------------------
-+ *  Generic Clocks
-+ * -------------------------------------------------------------------- */
-+
-+/* Mapping from GCCTRL:OSCSEL values to parent clocks */
-+static struct clk *const genclk_parent[] = {
-+	&rcosc,
-+	&osc32,
-+	&osc0,
-+	&osc1,
-+	&osc2,
-+	&pll0,
-+	&pll1,
-+	&pll2,
-+	&cpu_clk,
-+	&hsb_clk,
-+	&pba_clk,
-+	&pbb_clk,
-+};
-+
-+#define NR_GENERIC_CLOCKS	8
-+
-+static void genclk_mode(struct clk *clk, int enabled)
-+{
-+	u32 control;
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	if (enabled)
-+		control |= PM_BIT(GCCTRL_CEN);
-+	else
-+		control &= PM_BIT(GCCTRL_CEN);
-+	pm_writel(GCCTRL[clk->index], control);
-+}
-+
-+static unsigned long genclk_get_rate(struct clk *clk)
-+{
-+	u32 control;
-+	unsigned long div = 1;
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	if (control & PM_BIT(GCCTRL_DIVEN))
-+		div = 2 * (PM_BFEXT(GCCTRL_DIV, control) + 1);
-+
-+	return clk->parent->get_rate(clk->parent) / div;
-+}
-+
-+static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	unsigned long	parent_rate;
-+	unsigned long	actual_rate;
-+	unsigned long	div;
-+	u32		control;
-+
-+	parent_rate = clk->parent->get_rate(clk->parent);
-+	control = pm_readl(GCCTRL[clk->index]);
-+
-+	if (rate > 3 * parent_rate / 4) {
-+		actual_rate = parent_rate;
-+		control &= ~PM_BIT(GCCTRL_DIVEN);
-+	} else {
-+		div = (parent_rate + rate) / (2 * rate) - 1;
-+		control = PM_BFINS(GCCTRL_DIV, div, control)
-+				| PM_BIT(GCCTRL_DIVEN);
-+		actual_rate = parent_rate / (2 * (div + 1));
-+	}
-+
-+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+			clk->name, rate, actual_rate);
-+
-+	if (apply)
-+		pm_writel(GCCTRL[clk->index], control);
-+
-+	return actual_rate;
-+}
-+
-+static int genclk_set_parent(struct clk *clk, struct clk *parent)
-+{
-+	unsigned int	i;
-+	u32		control;
-+
-+	pr_debug("clk %s: new parent %s (was %s)\n",
-+			clk->name, parent->name,
-+			clk->parent ? clk->parent->name : "<none>");
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+
-+	for (i = 0; i < ARRAY_SIZE(genclk_parent); i++) {
-+		if (parent == genclk_parent[i]) {
-+			control = PM_BFINS(GCCTRL_OSCSEL, i, control);
-+			break;
-+		}
-+	}
-+
-+	if (i >= ARRAY_SIZE(genclk_parent))
-+		return -EINVAL;
-+
-+	pm_writel(GCCTRL[clk->index], control);
-+	clk->parent = parent;
-+
-+	return 0;
-+}
-+
-+#define DEFINE_GCLK(_name, i)				\
-+	static struct clk _name = {			\
-+		.name		= #_name,		\
-+		.mode		= genclk_mode,		\
-+		.get_rate	= genclk_get_rate,	\
-+		.set_rate	= genclk_set_rate,	\
-+		.set_parent	= genclk_set_parent,	\
-+		.index		= i,			\
-+	}
-+
-+DEFINE_GCLK(gclk0, 0);
-+DEFINE_GCLK(gclk1, 1);
-+DEFINE_GCLK(gclk2, 2);
-+DEFINE_GCLK(gclk3, 3);
-+DEFINE_GCLK(gclk4, 4);
-+DEFINE_GCLK(gclk5, 5);
-+
-+static void __init genclk_init_parent(struct clk *clk)
-+{
-+	unsigned int	parent;
-+	u32		control;
-+
-+	BUG_ON(clk->index > NR_GENERIC_CLOCKS);
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	parent = PM_BFEXT(GCCTRL_OSCSEL, control);
-+	if (parent >= ARRAY_SIZE(genclk_parent)) {
-+		/* Current parent is invalid. Reset to a sane value */
-+		parent = 0;
-+		control = PM_BF(GCCTRL_OSCSEL, parent);
-+	}
-+
-+	clk->parent = genclk_parent[parent];
-+}
-+
-+
-+/* --------------------------------------------------------------------
-+ *  System peripherals
-+ * -------------------------------------------------------------------- */
-+static struct dw_dma_platform_data dw_dmac0_data = {
-+	.nr_channels	= 4,
-+};
-+static struct pdca_pdata pdca_data = {
-+	.nr_channels	= 20,
-+};
-+
-+static struct resource intc_resource[] = {
-+	PBMEM(0xffd00000),
-+};
-+static struct resource pm_resource[] = {
-+	PBMEM(0xffd00400),
-+	IRQ(10),
-+};
-+static struct resource sdc_resource[] = {
-+	PBMEM(0xffd00800),
-+	IRQ(45),
-+};
-+static struct resource ast0_resource[] = {
-+	PBMEM(0xffd00c00),
-+	IRQ(11),
-+};
-+static struct resource ast1_resource[] = {
-+	PBMEM(0xffd01000),
-+	IRQ(12),
-+};
-+static struct resource wdt_resource[] = {
-+	PBMEM(0xffd01400),
-+};
-+static struct resource gpio_resource[] = {
-+	PBMEM(0xffd02000),
-+	{
-+		.start	= 16,
-+		.end	= 19,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+static struct resource pdca_resource[] = {
-+	{
-+		.start	= 0xffe00000,
-+		.end	= 0xffe01fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(1),
-+};
-+static struct resource smc_resource[] = {
-+	PBMEM(0xffe04400),
-+};
-+static struct resource dw_dmac0_resource[] = {
-+	{
-+		.start	= 0xff100000,
-+		.end	= 0xff1003ff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(5),
-+};
-+
-+struct platform_device at32_intc0_device = {
-+	.name		= "intc",
-+	.resource	= intc_resource,
-+	.num_resources	= ARRAY_SIZE(intc_resource),
-+};
-+static struct platform_device pm_device = {
-+	.name		= "pm",
-+	.resource	= pm_resource,
-+	.num_resources	= ARRAY_SIZE(pm_resource),
-+};
-+static struct platform_device sdc_device = {
-+	.name		= "sdc",
-+	.resource	= sdc_resource,
-+	.num_resources	= ARRAY_SIZE(sdc_resource),
-+};
-+static struct platform_device ast0_device = {
-+	.name		= "rtc-ast",
-+	.id		= 0,
-+	.resource	= ast0_resource,
-+	.num_resources	= ARRAY_SIZE(ast0_resource),
-+};
-+static struct platform_device ast1_device = {
-+	.name		= "timer-ast",
-+	.id		= 1,
-+	.resource	= ast1_resource,
-+	.num_resources	= ARRAY_SIZE(ast1_resource),
-+};
-+static struct platform_device wdt_device = {
-+	.name		= "at32_wdt",
-+	.id		= 0,
-+	.resource	= wdt_resource,
-+	.num_resources	= ARRAY_SIZE(wdt_resource),
-+};
-+static struct platform_device gpio_device = {
-+	.name		= "gpio",
-+	.id		= 0,
-+	.resource	= gpio_resource,
-+	.num_resources	= ARRAY_SIZE(gpio_resource),
-+};
-+static struct platform_device pdca_device = {
-+	.dev.platform_data = &pdca_data,
-+	.name		= "atmel_pdca",
-+	.id		= 0,
-+	.resource	= pdca_resource,
-+	.num_resources	= ARRAY_SIZE(pdca_resource),
-+};
-+static struct platform_device smc_device = {
-+	.name		= "smc",
-+	.id		= 0,
-+	.resource	= smc_resource,
-+	.num_resources	= ARRAY_SIZE(smc_resource),
-+};
-+static struct platform_device dw_dmac0_device = {
-+	.dev.platform_data = &dw_dmac0_data,
-+	.name		= "dw_dmac",
-+	.id		= 0,
-+	.resource	= dw_dmac0_resource,
-+	.num_resources	= ARRAY_SIZE(dw_dmac0_resource),
-+};
-+
-+DEV_CLK(pclk, at32_intc0, pba, 0);
-+DEV_CLK(pclk, pm, pba, 1);
-+DEV_CLK(pclk, sdc, pba, 2);
-+DEV_CLK(pclk, ast0, pba, 3);
-+DEV_CLK(pclk, ast1, pba, 4);
-+DEV_CLK(pclk, wdt, pba, 5);
-+DEV_CLK(pclk, gpio, pba, 8);
-+DEV_CLK(hclk, pdca, hsb, 9);
-+DEV_CLK(pclk, pdca, pbb, 0);
-+DEV_CLK(pclk, smc, pbb, 5);
-+DEV_CLK(hclk, dw_dmac0, hsb, 10);
-+
-+static struct clk ebi_hclk = {
-+	.name		= "ebi_hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.users		= 1,
-+};
-+static struct clk hramc_clk = {
-+	.name		= "hramc",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 4,
-+};
-+static struct clk sdramc_clk = {
-+	.name		= "sdramc_clk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 6,
-+};
-+
-+static int __init system_device_init(void)
-+{
-+	platform_device_register(&at32_intc0_device);
-+	platform_device_register(&pm_device);
-+	platform_device_register(&sdc_device);
-+	platform_device_register(&ast0_device);
-+	platform_device_register(&ast1_device);
-+	platform_device_register(&wdt_device);
-+	platform_device_register(&gpio_device);
-+	platform_device_register(&pdca_device);
-+	platform_device_register(&smc_device);
-+	platform_device_register(&dw_dmac0_device);
-+
-+	return 0;
-+}
-+core_initcall(system_device_init);
-+
-+/* --------------------------------------------------------------------
-+ * HMATRIX
-+ * -------------------------------------------------------------------- */
-+
-+struct clk at32_hmatrix_clk = {
-+	.name		= "hmatrix_clk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 8,
-+	.users		= 0,
-+};
-+
-+/* --------------------------------------------------------------------
-+ *  USART
-+ * -------------------------------------------------------------------- */
-+
-+static struct atmel_uart_data atmel_usart0_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart0_resource[] = {
-+	PBMEM(0xffd03000),
-+	IRQ(24),
-+};
-+static struct platform_device atmel_usart0_device = {
-+	.name		= "atmel_usart",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data	= &atmel_usart0_data,
-+	},
-+	.resource	= atmel_usart0_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart0_resource),
-+};
-+DEV_CLK(usart, atmel_usart0, pba, 9);
-+
-+static struct atmel_uart_data atmel_usart1_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart1_resource[] = {
-+	PBMEM(0xffd03400),
-+	IRQ(25),
-+};
-+static struct platform_device atmel_usart1_device = {
-+	.name		= "atmel_usart",
-+	.id		= 1,
-+	.dev		= {
-+		.platform_data	= &atmel_usart1_data,
-+	},
-+	.resource	= atmel_usart1_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart1_resource),
-+};
-+DEV_CLK(usart, atmel_usart1, pba, 10);
-+
-+static struct atmel_uart_data atmel_usart2_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart2_resource[] = {
-+	PBMEM(0xffd03800),
-+	IRQ(26),
-+};
-+static struct platform_device atmel_usart2_device = {
-+	.name		= "atmel_usart",
-+	.id		= 2,
-+	.dev		= {
-+		.platform_data	= &atmel_usart2_data,
-+	},
-+	.resource	= atmel_usart2_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart2_resource),
-+};
-+DEV_CLK(usart, atmel_usart2, pba, 11);
-+
-+static struct atmel_uart_data atmel_usart3_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart3_resource[] = {
-+	PBMEM(0xffd03c00),
-+	IRQ(27),
-+};
-+static struct platform_device atmel_usart3_device = {
-+	.name		= "atmel_usart",
-+	.id		= 3,
-+	.dev		= {
-+		.platform_data	= &atmel_usart3_data,
-+	},
-+	.resource	= atmel_usart3_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart3_resource),
-+};
-+DEV_CLK(usart, atmel_usart3, pba, 12);
-+
-+static struct atmel_uart_data atmel_usart4_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart4_resource[] = {
-+	PBMEM(0xffd04000),
-+	IRQ(28),
-+};
-+static struct platform_device atmel_usart4_device = {
-+	.name		= "atmel_usart",
-+	.id		= 4,
-+	.dev		= {
-+		.platform_data	= &atmel_usart4_data,
-+	},
-+	.resource	= atmel_usart4_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart4_resource),
-+};
-+DEV_CLK(usart, atmel_usart4, pba, 13);
-+
-+static struct atmel_uart_data atmel_usart5_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart5_resource[] = {
-+	PBMEM(0xffd04400),
-+	IRQ(29),
-+};
-+static struct platform_device atmel_usart5_device = {
-+	.name		= "atmel_usart",
-+	.id		= 5,
-+	.dev		= {
-+		.platform_data	= &atmel_usart5_data,
-+	},
-+	.resource	= atmel_usart5_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart5_resource),
-+};
-+DEV_CLK(usart, atmel_usart5, pba, 14);
-+
-+static void __init configure_usart0_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PB, (1 << 14) | (1 << 15), PERIPH_B, 0);
-+}
-+
-+static void __init configure_usart1_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 8) | (1 << 9), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart2_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 16) | (1 << 17), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart3_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PC, (1 << 10) | (1 << 11), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart4_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 14) | (1 << 15), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart5_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PA, (1 << 22) | (1 << 23), PERIPH_A, 0);
-+}
-+
-+static struct platform_device *__initdata at32_usarts[6];
-+
-+void __init at32_map_usart(unsigned int hw_id, unsigned int line)
-+{
-+	struct platform_device *pdev;
-+
-+	switch (hw_id) {
-+	case 0:
-+		pdev = &atmel_usart0_device;
-+		configure_usart0_pins();
-+		break;
-+	case 1:
-+		pdev = &atmel_usart1_device;
-+		configure_usart1_pins();
-+		break;
-+	case 2:
-+		pdev = &atmel_usart2_device;
-+		configure_usart2_pins();
-+		break;
-+	case 3:
-+		pdev = &atmel_usart3_device;
-+		configure_usart3_pins();
-+		break;
-+	case 4:
-+		pdev = &atmel_usart4_device;
-+		configure_usart4_pins();
-+		break;
-+	case 5:
-+		pdev = &atmel_usart5_device;
-+		configure_usart5_pins();
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	if (PXSEG(pdev->resource[0].start) == P4SEG) {
-+		/* Addresses in the P4 segment are permanently mapped 1:1 */
-+		struct atmel_uart_data *data = pdev->dev.platform_data;
-+		data->regs = (void __iomem __force *)pdev->resource[0].start;
-+	}
-+
-+	pdev->id = line;
-+	at32_usarts[line] = pdev;
-+}
-+
-+struct platform_device *__init at32_add_device_usart(unsigned int id)
-+{
-+	platform_device_register(at32_usarts[id]);
-+	return at32_usarts[id];
-+}
-+
-+struct platform_device *atmel_default_console_device;
-+
-+void __init at32_setup_serial_console(unsigned int usart_id)
-+{
-+	atmel_default_console_device = at32_usarts[usart_id];
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  Ethernet
-+ * -------------------------------------------------------------------- */
-+
-+static u64 macb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource macb0_resource[] __initdata = {
-+	PBMEM(0xffe04000),
-+	IRQ(8),
-+};
-+static struct clk macb0_hclk = {
-+	.name		= "hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 8,
-+};
-+static struct clk macb0_pclk = {
-+	.name		= "pclk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 4,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
-+{
-+	struct platform_device *pdev;
-+	u32 pin_mask_a;
-+	u32 pin_mask_c;
-+
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("macb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	if (platform_device_add_resources(pdev, macb0_resource,
-+				ARRAY_SIZE(macb0_resource)))
-+		goto out_free_pdev;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct eth_platform_data)))
-+		goto out_free_pdev;
-+
-+	pin_mask_a  = (1 << 4);  /* RXDV */
-+	pin_mask_c  = (1 << 10); /* MDC  */
-+	pin_mask_c |= (1 << 11); /* MDIO */
-+	pin_mask_c |= (1 << 12); /* TXCK */
-+	pin_mask_c |= (1 << 14); /* RXD0 */
-+	pin_mask_c |= (1 << 15); /* RXD1 */
-+	pin_mask_c |= (1 << 16); /* RXER */
-+	pin_mask_c |= (1 << 18); /* TXEN */
-+	pin_mask_c |= (1 << 19); /* TXD0 */
-+	pin_mask_c |= (1 << 20); /* TXD1 */
-+
-+	if (!data->is_rmii) {
-+		pin_mask_a |= (1<<0);  /* COL  */
-+		pin_mask_a |= (1<<1);  /* RXD2 */
-+		pin_mask_a |= (1<<2);  /* RXD3 */
-+		pin_mask_a |= (1<<3);  /* RXCK */
-+		pin_mask_a |= (1<<5);  /* TXER */
-+		pin_mask_a |= (1<<6);  /* TXD2 */
-+		pin_mask_a |= (1<<7);  /* TXD3 */
-+		pin_mask_c |= (1<<13); /* CRS  */
-+		pin_mask_c |= (1<<17); /* SPD  */
-+	}
-+
-+	select_peripheral(PA, pin_mask_a, PERIPH_B, 0);
-+	select_peripheral(PC, pin_mask_c, PERIPH_C, 0);
-+
-+	pdev->dev.dma_mask = &macb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	macb0_hclk.dev = &pdev->dev;
-+	macb0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+
-+	return pdev;
-+
-+out_free_pdev:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * SPI
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_spi_resource[][2] __initdata = {
-+	{
-+		PBMEM(0xffe05400),
-+		IRQ(36),
-+	}, {
-+		PBMEM(0xffe05800),
-+		IRQ(37),
-+	}, {
-+		PBMEM(0xffe05c00),
-+		IRQ(38),
-+	}, {
-+		PBMEM(0xffe06000),
-+		IRQ(39),
-+	}
-+};
-+static struct clk atmel_spi_clk[] = {
-+	{
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 9,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 10,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 11,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 12,
-+	}
-+};
-+static int __initdata atmel_spi_pins[][4] = {
-+	{
-+		/* SPI0 */
-+		GPIO_PIN_PB(3), GPIO_PIN_PB(4),
-+		GPIO_PIN_PB(5), GPIO_PIN_PB(6),
-+	}, {
-+		/* SPI1 */
-+		GPIO_PIN_PB(4), -1, -1, -1,
-+	}, {
-+		/* SPI2 */
-+		GPIO_PIN_PA(28), -1, -1, -1,
-+	}, {
-+		/* SPI3 */
-+		GPIO_PIN_PA(27), GPIO_PIN_PA(20),
-+		GPIO_PIN_PA(29), GPIO_PIN_PA(30),
-+	}
-+};
-+
-+
-+static void __init at32_spi_setup_dw_dma(unsigned int id,
-+		struct atmel_spi_pdata *pdata)
-+{
-+	struct dw_dma_slave	*rx_dws;
-+	struct dw_dma_slave	*tx_dws;
-+
-+	if (pdata->rx_dma_slave)
-+		rx_dws = kmemdup(to_dw_dma_slave(pdata->rx_dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		rx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	if (pdata->tx_dma_slave)
-+		tx_dws = kmemdup(to_dw_dma_slave(pdata->tx_dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		tx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	rx_dws->slave.dma_dev = tx_dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	rx_dws->slave.reg_width = tx_dws->slave.reg_width
-+		= DMA_SLAVE_WIDTH_8BIT;
-+
-+	rx_dws->cfg_hi = DWC_CFGH_SRC_PER(2);
-+	tx_dws->cfg_hi = DWC_CFGH_DST_PER(3);
-+	rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+	tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	pdata->rx_dma_slave = &rx_dws->slave;
-+	pdata->tx_dma_slave = &tx_dws->slave;
-+}
-+
-+static void __init at32_spi_setup_pdca(unsigned int id,
-+		struct atmel_spi_pdata *pdata)
-+{
-+	struct pdca_slave	*rx_pslave;
-+	struct pdca_slave	*tx_pslave;
-+
-+	if (pdata->rx_dma_slave)
-+		rx_pslave = kmemdup(dma_to_pdca_slave(pdata->rx_dma_slave),
-+				sizeof(struct pdca_slave), GFP_KERNEL);
-+	else
-+		rx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
-+	if (pdata->tx_dma_slave)
-+		tx_pslave = kmemdup(dma_to_pdca_slave(pdata->tx_dma_slave),
-+				sizeof(struct pdca_slave), GFP_KERNEL);
-+	else
-+		tx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
-+
-+	rx_pslave->slave.dma_dev = &pdca_device.dev;
-+	tx_pslave->slave.dma_dev = &pdca_device.dev;
-+	rx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
-+	tx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
-+
-+	rx_pslave->tx_periph_id = -1;
-+	tx_pslave->rx_periph_id = -1;
-+
-+	switch (id) {
-+	case 1:
-+		rx_pslave->rx_periph_id = 6;
-+		tx_pslave->tx_periph_id = 17;
-+		break;
-+	case 2:
-+		rx_pslave->rx_periph_id = 7;
-+		tx_pslave->tx_periph_id = 18;
-+		break;
-+	case 3:
-+		rx_pslave->rx_periph_id = 8;
-+		tx_pslave->tx_periph_id = 19;
-+		break;
-+	}
-+
-+	pdata->rx_dma_slave = &rx_pslave->slave;
-+	pdata->tx_dma_slave = &tx_pslave->slave;
-+}
-+
-+static void __init
-+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
-+		unsigned int n, const int *pins)
-+{
-+	unsigned int	mode;
-+	unsigned int	cs;
-+	int		pin;
-+
-+	for (; n; n--, b++) {
-+		b->bus_num = bus_num;
-+		cs = b->chip_select;
-+		if (cs >= 4 || !gpio_is_valid(pins[cs]))
-+			continue;
-+
-+		pin = (int)b->controller_data;
-+		if (!pin || !gpio_is_valid(pin)) {
-+			pin = pins[cs];
-+			b->controller_data = (void *)pin;
-+		}
-+
-+		mode = AT32_GPIOF_OUTPUT;
-+		if (!(b->mode & SPI_CS_HIGH))
-+			mode |= AT32_GPIOF_HIGH;
-+		at32_select_gpio(pin, mode);
-+	}
-+}
-+
-+struct platform_device *__init at32_add_device_spi(unsigned int id,
-+		struct spi_board_info *b, unsigned int n)
-+{
-+	struct atmel_spi_pdata	pdata;
-+	struct platform_device	*pdev;
-+
-+	BUILD_BUG_ON(ARRAY_SIZE(atmel_spi_resource)
-+			!= ARRAY_SIZE(atmel_spi_clk));
-+
-+	if (id >= ARRAY_SIZE(atmel_spi_resource))
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_spi", id);
-+	if (!pdev)
-+		goto fail;
-+
-+	if (platform_device_add_resources(pdev, atmel_spi_resource[id],
-+				ARRAY_SIZE(atmel_spi_resource[id])))
-+		goto fail;
-+
-+	memset(&pdata, 0, sizeof(struct atmel_spi_pdata));
-+
-+	if (id == 0)
-+		at32_spi_setup_dw_dma(id, &pdata);
-+	else
-+		at32_spi_setup_pdca(id, &pdata);
-+	pdata.rx_dma_slave->dev = pdata.tx_dma_slave->dev = &pdev->dev;
-+
-+	if (platform_device_add_data(pdev, &pdata,
-+				sizeof(struct atmel_spi_pdata)))
-+		goto fail;
-+
-+	switch (id) {
-+	case 0:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PB, (1 << 1), PERIPH_A, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PB, (1 << 0) | (1 << 2), PERIPH_A, 0);
-+
-+		at32_spi_setup_slaves(0, b, n, atmel_spi_pins[0]);
-+		break;
-+
-+	case 1:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PB, (1 << 7), PERIPH_B, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PB, (1 << 6) | (1 << 5), PERIPH_B, 0);
-+
-+		at32_spi_setup_slaves(1, b, n, atmel_spi_pins[1]);
-+		break;
-+
-+	case 2:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PA, (1 << 30), PERIPH_B, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PA, (1 << 31) || (1 << 29), PERIPH_B, 0);
-+
-+		at32_spi_setup_slaves(2, b, n, atmel_spi_pins[2]);
-+		break;
-+
-+	case 3:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PA, (1 << 25), PERIPH_A, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PA, (1 << 24) | (1 << 26), PERIPH_A, 0);
-+
-+		at32_spi_setup_slaves(3, b, n, atmel_spi_pins[3]);
-+		break;
-+
-+	default:
-+		goto fail;
-+	}
-+
-+	atmel_spi_clk[id].dev = &pdev->dev;
-+	spi_register_board_info(b, n);
-+	platform_device_add(pdev);
-+
-+	return pdev;
-+
-+fail:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * MMC
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_mci0_resource[] __initdata = {
-+	PBMEM(0xfff00000),
-+	IRQ(43),
-+};
-+/* MCI is on the PBC bus, but it is controlled by the PBBMASK register */
-+static struct clk atmel_mci0_pclk = {
-+	.name		= "mci_clk",
-+	.parent		= &pbc_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 16,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
-+{
-+	struct platform_device		*pdev;
-+	struct dw_dma_slave		*dws;
-+	u32 pin_mask_1 = 0;
-+	u32 pin_mask_2 = 0;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	/* Must have at least one usable slot */
-+	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_mci", id);
-+	if (!pdev)
-+		goto fail;
-+
-+	if (platform_device_add_resources(pdev, atmel_mci0_resource,
-+				ARRAY_SIZE(atmel_mci0_resource)))
-+		goto fail;
-+
-+	if (data->dma_slave)
-+		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	dws->slave.dev = &pdev->dev;
-+	dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
-+	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
-+				| DWC_CFGH_DST_PER(1));
-+	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	data->dma_slave = &dws->slave;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct mci_platform_data)))
-+		goto fail;
-+
-+	switch (data->slot[0].bus_width) {
-+	case 8:
-+		pin_mask_1 |= (1 << 20); /* DATA4 */
-+		pin_mask_1 |= (1 << 21); /* DATA5 */
-+		pin_mask_1 |= (1 << 22); /* DATA6 */
-+		pin_mask_1 |= (1 << 23); /* DATA7 */
-+		/* fall through */
-+	case 4:
-+		pin_mask_2 |= (1 << 19); /* DATA1 */
-+		pin_mask_2 |= (1 << 20); /* DATA2 */
-+		pin_mask_2 |= (1 << 21); /* DATA3 */
-+		/* fall through */
-+	case 1:
-+		pin_mask_2 |= (1 << 18); /* DATA0 */
-+		pin_mask_2 |= (1 << 17); /* CMD   */
-+
-+		select_peripheral(PA, pin_mask_1, PERIPH_D, AT32_GPIOF_PULLUP);
-+		select_peripheral(PB, pin_mask_2, PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PB, (1 << 16),  PERIPH_A, 0);	/* CLK */
-+
-+		if (gpio_is_valid(data->slot[0].detect_pin))
-+			at32_select_gpio(data->slot[0].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[0].wp_pin))
-+			at32_select_gpio(data->slot[0].wp_pin, 0);
-+
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	pin_mask_1 = 0;
-+
-+	switch (data->slot[1].bus_width) {
-+	case 8:
-+		pin_mask_1 |= (1 << 9); /* DATA7 */
-+		pin_mask_1 |= (1 << 8); /* DATA6 */
-+		pin_mask_1 |= (1 << 7); /* DATA5 */
-+		pin_mask_1 |= (1 << 6); /* DATA4 */
-+		/* fall through */
-+	case 4:
-+		pin_mask_1 |= (1 << 5); /* DATA3 */
-+		pin_mask_1 |= (1 << 4); /* DATA2 */
-+		pin_mask_1 |= (1 << 3); /* DATA1 */
-+		/* fall through */
-+	case 1:
-+		pin_mask_1 |= (1 << 2); /* DATA0 */
-+		pin_mask_1 |= (1 << 1); /* CMD   */
-+
-+		select_peripheral(PC, pin_mask_1, PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PC, (1 << 0),   PERIPH_A, 0);	/* CLK */
-+
-+		if (gpio_is_valid(data->slot[1].detect_pin))
-+			at32_select_gpio(data->slot[1].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[1].wp_pin))
-+			at32_select_gpio(data->slot[1].wp_pin, 0);
-+
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	atmel_mci0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+fail:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  LCDC
-+ * -------------------------------------------------------------------- */
-+static u64 atmel_lcdfb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource atmel_lcdfb0_resource[] __initdata = {
-+	{
-+		.start	= 0xff000000,
-+		.end	= 0xff000fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(3),
-+	{
-+		/* Placeholder for pre-allocated fb memory */
-+		.start	= 0x00000000,
-+		.end	= 0x00000000,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct clk atmel_lcdfb0_hck1 = {
-+	.name		= "hck1",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 7,
-+};
-+static struct clk atmel_lcdfb0_pixclk = {
-+	.name		= "lcdc_clk",
-+	.mode		= genclk_mode,
-+	.get_rate	= genclk_get_rate,
-+	.set_rate	= genclk_set_rate,
-+	.set_parent	= genclk_set_parent,
-+	.index		= 6,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-+		unsigned long fbmem_start, unsigned long fbmem_len,
-+		u64 pin_mask)
-+{
-+	struct {
-+		struct atmel_lcdfb_info	info;
-+		struct fb_monspecs	monspecs;
-+		struct fb_videomode	modedb[0];
-+	} *all_data;
-+	struct platform_device	*pdev;
-+	unsigned int		data_size;
-+	unsigned int		modedb_size;
-+	unsigned int		num_resources;
-+	int			ret;
-+
-+	if (id > 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_lcdfb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	num_resources = ARRAY_SIZE(atmel_lcdfb0_resource);
-+	if (fbmem_len) {
-+		atmel_lcdfb0_resource[num_resources - 1].start = fbmem_start;
-+		atmel_lcdfb0_resource[num_resources - 1].end
-+			= fbmem_start + fbmem_len - 1;
-+	} else {
-+		num_resources--;
-+	}
-+
-+	if (platform_device_add_resources(pdev, atmel_lcdfb0_resource,
-+				num_resources))
-+		goto error;
-+
-+	/*
-+	 * Allocate all data -- info struct, monspecs and modedb -- in
-+	 * a single chunk.
-+	 */
-+	modedb_size = data->default_monspecs->modedb_len
-+			* sizeof(struct fb_videomode);
-+	data_size = sizeof(*all_data) + modedb_size;
-+	all_data = kmalloc(data_size, GFP_KERNEL);
-+	if (!all_data)
-+		goto error;
-+
-+	memcpy(&all_data->info, data, sizeof(struct atmel_lcdfb_info));
-+	memcpy(&all_data->monspecs, data->default_monspecs,
-+			sizeof(struct fb_monspecs));
-+	memcpy(&all_data->modedb, data->default_monspecs->modedb, modedb_size);
-+
-+	ret = platform_device_add_data(pdev, all_data, data_size);
-+	kfree(all_data);
-+	if (ret)
-+		goto error;
-+
-+	/*
-+	 * Update internal pointers to use memory allocated by
-+	 * platform_device_add_data().
-+	 */
-+	all_data = pdev->dev.platform_data;
-+	all_data->info.default_monspecs = &all_data->monspecs;
-+	all_data->monspecs.modedb = all_data->modedb;
-+
-+	select_peripheral(PD, 0x7fffffff,  PERIPH_A, 0);
-+
-+	pdev->dev.dma_mask = &atmel_lcdfb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	atmel_lcdfb0_hck1.dev = &pdev->dev;
-+	atmel_lcdfb0_pixclk.dev = &pdev->dev;
-+
-+	clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
-+	clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  Media Post-Processor (MPOP)
-+ * -------------------------------------------------------------------- */
-+
-+static u64 atmel_mpopfb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource atmel_mpopfb0_resource[] = {
-+	{
-+		/* Configuration interface */
-+		.start	= 0xffe02000,
-+		.end	= 0xffe02fff,
-+		.flags	= IORESOURCE_MEM,
-+	}, {
-+		/* Data interface (output) */
-+		.start	= 0xf0000000,
-+		.end	= 0xf0ffffff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(4),
-+	{
-+		/* Placeholder for pre-allocated fb memory */
-+		.start	= 0x00000000,
-+		.end	= 0x00000000,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct clk atmel_mpopfb0_hclk = {
-+	.name		= "hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 12,
-+};
-+static struct clk atmel_mpopfb0_pclk = {
-+	.name		= "pclk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 2,
-+};
-+
-+struct platform_device *__init at32_add_device_mpop(unsigned int id,
-+		struct platform_device *lcdc_pdev,
-+		unsigned long fbmem_start, unsigned long fbmem_len)
-+{
-+	struct platform_device		*pdev;
-+	struct atmel_mpopfb_info	info;
-+	unsigned int			num_resources;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_mpopfb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	num_resources = ARRAY_SIZE(atmel_mpopfb0_resource);
-+	if (fbmem_len) {
-+		atmel_mpopfb0_resource[num_resources - 1].start = fbmem_start;
-+		atmel_mpopfb0_resource[num_resources - 1].end
-+			= fbmem_start + fbmem_len - 1;
-+	} else {
-+		num_resources--;
-+	}
-+	if (platform_device_add_resources(pdev, atmel_mpopfb0_resource,
-+				num_resources))
-+		goto error;
-+
-+	info.lcdc_pdev = lcdc_pdev;
-+	if (platform_device_add_data(pdev, &info, sizeof(info)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &atmel_mpopfb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	atmel_mpopfb0_hclk.dev = &pdev->dev;
-+	atmel_mpopfb0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ *  USB Host (OHCI/EHCI)
-+ * ------------------------------------------------------------------- */
-+
-+static u64 usbh_dma_mask = DMA_32BIT_MASK;
-+
-+static unsigned long parent_clk_get_rate(struct clk *clk)
-+{
-+	return clk->parent->get_rate(clk->parent);
-+}
-+
-+static void parent_clk_mode(struct clk *clk, int enabled)
-+{
-+	/* Parent clk enabled by clk core */
-+}
-+
-+/*
-+ * The UTMI clock is an internally controlled PLL. It is hardwired to
-+ * OSC2 and will run at 30 MHz or 60 MHz depending on the internal
-+ * UTMI <-> host controller data bus width.
-+ *
-+ * We can turn it on and off through the Power Manager. That's all.
-+ */
-+static void utmi_clk_mode(struct clk *clk, int enabled)
-+{
-+	u32 ppcr = pm_readl(PPCR);
-+
-+	if (enabled)
-+		/* Clear UTMI suspend signal */
-+		ppcr |= PM_BIT(PPCR_UTMI_CTRL);
-+	else
-+		/* Set UTMI suspend signal */
-+		ppcr &= ~PM_BIT(PPCR_UTMI_CTRL);
-+
-+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0x55));
-+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0xaa));
-+
-+	if (enabled)
-+		/* PLL startup time is 2.5 ms */
-+		udelay(2500);
-+}
-+
-+static unsigned long utmi_clk_get_rate(struct clk *clk)
-+{
-+	/*
-+	 * Not sure about this, but I think the UTMI interface on
-+	 * AP7200 is 16 bits wide, which means 30 MHz PHY clock.
-+	 */
-+	return 30000000;
-+}
-+
-+static struct clk usbh_utmi_clk = {
-+	.name		= "usbh_utmi_clk",
-+	.parent		= &osc2,
-+	.mode		= utmi_clk_mode,
-+	.get_rate	= utmi_clk_get_rate,
-+};
-+
-+static struct clk usbh_hclk = {
-+	.name		= "usbh_hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 6,
-+};
-+
-+/*
-+ * UTMI and HSB clocks are shared between OHCI and EHCI. These wrappers
-+ * make sure both can use the clocks as if they had their own.
-+ */
-+static struct clk ohci_utmi_clk = {
-+	.name		= "utmi_clk",
-+	.parent		= &usbh_utmi_clk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+static struct clk ohci_hclk = {
-+	.name		= "hclk",
-+	.parent		= &usbh_hclk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+static struct clk ehci_utmi_clk = {
-+	.name		= "utmi_clk",
-+	.parent		= &usbh_utmi_clk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+static struct clk ehci_hclk = {
-+	.name		= "hclk",
-+	.parent		= &usbh_hclk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+/*
-+ * The USBH needs both a 48 MHz and a 12 MHz clock, and the 12 MHz
-+ * must be generated by dividing the 48 MHz clock. There's only one
-+ * generic clock hooked up to the USBH which we must use to generate
-+ * both.
-+ *
-+ * This can be done because GCLK0 generates an additional "divided
-+ * clock", which is the normal clock output further divided by four
-+ * (this is hardcoded, but not surprisingly, exactly what we need.)
-+ *
-+ * So we generate the clocks as follows:
-+ *    OSC2 (12 MHz) -> PLL2 (48 MHz) --> GCLK0 undivided (48 MHz)
-+ *                                   |-> GCLK0 divided (12 MHz)
-+ *
-+ * This clock is only used by the OHCI part of the controller, not the
-+ * EHCI part.
-+ */
-+static struct clk ohci_gclk = {
-+	.name		= "ohci_clk",
-+	.parent		= &gclk0,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+static struct resource usbh_ohci_resource[] __initdata = {
-+	{
-+		.start	= 0xff400000,
-+		.end	= 0xff400400,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(7),
-+};
-+
-+static struct resource usbh_ehci_resource[] __initdata = {
-+	{
-+		.start	= 0xff300000,
-+		.end	= 0xff300400,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(7),
-+};
-+
-+static void __init usbh_setup_pins(void)
-+{
-+	static bool already_done __initdata;
-+
-+	if (!already_done) {
-+		already_done = true;
-+		/* OC_EN_N | OC_FLAG_N */
-+		select_peripheral(PA, (1 << 18) | (1 << 19), PERIPH_D, 0);
-+	}
-+}
-+
-+struct platform_device *__init at32_add_device_ohci(unsigned int id)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("ohci", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, usbh_ohci_resource,
-+				ARRAY_SIZE(usbh_ohci_resource)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &usbh_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	clk_set_parent(&pll2, &osc2);
-+	if (clk_round_rate(&pll2, 48000000) != 48000000) {
-+		pr_debug("USBH OHCI: Cannot generate 48 MHz clock\n");
-+		goto error;
-+	}
-+	clk_set_rate(&pll2, 48000000);
-+
-+	clk_set_parent(&gclk0, &pll2);
-+	clk_set_rate(&gclk0, 48000000);
-+
-+	ohci_utmi_clk.dev = &pdev->dev;
-+	ohci_hclk.dev = &pdev->dev;
-+	ohci_gclk.dev = &pdev->dev;
-+
-+	usbh_setup_pins();
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+struct platform_device *__init at32_add_device_ehci(unsigned int id)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("ehci", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, usbh_ehci_resource,
-+				ARRAY_SIZE(usbh_ehci_resource)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &usbh_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	ehci_utmi_clk.dev = &pdev->dev;
-+	ehci_hclk.dev = &pdev->dev;
-+
-+	usbh_setup_pins();
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ *  NAND Flash / SmartMedia
-+ * ------------------------------------------------------------------- */
-+static struct resource smc_cs3_resource[] __initdata = {
-+	{
-+		.start	= 0x24000000,
-+		.end	= 0x27ffffff,
-+		.flags	= IORESOURCE_MEM,
-+	}, {
-+		.start	= 0xffe04c00,
-+		.end	= 0xffe04fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+struct platform_device *__init
-+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_nand", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, smc_cs3_resource,
-+				ARRAY_SIZE(smc_cs3_resource)))
-+		goto error;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct atmel_nand_data)))
-+		goto error;
-+
-+	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
-+
-+	/* NANDOE | NANDWE */
-+	select_peripheral(PF, (1 << 0) | (1 << 1), PERIPH_A, 0);
-+
-+	if (gpio_is_valid(data->enable_pin))
-+		at32_select_gpio(data->enable_pin,
-+				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	if (gpio_is_valid(data->det_pin))
-+		at32_select_gpio(data->det_pin, 0);
-+	if (gpio_is_valid(data->rdy_pin))
-+		at32_select_gpio(data->rdy_pin, 0);
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ * Clock list
-+ * ------------------------------------------------------------------- */
-+static __initdata struct clk *init_clocks[] = {
-+	&rcosc,
-+	&osc0,
-+	&osc1,
-+	&osc2,
-+	&osc32,
-+	&pll0,
-+	&pll1,
-+	&pll2,
-+	&cpu_clk,
-+	&hsb_clk,
-+	&pba_clk,
-+	&pbb_clk,
-+	&pbc_clk,
-+	&gclk0,
-+	&gclk1,
-+	&gclk2,
-+	&gclk3,
-+	&gclk4,
-+	&gclk5,
-+	&at32_intc0_pclk,
-+	&pm_pclk,
-+	&sdc_pclk,
-+	&ast0_pclk,
-+	&ast1_pclk,
-+	&wdt_pclk,
-+	&gpio_pclk,
-+	&pdca_hclk,
-+	&pdca_pclk,
-+	&ebi_hclk,
-+	&hramc_clk,
-+	&smc_pclk,
-+	&sdramc_clk,
-+	&dw_dmac0_hclk,
-+	&atmel_usart0_usart,
-+	&atmel_usart1_usart,
-+	&atmel_usart2_usart,
-+	&atmel_usart3_usart,
-+	&atmel_usart4_usart,
-+	&atmel_usart5_usart,
-+	&atmel_spi_clk[0],
-+	&atmel_spi_clk[1],
-+	&atmel_spi_clk[2],
-+	&atmel_spi_clk[3],
-+	&macb0_hclk,
-+	&macb0_pclk,
-+	&atmel_mci0_pclk,
-+	&atmel_lcdfb0_hck1,
-+	&atmel_lcdfb0_pixclk,
-+	&atmel_mpopfb0_hclk,
-+	&atmel_mpopfb0_pclk,
-+	&usbh_utmi_clk,
-+	&usbh_hclk,
-+	&ohci_utmi_clk,
-+	&ohci_hclk,
-+	&ohci_gclk,
-+	&ehci_utmi_clk,
-+	&ehci_hclk,
-+};
-+
-+static void pll_init_parent(struct clk *pll)
-+{
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[pll->index]);
-+	switch (PM_BFEXT(PLLx_PLLOSC, ctrl)) {
-+	case 0:
-+		pll->parent = &osc0;
-+		break;
-+	case 1:
-+		pll->parent = &osc1;
-+		break;
-+	case 2:
-+		pll->parent = &osc2;
-+		break;
-+	}
-+}
-+
-+static void ap7200_power_off(void)
-+{
-+	/*
-+	 * Clear all wakeup events so that we don't wake up
-+	 * immediately after we shut down.
-+	 */
-+	sdc_writel(ECR, ~0UL);
-+	sdc_readl(STATUS);
-+	asm volatile("sleep %0; sub pc, -2"
-+			:: "i"(CPU_SLEEP_SHUTDOWN)
-+			: "memory");
-+}
-+
-+void __init setup_platform(void)
-+{
-+	unsigned int	i;
-+	u32		cpu_mask;
-+	u32		hsb_mask;
-+	u32		pba_mask;
-+	u32		pbb_mask;
-+
-+	switch (PM_BFEXT(MCCTRL_MCSEL, pm_readl(MCCTRL))) {
-+	case 0:
-+		main_clock = &rcosc;
-+		break;
-+	case 1:
-+		main_clock = &osc0;
-+		break;
-+	case 2:
-+		main_clock = &pll0;
-+		break;
-+	}
-+
-+	cpu_clk.parent = main_clock;
-+
-+	pll_init_parent(&pll0);
-+	pll_init_parent(&pll1);
-+	pll_init_parent(&pll2);
-+
-+	genclk_init_parent(&gclk0);
-+	genclk_init_parent(&gclk1);
-+	genclk_init_parent(&gclk2);
-+	genclk_init_parent(&gclk3);
-+	genclk_init_parent(&gclk4);
-+	genclk_init_parent(&gclk5);
-+	genclk_init_parent(&atmel_lcdfb0_pixclk);
-+
-+	/*
-+	 * Turn on all clocks that have at least one user already, and
-+	 * turn off everything else. We only do this for module
-+	 * clocks, and even though it isn't particularly pretty to
-+	 * check the address of the mode function, it should do the
-+	 * trick...
-+	 */
-+	cpu_mask = 0x10003;
-+	hsb_mask = pba_mask = pbb_mask = 0;
-+
-+	/* Make sure we don't disable the power manager or the SDRAM */
-+	pm_pclk.users = 1;
-+	pm_pclk.parent->users = 1;
-+	ebi_hclk.users = 1;
-+
-+	/* Can't recursively call clk_enable() from any of the clk ops */
-+	sdc_pclk.users = 1;
-+
-+	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
-+		struct clk *clk = init_clocks[i];
-+
-+		/* first, register clock */
-+		at32_clk_register(clk);
-+
-+		if (clk->users == 0)
-+			continue;
-+
-+		if (clk->mode == &cpu_clk_mode)
-+			cpu_mask |= 1 << clk->index;
-+		else if (clk->mode == &hsb_clk_mode)
-+			hsb_mask |= 1 << clk->index;
-+		else if (clk->mode == &pba_clk_mode)
-+			pba_mask |= 1 << clk->index;
-+		else if (clk->mode == &pbb_clk_mode)
-+			pbb_mask |= 1 << clk->index;
-+	}
-+
-+	pm_writel(CPUMASK, cpu_mask);
-+	pm_writel(HSBMASK, hsb_mask);
-+	pm_writel(PBAMASK, pba_mask);
-+	pm_writel(PBBMASK, pbb_mask);
-+
-+	at32_gpio_init(&gpio_device);
-+
-+	/* Enter shutdown mode when powering off. This happens very
-+	 * early, so board code may still override this. */
-+	pm_power_off = ap7200_power_off;
-+
-+	/* Enable WAKE pin */
-+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
-+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
-+			| SDC_BF(CTRL_KEY, 0x55));
-+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
-+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
-+			| SDC_BF(CTRL_KEY, 0xaa));
-+}
-+
-+void __init platform_time_init(void)
-+{
-+	ast_time_init(&ast1_device, AST_CLOCK_PB);
-+}
-+
-+unsigned long at32_get_reset_cause(void)
-+{
-+	return pm_readl(RCAUSE);
-+}
-+
-+struct gen_pool *sram_pool;
-+
-+static int __init sram_init(void)
-+{
-+	struct gen_pool *pool;
-+
-+	/* 1KiB granularity */
-+	pool = gen_pool_create(10, -1);
-+	if (!pool)
-+		goto fail;
-+
-+	if (gen_pool_add(pool, 0x08000000, 0x10000, -1))
-+		goto err_pool_add;
-+
-+	sram_pool = pool;
-+	return 0;
-+
-+err_pool_add:
-+	gen_pool_destroy(pool);
-+fail:
-+	pr_err("Failed to create SRAM pool\n");
-+	return -ENOMEM;
-+}
-+core_initcall(sram_init);
-diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c
-index 6c27dda..05877d6 100644
---- a/arch/avr32/mach-at32ap/clock.c
-+++ b/arch/avr32/mach-at32ap/clock.c
-@@ -15,24 +15,40 @@
- #include <linux/err.h>
- #include <linux/device.h>
- #include <linux/string.h>
-+#include <linux/list.h>
- 
- #include <mach/chip.h>
- 
- #include "clock.h"
- 
-+/* at32 clock list */
-+static LIST_HEAD(at32_clock_list);
-+
- static DEFINE_SPINLOCK(clk_lock);
-+static DEFINE_SPINLOCK(clk_list_lock);
-+
-+void at32_clk_register(struct clk *clk)
-+{
-+	spin_lock(&clk_list_lock);
-+	/* add the new item to the end of the list */
-+	list_add_tail(&clk->list, &at32_clock_list);
-+	spin_unlock(&clk_list_lock);
-+}
- 
- struct clk *clk_get(struct device *dev, const char *id)
- {
--	int i;
-+	struct clk *clk;
- 
--	for (i = 0; i < at32_nr_clocks; i++) {
--		struct clk *clk = at32_clock_list[i];
-+	spin_lock(&clk_list_lock);
- 
--		if (clk->dev == dev && strcmp(id, clk->name) == 0)
-+	list_for_each_entry(clk, &at32_clock_list, list) {
-+		if (clk->dev == dev && strcmp(id, clk->name) == 0) {
-+			spin_unlock(&clk_list_lock);
- 			return clk;
-+		}
- 	}
- 
-+	spin_unlock(&clk_list_lock);
- 	return ERR_PTR(-ENOENT);
- }
- EXPORT_SYMBOL(clk_get);
-@@ -162,7 +178,11 @@ EXPORT_SYMBOL(clk_get_parent);
- #include <linux/io.h>
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
--#include "pm.h"
-+#if defined(CONFIG_CPU_AT32AP700X)
-+# include "pm-v1.h"
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# include "pm-v3.h"
-+#endif
- 
- 
- #define	NEST_DELTA	2
-@@ -203,8 +223,8 @@ dump_clock(struct clk *parent, struct clkinf *r)
- 
- 	/* cost of this scan is small, but not linear... */
- 	r->nest = nest + NEST_DELTA;
--	for (i = 3; i < at32_nr_clocks; i++) {
--		clk = at32_clock_list[i];
-+
-+	list_for_each_entry(clk, &at32_clock_list, list) {
- 		if (clk->parent == parent)
- 			dump_clock(clk, r);
- 	}
-@@ -215,33 +235,76 @@ static int clk_show(struct seq_file *s, void *unused)
- {
- 	struct clkinf	r;
- 	int		i;
-+	struct clk 	*clk;
- 
- 	/* show all the power manager registers */
--	seq_printf(s, "MCCTRL  = %8x\n", pm_readl(MCCTRL));
--	seq_printf(s, "CKSEL   = %8x\n", pm_readl(CKSEL));
--	seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK));
--	seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK));
--	seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK));
--	seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK));
--	seq_printf(s, "PLL0    = %8x\n", pm_readl(PLL0));
--	seq_printf(s, "PLL1    = %8x\n", pm_readl(PLL1));
--	seq_printf(s, "IMR     = %8x\n", pm_readl(IMR));
-+	seq_printf(s, "MCCTRL     = %8x\n", pm_readl(MCCTRL));
-+	seq_printf(s, "CKSEL      = %8x\n", pm_readl(CKSEL));
-+#ifdef CONFIG_CPU_AT32AP700X
-+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPU_MASK));
-+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSB_MASK));
-+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBA_MASK));
-+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBB_MASK));
-+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL0));
-+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL1));
-+#else
-+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPUMASK));
-+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSBMASK));
-+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBAMASK));
-+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBBMASK));
-+	seq_printf(s, "PBADIVMASK = %8x\n", pm_readl(PBADIVMASK));
-+	seq_printf(s, "PBBDIVMASK = %8x\n", pm_readl(PBBDIVMASK));
-+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL[0]));
-+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL[1]));
-+	seq_printf(s, "PLL2       = %8x\n", pm_readl(PLL[2]));
-+	seq_printf(s, "OSCCTRL0   = %8x\n", pm_readl(OSCCTRL[0]));
-+	seq_printf(s, "OSCCTRL1   = %8x\n", pm_readl(OSCCTRL[1]));
-+	seq_printf(s, "OSCCTRL2   = %8x\n", pm_readl(OSCCTRL[2]));
-+	seq_printf(s, "POSCSR     = %8x\n", pm_readl(POSCSR));
-+	seq_printf(s, "PPCR       = %8x\n", pm_readl(PPCR));
-+#endif
-+	seq_printf(s, "IMR        = %8x\n", pm_readl(IMR));
- 	for (i = 0; i < 8; i++) {
- 		if (i == 5)
- 			continue;
--		seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
-+#ifdef CONFIG_CPU_AT32AP700X
-+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL(i)));
-+#else
-+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL[i]));
-+#endif
- 	}
- 
- 	seq_printf(s, "\n");
- 
--	/* show clock tree as derived from the three oscillators
--	 * we "know" are at the head of the list
--	 */
- 	r.s = s;
- 	r.nest = 0;
--	dump_clock(at32_clock_list[0], &r);
--	dump_clock(at32_clock_list[1], &r);
--	dump_clock(at32_clock_list[2], &r);
-+	/* protected from changes on the list while dumping */
-+	spin_lock(&clk_list_lock);
-+
-+	/* show clock tree as derived from the three oscillators */
-+	clk = clk_get(NULL, "osc32k");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "osc0");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "osc1");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+#ifdef CONFIG_CPU_AT32AP720X
-+	clk = clk_get(NULL, "osc2");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "rcosc");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+#endif
-+
-+	spin_unlock(&clk_list_lock);
- 
- 	return 0;
- }
-diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h
-index bb8e1f2..623bf0e 100644
---- a/arch/avr32/mach-at32ap/clock.h
-+++ b/arch/avr32/mach-at32ap/clock.h
-@@ -12,8 +12,13 @@
-  * published by the Free Software Foundation.
-  */
- #include <linux/clk.h>
-+#include <linux/list.h>
-+
-+
-+void at32_clk_register(struct clk *clk);
- 
- struct clk {
-+	struct list_head list;		/* linking element */
- 	const char	*name;		/* Clock name/function */
- 	struct device	*dev;		/* Device the clock is used by */
- 	struct clk	*parent;	/* Parent clock, if any */
-@@ -25,6 +30,3 @@ struct clk {
- 	u16		users;		/* Enabled if non-zero */
- 	u16		index;		/* Sibling index */
- };
--
--extern struct clk *at32_clock_list[];
--extern unsigned int at32_nr_clocks;
-diff --git a/arch/avr32/mach-at32ap/cpufreq.c b/arch/avr32/mach-at32ap/cpufreq.c
-index 5dd8d25..4cabc76 100644
---- a/arch/avr32/mach-at32ap/cpufreq.c
-+++ b/arch/avr32/mach-at32ap/cpufreq.c
-@@ -40,6 +40,9 @@ static unsigned int at32_get_speed(unsigned int cpu)
- 	return (unsigned int)((clk_get_rate(cpuclk) + 500) / 1000);
- }
- 
-+static unsigned int	ref_freq;
-+static unsigned long	loops_per_jiffy_ref;
-+
- static int at32_set_target(struct cpufreq_policy *policy,
- 			  unsigned int target_freq,
- 			  unsigned int relation)
-@@ -61,8 +64,19 @@ static int at32_set_target(struct cpufreq_policy *policy,
- 	freqs.cpu = 0;
- 	freqs.flags = 0;
- 
-+	if (!ref_freq) {
-+		ref_freq = freqs.old;
-+		loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy;
-+	}
-+
- 	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-+	if (freqs.old < freqs.new)
-+		boot_cpu_data.loops_per_jiffy = cpufreq_scale(
-+				loops_per_jiffy_ref, ref_freq, freqs.new);
- 	clk_set_rate(cpuclk, freq);
-+	if (freqs.new < freqs.old)
-+		boot_cpu_data.loops_per_jiffy = cpufreq_scale(
-+				loops_per_jiffy_ref, ref_freq, freqs.new);
- 	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- 
- 	pr_debug("cpufreq: set frequency %lu Hz\n", freq);
-diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
-index c36a6d5..b6870b5 100644
---- a/arch/avr32/mach-at32ap/extint.c
-+++ b/arch/avr32/mach-at32ap/extint.c
-@@ -17,6 +17,8 @@
- 
- #include <asm/io.h>
- 
-+#include <mach/cpu.h>
-+
- /* EIC register offsets */
- #define EIC_IER					0x0000
- #define EIC_IDR					0x0004
-@@ -26,24 +28,18 @@
- #define EIC_MODE				0x0014
- #define EIC_EDGE				0x0018
- #define EIC_LEVEL				0x001c
-+
-+/* This is only valid on v1 (AP700x) */
- #define EIC_NMIC				0x0024
-+# define EIC_NMIC_ENABLE			(1 << 0)
- 
--/* Bitfields in NMIC */
--#define EIC_NMIC_ENABLE				(1 << 0)
--
--/* Bit manipulation macros */
--#define EIC_BIT(name)					\
--	(1 << EIC_##name##_OFFSET)
--#define EIC_BF(name,value)				\
--	(((value) & ((1 << EIC_##name##_SIZE) - 1))	\
--	 << EIC_##name##_OFFSET)
--#define EIC_BFEXT(name,value)				\
--	(((value) >> EIC_##name##_OFFSET)		\
--	 & ((1 << EIC_##name##_SIZE) - 1))
--#define EIC_BFINS(name,value,old)			\
--	(((old) & ~(((1 << EIC_##name##_SIZE) - 1)	\
--		    << EIC_##name##_OFFSET))		\
--	 | EIC_BF(name,value))
-+/* These are only valid on v3 (AP720x) */
-+#define EIC_FILTER				0x0020
-+#define EIC_TEST				0x0024
-+#define EIC_ASYNC				0x0028
-+#define EIC_EN					0x0030
-+#define EIC_DIS					0x0034
-+#define EIC_CTRL				0x0038
- 
- /* Register access macros */
- #define eic_readl(port,reg)				\
-@@ -60,36 +56,68 @@ struct eic {
- static struct eic *nmi_eic;
- static bool nmi_enabled;
- 
-+static inline int eic_version(struct eic *eic)
-+{
-+	if (cpu_is_at32ap7000())
-+		return 1;
-+	if (cpu_is_at32ap7200())
-+		return 3;
-+
-+	BUG();
-+}
-+
-+static inline int eic_irq_bitmask(struct eic *eic, unsigned int irq)
-+{
-+	irq -= eic->first_irq;
-+
-+	if (eic_version(eic) > 2)
-+		irq++;
-+	return 1 << irq;
-+}
-+
- static void eic_ack_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_mask_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_mask_ack_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
--	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
-+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_unmask_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, IER, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, IER, eic_irq_bitmask(eic, irq));
-+}
-+
-+/* The following two hooks are only used on v2+ controllers */
-+static void eic_enable_irq(unsigned int irq)
-+{
-+	struct eic *eic = get_irq_chip_data(irq);
-+	eic_writel(eic, EN, eic_irq_bitmask(eic, irq));
-+}
-+
-+static void eic_disable_irq(unsigned int irq)
-+{
-+	struct eic *eic = get_irq_chip_data(irq);
-+	eic_writel(eic, DIS, eic_irq_bitmask(eic, irq));
- }
- 
- static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
- 	struct irq_desc *desc;
--	unsigned int i = irq - eic->first_irq;
-+	unsigned int irq_bitmask = eic_irq_bitmask(eic, irq);
- 	u32 mode, edge, level;
- 	int ret = 0;
- 
-@@ -105,20 +133,20 @@ static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
- 
- 	switch (flow_type) {
- 	case IRQ_TYPE_LEVEL_LOW:
--		mode |= 1 << i;
--		level &= ~(1 << i);
-+		mode |= irq_bitmask;
-+		level &= ~irq_bitmask;
- 		break;
- 	case IRQ_TYPE_LEVEL_HIGH:
--		mode |= 1 << i;
--		level |= 1 << i;
-+		mode |= irq_bitmask;
-+		level |= irq_bitmask;
- 		break;
- 	case IRQ_TYPE_EDGE_RISING:
--		mode &= ~(1 << i);
--		edge |= 1 << i;
-+		mode &= ~irq_bitmask;
-+		edge |= irq_bitmask;
- 		break;
- 	case IRQ_TYPE_EDGE_FALLING:
--		mode &= ~(1 << i);
--		edge &= ~(1 << i);
-+		mode &= ~irq_bitmask;
-+		edge &= ~irq_bitmask;
- 		break;
- 	default:
- 		ret = -EINVAL;
-@@ -160,6 +188,11 @@ static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
- 	status = eic_readl(eic, ISR);
- 	pending = status & eic_readl(eic, IMR);
- 
-+	if (eic_version(eic) > 1) {
-+		status >>= 1;
-+		pending >>= 1;
-+	}
-+
- 	while (pending) {
- 		i = fls(pending) - 1;
- 		pending &= ~(1 << i);
-@@ -172,16 +205,34 @@ int nmi_enable(void)
- {
- 	nmi_enabled = true;
- 
--	if (nmi_eic)
--		eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+	if (nmi_eic) {
-+		if (eic_version(nmi_eic) > 2) {
-+			eic_writel(nmi_eic, EN, 1 << 0);
-+			eic_writel(nmi_eic, IER, 1 << 0);
-+		} else if (eic_version(nmi_eic) > 1) {
-+			eic_writel(nmi_eic, EN, 1 << 8);
-+			eic_writel(nmi_eic, IER, 1 << 8);
-+		} else {
-+			eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+		}
-+	}
- 
- 	return 0;
- }
- 
- void nmi_disable(void)
- {
--	if (nmi_eic)
--		eic_writel(nmi_eic, NMIC, 0);
-+	if (nmi_eic) {
-+		if (eic_version(nmi_eic) > 2) {
-+			eic_writel(nmi_eic, IDR, 1 << 0);
-+			eic_writel(nmi_eic, DIS, 1 << 0);
-+		} else if (eic_version(nmi_eic) > 1) {
-+			eic_writel(nmi_eic, IDR, 1 << 8);
-+			eic_writel(nmi_eic, DIS, 1 << 8);
-+		} else {
-+			eic_writel(nmi_eic, NMIC, 0);
-+		}
-+	}
- 
- 	nmi_enabled = false;
- }
-@@ -230,6 +281,15 @@ static int __init eic_probe(struct platform_device *pdev)
- 	eic_writel(eic, EDGE, 0UL);
- 	eic_writel(eic, LEVEL, 0UL);
- 
-+	/*
-+	 * v2+ controllers have an extra enable/disable/mask set of
-+	 * registers.
-+	 */
-+	if (eic_version(eic) >= 2) {
-+		eic_chip.enable = eic_enable_irq;
-+		eic_chip.disable = eic_disable_irq;
-+	}
-+
- 	eic->chip = &eic_chip;
- 
- 	for (i = 0; i < nr_irqs; i++) {
-diff --git a/arch/avr32/mach-at32ap/gpio-v2.c b/arch/avr32/mach-at32ap/gpio-v2.c
-new file mode 100644
-index 0000000..63b8943
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/gpio-v2.c
-@@ -0,0 +1,534 @@
-+/*
-+ * Atmel GPIO Port Multiplexer support
-+ *
-+ * Copyright (C) 2004-2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/debugfs.h>
-+#include <linux/fs.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+
-+#include <mach/portmux.h>
-+#include <mach/chip.h>
-+
-+#include "gpio-v2.h"
-+
-+/*
-+ * One chip corresponds with one bank of I/O registers. They're really
-+ * all on the same controller.
-+ */
-+struct atmel_gpio_chip {
-+	void __iomem	*regs;
-+	u32		pinmux_mask;
-+	struct		gpio_chip chip;
-+	char		name[8];
-+	unsigned int	bank;
-+	int		irq;
-+};
-+
-+/* ...which means we only have one clock and one platform device */
-+static struct clk *gpio_clk;
-+static struct atmel_gpio_chip gpio_dev[NR_GPIO_BANKS];
-+
-+/* Pin multiplexing API */
-+static DEFINE_SPINLOCK(gpio_lock);
-+
-+static struct atmel_gpio_chip *to_atmel_gpio_chip(struct gpio_chip *chip)
-+{
-+	return container_of(chip, struct atmel_gpio_chip, chip);
-+}
-+
-+static struct atmel_gpio_chip *pin_to_chip(unsigned int gpio)
-+{
-+	struct atmel_gpio_chip *chip;
-+	unsigned int index;
-+
-+	index = gpio >> 5;
-+	if (index >= NR_GPIO_BANKS)
-+		return NULL;
-+	chip = &gpio_dev[index];
-+	if (!chip->regs)
-+		return NULL;
-+
-+	return chip;
-+}
-+
-+/* Pin multiplexing API */
-+
-+void __init at32_select_periph(unsigned int port, u32 pin_mask,
-+		unsigned int periph, unsigned long flags)
-+{
-+	struct atmel_gpio_chip *chip;
-+
-+	chip = pin_to_chip(port);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid port %u\n", port);
-+		goto fail;
-+	}
-+
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&gpio_lock);
-+	if (unlikely(gpiochip_is_requested(&chip->chip, port)
-+			|| unlikely(pin_mask & chip->pinmux_mask))) {
-+		printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
-+		       chip->name, pin_mask, chip->pinmux_mask & pin_mask);
-+		spin_unlock(&gpio_lock);
-+		goto fail;
-+	}
-+
-+	switch (periph) {
-+	case GPIO_PERIPH_A:
-+		gpio_writel(chip, PMR0C, pin_mask);
-+		gpio_writel(chip, PMR1C, pin_mask);
-+		break;
-+	case GPIO_PERIPH_B:
-+		gpio_writel(chip, PMR0S, pin_mask);
-+		gpio_writel(chip, PMR1C, pin_mask);
-+		break;
-+	case GPIO_PERIPH_C:
-+		gpio_writel(chip, PMR0C, pin_mask);
-+		gpio_writel(chip, PMR1S, pin_mask);
-+		break;
-+	case GPIO_PERIPH_D:
-+		gpio_writel(chip, PMR0S, pin_mask);
-+		gpio_writel(chip, PMR1S, pin_mask);
-+		break;
-+	default:
-+		printk("%s: unknown function for pin mask %u\n",
-+				chip->name, pin_mask);
-+		goto fail;
-+	}
-+
-+	gpio_writel(chip, PUERS, pin_mask);
-+
-+	gpio_writel(chip, GPERC, pin_mask);
-+	if (!(flags & AT32_GPIOF_PULLUP))
-+		gpio_writel(chip, PUERC, pin_mask);
-+
-+	spin_unlock(&gpio_lock);
-+
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+void __init at32_select_gpio(unsigned int pin, unsigned long flags)
-+{
-+	struct atmel_gpio_chip *chip;
-+	unsigned int pin_index = pin & 0x1f;
-+	u32 mask = 1 << pin_index;
-+
-+	chip = pin_to_chip(pin);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid pin %u\n", pin);
-+		goto fail;
-+	}
-+
-+	if (unlikely(test_and_set_bit(pin_index, &chip->pinmux_mask))) {
-+		printk("%s: pin %u is busy\n", chip->name, pin_index);
-+		goto fail;
-+	}
-+
-+	if (flags & AT32_GPIOF_PULLUP)
-+		gpio_writel(chip, PUERS, mask);
-+	else
-+		gpio_writel(chip, PUERC, mask);
-+	if (flags & AT32_GPIOF_MULTIDRV)
-+		gpio_writel(chip, ODMERS, mask);
-+	else
-+		gpio_writel(chip, ODMERC, mask);
-+	if (flags & AT32_GPIOF_DEGLITCH)
-+		gpio_writel(chip, GFERS, mask);
-+	else
-+		gpio_writel(chip, GFERC, mask);
-+
-+	if (flags & AT32_GPIOF_OUTPUT) {
-+		if (flags & AT32_GPIOF_HIGH)
-+			gpio_writel(chip, OVRS, mask);
-+		else
-+			gpio_writel(chip, OVRC, mask);
-+		gpio_writel(chip, ODERS, mask);
-+	} else {
-+		gpio_writel(chip, ODERC, mask);
-+	}
-+
-+	gpio_writel(chip, GPERS, mask);
-+
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+/* Reserve a pin, preventing anyone else from changing its configuration. */
-+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
-+{
-+	struct atmel_gpio_chip *chip;
-+
-+	chip = pin_to_chip(port);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid port %u\n", port);
-+		goto fail;
-+	}
-+
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&gpio_lock);
-+	if (unlikely(pin_mask & chip->pinmux_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
-+			chip->name, pin_mask, chip->pinmux_mask & pin_mask);
-+		spin_unlock(&gpio_lock);
-+		goto fail;
-+	}
-+
-+	/* Reserve pins */
-+	chip->pinmux_mask |= pin_mask;
-+	spin_unlock(&gpio_lock);
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+/* GPIO API */
-+
-+static int get_pin_state(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+
-+	return (gpio_readl(gpio, PVR) >> offset) & 1;
-+}
-+
-+static void set_pin_state(struct gpio_chip *chip, unsigned int offset, int high)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (high)
-+		gpio_writel(gpio, OVRS, mask);
-+	else
-+		gpio_writel(gpio, OVRC, mask);
-+}
-+
-+static int direction_input(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (!(gpio_readl(gpio, GPER) & mask))
-+		return -EINVAL;
-+
-+	gpio_writel(gpio, ODERC, mask);
-+	return 0;
-+}
-+
-+static int direction_output(struct gpio_chip *chip, unsigned int offset,
-+		int high)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (!(gpio_readl(gpio, GPER) & mask))
-+		return -EINVAL;
-+
-+	set_pin_state(chip, offset, high);
-+	gpio_writel(gpio, ODERS, mask);
-+	return 0;
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+/* GPIO IRQ support */
-+
-+static void gpio_irq_mask(unsigned irq)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+
-+	gpio_writel(chip, IERC, 1 << (pin & 0x1f));
-+}
-+
-+static void gpio_irq_unmask(unsigned irq)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+
-+	gpio_writel(chip, IERS, 1 << (pin & 0x1f));
-+}
-+
-+static int gpio_irq_type(unsigned irq, unsigned type)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+	u32			mask = 1 << (pin & 0x1f);
-+
-+	switch (type) {
-+	case IRQ_TYPE_EDGE_FALLING:
-+		gpio_writel(chip, IMR0C, mask);
-+		gpio_writel(chip, IMR1S, mask);
-+		break;
-+	case IRQ_TYPE_EDGE_RISING:
-+		gpio_writel(chip, IMR0S, mask);
-+		gpio_writel(chip, IMR1C, mask);
-+		break;
-+	case IRQ_TYPE_NONE:
-+		/* fall through */
-+	case IRQ_TYPE_EDGE_BOTH:
-+		gpio_writel(chip, IMR0C, mask);
-+		gpio_writel(chip, IMR1C, mask);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct irq_chip gpio_irqchip = {
-+	.name		= "gpio",
-+	.mask		= gpio_irq_mask,
-+	.unmask		= gpio_irq_unmask,
-+	.set_type	= gpio_irq_type,
-+};
-+
-+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+	struct atmel_gpio_chip	*chip = get_irq_chip_data(irq);
-+	unsigned int		gpio_irq;
-+
-+	gpio_irq = (unsigned int) get_irq_data(irq);
-+	for (;;) {
-+		u32		ifr;
-+		struct irq_desc	*d;
-+
-+		/* ack pending GPIO interrupts */
-+		ifr = gpio_readl(chip, IFR);
-+		if (!ifr)
-+			break;
-+		do {
-+			int pin;
-+
-+			pin = ffs(ifr) - 1;
-+			ifr &= ~(1 << pin);
-+			gpio_writel(chip, IFRC, (1 << pin));
-+
-+			pin += gpio_irq;
-+			d = &irq_desc[pin];
-+
-+			d->handle_irq(pin, d);
-+		} while (ifr);
-+	}
-+}
-+
-+static void __init
-+gpio_irq_setup(struct atmel_gpio_chip *chip, int irq, int gpio_irq)
-+{
-+	unsigned	i;
-+
-+	set_irq_chip_data(irq, chip);
-+	set_irq_data(irq, (void *) gpio_irq);
-+
-+	for (i = 0; i < 32; i++, gpio_irq++) {
-+		set_irq_chip_data(gpio_irq, chip);
-+		set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
-+				handle_simple_irq);
-+	}
-+
-+	set_irq_chained_handler(irq, gpio_irq_handler);
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+#ifdef CONFIG_DEBUG_FS
-+
-+#include <linux/seq_file.h>
-+
-+/*
-+ * This shows more info than the generic gpio dump code:
-+ * pullups, deglitching, open drain drive.
-+ */
-+static void gpio_bank_show(struct seq_file *s, struct gpio_chip *chip)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32		oder, ovr, puer, pder, gfer, odmer, ier, imr0, imr1;
-+	unsigned int	i;
-+	u32		mask;
-+
-+	oder = gpio_readl(gpio, ODER);
-+	ovr = gpio_readl(gpio, OVR);
-+	puer = gpio_readl(gpio, PUER);
-+	pder = gpio_readl(gpio, PDER);
-+	gfer = gpio_readl(gpio, GFER);
-+	odmer = gpio_readl(gpio, ODMER);
-+	ier = gpio_readl(gpio, IER);
-+	imr0 = gpio_readl(gpio, IMR0);
-+	imr1 = gpio_readl(gpio, IMR1);
-+
-+	for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
-+		const char *label;
-+
-+		label = gpiochip_is_requested(chip, i);
-+		if (!label)
-+			continue;
-+
-+		seq_printf(s, " gpio-%-3d ", chip->base + i);
-+		gpio_decode_pin(s, gpio->bank, i);
-+		seq_printf(s, " (%-12s) %s %s", label,
-+				(oder & mask) ? "out" : "in",
-+				(ovr & mask) ? "hi" : "lo");
-+		if ((puer & mask) && !(pder & mask))
-+			seq_printf(s, " pull-up");
-+		else if (!(puer & mask) && (pder & mask))
-+			seq_printf(s, " pull-down");
-+		else if ((puer & mask) && (pder & mask))
-+			seq_printf(s, " buskeeper");
-+		if (gfer & mask)
-+			seq_printf(s, " deglitch");
-+		if (odmer & mask)
-+			seq_printf(s, " open-drain");
-+		if ((gpio->irq >= 0) && (ier & mask)) {
-+			seq_printf(s, " irq-%d edge-",
-+					gpio_to_irq(chip->base + i));
-+			if (!(imr0 & mask) && !(imr1 & mask))
-+				seq_printf(s, "both");
-+			else if ((imr0 & mask) && !(imr1 & mask))
-+				seq_printf(s, "rising");
-+			else if (!(imr0 & mask) && (imr1 & mask))
-+				seq_printf(s, "falling");
-+			else
-+				seq_printf(s, "INVALID");
-+		}
-+		seq_printf(s, "\n");
-+	}
-+}
-+
-+#else
-+#define gpio_bank_show	NULL
-+#endif
-+
-+static int __init gpio_probe(struct platform_device *pdev)
-+{
-+	struct resource *regs;
-+	struct resource *irqs;
-+	int irq = -1;
-+	unsigned int i;
-+
-+	BUG_ON(pdev->id >= 1);
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "no mmio resource defined\n");
-+		return -ENXIO;
-+	}
-+	irqs = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	if (irqs)
-+		irq = irqs->start;
-+
-+	for (i = 0; i < NR_GPIO_BANKS; i++) {
-+		unsigned int gpio_irq_base;
-+		struct atmel_gpio_chip *chip;
-+
-+		chip = &gpio_dev[i];
-+		BUG_ON(!chip->regs);
-+
-+		chip->chip.label = chip->name;
-+		chip->chip.base = i * 32;
-+		chip->chip.ngpio = 32;
-+
-+		chip->chip.direction_input = direction_input;
-+		chip->chip.get = get_pin_state;
-+		chip->chip.direction_output = direction_output;
-+		chip->chip.set = set_pin_state;
-+		chip->chip.dbg_show = gpio_bank_show;
-+
-+		gpiochip_add(&chip->chip);
-+
-+		gpio_irq_base = GPIO_IRQ_BASE + (i * 32);
-+		if (irqs && irq <= irqs->end) {
-+			gpio_irq_setup(chip, irq, gpio_irq_base);
-+			chip->irq = irq;
-+			irq++;
-+		} else {
-+			chip->irq = -1;
-+		}
-+
-+		platform_set_drvdata(pdev, chip);
-+
-+		printk(KERN_DEBUG "%s: base 0x%p", chip->name, chip->regs);
-+		if (chip->irq >= 0)
-+			printk(" irq %d chains %d..%d", irq,
-+					gpio_irq_base, gpio_irq_base + 31);
-+		printk("\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_driver = {
-+	.probe		= gpio_probe,
-+	.driver		= {
-+		.name		= "gpio",
-+	},
-+};
-+
-+static int __init gpio_init(void)
-+{
-+	return platform_driver_register(&gpio_driver);
-+}
-+postcore_initcall(gpio_init);
-+
-+void __init at32_gpio_init(struct platform_device *pdev)
-+{
-+	int i;
-+	struct clk *clk;
-+	struct resource *regs;
-+	void __iomem *iomem_base;
-+	struct atmel_gpio_chip *chip;
-+
-+	if (pdev->id > 0) {
-+		dev_err(&pdev->dev, "only one GPIO controller supported\n");
-+		return;
-+	}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "no mmio resource defined\n");
-+		return;
-+	}
-+
-+	clk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "no mck clock defined\n");
-+		return;
-+	}
-+	clk_enable(clk);
-+
-+	gpio_clk = clk;
-+
-+	/*
-+	 * We may get called too early for ioremap() to work. But we
-+	 * know that the GPIO registers are permanently mapped 1:1
-+	 */
-+	iomem_base = (void __iomem __force *)regs->start;
-+
-+	for (i = 0; i < NR_GPIO_BANKS; i++) {
-+		chip = &gpio_dev[i];
-+		snprintf(chip->name, sizeof(chip->name), "gpio%d", i);
-+		chip->regs = iomem_base + (i * 0x200);
-+		chip->bank = i;
-+
-+		/* start with irqs disabled and acked */
-+		gpio_writel(chip, IERC, ~0UL);
-+		gpio_writel(chip, IFRC, ~0UL);
-+	}
-+}
-diff --git a/arch/avr32/mach-at32ap/gpio-v2.h b/arch/avr32/mach-at32ap/gpio-v2.h
-new file mode 100644
-index 0000000..77e4105
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/gpio-v2.h
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+#ifndef __GPIO_REGS_H__
-+#define __GPIO_REGS_H__
-+
-+/* Register offsets */
-+struct gpio_regs {
-+	u32	GPER;
-+	u32	GPERS;
-+	u32	GPERC;
-+	u32	GPERT;
-+	u32	PMR0;
-+	u32	PMR0S;
-+	u32	PMR0C;
-+	u32	PMR0T;
-+	u32	PMR1;
-+	u32	PMR1S;
-+	u32	PMR1C;
-+	u32	PMR1T;
-+	u32	__reserved0[4];
-+	u32	ODER;
-+	u32	ODERS;
-+	u32	ODERC;
-+	u32	ODERT;
-+	u32	OVR;
-+	u32	OVRS;
-+	u32	OVRC;
-+	u32	OVRT;
-+	u32	PVR;
-+	u32	__reserved_PVRS;
-+	u32	__reserved_PVRC;
-+	u32	__reserved_PVRT;
-+	u32	PUER;
-+	u32	PUERS;
-+	u32	PUERC;
-+	u32	PUERT;
-+	u32	PDER;
-+	u32	PDERS;
-+	u32	PDERC;
-+	u32	PDERT;
-+	u32	IER;
-+	u32	IERS;
-+	u32	IERC;
-+	u32	IERT;
-+	u32	IMR0;
-+	u32	IMR0S;
-+	u32	IMR0C;
-+	u32	IMR0T;
-+	u32	IMR1;
-+	u32	IMR1S;
-+	u32	IMR1C;
-+	u32	IMR1T;
-+	u32	GFER;
-+	u32	GFERS;
-+	u32	GFERC;
-+	u32	GFERT;
-+	u32	IFR;
-+	u32	__reserved_IFRS;
-+	u32	IFRC;
-+	u32	__reserved_IFRT;
-+	u32	ODMER;
-+	u32	ODMERS;
-+	u32	ODMERC;
-+	u32	ODMERT;
-+	u32	__reserved1[4];
-+	u32	ODCR0;
-+	u32	ODCR0S;
-+	u32	ODCR0C;
-+	u32	ODCR0T;
-+	u32	ODCR1;
-+	u32	ODCR1S;
-+	u32	ODCR1C;
-+	u32	ODCR1T;
-+	u32	__reserved2[4];
-+	u32	OSRR0;
-+	u32	OSRR0S;
-+	u32	OSRR0C;
-+	u32	OSRR0T;
-+	u32	__reserved3[8];
-+	u32	STER;
-+	u32	STERS;
-+	u32	STERC;
-+	u32	STERT;
-+	u32	__reserved4[35];
-+	u32	VERSION;
-+};
-+
-+/* Register access macros */
-+#define __gpio_regs(bank) ((struct gpio_regs __iomem *)(bank)->regs)
-+#define gpio_readl(bank, reg)						\
-+	__raw_readl(&__gpio_regs(bank)->reg)
-+#define gpio_writel(bank, reg, value)					\
-+	__raw_writel(value, &__gpio_regs(bank)->reg)
-+
-+void at32_gpio_init(struct platform_device *pdev);
-+
-+#endif /* __GPIO_REGS_H__ */
-diff --git a/arch/avr32/mach-at32ap/hmatrix.c b/arch/avr32/mach-at32ap/hmatrix.c
-index 48f5ede..2f55e69 100644
---- a/arch/avr32/mach-at32ap/hmatrix.c
-+++ b/arch/avr32/mach-at32ap/hmatrix.c
-@@ -54,6 +54,81 @@ u32 hmatrix_read_reg(unsigned long offset)
- }
- 
- /**
-+ * hmatrix_set_default_master - set default master on a given slave
-+ * @slave: HSB slave interface ID
-+ * @master: HSB master interface ID
-+ */
-+void hmatrix_set_default_master(unsigned int slave, unsigned int master)
-+{
-+	u32 value;
-+	unsigned int reg;
-+
-+	WARN_ON(slave > HMATRIX_MAX_SLAVE
-+			|| master > HMATRIX_MASTER_LAST);
-+
-+	reg = HMATRIX_SCFG(slave);
-+
-+	clk_enable(&at32_hmatrix_clk);
-+	value = __hmatrix_read_reg(reg);
-+	value &= ~(HMATRIX_SCFG_FIXED_DEFMSTR(HMATRIX_MAX_SLAVE)
-+			| HMATRIX_SCFG_DEFMSTR_MASK);
-+
-+	switch (master) {
-+	case HMATRIX_MASTER_NONE:
-+		value |= HMATRIX_SCFG_DEFMSTR_NONE;
-+		break;
-+	case HMATRIX_MASTER_LAST:
-+		value |= HMATRIX_SCFG_DEFMSTR_LAST;
-+		break;
-+	default:
-+		value |= HMATRIX_SCFG_DEFMSTR_FIXED;
-+		value |= HMATRIX_SCFG_FIXED_DEFMSTR(master);
-+		break;
-+	}
-+
-+	__hmatrix_write_reg(reg, value);
-+	__hmatrix_read_reg(reg);
-+	clk_disable(&at32_hmatrix_clk);
-+}
-+
-+/**
-+ * hmatrix_set_priority - set the priority of a master on a given slave
-+ * @slave: HSB slave interface ID
-+ * @master: HSB master interface ID
-+ * @priority: Priority of @master when competing for access to @slave.
-+ *
-+ * Note that this is currently broken -- we need some way to enable
-+ * fixed-priority arbitration, and that happens to be broken on AP7000
-+ * rev C.
-+ */
-+void hmatrix_set_priority(unsigned int slave, unsigned int master,
-+		unsigned int priority)
-+{
-+	u32 value;
-+	unsigned int reg;
-+
-+	WARN_ON(slave > HMATRIX_MAX_SLAVE
-+			|| master > HMATRIX_MAX_MASTER
-+			|| priority > HMATRIX_MAX_PRIO);
-+
-+	clk_enable(&at32_hmatrix_clk);
-+	if (master < 8) {
-+		reg = HMATRIX_PRAS(slave);
-+		value = __hmatrix_read_reg(reg);
-+		value &= ~HMATRIX_PRAS_PRIO(master, HMATRIX_MAX_PRIO);
-+		value |= HMATRIX_PRAS_PRIO(master, priority);
-+	} else {
-+		reg = HMATRIX_PRBS(slave);
-+		value = __hmatrix_read_reg(reg);
-+		value &= ~HMATRIX_PRBS_PRIO(master, HMATRIX_MAX_PRIO);
-+		value |= HMATRIX_PRBS_PRIO(master, priority);
-+	}
-+	__hmatrix_write_reg(reg, value);
-+	__hmatrix_read_reg(reg);
-+	clk_disable(&at32_hmatrix_clk);
-+}
-+
-+/**
-  * hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
-  * @slave_id: operate on the SFR belonging to this slave
-  * @mask: mask of bits to be set in the SFR
-diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
-index 2875c11..3152e0f 100644
---- a/arch/avr32/mach-at32ap/hsmc.c
-+++ b/arch/avr32/mach-at32ap/hsmc.c
-@@ -229,10 +229,8 @@ static int hsmc_probe(struct platform_device *pdev)
- 	if (IS_ERR(pclk))
- 		return PTR_ERR(pclk);
- 	mck = clk_get(&pdev->dev, "mck");
--	if (IS_ERR(mck)) {
--		ret = PTR_ERR(mck);
--		goto out_put_pclk;
--	}
-+	if (IS_ERR(mck))
-+		mck = pclk;
- 
- 	ret = -ENOMEM;
- 	hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
-@@ -260,8 +258,8 @@ out_disable_clocks:
- 	clk_disable(pclk);
- 	kfree(hsmc);
- out_put_clocks:
--	clk_put(mck);
--out_put_pclk:
-+	if (mck != pclk)
-+		clk_put(mck);
- 	clk_put(pclk);
- 	hsmc = NULL;
- 	return ret;
-diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
-index 1e9852d..5c4c971 100644
---- a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
-+++ b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
-@@ -83,4 +83,135 @@
- #define HMATRIX_BASE	0xfff00800
- #define SDRAMC_BASE	0xfff03800
- 
-+/* LCDC on port C */
-+#define ATMEL_LCDC_PC_CC	(1ULL << 19)
-+#define ATMEL_LCDC_PC_HSYNC	(1ULL << 20)
-+#define ATMEL_LCDC_PC_PCLK	(1ULL << 21)
-+#define ATMEL_LCDC_PC_VSYNC	(1ULL << 22)
-+#define ATMEL_LCDC_PC_DVAL	(1ULL << 23)
-+#define ATMEL_LCDC_PC_MODE	(1ULL << 24)
-+#define ATMEL_LCDC_PC_PWR	(1ULL << 25)
-+#define ATMEL_LCDC_PC_DATA0	(1ULL << 26)
-+#define ATMEL_LCDC_PC_DATA1	(1ULL << 27)
-+#define ATMEL_LCDC_PC_DATA2	(1ULL << 28)
-+#define ATMEL_LCDC_PC_DATA3	(1ULL << 29)
-+#define ATMEL_LCDC_PC_DATA4	(1ULL << 30)
-+#define ATMEL_LCDC_PC_DATA5	(1ULL << 31)
-+
-+/* LCDC on port D */
-+#define ATMEL_LCDC_PD_DATA6	(1ULL << 0)
-+#define ATMEL_LCDC_PD_DATA7	(1ULL << 1)
-+#define ATMEL_LCDC_PD_DATA8	(1ULL << 2)
-+#define ATMEL_LCDC_PD_DATA9	(1ULL << 3)
-+#define ATMEL_LCDC_PD_DATA10	(1ULL << 4)
-+#define ATMEL_LCDC_PD_DATA11	(1ULL << 5)
-+#define ATMEL_LCDC_PD_DATA12	(1ULL << 6)
-+#define ATMEL_LCDC_PD_DATA13	(1ULL << 7)
-+#define ATMEL_LCDC_PD_DATA14	(1ULL << 8)
-+#define ATMEL_LCDC_PD_DATA15	(1ULL << 9)
-+#define ATMEL_LCDC_PD_DATA16	(1ULL << 10)
-+#define ATMEL_LCDC_PD_DATA17	(1ULL << 11)
-+#define ATMEL_LCDC_PD_DATA18	(1ULL << 12)
-+#define ATMEL_LCDC_PD_DATA19	(1ULL << 13)
-+#define ATMEL_LCDC_PD_DATA20	(1ULL << 14)
-+#define ATMEL_LCDC_PD_DATA21	(1ULL << 15)
-+#define ATMEL_LCDC_PD_DATA22	(1ULL << 16)
-+#define ATMEL_LCDC_PD_DATA23	(1ULL << 17)
-+
-+/* LCDC on port E */
-+#define ATMEL_LCDC_PE_CC	(1ULL << (32 + 0))
-+#define ATMEL_LCDC_PE_DVAL	(1ULL << (32 + 1))
-+#define ATMEL_LCDC_PE_MODE	(1ULL << (32 + 2))
-+#define ATMEL_LCDC_PE_DATA0	(1ULL << (32 + 3))
-+#define ATMEL_LCDC_PE_DATA1	(1ULL << (32 + 4))
-+#define ATMEL_LCDC_PE_DATA2	(1ULL << (32 + 5))
-+#define ATMEL_LCDC_PE_DATA3	(1ULL << (32 + 6))
-+#define ATMEL_LCDC_PE_DATA4	(1ULL << (32 + 7))
-+#define ATMEL_LCDC_PE_DATA8	(1ULL << (32 + 8))
-+#define ATMEL_LCDC_PE_DATA9	(1ULL << (32 + 9))
-+#define ATMEL_LCDC_PE_DATA10	(1ULL << (32 + 10))
-+#define ATMEL_LCDC_PE_DATA11	(1ULL << (32 + 11))
-+#define ATMEL_LCDC_PE_DATA12	(1ULL << (32 + 12))
-+#define ATMEL_LCDC_PE_DATA16	(1ULL << (32 + 13))
-+#define ATMEL_LCDC_PE_DATA17	(1ULL << (32 + 14))
-+#define ATMEL_LCDC_PE_DATA18	(1ULL << (32 + 15))
-+#define ATMEL_LCDC_PE_DATA19	(1ULL << (32 + 16))
-+#define ATMEL_LCDC_PE_DATA20	(1ULL << (32 + 17))
-+#define ATMEL_LCDC_PE_DATA21	(1ULL << (32 + 18))
-+
-+
-+#define ATMEL_LCDC(PORT, PIN)	(ATMEL_LCDC_##PORT##_##PIN)
-+
-+
-+#define ATMEL_LCDC_PRI_24B_DATA	(					\
-+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
-+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
-+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
-+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
-+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
-+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
-+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
-+		ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) |	\
-+		ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) |	\
-+		ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) |	\
-+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-+
-+#define ATMEL_LCDC_ALT_24B_DATA (					\
-+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
-+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
-+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
-+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
-+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
-+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
-+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
-+		ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) |	\
-+		ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) |	\
-+		ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) |	\
-+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-+
-+#define ATMEL_LCDC_PRI_15B_DATA (					\
-+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
-+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
-+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
-+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
-+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA16) |	\
-+		ATMEL_LCDC(PD, DATA17) | ATMEL_LCDC(PD, DATA18) |	\
-+		ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20))
-+
-+#define ATMEL_LCDC_ALT_15B_DATA	(					\
-+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
-+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
-+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
-+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
-+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PE, DATA16) |	\
-+		ATMEL_LCDC(PE, DATA17) | ATMEL_LCDC(PE, DATA18) |	\
-+		ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20))
-+
-+#define ATMEL_LCDC_PRI_CONTROL (					\
-+		ATMEL_LCDC(PC, CC)   | ATMEL_LCDC(PC, DVAL) |		\
-+		ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))
-+
-+#define ATMEL_LCDC_ALT_CONTROL (					\
-+		ATMEL_LCDC(PE, CC)   | ATMEL_LCDC(PE, DVAL) |		\
-+		ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))
-+
-+#define ATMEL_LCDC_CONTROL (						\
-+		ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) |		\
-+		ATMEL_LCDC(PC, PCLK))
-+
-+#define ATMEL_LCDC_PRI_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)
-+
-+#define ATMEL_LCDC_ALT_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)
-+
-+#define ATMEL_LCDC_PRI_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)
-+
-+#define ATMEL_LCDC_ALT_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
-+
-+/* Bitmask for all EBI data (D16..D31) pins on port E */
-+#define ATMEL_EBI_PE_DATA_ALL  (0x0000FFFF)
-+
- #endif /* __ASM_ARCH_AT32AP700X_H__ */
-diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap720x.h b/arch/avr32/mach-at32ap/include/mach/at32ap720x.h
-new file mode 100644
-index 0000000..5a3082a
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/include/mach/at32ap720x.h
-@@ -0,0 +1,105 @@
-+/*
-+ * Pin definitions for AT32AP7200
-+ *
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ASM_ARCH_AT32AP7200_H__
-+#define __ASM_ARCH_AT32AP7200_H__
-+
-+#define GPIO_PERIPH_A	0x00
-+#define GPIO_PERIPH_B	0x01
-+#define GPIO_PERIPH_C	0x02
-+#define GPIO_PERIPH_D	0x03
-+
-+#define NR_GPIO_BANKS	8
-+
-+/*
-+ * Pin numbers identifying specific GPIO pins on the chip. They can
-+ * also be converted to IRQ numbers by passing them through
-+ * gpio_to_irq().
-+ */
-+#define GPIO_BASE	(0)
-+
-+#define GPIO_PA_BASE	(GPIO_BASE + 0 * 32)
-+#define GPIO_PB_BASE	(GPIO_BASE + 1 * 32)
-+#define GPIO_PC_BASE	(GPIO_BASE + 2 * 32)
-+#define GPIO_PD_BASE	(GPIO_BASE + 3 * 32)
-+#define GPIO_PE_BASE	(GPIO_BASE + 4 * 32)
-+#define GPIO_PF_BASE	(GPIO_BASE + 5 * 32)
-+#define GPIO_PX_BASE	(GPIO_BASE + 6 * 32)
-+
-+#define GPIO_PIN_PA(N)	(GPIO_PA_BASE + (N))
-+#define GPIO_PIN_PB(N)	(GPIO_PB_BASE + (N))
-+#define GPIO_PIN_PC(N)	(GPIO_PC_BASE + (N))
-+#define GPIO_PIN_PD(N)	(GPIO_PD_BASE + (N))
-+#define GPIO_PIN_PE(N)	(GPIO_PE_BASE + (N))
-+#define GPIO_PIN_PF(N)	(GPIO_PF_BASE + (N))
-+#define GPIO_PIN_PX(N)	(GPIO_PX_BASE + (N))
-+
-+#define gpio_decode_pin(s, bank, offset)				\
-+	do {								\
-+		switch (bank) {						\
-+		case 7:							\
-+			offset += 32;					\
-+			/* fall through */				\
-+		case 6:							\
-+			seq_printf(s, "PX%-2u", offset);		\
-+			break;						\
-+		default:						\
-+			seq_printf(s, "P%c%-2u", bank + 'A', offset);	\
-+			break;						\
-+		}							\
-+	} while (0)
-+
-+/* HSB master IDs */
-+#define HMATRIX_MASTER_CPU_ICACHE		 0
-+#define HMATRIX_MASTER_CPU_DCACHE		 1
-+#define HMATRIX_MASTER_PDCA			 2
-+#define HMATRIX_MASTER_LCDC			 4
-+#define HMATRIX_MASTER_MPOP_IBI			 5
-+#define HMATRIX_MASTER_MPOP_OBI			 6
-+#define HMATRIX_MASTER_MPOP_OM			 7
-+#define HMATRIX_MASTER_DMACA_M0			 8
-+#define HMATRIX_MASTER_DMACA_M1			 9
-+#define HMATRIX_MASTER_USBB			10
-+#define HMATRIX_MASTER_USBH_EHCI		11
-+#define HMATRIX_MASTER_USBH_OHCI		12
-+#define HMATRIX_MASTER_MACB			13
-+
-+/* HSB slave IDs */
-+#define HMATRIX_SLAVE_BOOTROM			 0
-+#define HMATRIX_SLAVE_PBA			 1
-+#define HMATRIX_SLAVE_PBB			 2
-+#define HMATRIX_SLAVE_PBC			 3
-+#define HMATRIX_SLAVE_SRAM0			 4
-+#define HMATRIX_SLAVE_SRAM1			 5
-+#define HMATRIX_SLAVE_EBI			 6
-+#define HMATRIX_SLAVE_LCDC			 7
-+#define HMATRIX_SLAVE_MPOP			 8
-+#define HMATRIX_SLAVE_DMACA			 9
-+#define HMATRIX_SLAVE_USBB			10
-+#define HMATRIX_SLAVE_EHCI			11
-+#define HMATRIX_SLAVE_OHCI			12
-+
-+/* Bits in HMATRIX SFR6 (EBI) */
-+#define HMATRIX_EBI_SDRAM_ENABLE		(1 << 1)
-+#define HMATRIX_EBI_NAND_ENABLE			(1 << 3)
-+#define HMATRIX_EBI_CF0_ENABLE			(1 << 4)
-+#define HMATRIX_EBI_CF1_ENABLE			(1 << 5)
-+
-+/*
-+ * Base addresses of controllers that may be accessed early by
-+ * platform code.
-+ */
-+#define GPIO_HW_BASE	0xffd02000
-+#define INTC_BASE	0xffd00000
-+#define PM_BASE		0xffd00400
-+#define SDC_BASE	0xffd00800
-+#define SDRAMC_BASE	0xffe04800
-+#define HMATRIX_BASE	0xffe05000
-+
-+#endif /* __ASM_ARCH_AT32AP7200_H__ */
-diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
-index e60e907..85441ff 100644
---- a/arch/avr32/mach-at32ap/include/mach/board.h
-+++ b/arch/avr32/mach-at32ap/include/mach/board.h
-@@ -14,8 +14,14 @@
-  */
- extern unsigned long at32_board_osc_rates[];
-   
--/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
--void at32_add_system_devices(void);
-+/*
-+ * This used to add essential system devices, but this is now done
-+ * automatically. Please don't use it in new board code.
-+ */
-+static inline void __deprecated at32_add_system_devices(void)
-+{
-+
-+}
- 
- #define ATMEL_MAX_UART	4
- extern struct platform_device *atmel_default_console_device;
-@@ -43,12 +49,20 @@ struct atmel_lcdfb_info;
- struct platform_device *
- at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- 		     unsigned long fbmem_start, unsigned long fbmem_len,
--		     unsigned int pin_config);
-+		     u64 pin_mask);
-+
-+
-+struct platform_device *
-+at32_add_device_mpop(unsigned int id, struct platform_device *lcdc_pdev,
-+		     unsigned long fbmem_start, unsigned long fbmem_len);
- 
- struct usba_platform_data;
- struct platform_device *
- at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
- 
-+struct platform_device *at32_add_device_ohci(unsigned int id);
-+struct platform_device *at32_add_device_ehci(unsigned int id);
-+
- struct ide_platform_data {
- 	u8      cs;
- };
-diff --git a/arch/avr32/mach-at32ap/include/mach/chip.h b/arch/avr32/mach-at32ap/include/mach/chip.h
-index 5efca6d..09c0fe7 100644
---- a/arch/avr32/mach-at32ap/include/mach/chip.h
-+++ b/arch/avr32/mach-at32ap/include/mach/chip.h
-@@ -12,6 +12,8 @@
- 
- #if defined(CONFIG_CPU_AT32AP700X)
- # include <mach/at32ap700x.h>
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# include <mach/at32ap720x.h>
- #else
- # error Unknown chip type selected
- #endif
-diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h
-index 44d0bfa..f4a5f26 100644
---- a/arch/avr32/mach-at32ap/include/mach/cpu.h
-+++ b/arch/avr32/mach-at32ap/include/mach/cpu.h
-@@ -20,6 +20,19 @@
- # define cpu_is_at32ap7000()	(0)
- #endif
- 
-+#ifdef CONFIG_CPU_AT32AP720X
-+# define cpu_is_at32ap7200()	(1)
-+#else
-+# define cpu_is_at32ap7200()	(0)
-+#endif
-+
-+/*
-+ * Unfortunately, only AP700x has a non-broken COUNT/COMPARE
-+ * implementation. Other chips need to use different timers. The good
-+ * news is that these timers are usually better anyway.
-+ */
-+#define cpu_has_working_compare()	(cpu_is_at32ap7000())
-+
- /*
-  * Since this is AVR32, we will never run on any AT91 CPU. But these
-  * definitions may reduce clutter in common drivers.
-diff --git a/arch/avr32/mach-at32ap/include/mach/hmatrix.h b/arch/avr32/mach-at32ap/include/mach/hmatrix.h
-index 7a368f2..8417737 100644
---- a/arch/avr32/mach-at32ap/include/mach/hmatrix.h
-+++ b/arch/avr32/mach-at32ap/include/mach/hmatrix.h
-@@ -15,6 +15,9 @@ extern struct clk at32_hmatrix_clk;
- void hmatrix_write_reg(unsigned long offset, u32 value);
- u32 hmatrix_read_reg(unsigned long offset);
- 
-+void hmatrix_set_default_master(unsigned int slave, unsigned int master);
-+void hmatrix_set_priority(unsigned int slave, unsigned int master,
-+		unsigned int priority);
- void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask);
- void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- 
-@@ -33,6 +36,7 @@ void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- # define HMATRIX_SCFG_DEFMSTR_NONE	(  0 << 16)	/* No default master */
- # define HMATRIX_SCFG_DEFMSTR_LAST	(  1 << 16)	/* Last def master */
- # define HMATRIX_SCFG_DEFMSTR_FIXED	(  2 << 16)	/* Fixed def master */
-+# define HMATRIX_SCFG_DEFMSTR_MASK	(  3 << 16)
- # define HMATRIX_SCFG_FIXED_DEFMSTR(m)	((m) << 18)	/* Fixed master ID */
- # define HMATRIX_SCFG_ARBT_ROUND_ROBIN	(  0 << 24)	/* RR arbitration */
- # define HMATRIX_SCFG_ARBT_FIXED_PRIO	(  1 << 24)	/* Fixed priority */
-@@ -52,4 +56,12 @@ void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- /* Special Function Register. Bit definitions are chip-specific */
- #define HMATRIX_SFR(s)			(0x0110 + 4 * (s))
- 
-+#define HMATRIX_MAX_SLAVE	15
-+#define HMATRIX_MAX_MASTER	15
-+#define HMATRIX_MAX_PRIO	15
-+
-+/* Special master IDs for use with hmatrix_set_default_master() */
-+#define HMATRIX_MASTER_NONE	16	/* No default master */
-+#define HMATRIX_MASTER_LAST	17	/* Last master stays connected */
-+
- #endif /* __HMATRIX_H */
-diff --git a/arch/avr32/mach-at32ap/include/mach/init.h b/arch/avr32/mach-at32ap/include/mach/init.h
-index bc40e3d..66a6866 100644
---- a/arch/avr32/mach-at32ap/include/mach/init.h
-+++ b/arch/avr32/mach-at32ap/include/mach/init.h
-@@ -15,4 +15,10 @@ void setup_board(void);
- 
- void at32_setup_serial_console(unsigned int usart_id);
- 
-+/*
-+ * Called from time_init() when a broken COUNT/COMPARE implementation
-+ * is detected.
-+ */
-+void platform_time_init(void);
-+
- #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
-diff --git a/arch/avr32/mach-at32ap/include/mach/io.h b/arch/avr32/mach-at32ap/include/mach/io.h
-index 4ec6abc..22ea79b 100644
---- a/arch/avr32/mach-at32ap/include/mach/io.h
-+++ b/arch/avr32/mach-at32ap/include/mach/io.h
-@@ -1,8 +1,7 @@
- #ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
- #define __ASM_AVR32_ARCH_AT32AP_IO_H
- 
--/* For "bizarre" halfword swapping */
--#include <linux/byteorder/swabb.h>
-+#include <linux/swab.h>
- 
- #if defined(CONFIG_AP700X_32_BIT_SMC)
- # define __swizzle_addr_b(addr)	(addr ^ 3UL)
-diff --git a/arch/avr32/mach-at32ap/include/mach/irq.h b/arch/avr32/mach-at32ap/include/mach/irq.h
-index 608e350..21f37f3 100644
---- a/arch/avr32/mach-at32ap/include/mach/irq.h
-+++ b/arch/avr32/mach-at32ap/include/mach/irq.h
-@@ -6,7 +6,7 @@
- #define AT32_EXTINT(n)	(EIM_IRQ_BASE + (n))
- 
- #define GPIO_IRQ_BASE	(EIM_IRQ_BASE + NR_EIM_IRQS)
--#define NR_GPIO_CTLR	(5 /*internal*/ + 1 /*external*/)
-+#define NR_GPIO_CTLR	(8 /*internal*/ + 1 /*external*/)
- #define NR_GPIO_IRQS	(NR_GPIO_CTLR * 32)
- 
- #define NR_IRQS		(GPIO_IRQ_BASE + NR_GPIO_IRQS)
-diff --git a/arch/avr32/mach-at32ap/include/mach/pm.h b/arch/avr32/mach-at32ap/include/mach/pm.h
-index 979b355..3f65ab1 100644
---- a/arch/avr32/mach-at32ap/include/mach/pm.h
-+++ b/arch/avr32/mach-at32ap/include/mach/pm.h
-@@ -11,13 +11,17 @@
- #define __ASM_AVR32_ARCH_PM_H
- 
- /* Possible arguments to the "sleep" instruction */
--#define CPU_SLEEP_IDLE		0
--#define CPU_SLEEP_FROZEN	1
--#define CPU_SLEEP_STANDBY	2
--#define CPU_SLEEP_STOP		3
--#define CPU_SLEEP_STATIC	5
-+#define CPU_SLEEP_IDLE		0x00
-+#define CPU_SLEEP_FROZEN	0x01
-+#define CPU_SLEEP_STANDBY	0x02
-+#define CPU_SLEEP_STOP		0x03
-+#define CPU_SLEEP_DEEPSTOP	0x04	/* Not valid on AP700x */
-+#define CPU_SLEEP_STATIC	0x05
-+#define CPU_SLEEP_SHUTDOWN	0x06	/* Not valid on AP700x */
-+#define CPU_SLEEP_UNMASK_IRQ	0x80	/* Not valid on AP700x */
- 
- #ifndef __ASSEMBLY__
-+#if defined(CONFIG_CPU_AT32AP700X)
- extern void cpu_enter_idle(void);
- extern void cpu_enter_standby(unsigned long sdramc_base);
- 
-@@ -37,15 +41,57 @@ static inline void cpu_idle_sleep(void)
- {
- 	/*
- 	 * If we're using the COUNT and COMPARE registers for
--	 * timekeeping, we can't use the IDLE state.
-+	 * timekeeping on AP7000, we can't use the IDLE state.
- 	 */
- 	if (disable_idle_sleep)
- 		cpu_relax();
- 	else
- 		cpu_enter_idle();
- }
-+#else
-+static inline void cpu_disable_idle_sleep(void)
-+{
-+
-+}
-+
-+static inline void cpu_enable_idle_sleep(void)
-+{
-+
-+}
-+
-+static inline void cpu_enter_idle(void)
-+{
-+	/* Enable interrupts and sleep */
-+	asm volatile("sleep %0"
-+			:
-+			: "i"(CPU_SLEEP_IDLE | CPU_SLEEP_UNMASK_IRQ)
-+			: "memory");
-+}
-+
-+static inline void cpu_idle_sleep(void)
-+{
-+	local_irq_disable();
-+	if (!test_thread_flag(TIF_NEED_RESCHED))
-+		cpu_enter_idle();
-+	local_irq_enable();
-+}
-+#endif
- 
- void intc_set_suspend_handler(unsigned long offset);
-+
-+extern unsigned long at32_get_reset_cause(void);
-+
- #endif
- 
-+#define AT32_RCAUSE_POR		(1 <<  0)	/* Power-On Reset */
-+#define AT32_RCAUSE_BOD		(1 <<  1)	/* Brown-Out Detected */
-+#define AT32_RCAUSE_EXT		(1 <<  2)	/* External Reset */
-+#define AT32_RCAUSE_WDT		(1 <<  3)	/* Watchdog Timeout */
-+#define AT32_RCAUSE_JTAG	(1 <<  4)	/* JTAG Reset */
-+#define AT32_RCAUSE_NTAE	(1 <<  5)	/* NanoTrace Access Error */
-+#define AT32_RCAUSE_SLEEP	(1 <<  6)	/* Shutdown or Static mode */
-+#define AT32_RCAUSE_CPUERR	(1 <<  7)	/* CPU Error */
-+#define AT32_RCAUSE_OCDRST	(1 <<  8)	/* OCD Reset */
-+#define AT32_RCAUSE_JTAGHARD	(1 <<  9)	/* JTAG Hard Reset */
-+
- #endif /* __ASM_AVR32_ARCH_PM_H */
-diff --git a/arch/avr32/mach-at32ap/include/mach/portmux.h b/arch/avr32/mach-at32ap/include/mach/portmux.h
-index b1abe6b..4873024 100644
---- a/arch/avr32/mach-at32ap/include/mach/portmux.h
-+++ b/arch/avr32/mach-at32ap/include/mach/portmux.h
-@@ -21,9 +21,10 @@
- #define AT32_GPIOF_DEGLITCH	0x00000008	/* (IN) Filter glitches */
- #define AT32_GPIOF_MULTIDRV	0x00000010	/* Enable multidriver option */
- 
--void at32_select_periph(unsigned int pin, unsigned int periph,
--			unsigned long flags);
-+void at32_select_periph(unsigned int port, unsigned int pin,
-+			unsigned int periph, unsigned long flags);
- void at32_select_gpio(unsigned int pin, unsigned long flags);
--void at32_reserve_pin(unsigned int pin);
-+void at32_deselect_pin(unsigned int pin);
-+void at32_reserve_pin(unsigned int port, u32 pin_mask);
- 
- #endif /* __ASM_ARCH_PORTMUX_H__ */
-diff --git a/arch/avr32/mach-at32ap/pdc.c b/arch/avr32/mach-at32ap/pdc.c
-index 1040bda..61ab15a 100644
---- a/arch/avr32/mach-at32ap/pdc.c
-+++ b/arch/avr32/mach-at32ap/pdc.c
-@@ -35,7 +35,6 @@ static int __init pdc_probe(struct platform_device *pdev)
- }
- 
- static struct platform_driver pdc_driver = {
--	.probe		= pdc_probe,
- 	.driver		= {
- 		.name	= "pdc",
- 	},
-@@ -43,6 +42,6 @@ static struct platform_driver pdc_driver = {
- 
- static int __init pdc_init(void)
- {
--	return platform_driver_register(&pdc_driver);
-+	return platform_driver_probe(&pdc_driver, pdc_probe);
- }
- arch_initcall(pdc_init);
-diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
-index 405ee6b..09a274c 100644
---- a/arch/avr32/mach-at32ap/pio.c
-+++ b/arch/avr32/mach-at32ap/pio.c
-@@ -50,35 +50,48 @@ static struct pio_device *gpio_to_pio(unsigned int gpio)
- }
- 
- /* Pin multiplexing API */
-+static DEFINE_SPINLOCK(pio_lock);
- 
--void __init at32_select_periph(unsigned int pin, unsigned int periph,
--			       unsigned long flags)
-+void __init at32_select_periph(unsigned int port, u32 pin_mask,
-+			       unsigned int periph, unsigned long flags)
- {
- 	struct pio_device *pio;
--	unsigned int pin_index = pin & 0x1f;
--	u32 mask = 1 << pin_index;
- 
--	pio = gpio_to_pio(pin);
-+	/* assign and verify pio */
-+	pio = gpio_to_pio(port);
- 	if (unlikely(!pio)) {
--		printk("pio: invalid pin %u\n", pin);
-+		printk(KERN_WARNING "pio: invalid port %u\n", port);
- 		goto fail;
- 	}
- 
--	if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask)
--			 || gpiochip_is_requested(&pio->chip, pin_index))) {
--		printk("%s: pin %u is busy\n", pio->name, pin_index);
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&pio_lock);
-+	if (unlikely(pio->pinmux_mask & pin_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
-+		       pio->name, pin_mask, pio->pinmux_mask & pin_mask);
-+		spin_unlock(&pio_lock);
- 		goto fail;
- 	}
- 
--	pio_writel(pio, PUER, mask);
-+	pio->pinmux_mask |= pin_mask;
-+
-+	/* enable pull ups */
-+	pio_writel(pio, PUER, pin_mask);
-+
-+	/* select either peripheral A or B */
- 	if (periph)
--		pio_writel(pio, BSR, mask);
-+		pio_writel(pio, BSR, pin_mask);
- 	else
--		pio_writel(pio, ASR, mask);
-+		pio_writel(pio, ASR, pin_mask);
- 
--	pio_writel(pio, PDR, mask);
-+	/* enable peripheral control */
-+	pio_writel(pio, PDR, pin_mask);
-+
-+	/* Disable pull ups if not requested. */
- 	if (!(flags & AT32_GPIOF_PULLUP))
--		pio_writel(pio, PUDR, mask);
-+		pio_writel(pio, PUDR, pin_mask);
-+
-+	spin_unlock(&pio_lock);
- 
- 	return;
- 
-@@ -134,8 +147,11 @@ fail:
- 	dump_stack();
- }
- 
--/* Reserve a pin, preventing anyone else from changing its configuration. */
--void __init at32_reserve_pin(unsigned int pin)
-+/*
-+ * Undo a previous pin reservation. Will not affect the hardware
-+ * configuration.
-+ */
-+void at32_deselect_pin(unsigned int pin)
- {
- 	struct pio_device *pio;
- 	unsigned int pin_index = pin & 0x1f;
-@@ -143,14 +159,37 @@ void __init at32_reserve_pin(unsigned int pin)
- 	pio = gpio_to_pio(pin);
- 	if (unlikely(!pio)) {
- 		printk("pio: invalid pin %u\n", pin);
-+		dump_stack();
-+		return;
-+	}
-+
-+	clear_bit(pin_index, &pio->pinmux_mask);
-+}
-+
-+/* Reserve a pin, preventing anyone else from changing its configuration. */
-+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
-+{
-+	struct pio_device *pio;
-+
-+	/* assign and verify pio */
-+	pio = gpio_to_pio(port);
-+	if (unlikely(!pio)) {
-+		printk(KERN_WARNING "pio: invalid port %u\n", port);
- 		goto fail;
- 	}
- 
--	if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
--		printk("%s: pin %u is busy\n", pio->name, pin_index);
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&pio_lock);
-+	if (unlikely(pio->pinmux_mask & pin_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
-+		       pio->name, pin_mask, pio->pinmux_mask & pin_mask);
-+		spin_unlock(&pio_lock);
- 		goto fail;
- 	}
- 
-+	/* Reserve pins */
-+	pio->pinmux_mask |= pin_mask;
-+	spin_unlock(&pio_lock);
- 	return;
- 
- fail:
-@@ -382,7 +421,6 @@ static int __init pio_probe(struct platform_device *pdev)
- }
- 
- static struct platform_driver pio_driver = {
--	.probe		= pio_probe,
- 	.driver		= {
- 		.name		= "pio",
- 	},
-@@ -390,7 +428,7 @@ static struct platform_driver pio_driver = {
- 
- static int __init pio_init(void)
- {
--	return platform_driver_register(&pio_driver);
-+	return platform_driver_probe(&pio_driver, pio_probe);
- }
- postcore_initcall(pio_init);
- 
-diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
-index 17503b0..3d210f8 100644
---- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
-+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
-@@ -12,12 +12,9 @@
- #include <asm/thread_info.h>
- #include <mach/pm.h>
- 
--#include "pm.h"
-+#include "pm-v1.h"
- #include "sdramc.h"
- 
--/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
--#define PM_BASE	-0x100000
--
- 	.section .bss, "wa", @nobits
- 	.global	disable_idle_sleep
- 	.type	disable_idle_sleep, @object
-diff --git a/arch/avr32/mach-at32ap/pm-at32ap720x.S b/arch/avr32/mach-at32ap/pm-at32ap720x.S
-new file mode 100644
-index 0000000..a765aa5
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-at32ap720x.S
-@@ -0,0 +1,110 @@
-+/*
-+ * Low-level Power Management code.
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <asm/asm.h>
-+#include <asm/asm-offsets.h>
-+#include <asm/thread_info.h>
-+#include <mach/pm.h>
-+
-+#include "pm-v3.h"
-+#include "sdramc.h"
-+
-+#ifdef CONFIG_PM
-+	.section .init.text, "ax", @progbits
-+
-+	.global	pm_exception
-+	.type	pm_exception, @function
-+pm_exception:
-+	/*
-+	 * Exceptions are masked when we switch to this handler, so
-+	 * we'll only get "unrecoverable" exceptions (offset 0.)
-+	 */
-+	sub	r12, pc, . - .Lpanic_msg
-+	lddpc	pc, .Lpanic_addr
-+
-+	.align	2
-+.Lpanic_addr:
-+	.long	panic
-+.Lpanic_msg:
-+	.asciz	"Unrecoverable exception during suspend\n"
-+	.size	pm_exception, . - pm_exception
-+
-+	.global	pm_irq0
-+	.type	pm_irq0, @function
-+pm_irq0:
-+	/* Disable interrupts and return after the sleep instruction */
-+	mfsr	r9, SYSREG_RSR_INT0
-+	mtsr	SYSREG_RAR_INT0, r8
-+	sbr	r9, SYSREG_GM_OFFSET
-+	mtsr	SYSREG_RSR_INT0, r9
-+	rete
-+
-+	/*
-+	 * void cpu_enter_standby(unsigned long sdramc_base)
-+	 *
-+	 * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
-+	 * are suspended and interrupts are disabled. Interrupts
-+	 * marked as 'wakeup' event sources may still come along and
-+	 * get us out of here.
-+	 *
-+	 * The SDRAM will be put into self-refresh mode (which does
-+	 * not require a clock from the CPU), and the CPU will be put
-+	 * into "frozen" mode (HSB bus stopped). The SDRAM controller
-+	 * will automatically bring the SDRAM into normal mode on the
-+	 * first access, and the power manager will automatically
-+	 * start the HSB and CPU clocks upon a wakeup event.
-+	 */
-+	.global	pm_standby
-+	.type	pm_standby, @function
-+pm_standby:
-+	/*
-+	 * interrupts are already masked at this point, and EVBA
-+	 * points to pm_exception above.
-+	 */
-+	ld.w	r10, r12[SDRAMC_LPR]
-+	sub	r8, pc, . - 1f		/* return address for irq handler */
-+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
-+	bfins	r10, r11, 0, 2		/* LPCB <- self Refresh */
-+	sync	0			/* flush write buffer */
-+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
-+	ld.w	r11, r12[SDRAMC_LPR]
-+	sleep	CPU_SLEEP_FROZEN | CPU_SLEEP_UNMASK_IRQ
-+1:	mask_interrupts
-+	retal	r12
-+	.size	pm_standby, . - pm_standby
-+
-+	.global	pm_suspend_to_ram
-+	.type	pm_suspend_to_ram, @function
-+pm_suspend_to_ram:
-+	/*
-+	 * interrupts are already masked at this point, and EVBA
-+	 * points to pm_exception above.
-+	 */
-+	mov	r11, 0
-+	cache	r11[2], 8		/* clean all dcache lines */
-+	sync	0			/* flush write buffer */
-+	ld.w	r10, r12[SDRAMC_LPR]
-+	sub	r8, pc, . - 1f		/* return address for irq handler */
-+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
-+	bfins	r10, r11, 0, 2		/* LPCB <- self refresh */
-+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
-+	ld.w	r11, r12[SDRAMC_LPR]
-+
-+	sleep	CPU_SLEEP_STOP | CPU_SLEEP_UNMASK_IRQ
-+1:	mask_interrupts
-+
-+	retal	r12
-+	.size	pm_suspend_to_ram, . - pm_suspend_to_ram
-+
-+	.global	pm_sram_end
-+	.type	pm_sram_end, @function
-+pm_sram_end:
-+	.size	pm_sram_end, 0
-+
-+#endif /* CONFIG_PM */
-diff --git a/arch/avr32/mach-at32ap/pm-v1.h b/arch/avr32/mach-at32ap/pm-v1.h
-new file mode 100644
-index 0000000..532a373
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-v1.h
-@@ -0,0 +1,112 @@
-+/*
-+ * Register definitions for the Power Manager (PM)
-+ */
-+#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
-+#define __ARCH_AVR32_MACH_AT32AP_PM_H__
-+
-+/* PM register offsets */
-+#define PM_MCCTRL				0x0000
-+#define PM_CKSEL				0x0004
-+#define PM_CPU_MASK				0x0008
-+#define PM_HSB_MASK				0x000c
-+#define PM_PBA_MASK				0x0010
-+#define PM_PBB_MASK				0x0014
-+#define PM_PLL0					0x0020
-+#define PM_PLL1					0x0024
-+#define PM_IER					0x0040
-+#define PM_IDR					0x0044
-+#define PM_IMR					0x0048
-+#define PM_ISR					0x004c
-+#define PM_ICR					0x0050
-+#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
-+#define PM_RCAUSE				0x00c0
-+
-+/* Bitfields in CKSEL */
-+#define PM_CPUSEL_OFFSET			0
-+#define PM_CPUSEL_SIZE				3
-+#define PM_CPUDIV_OFFSET			7
-+#define PM_CPUDIV_SIZE				1
-+#define PM_HSBSEL_OFFSET			8
-+#define PM_HSBSEL_SIZE				3
-+#define PM_HSBDIV_OFFSET			15
-+#define PM_HSBDIV_SIZE				1
-+#define PM_PBASEL_OFFSET			16
-+#define PM_PBASEL_SIZE				3
-+#define PM_PBADIV_OFFSET			23
-+#define PM_PBADIV_SIZE				1
-+#define PM_PBBSEL_OFFSET			24
-+#define PM_PBBSEL_SIZE				3
-+#define PM_PBBDIV_OFFSET			31
-+#define PM_PBBDIV_SIZE				1
-+
-+/* Bitfields in PLL0 */
-+#define PM_PLLEN_OFFSET				0
-+#define PM_PLLEN_SIZE				1
-+#define PM_PLLOSC_OFFSET			1
-+#define PM_PLLOSC_SIZE				1
-+#define PM_PLLOPT_OFFSET			2
-+#define PM_PLLOPT_SIZE				3
-+#define PM_PLLDIV_OFFSET			8
-+#define PM_PLLDIV_SIZE				8
-+#define PM_PLLMUL_OFFSET			16
-+#define PM_PLLMUL_SIZE				8
-+#define PM_PLLCOUNT_OFFSET			24
-+#define PM_PLLCOUNT_SIZE			6
-+#define PM_PLLTEST_OFFSET			31
-+#define PM_PLLTEST_SIZE				1
-+
-+/* Bitfields in ICR */
-+#define PM_LOCK0_OFFSET				0
-+#define PM_LOCK0_SIZE				1
-+#define PM_LOCK1_OFFSET				1
-+#define PM_LOCK1_SIZE				1
-+#define PM_WAKE_OFFSET				2
-+#define PM_WAKE_SIZE				1
-+#define PM_CKRDY_OFFSET				5
-+#define PM_CKRDY_SIZE				1
-+#define PM_MSKRDY_OFFSET			6
-+#define PM_MSKRDY_SIZE				1
-+
-+/* Bitfields in GCCTRL0 */
-+#define PM_OSCSEL_OFFSET			0
-+#define PM_OSCSEL_SIZE				1
-+#define PM_PLLSEL_OFFSET			1
-+#define PM_PLLSEL_SIZE				1
-+#define PM_CEN_OFFSET				2
-+#define PM_CEN_SIZE				1
-+#define PM_DIVEN_OFFSET				4
-+#define PM_DIVEN_SIZE				1
-+#define PM_DIV_OFFSET				8
-+#define PM_DIV_SIZE				8
-+
-+/* Bitfields in RCAUSE */
-+#define PM_POR_OFFSET				0
-+#define PM_POR_SIZE				1
-+#define PM_EXT_OFFSET				2
-+#define PM_EXT_SIZE				1
-+#define PM_WDT_OFFSET				3
-+#define PM_WDT_SIZE				1
-+#define PM_NTAE_OFFSET				4
-+#define PM_NTAE_SIZE				1
-+
-+/* Bit manipulation macros */
-+#define PM_BIT(name)					\
-+	(1 << PM_##name##_OFFSET)
-+#define PM_BF(name,value)				\
-+	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
-+	 << PM_##name##_OFFSET)
-+#define PM_BFEXT(name,value)				\
-+	(((value) >> PM_##name##_OFFSET)		\
-+	 & ((1 << PM_##name##_SIZE) - 1))
-+#define PM_BFINS(name,value,old)\
-+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
-+		    << PM_##name##_OFFSET))		\
-+	 | PM_BF(name,value))
-+
-+/* Register access macros */
-+#define pm_readl(reg)							\
-+	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
-+#define pm_writel(reg,value)						\
-+	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
-+
-+#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
-diff --git a/arch/avr32/mach-at32ap/pm-v3.h b/arch/avr32/mach-at32ap/pm-v3.h
-new file mode 100644
-index 0000000..3c507b9
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-v3.h
-@@ -0,0 +1,283 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __PM_V3_H__
-+#define __PM_V3_H__
-+
-+#include <mach/chip.h>
-+
-+/* PM Register offsets */
-+#ifndef __ASSEMBLY__
-+struct pm_regs {
-+	u32	MCCTRL;			/* Main Clock Control */
-+	u32	CKSEL;			/* Clock Select */
-+	u32	CPUMASK;		/* CPU Clock Mask */
-+	u32	HSBMASK;		/* HSB Clock Mask */
-+	u32	PBAMASK;		/* PBA Clock Mask */
-+	u32	PBBMASK;		/* PBB Clock Mask */
-+	u32	PBADIVMASK;		/* Divided PBA Clock Mask */
-+	u32	PBBDIVMASK;		/* Divided PBB Clock Mask */
-+	u32	__reserved1[8];
-+	u32	PLL[3];			/* PLL Control */
-+	u32	__reserved2[13];
-+	u32	OSCCTRL[3];		/* Oscillator Control */
-+	u32	__reserved3[5];
-+	u32	OSCCTRL32;		/* 32 kHz Oscillator Control */
-+	u32	__reserved4[7];
-+	u32	IER;			/* Interrupt Enable */
-+	u32	IDR;			/* Interrupt Disable */
-+	u32	IMR;			/* Interrupt Mask */
-+	u32	ISR;			/* Interrupt Status */
-+	u32	ICR;			/* Interrupt Clear */
-+	u32	POSCSR;			/* Power and Oscillator Status */
-+	u32	__reserved5[10];
-+	u32	GCCTRL[8];		/* Generic Clock Control */
-+	u32	__reserved6[8];
-+	u32	RCCR;			/* RC Oscillator Calibration */
-+	u32	BGCR;			/* Bandgap Calibration */
-+	u32	VREGCR;			/* Buck Regulator Calibration */
-+	u32	BOD;			/* BOD Level */
-+	u32	PPCR;			/* Peripheral Power Control */
-+	u32	__reserved7[11];
-+	u32	RCAUSE;			/* Reset Cause */
-+	u32	WCAUSE;			/* Wake Cause */
-+	u32	AWEN;			/* Asynchronous Wake Enable */
-+	u32	__reserved8[14];
-+	u32	GPLP;			/* General Purpose Low-Power */
-+};
-+#endif
-+
-+/* Assembly-friendly register offsets; same as above */
-+#define PM_MCCTRL			0x0000
-+#define PM_CKSEL			0x0004
-+#define PM_CPUMASK			0x0008
-+#define PM_HSBMASK			0x000c
-+#define PM_PBAMASK			0x0010
-+#define PM_PBBMASK			0x0014
-+#define PM_PBADIVMASK			0x0018
-+#define PM_PBBDIVMASK			0x001c
-+#define PM_PLL0				0x0040
-+#define PM_PLL1				0x0044
-+#define PM_PLL2				0x0048
-+#define PM_OSCCTRL0			0x0080
-+#define PM_OSCCTRL1			0x0084
-+#define PM_OSCCTRL2			0x0088
-+#define PM_OSCCTRL32			0x00a0
-+#define PM_IER				0x00c0
-+#define PM_IDR				0x00c4
-+#define PM_IMR				0x00c8
-+#define PM_ISR				0x00cc
-+#define PM_ICR				0x00d0
-+#define PM_POSCSR			0x00d4
-+#define PM_GCCTRL			0x0100
-+#define PM_RCCR				0x0140
-+#define PM_BGCR				0x0144
-+#define PM_VREGCR			0x0148
-+#define PM_BOD				0x014c
-+#define PM_PPCR				0x0150
-+#define PM_RC_RCAUSE			0x0180
-+#define PM_WCAUSE			0x0184
-+#define PM_AWEN				0x0188
-+#define PM_GPLP				0x01c0
-+
-+/* Bits in MCCTRL */
-+#define PM_MCCTRL_MCSEL_START		0
-+#define PM_MCCTRL_MCSEL_SIZE		2
-+#define PM_MCCTRL_OSC0EN_BIT		2
-+#define PM_MCCTRL_OSC1EN_BIT		3
-+#define PM_MCCTRL_OSC2EN_BIT		4
-+#define PM_MCCTRL_CRIPEL_BIT		24
-+
-+/* Bits in CKSEL */
-+#define PM_CKSEL_CPUSEL_START		0
-+#define PM_CKSEL_CPUSEL_SIZE		3
-+#define PM_CKSEL_CPUDIV_BIT		7
-+#define PM_CKSEL_HSBSEL_START		8
-+#define PM_CKSEL_HSBSEL_SIZE		3
-+#define PM_CKSEL_HSBDIV_BIT		15
-+#define PM_CKSEL_PBASEL_START		16
-+#define PM_CKSEL_PBASEL_SIZE		3
-+#define PM_CKSEL_PBADIV_BIT		23
-+#define PM_CKSEL_PBBSEL_START		24
-+#define PM_CKSEL_PBBSEL_SIZE		3
-+#define PM_CKSEL_PBBDIV_BIT		31
-+
-+/* Bits in CPUMASK */
-+#define PM_CPUMASK_SYSTIMER_BIT		16
-+
-+/* Bits in PLLx */
-+#define PM_PLLx_PLLEN_BIT		0
-+#define PM_PLLx_PLLOSC_START		1
-+#define PM_PLLx_PLLOSC_SIZE		2
-+#define PM_PLLx_PLLOPT_START		3
-+#define PM_PLLx_PLLOPT_SIZE		3
-+#define PM_PLLx_PLLBPL_BIT		7
-+#define PM_PLLx_PLLDIV_START		8
-+#define PM_PLLx_PLLDIV_SIZE		6
-+#define PM_PLLx_PLLMUL_START		16
-+#define PM_PLLx_PLLMUL_SIZE		6
-+#define PM_PLLx_PLLCOUNT_START		24
-+#define PM_PLLx_PLLCOUNT_SIZE		6
-+#define PM_PLLx_PLLIOTESTEN_BIT		30
-+#define PM_PLLx_PLLTEST_BIT		31
-+
-+/* Bits in OSCCTRLx */
-+#define PM_OSCCTRLx_MODE_START		0
-+#define PM_OSCCTRLx_MODE_SIZE		4
-+#define PM_OSCCTRLx_STARTUP_START	8
-+#define PM_OSCCTRLx_STARTUP_SIZE	3
-+
-+/* Bits in OSCCTRL32 */
-+#define PM_OSCCTRL32_OSC32EN_BIT	0
-+#define PM_OSCCTRL32_MODE_START		8
-+#define PM_OSCCTRL32_MODE_SIZE		3
-+#define PM_OSCCTRL32_STARTUP_START	16
-+#define PM_OSCCTRL32_STARTUP_SIZE	3
-+
-+/* Bits in IER/IDR/IMR/ISR/ICR */
-+#define PM_ISR_OSC0RDY_BIT		0
-+#define PM_ISR_OSC1RDY_BIT		1
-+#define PM_ISR_OSC2RDY_BIT		2
-+#define PM_ISR_OSC32RDY_BIT		7
-+#define PM_ISR_LOCK0_BIT		8
-+#define PM_ISR_LOCK1_BIT		9
-+#define PM_ISR_LOCK2_BIT		10
-+#define PM_ISR_LOCK0LOST_BIT		16
-+#define PM_ISR_LOCK1LOST_BIT		17
-+#define PM_ISR_LOCK2LOST_BIT		18
-+#define PM_ISR_CKRDY_BIT		24
-+#define PM_ISR_MSKRDY_BIT		25
-+#define PM_ISR_WAKE_BIT			26
-+#define PM_ISR_BODDET_BIT		27
-+#define PM_ISR_PERRDY_BIT		28
-+
-+/* Bits in POSCSR */
-+#define PM_POSCSR_OSC0RDY_BIT		0
-+#define PM_POSCSR_OSC1RDY_BIT		1
-+#define PM_POSCSR_OSC32RDY_BIT		7
-+#define PM_POSCSR_LOCK0_BIT		8
-+#define PM_POSCSR_LOCK1_BIT		9
-+#define PM_POSCSR_LOCK0LOST_BIT		16
-+#define PM_POSCSR_LOCK1LOST_BIT		17
-+#define PM_POSCSR_CKRDY_BIT		24
-+#define PM_POSCSR_MSKRDY_BIT		25
-+#define PM_POSCSR_WAKE_BIT		26
-+#define PM_POSCSR_BODDET_BIT		27
-+#define PM_POSCSR_PERRDY_BIT		28
-+
-+/* Bits in GCCTRL */
-+#define PM_GCCTRL_CEN_BIT		0
-+#define PM_GCCTRL_DIVEN_BIT		1
-+#define PM_GCCTRL_OSCSEL_START		8
-+#define PM_GCCTRL_OSCSEL_SIZE		4
-+#define PM_GCCTRL_DIV_START		16
-+#define PM_GCCTRL_DIV_SIZE		8
-+
-+/* Bits in RCCR */
-+#define PM_RCCR_CALIB_START		0
-+#define PM_RCCR_CALIB_SIZE		10
-+#define PM_RCCR_FCD_BIT			16
-+#define PM_RCCR_KEY_START		24
-+#define PM_RCCR_KEY_SIZE		8
-+
-+/* Bits in BGCR */
-+#define PM_BGCR_CALIB_START		0
-+#define PM_BGCR_CALIB_SIZE		3
-+#define PM_BGCR_FCD_BIT			16
-+#define PM_BGCR_KEY_START		24
-+#define PM_BGCR_KEY_SIZE		8
-+
-+/* Bits in VREGCR */
-+#define PM_VREGCR_CALIB_START		0
-+#define PM_VREGCR_CALIB_SIZE		3
-+#define PM_VREGCR_FCD_BIT		16
-+#define PM_VREGCR_KEY_START		24
-+#define PM_VREGCR_KEY_SIZE		8
-+
-+/* Bits in BOD */
-+#define PM_BOD_LEVEL_START		0
-+#define PM_BOD_LEVEL_SIZE		6
-+#define PM_BOD_HYST_BIT			6
-+#define PM_BOD_CTRL_START		8
-+#define PM_BOD_CTRL_SIZE		2
-+#define PM_BOD_FCD_BIT			16
-+#define PM_BOD_KEY_START		24
-+#define PM_BOD_KEY_SIZE			8
-+
-+/* Bits in PPCR */
-+#define PM_PPCR_EBI_VOLT_BIT		0
-+#define PM_PPCR_UTMI_CTRL_BIT		1
-+#define PM_PPCR_KEY_START		24
-+#define PM_PPCR_KEY_SIZE		8
-+
-+/* Bits in RC_RCAUSE */
-+#define PM_RC_RCAUSE_POR_BIT		0
-+#define PM_RC_RCAUSE_BOD_BIT		1
-+#define PM_RC_RCAUSE_EXT_BIT		2
-+#define PM_RC_RCAUSE_WDT_BIT		3
-+#define PM_RC_RCAUSE_JTAG_BIT		4
-+#define PM_RC_RCAUSE_NTAE_BIT		5
-+#define PM_RC_RCAUSE_SLEEP_BIT		6
-+#define PM_RC_RCAUSE_CPUERR_BIT		7
-+#define PM_RC_RCAUSE_OCDRST_BIT		8
-+#define PM_RC_RCAUSE_JTAGHARD_BIT	9
-+
-+/* Bits in WCAUSE */
-+#define PM_WCAUSE_PERIPH0_BIT		0
-+#define PM_WCAUSE_PERIPH1_BIT		1
-+#define PM_WCAUSE_EIC_BIT		16
-+#define PM_WCAUSE_RTC_BIT		17
-+
-+/* Constants for MCCTRL:MCSEL */
-+#define PM_MCSEL_SLOW			0
-+#define PM_MCSEL_OSC0			1
-+#define PM_MCSEL_PLL0			2
-+
-+/* Constants for OSCCTRLx:MODE */
-+#define PM_MODE_EXT_CLOCK		0
-+#define PM_MODE_CRYSTAL_ACG		1
-+#define PM_MODE_CRYSTAL_G0		4
-+#define PM_MODE_CRYSTAL_G1		5
-+#define PM_MODE_CRYSTAL_G2		6
-+#define PM_MODE_CRYSTAL_G3		7
-+
-+/* Constants for GCCTRL:OSCSEL */
-+#define PM_OSCSEL_SLOW			0
-+#define PM_OSCSEL_CLK32			1
-+#define PM_OSCSEL_OSC0			2
-+#define PM_OSCSEL_OSC1			3
-+#define PM_OSCSEL_PLL0			4
-+#define PM_OSCSEL_PLL1			5
-+
-+/* Constants for BOD:CTRL */
-+#define PM_CTRL_OFF1			0
-+#define PM_CTRL_ENABLED			1
-+#define PM_CTRL_ENABLED_NORESET		2
-+#define PM_CTRL_OFF2			3
-+
-+/* Bit manipulation macros */
-+#define PM_BIT(name)						\
-+	(1 << PM_##name##_BIT)
-+#define PM_BF(name,value)					\
-+	(((value) & ((1 << PM_##name##_SIZE) - 1))		\
-+	 << PM_##name##_START)
-+#define PM_BFEXT(name,value)					\
-+	(((value) >> PM_##name##_START)				\
-+	 & ((1 << PM_##name##_SIZE) - 1))
-+#define PM_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)		\
-+		    << PM_##name##_START))			\
-+	 | PM_BF(name,value))
-+
-+/* Register access macros */
-+#define __pm_regs ((struct pm_regs __iomem __force *)PM_BASE)
-+#define pm_readl(reg)						\
-+	__raw_readl(&__pm_regs->reg)
-+#define pm_writel(reg, value)					\
-+	__raw_writel(value, &__pm_regs->reg)
-+
-+#endif /* __PM_V3_H__ */
-diff --git a/arch/avr32/mach-at32ap/pm.h b/arch/avr32/mach-at32ap/pm.h
-deleted file mode 100644
-index 532a373..0000000
---- a/arch/avr32/mach-at32ap/pm.h
-+++ /dev/null
-@@ -1,112 +0,0 @@
--/*
-- * Register definitions for the Power Manager (PM)
-- */
--#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
--#define __ARCH_AVR32_MACH_AT32AP_PM_H__
--
--/* PM register offsets */
--#define PM_MCCTRL				0x0000
--#define PM_CKSEL				0x0004
--#define PM_CPU_MASK				0x0008
--#define PM_HSB_MASK				0x000c
--#define PM_PBA_MASK				0x0010
--#define PM_PBB_MASK				0x0014
--#define PM_PLL0					0x0020
--#define PM_PLL1					0x0024
--#define PM_IER					0x0040
--#define PM_IDR					0x0044
--#define PM_IMR					0x0048
--#define PM_ISR					0x004c
--#define PM_ICR					0x0050
--#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
--#define PM_RCAUSE				0x00c0
--
--/* Bitfields in CKSEL */
--#define PM_CPUSEL_OFFSET			0
--#define PM_CPUSEL_SIZE				3
--#define PM_CPUDIV_OFFSET			7
--#define PM_CPUDIV_SIZE				1
--#define PM_HSBSEL_OFFSET			8
--#define PM_HSBSEL_SIZE				3
--#define PM_HSBDIV_OFFSET			15
--#define PM_HSBDIV_SIZE				1
--#define PM_PBASEL_OFFSET			16
--#define PM_PBASEL_SIZE				3
--#define PM_PBADIV_OFFSET			23
--#define PM_PBADIV_SIZE				1
--#define PM_PBBSEL_OFFSET			24
--#define PM_PBBSEL_SIZE				3
--#define PM_PBBDIV_OFFSET			31
--#define PM_PBBDIV_SIZE				1
--
--/* Bitfields in PLL0 */
--#define PM_PLLEN_OFFSET				0
--#define PM_PLLEN_SIZE				1
--#define PM_PLLOSC_OFFSET			1
--#define PM_PLLOSC_SIZE				1
--#define PM_PLLOPT_OFFSET			2
--#define PM_PLLOPT_SIZE				3
--#define PM_PLLDIV_OFFSET			8
--#define PM_PLLDIV_SIZE				8
--#define PM_PLLMUL_OFFSET			16
--#define PM_PLLMUL_SIZE				8
--#define PM_PLLCOUNT_OFFSET			24
--#define PM_PLLCOUNT_SIZE			6
--#define PM_PLLTEST_OFFSET			31
--#define PM_PLLTEST_SIZE				1
--
--/* Bitfields in ICR */
--#define PM_LOCK0_OFFSET				0
--#define PM_LOCK0_SIZE				1
--#define PM_LOCK1_OFFSET				1
--#define PM_LOCK1_SIZE				1
--#define PM_WAKE_OFFSET				2
--#define PM_WAKE_SIZE				1
--#define PM_CKRDY_OFFSET				5
--#define PM_CKRDY_SIZE				1
--#define PM_MSKRDY_OFFSET			6
--#define PM_MSKRDY_SIZE				1
--
--/* Bitfields in GCCTRL0 */
--#define PM_OSCSEL_OFFSET			0
--#define PM_OSCSEL_SIZE				1
--#define PM_PLLSEL_OFFSET			1
--#define PM_PLLSEL_SIZE				1
--#define PM_CEN_OFFSET				2
--#define PM_CEN_SIZE				1
--#define PM_DIVEN_OFFSET				4
--#define PM_DIVEN_SIZE				1
--#define PM_DIV_OFFSET				8
--#define PM_DIV_SIZE				8
--
--/* Bitfields in RCAUSE */
--#define PM_POR_OFFSET				0
--#define PM_POR_SIZE				1
--#define PM_EXT_OFFSET				2
--#define PM_EXT_SIZE				1
--#define PM_WDT_OFFSET				3
--#define PM_WDT_SIZE				1
--#define PM_NTAE_OFFSET				4
--#define PM_NTAE_SIZE				1
--
--/* Bit manipulation macros */
--#define PM_BIT(name)					\
--	(1 << PM_##name##_OFFSET)
--#define PM_BF(name,value)				\
--	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
--	 << PM_##name##_OFFSET)
--#define PM_BFEXT(name,value)				\
--	(((value) >> PM_##name##_OFFSET)		\
--	 & ((1 << PM_##name##_SIZE) - 1))
--#define PM_BFINS(name,value,old)\
--	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
--		    << PM_##name##_OFFSET))		\
--	 | PM_BF(name,value))
--
--/* Register access macros */
--#define pm_readl(reg)							\
--	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
--#define pm_writel(reg,value)						\
--	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
--
--#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
-diff --git a/arch/avr32/mach-at32ap/sdc.h b/arch/avr32/mach-at32ap/sdc.h
-new file mode 100644
-index 0000000..6f5ec00
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/sdc.h
-@@ -0,0 +1,103 @@
-+/* SDC */
-+
-+/* Register offsets */
-+#define SDC_CTRL			0x0000
-+#define SDC_ASYNC			0x0004
-+#define SDC_SYNC			0x0008
-+#define SDC_FILTERDUR			0x000c
-+#define SDC_OSCCTRL32			0x0010
-+#define SDC_STATUS			0x0014
-+#define SDC_ECR				0x0018
-+#define SDC_IER				0x001c
-+#define SDC_IDR				0x0020
-+#define SDC_IMR				0x0024
-+#define SDC_GPLP			0x0040
-+
-+/* Bits in CTRL */
-+#define SDC_CTRL_PIN_EN_BIT		0
-+#define SDC_CTRL_AST_EN_BIT		8
-+#define SDC_CTRL_WDT_EN_BIT		9
-+#define SDC_CTRL_OCD_EN_BIT		10
-+#define SDC_CTRL_JTAG_EN_BIT		11
-+#define SDC_CTRL_CORE_POR_TEST_BIT	23
-+#define SDC_CTRL_KEY_START		24
-+#define SDC_CTRL_KEY_SIZE		8
-+
-+/* Bits in ASYNC */
-+#define SDC_ASYNC_MODE_BIT		4
-+#define SDC_ASYNC_POL_BIT		8
-+#define SDC_ASYNC_KEY_START		24
-+#define SDC_ASYNC_KEY_SIZE		8
-+
-+/* Bits in SYNC */
-+#define SDC_SYNC_EN_BIT			0
-+#define SDC_SYNC_MODE_BIT		4
-+#define SDC_SYNC_POL_BIT		8
-+#define SDC_SYNC_FILTER_BIT		12
-+#define SDC_SYNC_KEY_START		24
-+#define SDC_SYNC_KEY_SIZE		8
-+
-+/* Bits in FILTERDUR */
-+#define SDC_FILTERDUR_Duration_START	0
-+#define SDC_FILTERDUR_Duration_SIZE	16
-+#define SDC_FILTERDUR_KEY_START		24
-+#define SDC_FILTERDUR_KEY_SIZE		8
-+
-+/* Bits in OSCCTRL32 */
-+#define SDC_OSCCTRL32_OSC32EN_BIT	0
-+#define SDC_OSCCTRL32_MODE_START	8
-+#define SDC_OSCCTRL32_MODE_SIZE		4
-+#define SDC_OSCCTRL32_STARTUP_START	16
-+#define SDC_OSCCTRL32_STARTUP_SIZE	3
-+#define SDC_OSCCTRL32_KEY_START		24
-+#define SDC_OSCCTRL32_KEY_SIZE		8
-+
-+/* Bits in STATUS */
-+#define SDC_STATUS_PIN_EVENT_BIT	0
-+#define SDC_STATUS_AST_EVENT_BIT	8
-+#define SDC_STATUS_WDT_EVENT_BIT	9
-+#define SDC_STATUS_OCD_EVENT_BIT	10
-+#define SDC_STATUS_JTAG_EVENT_BIT	11
-+#define SDC_STATUS_PIN_BIT		16
-+#define SDC_STATUS_BUSY_BIT		24
-+#define SDC_STATUS_SWTCH_BIT		30
-+#define SDC_STATUS_VBAT_BIT		31
-+
-+/* Bits in ECR */
-+#define SDC_ECR_PIN_EVENT_BIT		0
-+#define SDC_ECR_AST_EVENT_BIT		8
-+#define SDC_ECR_WDT_EVENT_BIT		9
-+#define SDC_ECR_OCD_EVENT_BIT		10
-+#define SDC_ECR_JTAG_EVENT_BIT		11
-+
-+/* Bits in IER */
-+#define SDC_IER_PIN_EVENT_BIT		0
-+#define SDC_IER_READY_BIT		24
-+
-+/* Bits in IDR */
-+#define SDC_IDR_PIN_EVENT_BIT		0
-+#define SDC_IDR_READY_BIT		24
-+
-+/* Bits in IMR */
-+#define SDC_IMR_PIN_EVENT_BIT		0
-+#define SDC_IMR_READY_BIT		24
-+
-+/* Bit manipulation macros */
-+#define SDC_BIT(name)						\
-+	(1 << SDC_##name##_BIT)
-+#define SDC_BF(name,value)					\
-+	(((value) & ((1 << SDC_##name##_SIZE) - 1))		\
-+	 << SDC_##name##_START)
-+#define SDC_BFEXT(name,value)					\
-+	(((value) >> SDC_##name##_START)			\
-+	 & ((1 << SDC_##name##_SIZE) - 1))
-+#define SDC_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << SDC_##name##_SIZE) - 1)		\
-+		    << SDC_##name##_START))			\
-+	 | SDC_BF(name,value))
-+
-+/* Register access macros */
-+#define sdc_readl(reg)						\
-+	__raw_readl((void __iomem __force *)(SDC_BASE + SDC_##reg))
-+#define sdc_writel(reg, value)					\
-+	__raw_writel(value, (void __iomem __force *)(SDC_BASE + SDC_##reg))
-diff --git a/arch/avr32/mach-at32ap/timer-ast.c b/arch/avr32/mach-at32ap/timer-ast.c
-new file mode 100644
-index 0000000..0afff19
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/timer-ast.c
-@@ -0,0 +1,191 @@
-+/*
-+ * Asynchronous Timer (AST) used as clocksource / clockevent
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/clockchips.h>
-+#include <linux/clocksource.h>
-+#include <linux/interrupt.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/ast_regs.h>
-+
-+static void __iomem *ast_regs;
-+
-+static inline void ast_wait_ready(void)
-+{
-+	while (ast_readl(ast_regs, SR) & AST_BIT(BUSY))
-+		cpu_relax();
-+}
-+
-+static cycle_t read_ast_counter(void)
-+{
-+	return ast_readl(ast_regs, CV);
-+}
-+
-+static struct clocksource ast_clksrc = {
-+	.name	= "ast",
-+	.rating	= 400,
-+	.read	= read_ast_counter,
-+	.mask	= CLOCKSOURCE_MASK(32),
-+	.shift	= 16,
-+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+static irqreturn_t ast_clkevt_interrupt(int irq, void *dev_id)
-+{
-+	struct clock_event_device *clkevt = dev_id;
-+
-+	/*
-+	 * We make sure delta is always long enough so that the BUSY
-+	 * bit is never set at this point.
-+	 */
-+	ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
-+	clkevt->event_handler(clkevt);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static struct irqaction ast_clkevt_irqaction = {
-+	.handler	= ast_clkevt_interrupt,
-+	.flags		= IRQF_TIMER | IRQF_DISABLED,
-+	.name		= "timer-ast",
-+};
-+
-+static int ast_next_event(unsigned long delta,
-+		struct clock_event_device *clkevt)
-+{
-+	ast_wait_ready();
-+	ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) + delta);
-+
-+	return 0;
-+}
-+
-+static void ast_mode(enum clock_event_mode mode,
-+		struct clock_event_device *evdev)
-+{
-+	switch (mode) {
-+	case CLOCK_EVT_MODE_ONESHOT:
-+	case CLOCK_EVT_MODE_RESUME:
-+		/* Make sure we don't trigger an alarm before we get
-+		 * around to reprogramming it.
-+		 */
-+		ast_wait_ready();
-+		ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) - 1);
-+		ast_wait_ready();
-+		ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
-+		ast_wait_ready();
-+		ast_writel(ast_regs, IER, AST_BIT(ALARM0));
-+		break;
-+	case CLOCK_EVT_MODE_UNUSED:
-+	case CLOCK_EVT_MODE_SHUTDOWN:
-+		ast_writel(ast_regs, IDR, AST_BIT(ALARM0));
-+		break;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static struct clock_event_device ast_clkevt = {
-+	.name		= "ast",
-+	.features	= CLOCK_EVT_FEAT_ONESHOT,
-+	.shift		= 16,
-+	.rating		= 400,
-+	.cpumask	= CPU_MASK_CPU0,
-+	.set_next_event	= ast_next_event,
-+	.set_mode	= ast_mode,
-+};
-+
-+void __init ast_time_init(struct platform_device *pdev, unsigned int clksel)
-+{
-+	struct clk *clk, *pclk;
-+	struct resource *regs;
-+	unsigned long ast_hz;
-+	int irq;
-+	int ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		pr_debug("AST: No MMIO resource\n");
-+		return;
-+	}
-+
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk) {
-+		pr_debug("AST: No peripheral clock (pclk)\n");
-+		return;
-+	}
-+	clk_enable(pclk);
-+
-+	/* Too early for ioremap() */
-+	ast_regs = (void __iomem __force *)regs->start;
-+
-+	switch (clksel) {
-+	case AST_CLOCK_SLOW:
-+		clk = clk_get(NULL, "rcosc");
-+		break;
-+	case AST_CLOCK_OSC32:
-+		clk = clk_get(NULL, "osc32");
-+		break;
-+	case AST_CLOCK_PB:
-+		clk = pclk;
-+		break;
-+	case AST_CLOCK_GC:
-+		clk = clk_get(&pdev->dev, "gclk");
-+		break;
-+	default:
-+		clk = NULL;
-+		break;
-+	}
-+
-+	if (!clk) {
-+		pr_debug("AST: clock %u invalid, using pb clock\n", clksel);
-+		clk = pclk;
-+	}
-+	clk_enable(clk);
-+
-+	ast_writel(ast_regs, CLOCK,
-+			AST_BF(CLOCK_CSSEL, clksel) | AST_BIT(CLOCK_CEN));
-+	ast_writel(ast_regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR));
-+
-+	/* Using hardcoded divide-by-two prescaler */
-+	ast_hz = clk_get_rate(clk) / 2;
-+	ast_clksrc.mult = clocksource_hz2mult(ast_hz, ast_clksrc.shift);
-+
-+	ret = clocksource_register(&ast_clksrc);
-+	if (ret)
-+		pr_debug("AST: could not register clocksource: %d\n", ret);
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		pr_debug("AST: No IRQ resource, won't setup clockevent\n");
-+		return;
-+	}
-+
-+	ast_clkevt.mult = div_sc(ast_hz, NSEC_PER_SEC, ast_clkevt.shift);
-+	ast_clkevt.max_delta_ns = clockevent_delta2ns((u32)~0U, &ast_clkevt);
-+	ast_clkevt.min_delta_ns = clockevent_delta2ns(2, &ast_clkevt) + 100;
-+
-+	ast_clkevt_irqaction.dev_id = &ast_clkevt;
-+
-+	ret = setup_irq(irq, &ast_clkevt_irqaction);
-+	if (ret) {
-+		pr_debug("AST: Could not request IRQ %d: %d\n", irq, ret);
-+		return;
-+	}
-+
-+	clockevents_register_device(&ast_clkevt);
-+
-+	pr_info("Using Asynchronous Timer %d @ %lu.%03lu Mhz"
-+			" (regs 0x%p, irq %d)\n",
-+			pdev->id, ((ast_hz + 500) / 1000) / 1000,
-+			((ast_hz + 500) / 1000) % 1000, ast_regs, irq);
-+}
-diff --git a/arch/avr32/mm/tlb.c b/arch/avr32/mm/tlb.c
-index 06677be..cede41b 100644
---- a/arch/avr32/mm/tlb.c
-+++ b/arch/avr32/mm/tlb.c
-@@ -12,7 +12,13 @@
- #include <asm/mmu_context.h>
- 
- /* TODO: Get the correct number from the CONFIG1 system register */
--#define NR_TLB_ENTRIES 32
-+#if defined(CONFIG_CPU_AT32AP700X)
-+# define NR_TLB_ENTRIES 32
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# define NR_TLB_ENTRIES 64
-+#else
-+# error Unknown CPU type
-+#endif
- 
- static void show_dtlb_entry(unsigned int index)
- {
-@@ -85,9 +91,15 @@ static void update_dtlb(unsigned long address, pte_t pte)
- 		u32 tlbar = sysreg_read(TLBARLO);
- 
- 		rp = 32 - fls(tlbar);
--		if (rp == 32) {
-+		if (NR_TLB_ENTRIES > 32 && rp >= 32) {
-+			tlbar = sysreg_read(TLBARHI);
-+			rp = 64 - fls(tlbar);
-+		}
-+		if (rp >= NR_TLB_ENTRIES) {
- 			rp = 0;
- 			sysreg_write(TLBARLO, -1L);
-+			if (NR_TLB_ENTRIES > 32)
-+				sysreg_write(TLBARHI, -1L);
- 		}
- 
- 		mmucr = SYSREG_BFINS(DRP, rp, mmucr);
-@@ -131,16 +143,22 @@ static void __flush_tlb_page(unsigned long asid, unsigned long page)
- 
- 	if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
- 		unsigned int entry;
--		u32 tlbarlo;
-+		u32 tlbarlo, tlbarhi;
- 
- 		/* Clear the "valid" bit */
- 		sysreg_write(TLBEHI, tlbehi);
- 
- 		/* mark the entry as "not accessed" */
- 		entry = SYSREG_BFEXT(DRP, mmucr);
--		tlbarlo = sysreg_read(TLBARLO);
--		tlbarlo |= (0x80000000UL >> entry);
--		sysreg_write(TLBARLO, tlbarlo);
-+		if (NR_TLB_ENTRIES > 32 && entry > 32) {
-+			tlbarhi = sysreg_read(TLBARHI);
-+			tlbarhi |= (0x80000000UL >> (entry - 32));
-+			sysreg_write(TLBARHI, tlbarhi);
-+		} else {
-+			tlbarlo = sysreg_read(TLBARLO);
-+			tlbarlo |= (0x80000000UL >> entry);
-+			sysreg_write(TLBARLO, tlbarlo);
-+		}
- 
- 		/* update the entry with valid bit clear */
- 		__builtin_tlbw();
-@@ -179,9 +197,10 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- 		unsigned long flags;
- 		int size;
- 
--		local_irq_save(flags);
- 		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- 
-+		local_irq_save(flags);
-+
- 		if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
- 			mm->context = NO_CONTEXT;
- 			if (mm == current->mm)
-diff --git a/arch/avr32/oprofile/Makefile b/arch/avr32/oprofile/Makefile
-index 1fe81c3..e0eb520 100644
---- a/arch/avr32/oprofile/Makefile
-+++ b/arch/avr32/oprofile/Makefile
-@@ -5,4 +5,4 @@ oprofile-y		:= $(addprefix ../../../drivers/oprofile/,	\
- 				event_buffer.o oprofile_files.o		\
- 				oprofilefs.o oprofile_stats.o		\
- 				timer_int.o)
--oprofile-y		+= op_model_avr32.o
-+oprofile-y		+= op_model_avr32.o backtrace.o
-diff --git a/arch/avr32/oprofile/backtrace.c b/arch/avr32/oprofile/backtrace.c
-new file mode 100644
-index 0000000..75d9ad6
---- /dev/null
-+++ b/arch/avr32/oprofile/backtrace.c
-@@ -0,0 +1,81 @@
-+/*
-+ * AVR32 specific backtracing code for oprofile
-+ *
-+ * Copyright 2008 Weinmann GmbH
-+ *
-+ * Author: Nikolaus Voss <n.voss@weinmann.de>
-+ *
-+ * Based on i386 oprofile backtrace code by John Levon and David Smith
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/oprofile.h>
-+#include <linux/sched.h>
-+#include <linux/uaccess.h>
-+
-+/* The first two words of each frame on the stack look like this if we have
-+ * frame pointers */
-+struct frame_head {
-+	unsigned long lr;
-+	struct frame_head *fp;
-+};
-+
-+/* copied from arch/avr32/kernel/process.c */
-+static inline int valid_stack_ptr(struct thread_info *tinfo, unsigned long p)
-+{
-+	return (p > (unsigned long)tinfo)
-+		&& (p < (unsigned long)tinfo + THREAD_SIZE - 3);
-+}
-+
-+/* copied from arch/x86/oprofile/backtrace.c */
-+static struct frame_head *dump_user_backtrace(struct frame_head *head)
-+{
-+	struct frame_head bufhead[2];
-+
-+	/* Also check accessibility of one struct frame_head beyond */
-+	if (!access_ok(VERIFY_READ, head, sizeof(bufhead)))
-+		return NULL;
-+	if (__copy_from_user_inatomic(bufhead, head, sizeof(bufhead)))
-+		return NULL;
-+
-+	oprofile_add_trace(bufhead[0].lr);
-+
-+	/* frame pointers should strictly progress back up the stack
-+	 * (towards higher addresses) */
-+	if (bufhead[0].fp <= head)
-+		return NULL;
-+
-+	return bufhead[0].fp;
-+}
-+
-+void avr32_backtrace(struct pt_regs * const regs, unsigned int depth)
-+{
-+	/* Get first frame pointer */
-+	struct frame_head *head = (struct frame_head *)(regs->r7);
-+
-+	if (!user_mode(regs)) {
-+#ifdef CONFIG_FRAME_POINTER
-+		/*
-+		 * Traverse the kernel stack from frame to frame up to
-+		 * "depth" steps.
-+		 */
-+		while (depth-- && valid_stack_ptr(task_thread_info(current),
-+						  (unsigned long)head)) {
-+			oprofile_add_trace(head->lr);
-+			if (head->fp <= head)
-+				break;
-+			head = head->fp;
-+		}
-+#endif
-+	} else {
-+		/* Assume we have frame pointers in user mode process */
-+		while (depth-- && head)
-+			head = dump_user_backtrace(head);
-+	}
-+}
-+
-+
-diff --git a/arch/avr32/oprofile/op_model_avr32.c b/arch/avr32/oprofile/op_model_avr32.c
-index df42325..a3e9b3c 100644
---- a/arch/avr32/oprofile/op_model_avr32.c
-+++ b/arch/avr32/oprofile/op_model_avr32.c
-@@ -22,6 +22,8 @@
- #define AVR32_PERFCTR_IRQ_GROUP	0
- #define AVR32_PERFCTR_IRQ_LINE	1
- 
-+void avr32_backtrace(struct pt_regs * const regs, unsigned int depth);
-+
- enum { PCCNT, PCNT0, PCNT1, NR_counter };
- 
- struct avr32_perf_counter {
-@@ -223,6 +225,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
- 	memcpy(ops, &avr32_perf_counter_ops,
- 			sizeof(struct oprofile_operations));
- 
-+	ops->backtrace = avr32_backtrace;
-+
- 	printk(KERN_INFO "oprofile: using AVR32 performance monitoring.\n");
- 
- 	return 0;
-diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
-index cd30390..9322b91 100644
---- a/drivers/dma/Kconfig
-+++ b/drivers/dma/Kconfig
-@@ -38,6 +38,20 @@ config INTEL_IOP_ADMA
- 	help
- 	  Enable support for the Intel(R) IOP Series RAID engines.
- 
-+config ATMEL_PDCA
-+	tristate "Atmel Peripheral DMA Controller A support"
-+	depends on AVR32
-+	select DMA_ENGINE
-+	default y if CPU_AT32AP7200
-+	help
-+	  Support the Atmel Peripheral DMA Controller found on AVR32
-+	  UC3 chips as well as newer AP7 chips. This controller is
-+	  similar to the PDC found on AT32AP7000 and various AT91
-+	  chips, but has its own register bank.
-+
-+	  This controller only supports peripheral (slave) transfers,
-+	  not memory-to-memory transfers.
-+
- config DW_DMAC
- 	tristate "Synopsys DesignWare AHB DMA support"
- 	depends on AVR32
-diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
-index 14f5952..1623a6d 100644
---- a/drivers/dma/Makefile
-+++ b/drivers/dma/Makefile
-@@ -4,6 +4,7 @@ obj-$(CONFIG_DMATEST) += dmatest.o
- obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
- ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
- obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
-+obj-$(CONFIG_ATMEL_PDCA) += atmel_pdca.o
- obj-$(CONFIG_FSL_DMA) += fsldma.o
- obj-$(CONFIG_MV_XOR) += mv_xor.o
- obj-$(CONFIG_DW_DMAC) += dw_dmac.o
-diff --git a/drivers/dma/atmel_pdca.c b/drivers/dma/atmel_pdca.c
-new file mode 100644
-index 0000000..0d2f49f
---- /dev/null
-+++ b/drivers/dma/atmel_pdca.c
-@@ -0,0 +1,668 @@
-+/*
-+ * Driver for the Atmel PDCA Peripheral DMA Controller
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#define DEBUG
-+#include <linux/atmel_pdca.h>
-+#include <linux/clk.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/scatterlist.h>
-+#include <linux/spinlock.h>
-+
-+/*
-+ * Since each descriptor can hold a whole scatterlist, we don't need
-+ * many of them.
-+ */
-+#define NR_DESCS_PER_CHANNEL	8
-+
-+static struct pdca_desc *pdca_desc_entry(struct list_head *node)
-+{
-+	return list_entry(node, struct pdca_desc, desc_node);
-+}
-+
-+static struct pdca_desc *pdca_next_desc(struct pdca_chan *pch,
-+		struct pdca_desc *desc)
-+{
-+	if (desc->desc_node.next != &pch->queue)
-+		return pdca_desc_entry(desc->desc_node.next);
-+	return NULL;
-+}
-+
-+static struct pdca_desc *pdca_desc_get(struct pdca_chan *pch)
-+{
-+	struct pdca_desc		*desc = NULL;
-+
-+	spin_lock_bh(&pch->lock);
-+	if (likely(!list_empty(&pch->freelist))) {
-+		desc = pdca_desc_entry(pch->freelist.next);
-+		list_del(&desc->desc_node);
-+	}
-+	spin_unlock_bh(&pch->lock);
-+
-+	return desc;
-+}
-+
-+static dma_cookie_t pdca_assign_cookie(struct pdca_chan *pch,
-+		struct pdca_desc *desc)
-+{
-+	dma_cookie_t cookie = pch->chan.cookie;
-+
-+	if (++cookie < 0)
-+		cookie = 1;
-+
-+	pch->chan.cookie = cookie;
-+	desc->txd.cookie = cookie;
-+
-+	return cookie;
-+}
-+
-+static void pdca_desc_done(struct pdca_chan *pch, struct pdca_desc *desc)
-+{
-+	struct dma_async_tx_descriptor	*txd = &desc->txd;
-+	dma_async_tx_callback		callback;
-+	void				*param;
-+
-+	pch->completed = txd->cookie;
-+	callback = txd->callback;
-+	param = txd->callback_param;
-+
-+	dev_vdbg(&pch->chan.dev, "  completed %u\n", txd->cookie);
-+
-+	/*
-+	 * We can only handle scatterlists, so this is easy. No other
-+	 * drivers do the right thing with scatterlists though...
-+	 *
-+	 * Note that we ensure that at least one of these flags are
-+	 * set when the descriptor is prepared, as we never need to
-+	 * unmap the peripheral side.
-+	 */
-+	if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP))
-+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
-+				DMA_FROM_DEVICE);
-+	if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
-+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
-+				DMA_TO_DEVICE);
-+
-+	list_move(&desc->desc_node, &pch->freelist);
-+
-+	if (callback)
-+		callback(param);
-+}
-+
-+static void pdca_chan_tasklet(unsigned long param)
-+{
-+	struct pdca_chan		*pch = (struct pdca_chan *)param;
-+	void __iomem			*regs = pch->regs;
-+	struct pdca_desc		*cur;
-+	struct pdca_desc		*next;
-+	struct scatterlist		*cur_sg;
-+	struct scatterlist		*next_sg;
-+	u32				intflags;
-+	u32				status;
-+
-+	spin_lock(&pch->lock);
-+
-+	cur = pdca_desc_entry(pch->queue.next);
-+	next = pdca_next_desc(pch, cur);
-+
-+	cur_sg = pch->cur_sg;
-+	next_sg = pch->next_sg;
-+
-+	intflags = PDCA_TERR | PDCA_TRC | PDCA_RCZ;
-+
-+	status = pdca_readl(regs, ISR);
-+	dev_vdbg(&pch->chan.dev, "tasklet: status=%08x\n", status);
-+
-+	if (status & PDCA_TRC) {
-+		if (cur_sg) {
-+			if (sg_is_last(cur_sg)) {
-+				dev_vdbg(&pch->chan.dev,
-+						"  cur sg was last in %u\n",
-+						cur->txd.cookie);
-+				pdca_desc_done(pch, cur);
-+				cur = next;
-+				next = NULL;
-+			}
-+			if (next_sg && sg_is_last(next_sg)) {
-+				dev_vdbg(&pch->chan.dev,
-+						"  next sg was last in %u\n",
-+						cur->txd.cookie);
-+				pdca_desc_done(pch, cur);
-+				cur = next;
-+				next = NULL;
-+			}
-+			if (!cur) {
-+				dev_vdbg(&pch->chan.dev, "  all done\n");
-+				pdca_writel(regs, CR, PDCA_CR_TDIS);
-+				cur_sg = next_sg = NULL;
-+				intflags = 0;
-+				goto done;
-+			}
-+			cur_sg = next_sg ? sg_next(next_sg) : NULL;
-+		}
-+
-+		if (!cur_sg) {
-+			dev_vdbg(&pch->chan.dev, "  load sg from %u\n",
-+					cur->txd.cookie);
-+			cur_sg = cur->sg;
-+			pdca_writel(regs, PSR, cur->periph_id);
-+			pdca_writel(regs, MR, cur->reg_width);
-+		}
-+		dev_vdbg(&pch->chan.dev, "  START: %08x count: %08x\n",
-+				sg_dma_address(cur_sg),
-+				sg_dma_len(cur_sg) >> cur->reg_width);
-+		pdca_writel(regs, MAR, sg_dma_address(cur_sg));
-+		pdca_writel(regs, TCR, sg_dma_len(cur_sg) >> cur->reg_width);
-+
-+		next_sg = sg_next(cur_sg);
-+		if (!next_sg) {
-+			next = pdca_next_desc(pch, cur);
-+			if (next && next->reg_width == cur->reg_width
-+					&& next->periph_id == cur->periph_id) {
-+				dev_vdbg(&pch->chan.dev,
-+						"loading next_sg from %u\n",
-+						next->txd.cookie);
-+				next_sg = next->sg;
-+			}
-+		}
-+		if (next_sg) {
-+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
-+					sg_dma_address(next_sg),
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
-+			pdca_writel(regs, TCRR,
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+		} else {
-+			intflags &= ~PDCA_RCZ;
-+		}
-+	} else if (next_sg && (status & PDCA_RCZ)) {
-+		if (sg_is_last(cur_sg)) {
-+			dev_vdbg(&pch->chan.dev, "  cur sg was last in %u\n",
-+					cur->txd.cookie);
-+			next = pdca_next_desc(pch, cur);
-+			pdca_desc_done(pch, cur);
-+			cur = next;
-+			next = NULL;
-+		}
-+
-+		cur_sg = next_sg;
-+		next_sg = sg_next(cur_sg);
-+		if (!next_sg) {
-+			next = pdca_next_desc(pch, cur);
-+			if (next && next->reg_width == cur->reg_width
-+					&& next->periph_id == cur->periph_id)
-+				next_sg = next->sg;
-+		}
-+
-+		if (next_sg) {
-+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
-+					sg_dma_address(next_sg),
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
-+			pdca_writel(regs, TCRR,
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+		} else {
-+			dev_vdbg(&pch->chan.dev, "  no next sg\n");
-+			intflags &= ~PDCA_RCZ;
-+		}
-+	}
-+
-+done:
-+	if (status & PDCA_TERR) {
-+		/*
-+		 * Head of queue is busted. We must remove it, clear
-+		 * the error and restart the queue.
-+		 */
-+		pdca_writel(regs, TCRR, 0);
-+		pdca_writel(regs, TCR, 0);
-+		pdca_writel(regs, CR, PDCA_CR_ECLR);
-+		cur_sg = next_sg = NULL;
-+
-+		if (!cur)
-+			dev_err(&pch->chan.dev,
-+					"Transfer Error with empty queue\n");
-+		else {
-+			dev_vdbg(&pch->chan.dev,
-+					"  %u is busted\n", cur->txd.cookie);
-+			pdca_desc_done(pch, cur);
-+		}
-+
-+		if (list_empty(&pch->queue)) {
-+			pdca_writel(regs, CR, PDCA_CR_TDIS);
-+			intflags = 0;
-+		}
-+	}
-+
-+	pch->cur_sg = cur_sg;
-+	pch->next_sg = next_sg;
-+
-+	dev_vdbg(&pch->chan.dev, "  enabling interrupts: %08x\n", intflags);
-+	pdca_writel(regs, IER, intflags);
-+	pdca_readl(regs, SR);
-+
-+	spin_unlock(&pch->lock);
-+}
-+
-+static irqreturn_t pdca_interrupt(int irq, void *dev_id)
-+{
-+	struct pdca_dev			*pdca = dev_id;
-+	struct pdca_chan		*pch;
-+	void __iomem			*regs;
-+	unsigned long			pending;
-+	unsigned int			chan;
-+
-+	pending = intc_get_pending(irq);
-+	if (unlikely(!pending))
-+		return IRQ_NONE;
-+
-+	do {
-+		chan = __ffs(pending);
-+		pch = &pdca->chan[chan];
-+		regs = pch->regs;
-+		pdca_writel(regs, IDR, ~0UL);
-+		tasklet_schedule(&pch->tasklet);
-+		pdca_readl(regs, IMR);
-+		pending &= ~(1 << chan);
-+	} while (pending);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static dma_cookie_t pdca_tx_submit(struct dma_async_tx_descriptor *txd)
-+{
-+	struct pdca_desc		*desc = txd_to_pdca_desc(txd);
-+	struct pdca_chan		*pch = dma_to_pdca_chan(txd->chan);
-+	void __iomem			*regs = pch->regs;
-+	dma_cookie_t			cookie;
-+
-+	spin_lock_bh(&pch->lock);
-+	cookie = pdca_assign_cookie(pch, desc);
-+	dev_vdbg(&pch->chan.dev, "submitted %u\n", cookie);
-+	list_add_tail(&desc->desc_node, &pch->queue);
-+	pdca_writel(regs, CR, PDCA_CR_TEN);
-+	pdca_writel(regs, IER, PDCA_TERR | PDCA_RCZ);
-+	/* The tasklet will kickstart the queue if necessary */
-+	spin_unlock_bh(&pch->lock);
-+
-+	return cookie;
-+}
-+
-+static struct dma_async_tx_descriptor *pdca_prep_slave_sg(struct dma_chan *chan,
-+		struct scatterlist *sgl, unsigned int sg_len,
-+		enum dma_data_direction direction, unsigned long flags)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_slave		*pslave = pch->pslave;
-+	struct pdca_desc		*desc;
-+	unsigned int			periph_id;
-+
-+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
-+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
-+			sg_len, flags);
-+
-+	switch (direction) {
-+	case DMA_TO_DEVICE:
-+		periph_id = pslave->tx_periph_id;
-+		flags |= DMA_COMPL_SKIP_DEST_UNMAP;
-+		break;
-+	case DMA_FROM_DEVICE:
-+		periph_id = pslave->rx_periph_id;
-+		flags |= DMA_COMPL_SKIP_SRC_UNMAP;
-+		break;
-+	default:
-+		return NULL;
-+	}
-+
-+	desc = pdca_desc_get(pch);
-+	if (!desc) {
-+		dev_err(&chan->dev,
-+			"not enough descriptors available\n");
-+		return NULL;
-+	}
-+	desc->sg = sgl;
-+	desc->sg_len = sg_len;
-+	desc->periph_id = periph_id;
-+	desc->reg_width = pslave->slave.reg_width;
-+	desc->txd.flags = flags;
-+
-+	return &desc->txd;
-+}
-+
-+static void pdca_terminate_all(struct dma_chan *chan)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_desc		*desc, *_desc;
-+	void __iomem			*regs = pch->regs;
-+
-+	spin_lock_bh(&pch->lock);
-+	pdca_writel(regs, CR, PDCA_CR_TDIS);
-+	pdca_writel(regs, TCRR, 0);
-+	pdca_writel(regs, TCR, 0);
-+	while (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+		cpu_relax();
-+
-+	list_for_each_entry_safe(desc, _desc, &pch->queue, desc_node)
-+		pdca_desc_done(pch, desc);
-+	spin_unlock_bh(&pch->lock);
-+}
-+
-+static enum dma_status pdca_is_tx_complete(struct dma_chan *chan,
-+		dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	dma_cookie_t			last_used;
-+	dma_cookie_t			last_complete;
-+
-+	last_complete = pch->completed;
-+	last_used = chan->cookie;
-+
-+	if (done)
-+		*done = last_complete;
-+	if (used)
-+		*used = last_used;
-+
-+	return dma_async_is_complete(cookie, last_complete, last_used);
-+}
-+
-+static void pdca_issue_pending(struct dma_chan *chan)
-+{
-+	/* We always issue descriptors ASAP */
-+}
-+
-+static int pdca_alloc_chan_resources(struct dma_chan *chan,
-+		struct dma_client *client)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
-+	struct dma_slave		*slave = client->slave;
-+	void __iomem			*regs = pch->regs;
-+
-+	/*
-+	 * Channels doing slave DMA can only handle one client. This
-+	 * controller can only do slave DMA.
-+	 */
-+	if (chan->client_count)
-+		return -EBUSY;
-+	if (!slave || !slave->dma_dev || slave->dma_dev != pdca->dma.dev)
-+		return -EINVAL;
-+
-+	if (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+		dev_err(&chan->dev, "DMA channel not idle!\n");
-+
-+	/*
-+	 * We may get called multiple times if a client rejects the
-+	 * channel...
-+	 */
-+	if (!pch->enabled) {
-+		pch->enabled = true;
-+		clk_enable(pdca->pclk);
-+		clk_enable(pdca->hclk);
-+	}
-+
-+	pch->chan.cookie = pch->completed = 1;
-+	pch->pslave = dma_to_pdca_slave(slave);
-+
-+	while (pch->descs_allocated < NR_DESCS_PER_CHANNEL) {
-+		struct pdca_desc	*desc;
-+
-+		desc = kzalloc(sizeof(struct pdca_desc), GFP_KERNEL);
-+		if (!desc) {
-+			dev_info(&chan->dev, "only allocated %d descriptors\n",
-+					pch->descs_allocated);
-+			break;
-+		}
-+
-+		dma_async_tx_descriptor_init(&desc->txd, chan);
-+		desc->txd.tx_submit = pdca_tx_submit;
-+		desc->txd.flags = DMA_CTRL_ACK;
-+		INIT_LIST_HEAD(&desc->txd.tx_list);
-+		list_add(&desc->desc_node, &pch->freelist);
-+		pch->descs_allocated++;
-+	}
-+
-+	return pch->descs_allocated ? 0 : -ENOMEM;
-+}
-+
-+static void pdca_free_chan_resources(struct dma_chan *chan)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
-+	struct pdca_desc		*desc, *_desc;
-+
-+	WARN_ON(!list_empty(&pch->queue));
-+	WARN_ON(pdca_readl(pch->regs, SR) & PDCA_SR_TEN);
-+	WARN_ON(pdca_readl(pch->regs, IMR));
-+
-+	clk_disable(pdca->hclk);
-+	clk_disable(pdca->pclk);
-+	pch->enabled = false;
-+
-+	list_for_each_entry_safe(desc, _desc, &pch->freelist, desc_node) {
-+		list_del(&desc->desc_node);
-+		kfree(desc);
-+	}
-+
-+	pch->descs_allocated = 0;
-+}
-+
-+static void pdca_suspend_channel(struct pdca_dev *pdca, struct pdca_chan *pch)
-+{
-+	void __iomem			*regs = pch->regs;
-+
-+	/*
-+	 * REVISIT this whole business.
-+	 *
-+	 * The plan is to ensure that the PDCA doesn't do any bus
-+	 * transactions when we're suspended or shut down. Ideally,
-+	 * the client should make sure that all transfers have already
-+	 * been completed or terminated when we reach suspend_late(),
-+	 * but just in case that didn't happen, we should just stop
-+	 * the controller and turn it back on when resuming. Hopefully
-+	 * it will simply continue where it left off.
-+	 *
-+	 * We _probably_ need to save some sort of state to make this
-+	 * happen. Or we can just rely on interrupts being globally
-+	 * disabled at least until we reach resume_early. But that
-+	 * might not be the case for shutdown.
-+	 */
-+	tasklet_kill(&pch->tasklet);
-+	spin_lock_bh(&pch->lock);
-+	if (pdca_readl(regs, SR) & PDCA_SR_TEN) {
-+		pdca_writel(regs, CR, PDCA_CR_TDIS);
-+		while (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+			cpu_relax();
-+
-+		clk_disable(pdca->hclk);
-+		clk_disable(pdca->pclk);
-+	}
-+	spin_unlock_bh(&pch->lock);
-+}
-+
-+static void __init pdca_init_channel(struct pdca_dev *pdca, unsigned int i)
-+{
-+	struct pdca_chan		*pch = &pdca->chan[i];
-+
-+	pch->chan.device = &pdca->dma;
-+	pch->chan.chan_id = i;
-+	pch->regs = pdca->regs + i * PDCA_CHAN_SIZE;
-+	tasklet_init(&pch->tasklet, pdca_chan_tasklet, (unsigned long)pch);
-+	spin_lock_init(&pch->lock);
-+	INIT_LIST_HEAD(&pch->freelist);
-+	INIT_LIST_HEAD(&pch->queue);
-+
-+	list_add_tail(&pch->chan.device_node, &pdca->dma.channels);
-+}
-+
-+static int __init pdca_probe(struct platform_device *pdev)
-+{
-+	struct pdca_pdata		*pdata;
-+	struct resource			*mmio;
-+	struct pdca_dev			*pdca;
-+	size_t				mmio_len;
-+	size_t				size;
-+	unsigned int			i;
-+	int				irq;
-+	int				ret;
-+
-+	pdata = pdev->dev.platform_data;
-+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	irq = platform_get_irq(pdev, 0);
-+	if (!pdata || pdata->nr_channels > 32 || !mmio || !irq) {
-+		dev_dbg(&pdev->dev, "invalid params from platform code\n");
-+		return -EINVAL;
-+	}
-+
-+	mmio_len = mmio->end - mmio->start + 1;
-+	if (!request_mem_region(mmio->start, mmio_len, "atmel_pdca")) {
-+		dev_dbg(&pdev->dev, "mmio resource busy\n");
-+		return -EBUSY;
-+	}
-+
-+	size = sizeof(struct pdca_dev);
-+	size += pdata->nr_channels * sizeof(struct pdca_chan);
-+	pdca = kzalloc(size, GFP_KERNEL);
-+	if (!pdca) {
-+		dev_dbg(&pdev->dev, "insufficient memory\n");
-+		ret = -ENOMEM;
-+		goto err_alloc_pdca;
-+	}
-+
-+	pdca->hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(pdca->hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		ret = PTR_ERR(pdca->hclk);
-+		goto err_get_hclk;
-+	}
-+	pdca->pclk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(pdca->pclk)) {
-+		dev_dbg(&pdev->dev, "no PB clock\n");
-+		ret = PTR_ERR(pdca->pclk);
-+		goto err_get_pclk;
-+	}
-+
-+	pdca->regs = ioremap(mmio->start, mmio_len);
-+	if (!pdca->regs) {
-+		dev_dbg(&pdev->dev, "ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto err_ioremap;
-+	}
-+
-+	INIT_LIST_HEAD(&pdca->dma.channels);
-+	for (i = 0; i < pdata->nr_channels; i++, pdca->dma.chancnt++)
-+		pdca_init_channel(pdca, i);
-+
-+	ret = request_irq(irq, pdca_interrupt, 0, pdev->dev.bus_id, pdca);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "request_irq failed\n");
-+		goto err_irq;
-+	}
-+
-+	dma_cap_set(DMA_SLAVE, pdca->dma.cap_mask);
-+	pdca->dma.dev = &pdev->dev;
-+	pdca->dma.device_alloc_chan_resources = pdca_alloc_chan_resources;
-+	pdca->dma.device_free_chan_resources = pdca_free_chan_resources;
-+	pdca->dma.device_prep_slave_sg = pdca_prep_slave_sg;
-+	pdca->dma.device_terminate_all = pdca_terminate_all;
-+	pdca->dma.device_is_tx_complete = pdca_is_tx_complete;
-+	pdca->dma.device_issue_pending = pdca_issue_pending;
-+
-+	platform_set_drvdata(pdev, pdca);
-+	dma_async_device_register(&pdca->dma);
-+
-+	dev_info(&pdev->dev, "Atmel PDCA at 0x%08lx (irq %d) %u channels\n",
-+			(unsigned long)mmio->start, irq, pdca->dma.chancnt);
-+
-+	return 0;
-+
-+err_irq:
-+	iounmap(pdca->regs);
-+err_ioremap:
-+	clk_put(pdca->pclk);
-+err_get_pclk:
-+	clk_put(pdca->hclk);
-+err_get_hclk:
-+	kfree(pdca);
-+err_alloc_pdca:
-+	release_resource(mmio);
-+	return ret;
-+}
-+
-+static int __exit pdca_remove(struct platform_device *pdev)
-+{
-+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
-+	struct pdca_chan	*pch;
-+	struct resource		*mmio;
-+
-+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
-+		pdca_suspend_channel(pdca, pch);
-+
-+	dma_async_device_unregister(&pdca->dma);
-+	free_irq(platform_get_irq(pdev, 0), pdca);
-+	clk_put(pdca->pclk);
-+	clk_put(pdca->hclk);
-+	iounmap(pdca->regs);
-+	kfree(pdca);
-+
-+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	release_resource(mmio);
-+
-+	return 0;
-+}
-+
-+static void pdca_shutdown(struct platform_device *pdev)
-+{
-+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
-+	struct pdca_chan	*pch;
-+
-+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
-+		pdca_suspend_channel(pdca, pch);
-+}
-+
-+static int pdca_suspend_late(struct platform_device *pdev, pm_message_t state)
-+{
-+	return 0;
-+}
-+
-+static int pdca_resume_early(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+
-+static struct platform_driver pdca_driver = {
-+	.remove		= __exit_p(pdca_remove),
-+	.shutdown	= pdca_shutdown,
-+	.suspend_late	= pdca_suspend_late,
-+	.resume_early	= pdca_resume_early,
-+	.driver		= {
-+		.name	= "atmel_pdca",
-+	},
-+};
-+
-+static int __init pdca_init(void)
-+{
-+	return platform_driver_probe(&pdca_driver, pdca_probe);
-+}
-+subsys_initcall(pdca_init);
-+
-+static void __exit pdca_exit(void)
-+{
-+	platform_driver_unregister(&pdca_driver);
-+}
-+module_exit(pdca_exit);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("Atmel PDCA DMA Controller driver");
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
-diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
-index 0778d99..a7686b9 100644
---- a/drivers/dma/dw_dmac.c
-+++ b/drivers/dma/dw_dmac.c
-@@ -545,109 +545,51 @@ err_desc_get:
- 	return NULL;
- }
- 
--static struct dma_async_tx_descriptor *
--dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
--		unsigned int sg_len, enum dma_data_direction direction,
--		unsigned long flags)
-+static struct dw_desc *dwc_init_slave_descs(struct dw_dma_chan *dwc,
-+		struct scatterlist *sgl, unsigned int sg_len,
-+		u32 ctllo, dma_addr_t src_reg, dma_addr_t dst_reg,
-+		unsigned int reg_width, unsigned long flags)
- {
--	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
--	struct dw_dma_slave	*dws = dwc->dws;
--	struct dw_desc		*prev;
--	struct dw_desc		*first;
--	u32			ctllo;
--	dma_addr_t		reg;
--	unsigned int		reg_width;
--	unsigned int		mem_width;
--	unsigned int		i;
-+	struct dma_chan		*chan = &dwc->chan;
- 	struct scatterlist	*sg;
-+	struct dw_desc		*desc;
-+	struct dw_desc		*first = NULL;
-+	struct dw_desc		*prev = NULL;
-+	unsigned int		align_mask;
-+	unsigned int		i;
- 	size_t			total_len = 0;
- 
--	dev_vdbg(&chan->dev, "prep_dma_slave\n");
--
--	if (unlikely(!dws || !sg_len))
--		return NULL;
--
--	reg_width = dws->slave.reg_width;
--	prev = first = NULL;
--
--	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
-+	align_mask = (1 << reg_width) - 1;
-+	for_each_sg(sgl, sg, sg_len, i) {
-+		u32		len;
-+		u32		desc_len;
-+		u32		mem;
- 
--	switch (direction) {
--	case DMA_TO_DEVICE:
--		ctllo = (DWC_DEFAULT_CTLLO
--				| DWC_CTLL_DST_WIDTH(reg_width)
--				| DWC_CTLL_DST_FIX
--				| DWC_CTLL_SRC_INC
--				| DWC_CTLL_FC_M2P);
--		reg = dws->slave.tx_reg;
--		for_each_sg(sgl, sg, sg_len, i) {
--			struct dw_desc	*desc;
--			u32		len;
--			u32		mem;
-+		mem = sg_phys(sg);
-+		len = sg_dma_len(sg);
-+		total_len += len;
- 
-+		while (len) {
-+			desc_len = min(len, DWC_MAX_COUNT << reg_width);
- 			desc = dwc_desc_get(dwc);
- 			if (!desc) {
- 				dev_err(&chan->dev,
- 					"not enough descriptors available\n");
- 				goto err_desc_get;
- 			}
-+			len -= desc_len;
- 
--			mem = sg_phys(sg);
--			len = sg_dma_len(sg);
--			mem_width = 2;
--			if (unlikely(mem & 3 || len & 3))
--				mem_width = 0;
-+			if (unlikely((mem & align_mask) || (len & align_mask)))
-+				goto err_align;
- 
--			desc->lli.sar = mem;
--			desc->lli.dar = reg;
--			desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
--			desc->lli.ctlhi = len >> mem_width;
--
--			if (!first) {
--				first = desc;
--			} else {
--				prev->lli.llp = desc->txd.phys;
--				dma_sync_single_for_device(chan->dev.parent,
--						prev->txd.phys,
--						sizeof(prev->lli),
--						DMA_TO_DEVICE);
--				list_add_tail(&desc->desc_node,
--						&first->txd.tx_list);
--			}
--			prev = desc;
--			total_len += len;
--		}
--		break;
--	case DMA_FROM_DEVICE:
--		ctllo = (DWC_DEFAULT_CTLLO
--				| DWC_CTLL_SRC_WIDTH(reg_width)
--				| DWC_CTLL_DST_INC
--				| DWC_CTLL_SRC_FIX
--				| DWC_CTLL_FC_P2M);
--
--		reg = dws->slave.rx_reg;
--		for_each_sg(sgl, sg, sg_len, i) {
--			struct dw_desc	*desc;
--			u32		len;
--			u32		mem;
--
--			desc = dwc_desc_get(dwc);
--			if (!desc) {
--				dev_err(&chan->dev,
--					"not enough descriptors available\n");
--				goto err_desc_get;
--			}
--
--			mem = sg_phys(sg);
--			len = sg_dma_len(sg);
--			mem_width = 2;
--			if (unlikely(mem & 3 || len & 3))
--				mem_width = 0;
--
--			desc->lli.sar = reg;
--			desc->lli.dar = mem;
--			desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
--			desc->lli.ctlhi = len >> reg_width;
-+			desc->lli.sar = src_reg ? src_reg : mem;
-+			desc->lli.dar = dst_reg ? dst_reg : mem;
-+			desc->lli.ctllo = ctllo;
-+			desc->lli.ctlhi = desc_len >> reg_width;
-+			dev_vdbg(&dwc->chan.dev,
-+					"  s%08x d%08x c%08x:%08x\n",
-+					desc->lli.sar, desc->lli.dar,
-+					ctllo, desc_len >> reg_width);
- 
- 			if (!first) {
- 				first = desc;
-@@ -661,11 +603,8 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
- 						&first->txd.tx_list);
- 			}
- 			prev = desc;
--			total_len += len;
-+			mem += desc_len;
- 		}
--		break;
--	default:
--		return NULL;
- 	}
- 
- 	if (flags & DMA_PREP_INTERRUPT)
-@@ -679,13 +618,69 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
- 
- 	first->len = total_len;
- 
--	return &first->txd;
-+	return first;
- 
-+err_align:
-+	dwc_desc_put(dwc, desc);
- err_desc_get:
- 	dwc_desc_put(dwc, first);
- 	return NULL;
- }
- 
-+static struct dma_async_tx_descriptor *
-+dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-+		unsigned int sg_len, enum dma_data_direction direction,
-+		unsigned long flags)
-+{
-+	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-+	struct dw_dma_slave	*dws = dwc->dws;
-+	struct dw_desc		*first;
-+	u32			ctllo;
-+	unsigned int		reg_width;
-+
-+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
-+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
-+			sg_len, flags);
-+
-+	if (unlikely(!dws || !sg_len))
-+		return NULL;
-+
-+	reg_width = dws->slave.reg_width;
-+	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
-+
-+	switch (direction) {
-+	case DMA_TO_DEVICE:
-+		ctllo = (DWC_DEFAULT_CTLLO
-+				| DWC_CTLL_DST_WIDTH(reg_width)
-+				| DWC_CTLL_SRC_WIDTH(reg_width)
-+				| DWC_CTLL_DST_FIX
-+				| DWC_CTLL_SRC_INC
-+				| DWC_CTLL_FC_M2P);
-+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
-+				0, dws->slave.tx_reg, reg_width, flags);
-+		break;
-+	case DMA_FROM_DEVICE:
-+		ctllo = (DWC_DEFAULT_CTLLO
-+				| DWC_CTLL_SRC_WIDTH(reg_width)
-+				| DWC_CTLL_DST_WIDTH(reg_width)
-+				| DWC_CTLL_DST_INC
-+				| DWC_CTLL_SRC_FIX
-+				| DWC_CTLL_FC_P2M);
-+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
-+				dws->slave.rx_reg, 0, reg_width, flags);
-+		break;
-+	default:
-+		return NULL;
-+	}
-+
-+	if (unlikely(!first)) {
-+		dma_unmap_sg(chan->dev.parent, sgl, sg_len, direction);
-+		return NULL;
-+	}
-+
-+	return &first->txd;
-+}
-+
- static void dwc_terminate_all(struct dma_chan *chan)
- {
- 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-@@ -1109,7 +1104,7 @@ static int __init dw_init(void)
- {
- 	return platform_driver_probe(&dw_driver, dw_probe);
- }
--module_init(dw_init);
-+subsys_initcall(dw_init);
- 
- static void __exit dw_exit(void)
- {
-diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
-index ea8d7a3..1ce21d4 100644
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -114,6 +114,17 @@ config MMC_ATMELMCI
- 
- 	  If unsure, say N.
- 
-+config MMC_ATMELMCI_DMA
-+	bool "Atmel MCI DMA support (EXPERIMENTAL)"
-+	depends on MMC_ATMELMCI && DMA_ENGINE && EXPERIMENTAL
-+	help
-+	  Say Y here to have the Atmel MCI driver use a DMA engine to
-+	  do data transfers and thus increase the throughput and
-+	  reduce the CPU utilization. Note that this is highly
-+	  experimental and may cause the driver to lock up.
-+
-+	  If unsure, say N.
-+
- config MMC_IMX
- 	tristate "Motorola i.MX Multimedia Card Interface support"
- 	depends on ARCH_IMX
-diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
-index 26bd80e..cfb7ce1 100644
---- a/drivers/mmc/host/atmel-mci-regs.h
-+++ b/drivers/mmc/host/atmel-mci-regs.h
-@@ -10,13 +10,21 @@
- #ifndef __DRIVERS_MMC_ATMEL_MCI_H__
- #define __DRIVERS_MMC_ATMEL_MCI_H__
- 
--/* MCI Register Definitions */
-+/*
-+ * MCI Register Definitions. Registers and bitfields marked with [2]
-+ * are only available in MCI2.
-+ */
- #define MCI_CR			0x0000	/* Control */
- # define MCI_CR_MCIEN		(  1 <<  0)	/* MCI Enable */
- # define MCI_CR_MCIDIS		(  1 <<  1)	/* MCI Disable */
-+# define MCI_CR_PWSEN		(  1 <<  2)	/* Powersave Enable[2] */
-+# define MCI_CR_PWSDIS		(  1 <<  3)	/* Powersave Disable[2] */
-+# define MCI_CR_IOWAITEN	(  1 <<  4)	/* SDIO Read Wait Enable[2] */
-+# define MCI_CR_IOWAITDIS	(  1 <<  5)	/* SDIO Read Wait Disable[2] */
- # define MCI_CR_SWRST		(  1 <<  7)	/* Software Reset */
- #define MCI_MR			0x0004	/* Mode */
- # define MCI_MR_CLKDIV(x)	((x) <<  0)	/* Clock Divider */
-+# define MCI_MR_PWSDIV(x)	((x) <<  8)	/* Powersave Divider[2] */
- # define MCI_MR_RDPROOF		(  1 << 11)	/* Read Proof */
- # define MCI_MR_WRPROOF		(  1 << 12)	/* Write Proof */
- #define MCI_DTOR		0x0008	/* Data Timeout */
-@@ -24,9 +32,12 @@
- # define MCI_DTOMUL(x)		((x) <<  4)	/* Data Timeout Multiplier */
- #define MCI_SDCR		0x000c	/* SD Card / SDIO */
- # define MCI_SDCSEL_SLOT_A	(  0 <<  0)	/* Select SD slot A */
--# define MCI_SDCSEL_SLOT_B	(  1 <<  0)	/* Select SD slot A */
--# define MCI_SDCBUS_1BIT	(  0 <<  7)	/* 1-bit data bus */
--# define MCI_SDCBUS_4BIT	(  1 <<  7)	/* 4-bit data bus */
-+# define MCI_SDCSEL_SLOT_B	(  1 <<  0)	/* Select SD slot B */
-+# define MCI_SDCSEL_MASK	(  3 <<  0)
-+# define MCI_SDCBUS_1BIT	(  0 <<  6)	/* 1-bit data bus */
-+# define MCI_SDCBUS_4BIT	(  2 <<  6)	/* 4-bit data bus */
-+# define MCI_SDCBUS_8BIT	(  3 <<  6)	/* 8-bit data bus[2] */
-+# define MCI_SDCBUS_MASK	(  3 <<  6)
- #define MCI_ARGR		0x0010	/* Command Argument */
- #define MCI_CMDR		0x0014	/* Command */
- # define MCI_CMDR_CMDNB(x)	((x) <<  0)	/* Command Opcode */
-@@ -54,6 +65,9 @@
- #define MCI_BLKR		0x0018	/* Block */
- # define MCI_BCNT(x)		((x) <<  0)	/* Data Block Count */
- # define MCI_BLKLEN(x)		((x) << 16)	/* Data Block Length */
-+#define MCI_CSTOR		0x001c	/* Completion Signal Timeout[2] */
-+# define MCI_CSTOCYC(x)		((x) <<  0)	/* CST cycles */
-+# define MCI_CSTOMUL(x)		((x) <<  4)	/* CST multiplier */
- #define MCI_RSPR		0x0020	/* Response 0 */
- #define MCI_RSPR1		0x0024	/* Response 1 */
- #define MCI_RSPR2		0x0028	/* Response 2 */
-@@ -64,24 +78,45 @@
- #define MCI_IER			0x0044	/* Interrupt Enable */
- #define MCI_IDR			0x0048	/* Interrupt Disable */
- #define MCI_IMR			0x004c	/* Interrupt Mask */
--# define MCI_CMDRDY		(  1 <<   0)	/* Command Ready */
--# define MCI_RXRDY		(  1 <<   1)	/* Receiver Ready */
--# define MCI_TXRDY		(  1 <<   2)	/* Transmitter Ready */
--# define MCI_BLKE		(  1 <<   3)	/* Data Block Ended */
--# define MCI_DTIP		(  1 <<   4)	/* Data Transfer In Progress */
--# define MCI_NOTBUSY		(  1 <<   5)	/* Data Not Busy */
--# define MCI_SDIOIRQA		(  1 <<   8)	/* SDIO IRQ in slot A */
--# define MCI_SDIOIRQB		(  1 <<   9)	/* SDIO IRQ in slot B */
--# define MCI_RINDE		(  1 <<  16)	/* Response Index Error */
--# define MCI_RDIRE		(  1 <<  17)	/* Response Direction Error */
--# define MCI_RCRCE		(  1 <<  18)	/* Response CRC Error */
--# define MCI_RENDE		(  1 <<  19)	/* Response End Bit Error */
--# define MCI_RTOE		(  1 <<  20)	/* Response Time-Out Error */
--# define MCI_DCRCE		(  1 <<  21)	/* Data CRC Error */
--# define MCI_DTOE		(  1 <<  22)	/* Data Time-Out Error */
--# define MCI_OVRE		(  1 <<  30)	/* RX Overrun Error */
--# define MCI_UNRE		(  1 <<  31)	/* TX Underrun Error */
-+# define MCI_CMDRDY		(  1 <<  0)	/* Command Ready */
-+# define MCI_RXRDY		(  1 <<  1)	/* Receiver Ready */
-+# define MCI_TXRDY		(  1 <<  2)	/* Transmitter Ready */
-+# define MCI_BLKE		(  1 <<  3)	/* Data Block Ended */
-+# define MCI_DTIP		(  1 <<  4)	/* Data Transfer In Progress */
-+# define MCI_NOTBUSY		(  1 <<  5)	/* Data Not Busy */
-+# define MCI_SDIOIRQA		(  1 <<  8)	/* SDIO IRQ in slot A */
-+# define MCI_SDIOIRQB		(  1 <<  9)	/* SDIO IRQ in slot B */
-+# define MCI_RINDE		(  1 << 16)	/* Response Index Error */
-+# define MCI_RDIRE		(  1 << 17)	/* Response Direction Error */
-+# define MCI_RCRCE		(  1 << 18)	/* Response CRC Error */
-+# define MCI_RENDE		(  1 << 19)	/* Response End Bit Error */
-+# define MCI_RTOE		(  1 << 20)	/* Response Time-Out Error */
-+# define MCI_DCRCE		(  1 << 21)	/* Data CRC Error */
-+# define MCI_DTOE		(  1 << 22)	/* Data Time-Out Error */
-+# define MCI_OVRE		(  1 << 30)	/* RX Overrun Error */
-+# define MCI_UNRE		(  1 << 31)	/* TX Underrun Error */
-+#define MCI_DMA			0x0050	/* DMA Configuration[2] */
-+# define MCI_DMA_OFFSET(x)	((x) <<  0)	/* DMA write buffer offset */
-+# define MCI_DMA_CHKSIZE_1	(  0 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_4	(  1 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_8	(  2 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_16	(  3 <<  5)	/* DMA chunk size */
-+# define MCI_DMAEN		(  1 <<  8)	/* DMA HW handshake enable */
-+#define MCI_CFG			0x0054	/* Configuration[2] */
-+# define MCI_CFG_FIFOMODE	(  1 <<  0)	/* Start transfer ASAP */
-+# define MCI_CFG_FERRCTRL	(  1 <<  4)	/* xrun flags clear-on-read */
-+# define MCI_CFG_HSMODE		(  1 <<  8)	/* Use high-speed signaling */
-+# define MCI_CFG_LSYNC		(  1 << 12)	/* Synchronize on last block */
-+#define MCI_WPMR		0x00e4	/* Write Protect Mode[2] */
-+# define MCI_WP_EN		(  1 <<  0)	/* WP Enable */
-+# define MCI_WP_KEY		(0x4d4349 << 8)	/* WP Key */
-+#define MCI_WPSR		0x00e8	/* Write Protect Status[2] */
-+# define MCI_GET_WP_VS(x)	((x) & 0x0f)
-+# define MCI_GET_WP_VSRC(x)	(((x) >> 8) & 0xffff)
-+#define MCI_VERSION		0x00fc	/* MCI Core Version[2] */
-+#define MCI_FIFO_APERTURE	0x0200	/* FIFO Aperture[2] */
- 
-+/* This is not including the FIFO Aperture on MCI2 */
- #define MCI_REGS_SIZE		0x100
- 
- /* Register access macros */
-diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
-index 0000896..3480a5a 100644
---- a/drivers/mmc/host/atmel-mci.c
-+++ b/drivers/mmc/host/atmel-mci.c
-@@ -11,6 +11,8 @@
- #include <linux/clk.h>
- #include <linux/debugfs.h>
- #include <linux/device.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
- #include <linux/err.h>
- #include <linux/gpio.h>
- #include <linux/init.h>
-@@ -29,68 +31,195 @@
- #include <asm/unaligned.h>
- 
- #include <mach/board.h>
-+#include <mach/cpu.h>
- 
- #include "atmel-mci-regs.h"
- 
- #define ATMCI_DATA_ERROR_FLAGS	(MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE)
-+#define ATMCI_DMA_THRESHOLD	16
- 
- enum {
- 	EVENT_CMD_COMPLETE = 0,
--	EVENT_DATA_ERROR,
--	EVENT_DATA_COMPLETE,
--	EVENT_STOP_SENT,
--	EVENT_STOP_COMPLETE,
- 	EVENT_XFER_COMPLETE,
-+	EVENT_DATA_COMPLETE,
-+	EVENT_DATA_ERROR,
-+};
-+
-+enum atmel_mci_state {
-+	STATE_IDLE = 0,
-+	STATE_SENDING_CMD,
-+	STATE_SENDING_DATA,
-+	STATE_DATA_BUSY,
-+	STATE_SENDING_STOP,
-+	STATE_DATA_ERROR,
-+};
-+
-+struct atmel_mci_dma {
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	struct dma_client		client;
-+	struct dma_chan			*chan;
-+	struct dma_async_tx_descriptor	*data_desc;
-+#endif
- };
- 
-+/**
-+ * struct atmel_mci - MMC controller state shared between all slots
-+ * @lock: Spinlock protecting the queue and associated data.
-+ * @regs: Pointer to MMIO registers.
-+ * @sg: Scatterlist entry currently being processed by PIO code, if any.
-+ * @pio_offset: Offset into the current scatterlist entry.
-+ * @cur_slot: The slot which is currently using the controller.
-+ * @mrq: The request currently being processed on @cur_slot,
-+ *	or NULL if the controller is idle.
-+ * @cmd: The command currently being sent to the card, or NULL.
-+ * @data: The data currently being transferred, or NULL if no data
-+ *	transfer is in progress.
-+ * @dma: DMA client state.
-+ * @data_chan: DMA channel being used for the current data transfer.
-+ * @cmd_status: Snapshot of SR taken upon completion of the current
-+ *	command. Only valid when EVENT_CMD_COMPLETE is pending.
-+ * @data_status: Snapshot of SR taken upon completion of the current
-+ *	data transfer. Only valid when EVENT_DATA_COMPLETE or
-+ *	EVENT_DATA_ERROR is pending.
-+ * @stop_cmdr: Value to be loaded into CMDR when the stop command is
-+ *	to be sent.
-+ * @tasklet: Tasklet running the request state machine.
-+ * @pending_events: Bitmask of events flagged by the interrupt handler
-+ *	to be processed by the tasklet.
-+ * @completed_events: Bitmask of events which the state machine has
-+ *	processed.
-+ * @state: Tasklet state.
-+ * @queue: List of slots waiting for access to the controller.
-+ * @need_clock_update: Update the clock rate before the next request.
-+ * @need_reset: Reset controller before next request.
-+ * @mode_reg: Value of the MR register.
-+ * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
-+ *	rate and timeout calculations.
-+ * @mapbase: Physical address of the MMIO registers.
-+ * @mck: The peripheral bus clock hooked up to the MMC controller.
-+ * @pdev: Platform device associated with the MMC controller.
-+ * @slot: Slots sharing this MMC controller.
-+ *
-+ * Locking
-+ * =======
-+ *
-+ * @lock is a softirq-safe spinlock protecting @queue as well as
-+ * @cur_slot, @mrq and @state. These must always be updated
-+ * at the same time while holding @lock.
-+ *
-+ * @lock also protects mode_reg and need_clock_update since these are
-+ * used to synchronize mode register updates with the queue
-+ * processing.
-+ *
-+ * The @mrq field of struct atmel_mci_slot is also protected by @lock,
-+ * and must always be written at the same time as the slot is added to
-+ * @queue.
-+ *
-+ * @pending_events and @completed_events are accessed using atomic bit
-+ * operations, so they don't need any locking.
-+ *
-+ * None of the fields touched by the interrupt handler need any
-+ * locking. However, ordering is important: Before EVENT_DATA_ERROR or
-+ * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
-+ * interrupts must be disabled and @data_status updated with a
-+ * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
-+ * CMDRDY interupt must be disabled and @cmd_status updated with a
-+ * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
-+ * bytes_xfered field of @data must be written. This is ensured by
-+ * using barriers.
-+ */
- struct atmel_mci {
--	struct mmc_host		*mmc;
-+	spinlock_t		lock;
- 	void __iomem		*regs;
- 
- 	struct scatterlist	*sg;
- 	unsigned int		pio_offset;
- 
-+	struct atmel_mci_slot	*cur_slot;
- 	struct mmc_request	*mrq;
- 	struct mmc_command	*cmd;
- 	struct mmc_data		*data;
- 
-+	struct atmel_mci_dma	dma;
-+	struct dma_chan		*data_chan;
-+
- 	u32			cmd_status;
- 	u32			data_status;
--	u32			stop_status;
- 	u32			stop_cmdr;
- 
--	u32			mode_reg;
--	u32			sdc_reg;
--
- 	struct tasklet_struct	tasklet;
- 	unsigned long		pending_events;
- 	unsigned long		completed_events;
-+	enum atmel_mci_state	state;
-+	struct list_head	queue;
- 
--	int			present;
--	int			detect_pin;
--	int			wp_pin;
--
--	/* For detect pin debouncing */
--	struct timer_list	detect_timer;
--
-+	bool			need_clock_update;
-+	bool			need_reset;
-+	u32			mode_reg;
- 	unsigned long		bus_hz;
- 	unsigned long		mapbase;
- 	struct clk		*mck;
- 	struct platform_device	*pdev;
-+
-+	struct atmel_mci_slot	*slot[ATMEL_MCI_MAX_NR_SLOTS];
-+};
-+
-+/**
-+ * struct atmel_mci_slot - MMC slot state
-+ * @mmc: The mmc_host representing this slot.
-+ * @host: The MMC controller this slot is using.
-+ * @sdc_reg: Value of SDCR to be written before using this slot.
-+ * @mrq: mmc_request currently being processed or waiting to be
-+ *	processed, or NULL when the slot is idle.
-+ * @queue_node: List node for placing this node in the @queue list of
-+ *	&struct atmel_mci.
-+ * @clock: Clock rate configured by set_ios(). Protected by host->lock.
-+ * @flags: Random state bits associated with the slot.
-+ * @detect_pin: GPIO pin used for card detection, or negative if not
-+ *	available.
-+ * @wp_pin: GPIO pin used for card write protect sending, or negative
-+ *	if not available.
-+ * @detect_timer: Timer used for debouncing @detect_pin interrupts.
-+ */
-+struct atmel_mci_slot {
-+	struct mmc_host		*mmc;
-+	struct atmel_mci	*host;
-+
-+	u32			sdc_reg;
-+
-+	struct mmc_request	*mrq;
-+	struct list_head	queue_node;
-+
-+	unsigned int		clock;
-+	unsigned long		flags;
-+#define ATMCI_CARD_PRESENT	0
-+#define ATMCI_CARD_NEED_INIT	1
-+#define ATMCI_SHUTDOWN		2
-+
-+	int			detect_pin;
-+	int			wp_pin;
-+
-+	struct timer_list	detect_timer;
- };
- 
--#define atmci_is_completed(host, event)				\
--	test_bit(event, &host->completed_events)
- #define atmci_test_and_clear_pending(host, event)		\
- 	test_and_clear_bit(event, &host->pending_events)
--#define atmci_test_and_set_completed(host, event)		\
--	test_and_set_bit(event, &host->completed_events)
- #define atmci_set_completed(host, event)			\
- 	set_bit(event, &host->completed_events)
- #define atmci_set_pending(host, event)				\
- 	set_bit(event, &host->pending_events)
--#define atmci_clear_pending(host, event)			\
--	clear_bit(event, &host->pending_events)
-+
-+/*
-+ * The new MCI2 module isn't 100% compatible with the old MCI module,
-+ * and it has a few nice features which we want to use...
-+ */
-+static inline bool atmci_is_mci2(void)
-+{
-+	if (cpu_is_at32ap7200())
-+		return true;
-+
-+	return false;
-+}
- 
- /*
-  * The debugfs stuff below is mostly optimized away when
-@@ -98,14 +227,15 @@ struct atmel_mci {
-  */
- static int atmci_req_show(struct seq_file *s, void *v)
- {
--	struct atmel_mci	*host = s->private;
--	struct mmc_request	*mrq = host->mrq;
-+	struct atmel_mci_slot	*slot = s->private;
-+	struct mmc_request	*mrq;
- 	struct mmc_command	*cmd;
- 	struct mmc_command	*stop;
- 	struct mmc_data		*data;
- 
- 	/* Make sure we get a consistent snapshot */
--	spin_lock_irq(&host->mmc->lock);
-+	spin_lock_bh(&slot->host->lock);
-+	mrq = slot->mrq;
- 
- 	if (mrq) {
- 		cmd = mrq->cmd;
-@@ -130,7 +260,7 @@ static int atmci_req_show(struct seq_file *s, void *v)
- 				stop->resp[2], stop->error);
- 	}
- 
--	spin_unlock_irq(&host->mmc->lock);
-+	spin_unlock_bh(&slot->host->lock);
- 
- 	return 0;
- }
-@@ -158,8 +288,15 @@ static void atmci_show_status_reg(struct seq_file *s,
- 		[3]	= "BLKE",
- 		[4]	= "DTIP",
- 		[5]	= "NOTBUSY",
-+		[6]	= "ENDRX",
-+		[7]	= "ENDTX",
- 		[8]	= "SDIOIRQA",
- 		[9]	= "SDIOIRQB",
-+		[10]	= "SDIOIRQC",
-+		[11]	= "SDIOIRQD",
-+		[12]	= "SDIOWAIT",
-+		[14]	= "RXBUFF",
-+		[15]	= "TXBUFE",
- 		[16]	= "RINDE",
- 		[17]	= "RDIRE",
- 		[18]	= "RCRCE",
-@@ -167,6 +304,11 @@ static void atmci_show_status_reg(struct seq_file *s,
- 		[20]	= "RTOE",
- 		[21]	= "DCRCE",
- 		[22]	= "DTOE",
-+		[23]	= "CSTOE",
-+		[24]	= "BLKOVRE",
-+		[25]	= "DMADONE",
-+		[26]	= "FIFOEMPTY",
-+		[27]	= "XFRDONE",
- 		[30]	= "OVRE",
- 		[31]	= "UNRE",
- 	};
-@@ -193,12 +335,16 @@ static int atmci_regs_show(struct seq_file *s, void *v)
- 	if (!buf)
- 		return -ENOMEM;
- 
--	/* Grab a more or less consistent snapshot */
--	spin_lock_irq(&host->mmc->lock);
-+	/*
-+	 * Grab a more or less consistent snapshot. Note that we're
-+	 * not disabling interrupts, so IMR and SR may not be
-+	 * consistent.
-+	 */
-+	spin_lock_bh(&host->lock);
- 	clk_enable(host->mck);
- 	memcpy_fromio(buf, host->regs, MCI_REGS_SIZE);
- 	clk_disable(host->mck);
--	spin_unlock_irq(&host->mmc->lock);
-+	spin_unlock_bh(&host->lock);
- 
- 	seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
- 			buf[MCI_MR / 4],
-@@ -236,13 +382,13 @@ static const struct file_operations atmci_regs_fops = {
- 	.release	= single_release,
- };
- 
--static void atmci_init_debugfs(struct atmel_mci *host)
-+static void atmci_init_debugfs(struct atmel_mci_slot *slot)
- {
--	struct mmc_host	*mmc;
--	struct dentry	*root;
--	struct dentry	*node;
-+	struct mmc_host		*mmc = slot->mmc;
-+	struct atmel_mci	*host = slot->host;
-+	struct dentry		*root;
-+	struct dentry		*node;
- 
--	mmc = host->mmc;
- 	root = mmc->debugfs_root;
- 	if (!root)
- 		return;
-@@ -254,7 +400,11 @@ static void atmci_init_debugfs(struct atmel_mci *host)
- 	if (!node)
- 		goto err;
- 
--	node = debugfs_create_file("req", S_IRUSR, root, host, &atmci_req_fops);
-+	node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
-+	if (!node)
-+		goto err;
-+
-+	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
- 	if (!node)
- 		goto err;
- 
-@@ -271,25 +421,7 @@ static void atmci_init_debugfs(struct atmel_mci *host)
- 	return;
- 
- err:
--	dev_err(&host->pdev->dev,
--		"failed to initialize debugfs for controller\n");
--}
--
--static void atmci_enable(struct atmel_mci *host)
--{
--	clk_enable(host->mck);
--	mci_writel(host, CR, MCI_CR_MCIEN);
--	mci_writel(host, MR, host->mode_reg);
--	mci_writel(host, SDCR, host->sdc_reg);
--}
--
--static void atmci_disable(struct atmel_mci *host)
--{
--	mci_writel(host, CR, MCI_CR_SWRST);
--
--	/* Stall until write is complete, then disable the bus clock */
--	mci_readl(host, SR);
--	clk_disable(host->mck);
-+	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
- }
- 
- static inline unsigned int ns_to_clocks(struct atmel_mci *host,
-@@ -299,7 +431,7 @@ static inline unsigned int ns_to_clocks(struct atmel_mci *host,
- }
- 
- static void atmci_set_timeout(struct atmel_mci *host,
--			      struct mmc_data *data)
-+		struct atmel_mci_slot *slot, struct mmc_data *data)
- {
- 	static unsigned	dtomul_to_shift[] = {
- 		0, 4, 7, 8, 10, 12, 16, 20
-@@ -322,7 +454,7 @@ static void atmci_set_timeout(struct atmel_mci *host,
- 		dtocyc = 15;
- 	}
- 
--	dev_vdbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
-+	dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
- 			dtocyc << dtomul_to_shift[dtomul]);
- 	mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc)));
- }
-@@ -375,15 +507,12 @@ static u32 atmci_prepare_command(struct mmc_host *mmc,
- }
- 
- static void atmci_start_command(struct atmel_mci *host,
--				struct mmc_command *cmd,
--				u32 cmd_flags)
-+		struct mmc_command *cmd, u32 cmd_flags)
- {
--	/* Must read host->cmd after testing event flags */
--	smp_rmb();
- 	WARN_ON(host->cmd);
- 	host->cmd = cmd;
- 
--	dev_vdbg(&host->mmc->class_dev,
-+	dev_vdbg(&host->pdev->dev,
- 			"start command: ARGR=0x%08x CMDR=0x%08x\n",
- 			cmd->arg, cmd_flags);
- 
-@@ -391,34 +520,172 @@ static void atmci_start_command(struct atmel_mci *host,
- 	mci_writel(host, CMDR, cmd_flags);
- }
- 
--static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data)
-+static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
- {
--	struct atmel_mci *host = mmc_priv(mmc);
--
- 	atmci_start_command(host, data->stop, host->stop_cmdr);
- 	mci_writel(host, IER, MCI_CMDRDY);
- }
- 
--static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+static void atmci_dma_cleanup(struct atmel_mci *host)
- {
--	struct atmel_mci *host = mmc_priv(mmc);
-+	struct mmc_data			*data = host->data;
- 
--	WARN_ON(host->cmd || host->data);
--	host->mrq = NULL;
-+	dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
-+		     ((data->flags & MMC_DATA_WRITE)
-+		      ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
-+}
-+
-+static void atmci_stop_dma(struct atmel_mci *host)
-+{
-+	struct dma_chan *chan = host->data_chan;
-+
-+	if (chan) {
-+		chan->device->device_terminate_all(chan);
-+		atmci_dma_cleanup(host);
-+	} else {
-+		/* Data transfer was stopped by the interrupt handler */
-+		atmci_set_pending(host, EVENT_XFER_COMPLETE);
-+		mci_writel(host, IER, MCI_NOTBUSY);
-+	}
-+}
-+
-+/* This function is called by the DMA driver from tasklet context. */
-+static void atmci_dma_complete(void *arg)
-+{
-+	struct atmel_mci	*host = arg;
-+	struct mmc_data		*data = host->data;
-+
-+	dev_vdbg(&host->pdev->dev, "DMA complete\n");
-+
-+	atmci_dma_cleanup(host);
-+
-+	/*
-+	 * If the card was removed, data will be NULL. No point trying
-+	 * to send the stop command or waiting for NBUSY in this case.
-+	 */
-+	if (data) {
-+		atmci_set_pending(host, EVENT_XFER_COMPLETE);
-+		tasklet_schedule(&host->tasklet);
-+
-+		/*
-+		 * Regardless of what the documentation says, we have
-+		 * to wait for NOTBUSY even after block read
-+		 * operations.
-+		 *
-+		 * When the DMA transfer is complete, the controller
-+		 * may still be reading the CRC from the card, i.e.
-+		 * the data transfer is still in progress and we
-+		 * haven't seen all the potential error bits yet.
-+		 *
-+		 * The interrupt handler will schedule a different
-+		 * tasklet to finish things up when the data transfer
-+		 * is completely done.
-+		 *
-+		 * We may not complete the mmc request here anyway
-+		 * because the mmc layer may call back and cause us to
-+		 * violate the "don't submit new operations from the
-+		 * completion callback" rule of the dma engine
-+		 * framework.
-+		 */
-+		mci_writel(host, IER, MCI_NOTBUSY);
-+	}
-+}
-+
-+static int
-+atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
-+{
-+	struct dma_chan			*chan;
-+	struct dma_async_tx_descriptor	*desc;
-+	struct scatterlist		*sg;
-+	unsigned int			i;
-+	enum dma_data_direction		direction;
-+
-+	/*
-+	 * We don't do DMA on "complex" transfers, i.e. with
-+	 * non-word-aligned buffers or lengths. Also, we don't bother
-+	 * with all the DMA setup overhead for short transfers.
-+	 */
-+	if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
-+		return -EINVAL;
-+	if (data->blksz & 3)
-+		return -EINVAL;
-+
-+	for_each_sg(data->sg, sg, data->sg_len, i) {
-+		if (sg->offset & 3 || sg->length & 3)
-+			return -EINVAL;
-+	}
-+
-+	/* If we don't have a channel, we can't do DMA */
-+	chan = host->dma.chan;
-+	if (chan) {
-+		dma_chan_get(chan);
-+		host->data_chan = chan;
-+	}
-+
-+	if (!chan)
-+		return -ENODEV;
-+
-+	if (atmci_is_mci2())
-+		mci_writel(host, DMA, MCI_DMAEN);
-+
-+	if (data->flags & MMC_DATA_READ)
-+		direction = DMA_FROM_DEVICE;
-+	else
-+		direction = DMA_TO_DEVICE;
-+
-+	desc = chan->device->device_prep_slave_sg(chan,
-+			data->sg, data->sg_len, direction,
-+			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+	if (!desc)
-+		return -ENOMEM;
-+
-+	host->dma.data_desc = desc;
-+	desc->callback = atmci_dma_complete;
-+	desc->callback_param = host;
-+
-+	return 0;
-+}
-+
-+static void atmci_submit_data(struct atmel_mci *host)
-+{
-+	struct dma_chan			*chan = host->data_chan;
-+	struct dma_async_tx_descriptor	*desc = host->dma.data_desc;
-+
-+	if (chan) {
-+		desc->tx_submit(desc);
-+		chan->device->device_issue_pending(chan);
-+	}
-+}
- 
--	atmci_disable(host);
-+#else /* CONFIG_MMC_ATMELMCI_DMA */
- 
--	mmc_request_done(mmc, mrq);
-+static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
-+{
-+	return -ENOSYS;
- }
- 
-+static void atmci_submit_data(struct atmel_mci *host)
-+{
-+
-+}
-+
-+static void atmci_stop_dma(struct atmel_mci *host)
-+{
-+	/* Data transfer was stopped by the interrupt handler */
-+	atmci_set_pending(host, EVENT_XFER_COMPLETE);
-+	mci_writel(host, IER, MCI_NOTBUSY);
-+}
-+
-+#endif /* CONFIG_MMC_ATMELMCI_DMA */
-+
- /*
-  * Returns a mask of interrupt flags to be enabled after the whole
-  * request has been prepared.
-  */
--static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data)
-+static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
--	u32			iflags;
-+	u32 iflags;
- 
- 	data->error = -EINPROGRESS;
- 
-@@ -426,77 +693,95 @@ static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data)
- 	host->sg = NULL;
- 	host->data = data;
- 
--	dev_vdbg(&mmc->class_dev, "BLKR=0x%08x\n",
--			MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
--
- 	iflags = ATMCI_DATA_ERROR_FLAGS;
--	host->sg = data->sg;
--	host->pio_offset = 0;
--	if (data->flags & MMC_DATA_READ)
--		iflags |= MCI_RXRDY;
--	else
--		iflags |= MCI_TXRDY;
-+	if (atmci_prepare_data_dma(host, data)) {
-+		if (atmci_is_mci2())
-+			mci_writel(host, DMA, 0);
-+		host->data_chan = NULL;
-+
-+		/*
-+		 * Errata: MMC data write operation with less than 12
-+		 * bytes is impossible.
-+		 *
-+		 * Errata: MCI Transmit Data Register (TDR) FIFO
-+		 * corruption when length is not multiple of 4.
-+		 */
-+		if (data->blocks * data->blksz < 12
-+				|| (data->blocks * data->blksz) & 3)
-+			host->need_reset = true;
-+
-+		host->sg = data->sg;
-+		host->pio_offset = 0;
-+		if (data->flags & MMC_DATA_READ)
-+			iflags |= MCI_RXRDY;
-+		else
-+			iflags |= MCI_TXRDY;
-+	}
- 
- 	return iflags;
- }
- 
--static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+static void atmci_start_request(struct atmel_mci *host,
-+		struct atmel_mci_slot *slot)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
--	struct mmc_data		*data;
-+	struct mmc_request	*mrq;
- 	struct mmc_command	*cmd;
-+	struct mmc_data		*data;
- 	u32			iflags;
--	u32			cmdflags = 0;
-+	u32			cmdflags;
- 
--	iflags = mci_readl(host, IMR);
--	if (iflags)
--		dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
--				mci_readl(host, IMR));
-+	mrq = slot->mrq;
-+	host->cur_slot = slot;
-+	host->mrq = mrq;
- 
--	WARN_ON(host->mrq != NULL);
-+	host->pending_events = 0;
-+	host->completed_events = 0;
-+	host->data_status = 0;
- 
--	/*
--	 * We may "know" the card is gone even though there's still an
--	 * electrical connection. If so, we really need to communicate
--	 * this to the MMC core since there won't be any more
--	 * interrupts as the card is completely removed. Otherwise,
--	 * the MMC core might believe the card is still there even
--	 * though the card was just removed very slowly.
--	 */
--	if (!host->present) {
--		mrq->cmd->error = -ENOMEDIUM;
--		mmc_request_done(mmc, mrq);
--		return;
-+	if (host->need_reset) {
-+		mci_writel(host, CR, MCI_CR_SWRST);
-+		mci_writel(host, CR, MCI_CR_MCIEN);
-+		mci_writel(host, MR, host->mode_reg);
-+		host->need_reset = false;
- 	}
-+	mci_writel(host, SDCR, slot->sdc_reg);
- 
--	host->mrq = mrq;
--	host->pending_events = 0;
--	host->completed_events = 0;
-+	iflags = mci_readl(host, IMR);
-+	if (iflags)
-+		dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
-+				iflags);
- 
--	atmci_enable(host);
-+	if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
-+		/* Send init sequence (74 clock cycles) */
-+		mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
-+		while (!(mci_readl(host, SR) & MCI_CMDRDY))
-+			cpu_relax();
-+	}
- 
--	/* We don't support multiple blocks of weird lengths. */
-+	iflags = 0;
- 	data = mrq->data;
- 	if (data) {
--		if (data->blocks > 1 && data->blksz & 3)
--			goto fail;
--		atmci_set_timeout(host, data);
-+		atmci_set_timeout(host, slot, data);
- 
- 		/* Must set block count/size before sending command */
- 		mci_writel(host, BLKR, MCI_BCNT(data->blocks)
- 				| MCI_BLKLEN(data->blksz));
-+		dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
-+			MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
-+
-+		iflags |= atmci_prepare_data(host, data);
- 	}
- 
--	iflags = MCI_CMDRDY;
-+	iflags |= MCI_CMDRDY;
- 	cmd = mrq->cmd;
--	cmdflags = atmci_prepare_command(mmc, cmd);
-+	cmdflags = atmci_prepare_command(slot->mmc, cmd);
- 	atmci_start_command(host, cmd, cmdflags);
- 
- 	if (data)
--		iflags |= atmci_submit_data(mmc, data);
-+		atmci_submit_data(host);
- 
- 	if (mrq->stop) {
--		host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
-+		host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
- 		host->stop_cmdr |= MCI_CMDR_STOP_XFER;
- 		if (!(data->flags & MMC_DATA_WRITE))
- 			host->stop_cmdr |= MCI_CMDR_TRDIR_READ;
-@@ -513,59 +798,156 @@ static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
- 	 * prepared yet.)
- 	 */
- 	mci_writel(host, IER, iflags);
-+}
- 
--	return;
-+static void atmci_queue_request(struct atmel_mci *host,
-+		struct atmel_mci_slot *slot, struct mmc_request *mrq)
-+{
-+	dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
-+			host->state);
-+
-+	spin_lock_bh(&host->lock);
-+	slot->mrq = mrq;
-+	if (host->state == STATE_IDLE) {
-+		host->state = STATE_SENDING_CMD;
-+		atmci_start_request(host, slot);
-+	} else {
-+		list_add_tail(&slot->queue_node, &host->queue);
-+	}
-+	spin_unlock_bh(&host->lock);
-+}
- 
--fail:
--	atmci_disable(host);
--	host->mrq = NULL;
--	mrq->cmd->error = -EINVAL;
--	mmc_request_done(mmc, mrq);
-+static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
-+	struct atmel_mci	*host = slot->host;
-+	struct mmc_data		*data;
-+
-+	WARN_ON(slot->mrq);
-+
-+	/*
-+	 * We may "know" the card is gone even though there's still an
-+	 * electrical connection. If so, we really need to communicate
-+	 * this to the MMC core since there won't be any more
-+	 * interrupts as the card is completely removed. Otherwise,
-+	 * the MMC core might believe the card is still there even
-+	 * though the card was just removed very slowly.
-+	 */
-+	if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
-+		mrq->cmd->error = -ENOMEDIUM;
-+		mmc_request_done(mmc, mrq);
-+		return;
-+	}
-+
-+	/* We don't support multiple blocks of weird lengths. */
-+	data = mrq->data;
-+	if (data && data->blocks > 1 && data->blksz & 3) {
-+		mrq->cmd->error = -EINVAL;
-+		mmc_request_done(mmc, mrq);
-+	}
-+
-+	atmci_queue_request(host, slot, mrq);
- }
- 
- static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
-+	struct atmel_mci	*host = slot->host;
-+	unsigned int		i;
-+
-+	slot->sdc_reg &= ~MCI_SDCBUS_MASK;
-+	switch (ios->bus_width) {
-+	case MMC_BUS_WIDTH_1:
-+		slot->sdc_reg |= MCI_SDCBUS_1BIT;
-+		break;
-+	case MMC_BUS_WIDTH_4:
-+		slot->sdc_reg |= MCI_SDCBUS_4BIT;
-+		break;
-+	}
- 
- 	if (ios->clock) {
-+		unsigned int clock_min = ~0U;
- 		u32 clkdiv;
- 
--		/* Set clock rate */
--		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1;
-+		spin_lock_bh(&host->lock);
-+		if (!host->mode_reg) {
-+			clk_enable(host->mck);
-+			mci_writel(host, CR, MCI_CR_SWRST);
-+			mci_writel(host, CR, MCI_CR_MCIEN);
-+		}
-+
-+		/*
-+		 * Use mirror of ios->clock to prevent race with mmc
-+		 * core ios update when finding the minimum.
-+		 */
-+		slot->clock = ios->clock;
-+		for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
-+			if (host->slot[i] && host->slot[i]->clock
-+					&& host->slot[i]->clock < clock_min)
-+				clock_min = host->slot[i]->clock;
-+		}
-+
-+		/* Calculate clock divider */
-+		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
- 		if (clkdiv > 255) {
- 			dev_warn(&mmc->class_dev,
- 				"clock %u too slow; using %lu\n",
--				ios->clock, host->bus_hz / (2 * 256));
-+				clock_min, host->bus_hz / (2 * 256));
- 			clkdiv = 255;
- 		}
- 
-+		/*
-+		 * WRPROOF and RDPROOF prevent overruns/underruns by
-+		 * stopping the clock when the FIFO is full/empty.
-+		 * This state is not expected to last for long.
-+		 */
- 		host->mode_reg = MCI_MR_CLKDIV(clkdiv) | MCI_MR_WRPROOF
- 					| MCI_MR_RDPROOF;
--	}
- 
--	switch (ios->bus_width) {
--	case MMC_BUS_WIDTH_1:
--		host->sdc_reg = 0;
--		break;
--	case MMC_BUS_WIDTH_4:
--		host->sdc_reg = MCI_SDCBUS_4BIT;
--		break;
-+		if (list_empty(&host->queue))
-+			mci_writel(host, MR, host->mode_reg);
-+		else
-+			host->need_clock_update = true;
-+
-+		spin_unlock_bh(&host->lock);
-+	} else {
-+		bool any_slot_active = false;
-+
-+		spin_lock_bh(&host->lock);
-+		slot->clock = 0;
-+		for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
-+			if (host->slot[i] && host->slot[i]->clock) {
-+				any_slot_active = true;
-+				break;
-+			}
-+		}
-+		if (!any_slot_active) {
-+			mci_writel(host, CR, MCI_CR_MCIDIS);
-+			if (host->mode_reg) {
-+				mci_readl(host, MR);
-+				clk_disable(host->mck);
-+			}
-+			host->mode_reg = 0;
-+		}
-+		spin_unlock_bh(&host->lock);
- 	}
- 
- 	switch (ios->power_mode) {
--	case MMC_POWER_ON:
--		/* Send init sequence (74 clock cycles) */
--		atmci_enable(host);
--		mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
--		while (!(mci_readl(host, SR) & MCI_CMDRDY))
--			cpu_relax();
--		atmci_disable(host);
-+	case MMC_POWER_UP:
-+		set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
- 		break;
- 	default:
- 		/*
- 		 * TODO: None of the currently available AVR32-based
- 		 * boards allow MMC power to be turned off. Implement
- 		 * power control when this can be tested properly.
-+		 *
-+		 * We also need to hook this into the clock management
-+		 * somehow so that newly inserted cards aren't
-+		 * subjected to a fast clock before we have a chance
-+		 * to figure out what the maximum rate is. Currently,
-+		 * there's no way to avoid this, and there never will
-+		 * be for boards that don't support power control.
- 		 */
- 		break;
- 	}
-@@ -573,31 +955,82 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
- 
- static int atmci_get_ro(struct mmc_host *mmc)
- {
--	int			read_only = 0;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	int			read_only = -ENOSYS;
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
- 
--	if (gpio_is_valid(host->wp_pin)) {
--		read_only = gpio_get_value(host->wp_pin);
-+	if (gpio_is_valid(slot->wp_pin)) {
-+		read_only = gpio_get_value(slot->wp_pin);
- 		dev_dbg(&mmc->class_dev, "card is %s\n",
- 				read_only ? "read-only" : "read-write");
--	} else {
--		dev_dbg(&mmc->class_dev,
--			"no pin for checking read-only switch."
--			" Assuming write-enable.\n");
- 	}
- 
- 	return read_only;
- }
- 
--static struct mmc_host_ops atmci_ops = {
-+static int atmci_get_cd(struct mmc_host *mmc)
-+{
-+	int			present = -ENOSYS;
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
-+
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		present = !gpio_get_value(slot->detect_pin);
-+		dev_dbg(&mmc->class_dev, "card is %spresent\n",
-+				present ? "" : "not ");
-+	}
-+
-+	return present;
-+}
-+
-+static const struct mmc_host_ops atmci_ops = {
- 	.request	= atmci_request,
- 	.set_ios	= atmci_set_ios,
- 	.get_ro		= atmci_get_ro,
-+	.get_cd		= atmci_get_cd,
- };
- 
-+/* Called with host->lock held */
-+static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
-+	__releases(&host->lock)
-+	__acquires(&host->lock)
-+{
-+	struct atmel_mci_slot	*slot = NULL;
-+	struct mmc_host		*prev_mmc = host->cur_slot->mmc;
-+
-+	WARN_ON(host->cmd || host->data);
-+
-+	/*
-+	 * Update the MMC clock rate if necessary. This may be
-+	 * necessary if set_ios() is called when a different slot is
-+	 * busy transfering data.
-+	 */
-+	if (host->need_clock_update)
-+		mci_writel(host, MR, host->mode_reg);
-+
-+	host->cur_slot->mrq = NULL;
-+	host->mrq = NULL;
-+	if (!list_empty(&host->queue)) {
-+		slot = list_entry(host->queue.next,
-+				struct atmel_mci_slot, queue_node);
-+		list_del(&slot->queue_node);
-+		dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
-+				mmc_hostname(slot->mmc));
-+		host->state = STATE_SENDING_CMD;
-+		atmci_start_request(host, slot);
-+	} else {
-+		dev_vdbg(&host->pdev->dev, "list empty\n");
-+		host->state = STATE_IDLE;
-+	}
-+
-+	spin_unlock(&host->lock);
-+	mmc_request_done(prev_mmc, mrq);
-+	spin_lock(&host->lock);
-+}
-+
- static void atmci_command_complete(struct atmel_mci *host,
--			struct mmc_command *cmd, u32 status)
-+			struct mmc_command *cmd)
- {
-+	u32		status = host->cmd_status;
-+
- 	/* Read the response from the card (up to 16 bytes) */
- 	cmd->resp[0] = mci_readl(host, RSPR);
- 	cmd->resp[1] = mci_readl(host, RSPR);
-@@ -614,11 +1047,12 @@ static void atmci_command_complete(struct atmel_mci *host,
- 		cmd->error = 0;
- 
- 	if (cmd->error) {
--		dev_dbg(&host->mmc->class_dev,
-+		dev_dbg(&host->pdev->dev,
- 			"command error: status=0x%08x\n", status);
- 
- 		if (cmd->data) {
- 			host->data = NULL;
-+			atmci_stop_dma(host);
- 			mci_writel(host, IDR, MCI_NOTBUSY
- 					| MCI_TXRDY | MCI_RXRDY
- 					| ATMCI_DATA_ERROR_FLAGS);
-@@ -628,146 +1062,222 @@ static void atmci_command_complete(struct atmel_mci *host,
- 
- static void atmci_detect_change(unsigned long data)
- {
--	struct atmel_mci *host = (struct atmel_mci *)data;
--	struct mmc_request *mrq = host->mrq;
--	int present;
-+	struct atmel_mci_slot	*slot = (struct atmel_mci_slot *)data;
-+	bool			present;
-+	bool			present_old;
- 
- 	/*
--	 * atmci_remove() sets detect_pin to -1 before freeing the
--	 * interrupt. We must not re-enable the interrupt if it has
--	 * been freed.
-+	 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
-+	 * freeing the interrupt. We must not re-enable the interrupt
-+	 * if it has been freed, and if we're shutting down, it
-+	 * doesn't really matter whether the card is present or not.
- 	 */
- 	smp_rmb();
--	if (!gpio_is_valid(host->detect_pin))
-+	if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
- 		return;
- 
--	enable_irq(gpio_to_irq(host->detect_pin));
--	present = !gpio_get_value(host->detect_pin);
-+	enable_irq(gpio_to_irq(slot->detect_pin));
-+	present = !gpio_get_value(slot->detect_pin);
-+	present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+
-+	dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
-+			present, present_old);
- 
--	dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n",
--			present, host->present);
-+	if (present != present_old) {
-+		struct atmel_mci	*host = slot->host;
-+		struct mmc_request	*mrq;
- 
--	if (present != host->present) {
--		dev_dbg(&host->mmc->class_dev, "card %s\n",
-+		dev_dbg(&slot->mmc->class_dev, "card %s\n",
- 			present ? "inserted" : "removed");
--		host->present = present;
- 
--		/* Reset controller if card is gone */
--		if (!present) {
--			mci_writel(host, CR, MCI_CR_SWRST);
--			mci_writel(host, IDR, ~0UL);
--			mci_writel(host, CR, MCI_CR_MCIEN);
--		}
-+		spin_lock(&host->lock);
-+
-+		if (!present)
-+			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+		else
-+			set_bit(ATMCI_CARD_PRESENT, &slot->flags);
- 
- 		/* Clean up queue if present */
-+		mrq = slot->mrq;
- 		if (mrq) {
--			/*
--			 * Reset controller to terminate any ongoing
--			 * commands or data transfers.
--			 */
--			mci_writel(host, CR, MCI_CR_SWRST);
-+			if (mrq == host->mrq) {
-+				/*
-+				 * Reset controller to terminate any ongoing
-+				 * commands or data transfers.
-+				 */
-+				mci_writel(host, CR, MCI_CR_SWRST);
-+				mci_writel(host, CR, MCI_CR_MCIEN);
-+				mci_writel(host, MR, host->mode_reg);
- 
--			if (!atmci_is_completed(host, EVENT_CMD_COMPLETE))
--				mrq->cmd->error = -ENOMEDIUM;
--
--			if (mrq->data && !atmci_is_completed(host,
--						EVENT_DATA_COMPLETE)) {
- 				host->data = NULL;
--				mrq->data->error = -ENOMEDIUM;
-+				host->cmd = NULL;
-+
-+				switch (host->state) {
-+				case STATE_IDLE:
-+					break;
-+				case STATE_SENDING_CMD:
-+					mrq->cmd->error = -ENOMEDIUM;
-+					if (!mrq->data)
-+						break;
-+					/* fall through */
-+				case STATE_SENDING_DATA:
-+					mrq->data->error = -ENOMEDIUM;
-+					atmci_stop_dma(host);
-+					break;
-+				case STATE_DATA_BUSY:
-+				case STATE_DATA_ERROR:
-+					if (mrq->data->error == -EINPROGRESS)
-+						mrq->data->error = -ENOMEDIUM;
-+					if (!mrq->stop)
-+						break;
-+					/* fall through */
-+				case STATE_SENDING_STOP:
-+					mrq->stop->error = -ENOMEDIUM;
-+					break;
-+				}
-+
-+				atmci_request_end(host, mrq);
-+			} else {
-+				list_del(&slot->queue_node);
-+				mrq->cmd->error = -ENOMEDIUM;
-+				if (mrq->data)
-+					mrq->data->error = -ENOMEDIUM;
-+				if (mrq->stop)
-+					mrq->stop->error = -ENOMEDIUM;
-+
-+				spin_unlock(&host->lock);
-+				mmc_request_done(slot->mmc, mrq);
-+				spin_lock(&host->lock);
- 			}
--			if (mrq->stop && !atmci_is_completed(host,
--						EVENT_STOP_COMPLETE))
--				mrq->stop->error = -ENOMEDIUM;
--
--			host->cmd = NULL;
--			atmci_request_end(host->mmc, mrq);
- 		}
-+		spin_unlock(&host->lock);
- 
--		mmc_detect_change(host->mmc, 0);
-+		mmc_detect_change(slot->mmc, 0);
- 	}
- }
- 
- static void atmci_tasklet_func(unsigned long priv)
- {
--	struct mmc_host		*mmc = (struct mmc_host *)priv;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci	*host = (struct atmel_mci *)priv;
- 	struct mmc_request	*mrq = host->mrq;
- 	struct mmc_data		*data = host->data;
-+	struct mmc_command	*cmd = host->cmd;
-+	enum atmel_mci_state	state = host->state;
-+	enum atmel_mci_state	prev_state;
-+	u32			status;
-+
-+	spin_lock(&host->lock);
- 
--	dev_vdbg(&mmc->class_dev,
--		"tasklet: pending/completed/mask %lx/%lx/%x\n",
--		host->pending_events, host->completed_events,
-+	state = host->state;
-+
-+	dev_vdbg(&host->pdev->dev,
-+		"tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
-+		state, host->pending_events, host->completed_events,
- 		mci_readl(host, IMR));
- 
--	if (atmci_test_and_clear_pending(host, EVENT_CMD_COMPLETE)) {
--		/*
--		 * host->cmd must be set to NULL before the interrupt
--		 * handler sees EVENT_CMD_COMPLETE
--		 */
--		host->cmd = NULL;
--		smp_wmb();
--		atmci_set_completed(host, EVENT_CMD_COMPLETE);
--		atmci_command_complete(host, mrq->cmd, host->cmd_status);
--
--		if (!mrq->cmd->error && mrq->stop
--				&& atmci_is_completed(host, EVENT_XFER_COMPLETE)
--				&& !atmci_test_and_set_completed(host,
--					EVENT_STOP_SENT))
--			send_stop_cmd(host->mmc, mrq->data);
--	}
--	if (atmci_test_and_clear_pending(host, EVENT_STOP_COMPLETE)) {
--		/*
--		 * host->cmd must be set to NULL before the interrupt
--		 * handler sees EVENT_STOP_COMPLETE
--		 */
--		host->cmd = NULL;
--		smp_wmb();
--		atmci_set_completed(host, EVENT_STOP_COMPLETE);
--		atmci_command_complete(host, mrq->stop, host->stop_status);
--	}
--	if (atmci_test_and_clear_pending(host, EVENT_DATA_ERROR)) {
--		u32 status = host->data_status;
-+	do {
-+		prev_state = state;
- 
--		dev_vdbg(&mmc->class_dev, "data error: status=%08x\n", status);
-+		switch (state) {
-+		case STATE_IDLE:
-+			break;
- 
--		atmci_set_completed(host, EVENT_DATA_ERROR);
--		atmci_set_completed(host, EVENT_DATA_COMPLETE);
-+		case STATE_SENDING_CMD:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_CMD_COMPLETE))
-+				break;
- 
--		if (status & MCI_DTOE) {
--			dev_dbg(&mmc->class_dev,
--					"data timeout error\n");
--			data->error = -ETIMEDOUT;
--		} else if (status & MCI_DCRCE) {
--			dev_dbg(&mmc->class_dev, "data CRC error\n");
--			data->error = -EILSEQ;
--		} else {
--			dev_dbg(&mmc->class_dev,
--					"data FIFO error (status=%08x)\n",
--					status);
--			data->error = -EIO;
--		}
-+			host->cmd = NULL;
-+			atmci_set_completed(host, EVENT_CMD_COMPLETE);
-+			atmci_command_complete(host, mrq->cmd);
-+			if (!mrq->data || cmd->error) {
-+				atmci_request_end(host, host->mrq);
-+				goto unlock;
-+			}
-+
-+			prev_state = state = STATE_SENDING_DATA;
-+			/* fall through */
-+
-+		case STATE_SENDING_DATA:
-+			if (atmci_test_and_clear_pending(host,
-+						EVENT_DATA_ERROR)) {
-+				atmci_stop_dma(host);
-+				if (data->stop)
-+					send_stop_cmd(host, data);
-+				state = STATE_DATA_ERROR;
-+				break;
-+			}
- 
--		if (host->present && data->stop
--				&& atmci_is_completed(host, EVENT_CMD_COMPLETE)
--				&& !atmci_test_and_set_completed(
--					host, EVENT_STOP_SENT))
--			send_stop_cmd(host->mmc, data);
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_XFER_COMPLETE))
-+				break;
- 
--		host->data = NULL;
--	}
--	if (atmci_test_and_clear_pending(host, EVENT_DATA_COMPLETE)) {
--		atmci_set_completed(host, EVENT_DATA_COMPLETE);
-+			atmci_set_completed(host, EVENT_XFER_COMPLETE);
-+			prev_state = state = STATE_DATA_BUSY;
-+			/* fall through */
-+
-+		case STATE_DATA_BUSY:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_DATA_COMPLETE))
-+				break;
-+
-+			host->data = NULL;
-+			atmci_set_completed(host, EVENT_DATA_COMPLETE);
-+			status = host->data_status;
-+			if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
-+				if (status & MCI_DTOE) {
-+					dev_dbg(&host->pdev->dev,
-+							"data timeout error\n");
-+					data->error = -ETIMEDOUT;
-+				} else if (status & MCI_DCRCE) {
-+					dev_dbg(&host->pdev->dev,
-+							"data CRC error\n");
-+					data->error = -EILSEQ;
-+				} else {
-+					dev_dbg(&host->pdev->dev,
-+						"data FIFO error (status=%08x)\n",
-+						status);
-+					data->error = -EIO;
-+				}
-+			} else {
-+				data->bytes_xfered = data->blocks * data->blksz;
-+				data->error = 0;
-+			}
-+
-+			if (!data->stop) {
-+				atmci_request_end(host, host->mrq);
-+				goto unlock;
-+			}
-+
-+			prev_state = state = STATE_SENDING_STOP;
-+			if (!data->error)
-+				send_stop_cmd(host, data);
-+			/* fall through */
-+
-+		case STATE_SENDING_STOP:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_CMD_COMPLETE))
-+				break;
-+
-+			host->cmd = NULL;
-+			atmci_command_complete(host, mrq->stop);
-+			atmci_request_end(host, host->mrq);
-+			goto unlock;
-+
-+		case STATE_DATA_ERROR:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_XFER_COMPLETE))
-+				break;
- 
--		if (!atmci_is_completed(host, EVENT_DATA_ERROR)) {
--			data->bytes_xfered = data->blocks * data->blksz;
--			data->error = 0;
-+			state = STATE_DATA_BUSY;
-+			break;
- 		}
-+	} while (state != prev_state);
- 
--		host->data = NULL;
--	}
-+	host->state = state;
- 
--	if (host->mrq && !host->cmd && !host->data)
--		atmci_request_end(mmc, host->mrq);
-+unlock:
-+	spin_unlock(&host->lock);
- }
- 
- static void atmci_read_data_pio(struct atmel_mci *host)
-@@ -789,6 +1299,7 @@ static void atmci_read_data_pio(struct atmel_mci *host)
- 			nbytes += 4;
- 
- 			if (offset == sg->length) {
-+				flush_dcache_page(sg_page(sg));
- 				host->sg = sg = sg_next(sg);
- 				if (!sg)
- 					goto done;
-@@ -817,9 +1328,11 @@ static void atmci_read_data_pio(struct atmel_mci *host)
- 			mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY
- 						| ATMCI_DATA_ERROR_FLAGS));
- 			host->data_status = status;
-+			data->bytes_xfered += nbytes;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_ERROR);
- 			tasklet_schedule(&host->tasklet);
--			break;
-+			return;
- 		}
- 	} while (status & MCI_RXRDY);
- 
-@@ -832,10 +1345,8 @@ done:
- 	mci_writel(host, IDR, MCI_RXRDY);
- 	mci_writel(host, IER, MCI_NOTBUSY);
- 	data->bytes_xfered += nbytes;
--	atmci_set_completed(host, EVENT_XFER_COMPLETE);
--	if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE)
--			&& !atmci_test_and_set_completed(host, EVENT_STOP_SENT))
--		send_stop_cmd(host->mmc, data);
-+	smp_wmb();
-+	atmci_set_pending(host, EVENT_XFER_COMPLETE);
- }
- 
- static void atmci_write_data_pio(struct atmel_mci *host)
-@@ -888,9 +1399,11 @@ static void atmci_write_data_pio(struct atmel_mci *host)
- 			mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY
- 						| ATMCI_DATA_ERROR_FLAGS));
- 			host->data_status = status;
-+			data->bytes_xfered += nbytes;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_ERROR);
- 			tasklet_schedule(&host->tasklet);
--			break;
-+			return;
- 		}
- 	} while (status & MCI_TXRDY);
- 
-@@ -903,38 +1416,26 @@ done:
- 	mci_writel(host, IDR, MCI_TXRDY);
- 	mci_writel(host, IER, MCI_NOTBUSY);
- 	data->bytes_xfered += nbytes;
--	atmci_set_completed(host, EVENT_XFER_COMPLETE);
--	if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE)
--			&& !atmci_test_and_set_completed(host, EVENT_STOP_SENT))
--		send_stop_cmd(host->mmc, data);
-+	smp_wmb();
-+	atmci_set_pending(host, EVENT_XFER_COMPLETE);
- }
- 
--static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
-+static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
--
- 	mci_writel(host, IDR, MCI_CMDRDY);
- 
--	if (atmci_is_completed(host, EVENT_STOP_SENT)) {
--		host->stop_status = status;
--		atmci_set_pending(host, EVENT_STOP_COMPLETE);
--	} else {
--		host->cmd_status = status;
--		atmci_set_pending(host, EVENT_CMD_COMPLETE);
--	}
--
-+	host->cmd_status = status;
-+	smp_wmb();
-+	atmci_set_pending(host, EVENT_CMD_COMPLETE);
- 	tasklet_schedule(&host->tasklet);
- }
- 
- static irqreturn_t atmci_interrupt(int irq, void *dev_id)
- {
--	struct mmc_host		*mmc = dev_id;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci	*host = dev_id;
- 	u32			status, mask, pending;
- 	unsigned int		pass_count = 0;
- 
--	spin_lock(&mmc->lock);
--
- 	do {
- 		status = mci_readl(host, SR);
- 		mask = mci_readl(host, IMR);
-@@ -946,13 +1447,18 @@ static irqreturn_t atmci_interrupt(int irq, void *dev_id)
- 			mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
- 					| MCI_RXRDY | MCI_TXRDY);
- 			pending &= mci_readl(host, IMR);
-+
- 			host->data_status = status;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_ERROR);
- 			tasklet_schedule(&host->tasklet);
- 		}
- 		if (pending & MCI_NOTBUSY) {
--			mci_writel(host, IDR, (MCI_NOTBUSY
--					       | ATMCI_DATA_ERROR_FLAGS));
-+			mci_writel(host, IDR,
-+					ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY);
-+			if (!host->data_status)
-+				host->data_status = status;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_COMPLETE);
- 			tasklet_schedule(&host->tasklet);
- 		}
-@@ -962,18 +1468,15 @@ static irqreturn_t atmci_interrupt(int irq, void *dev_id)
- 			atmci_write_data_pio(host);
- 
- 		if (pending & MCI_CMDRDY)
--			atmci_cmd_interrupt(mmc, status);
-+			atmci_cmd_interrupt(host, status);
- 	} while (pass_count++ < 5);
- 
--	spin_unlock(&mmc->lock);
--
- 	return pass_count ? IRQ_HANDLED : IRQ_NONE;
- }
- 
- static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
- {
--	struct mmc_host		*mmc = dev_id;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci_slot	*slot = dev_id;
- 
- 	/*
- 	 * Disable interrupts until the pin has stabilized and check
-@@ -981,19 +1484,176 @@ static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
- 	 * middle of the timer routine when this interrupt triggers.
- 	 */
- 	disable_irq_nosync(irq);
--	mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
-+	mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
- 
- 	return IRQ_HANDLED;
- }
- 
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+
-+static inline struct atmel_mci *
-+dma_client_to_atmel_mci(struct dma_client *client)
-+{
-+	return container_of(client, struct atmel_mci, dma.client);
-+}
-+
-+static enum dma_state_client atmci_dma_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_mci	*host;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	host = dma_client_to_atmel_mci(client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		spin_lock_bh(&host->lock);
-+		if (!host->dma.chan) {
-+			host->dma.chan = chan;
-+			ret = DMA_ACK;
-+		}
-+		spin_unlock_bh(&host->lock);
-+
-+		if (ret == DMA_ACK)
-+			dev_info(&host->pdev->dev,
-+					"Using %s for DMA transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		spin_lock_bh(&host->lock);
-+		if (host->dma.chan == chan) {
-+			host->dma.chan = NULL;
-+			ret = DMA_ACK;
-+		}
-+		spin_unlock_bh(&host->lock);
-+
-+		if (ret == DMA_ACK)
-+			dev_info(&host->pdev->dev,
-+					"Lost %s, falling back to PIO\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+
-+	return ret;
-+}
-+#endif /* CONFIG_MMC_ATMELMCI_DMA */
-+
-+static int __init atmci_init_slot(struct atmel_mci *host,
-+		struct mci_slot_pdata *slot_data, unsigned int id,
-+		u32 sdc_reg)
-+{
-+	struct mmc_host			*mmc;
-+	struct atmel_mci_slot		*slot;
-+
-+	mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
-+	if (!mmc)
-+		return -ENOMEM;
-+
-+	slot = mmc_priv(mmc);
-+	slot->mmc = mmc;
-+	slot->host = host;
-+	slot->detect_pin = slot_data->detect_pin;
-+	slot->wp_pin = slot_data->wp_pin;
-+	slot->sdc_reg = sdc_reg;
-+
-+	mmc->ops = &atmci_ops;
-+	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
-+	mmc->f_max = host->bus_hz / 2;
-+	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
-+	if (slot_data->bus_width >= 4)
-+		mmc->caps |= MMC_CAP_4_BIT_DATA;
-+
-+	mmc->max_hw_segs = 64;
-+	mmc->max_phys_segs = 64;
-+	mmc->max_req_size = 32768 * 512;
-+	mmc->max_blk_size = 32768;
-+	mmc->max_blk_count = 512;
-+
-+	/* Assume card is present initially */
-+	set_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		if (gpio_request(slot->detect_pin, "mmc_detect")) {
-+			dev_dbg(&mmc->class_dev, "no detect pin available\n");
-+			slot->detect_pin = -EBUSY;
-+		} else if (gpio_get_value(slot->detect_pin)) {
-+			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+		}
-+	}
-+
-+	if (!gpio_is_valid(slot->detect_pin))
-+		mmc->caps |= MMC_CAP_NEEDS_POLL;
-+
-+	if (gpio_is_valid(slot->wp_pin)) {
-+		if (gpio_request(slot->wp_pin, "mmc_wp")) {
-+			dev_dbg(&mmc->class_dev, "no WP pin available\n");
-+			slot->wp_pin = -EBUSY;
-+		}
-+	}
-+
-+	host->slot[id] = slot;
-+	mmc_add_host(mmc);
-+
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		int ret;
-+
-+		setup_timer(&slot->detect_timer, atmci_detect_change,
-+				(unsigned long)slot);
-+
-+		ret = request_irq(gpio_to_irq(slot->detect_pin),
-+				atmci_detect_interrupt,
-+				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-+				"mmc-detect", slot);
-+		if (ret) {
-+			dev_dbg(&mmc->class_dev,
-+				"could not request IRQ %d for detect pin\n",
-+				gpio_to_irq(slot->detect_pin));
-+			gpio_free(slot->detect_pin);
-+			slot->detect_pin = -EBUSY;
-+		}
-+	}
-+
-+	atmci_init_debugfs(slot);
-+
-+	return 0;
-+}
-+
-+static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
-+		unsigned int id)
-+{
-+	/* Debugfs stuff is cleaned up by mmc core */
-+
-+	set_bit(ATMCI_SHUTDOWN, &slot->flags);
-+	smp_wmb();
-+
-+	mmc_remove_host(slot->mmc);
-+
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		int pin = slot->detect_pin;
-+
-+		free_irq(gpio_to_irq(pin), slot);
-+		del_timer_sync(&slot->detect_timer);
-+		gpio_free(pin);
-+	}
-+	if (gpio_is_valid(slot->wp_pin))
-+		gpio_free(slot->wp_pin);
-+
-+	slot->host->slot[id] = NULL;
-+	mmc_free_host(slot->mmc);
-+}
-+
- static int __init atmci_probe(struct platform_device *pdev)
- {
- 	struct mci_platform_data	*pdata;
--	struct atmel_mci *host;
--	struct mmc_host *mmc;
--	struct resource *regs;
--	int irq;
--	int ret;
-+	struct atmel_mci		*host;
-+	struct resource			*regs;
-+	unsigned int			nr_slots;
-+	int				irq;
-+	int				ret;
- 
- 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (!regs)
-@@ -1005,15 +1665,13 @@ static int __init atmci_probe(struct platform_device *pdev)
- 	if (irq < 0)
- 		return irq;
- 
--	mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
--	if (!mmc)
-+	host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
-+	if (!host)
- 		return -ENOMEM;
- 
--	host = mmc_priv(mmc);
- 	host->pdev = pdev;
--	host->mmc = mmc;
--	host->detect_pin = pdata->detect_pin;
--	host->wp_pin = pdata->wp_pin;
-+	spin_lock_init(&host->lock);
-+	INIT_LIST_HEAD(&host->queue);
- 
- 	host->mck = clk_get(&pdev->dev, "mci_clk");
- 	if (IS_ERR(host->mck)) {
-@@ -1033,122 +1691,102 @@ static int __init atmci_probe(struct platform_device *pdev)
- 
- 	host->mapbase = regs->start;
- 
--	mmc->ops = &atmci_ops;
--	mmc->f_min = (host->bus_hz + 511) / 512;
--	mmc->f_max = host->bus_hz / 2;
--	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
--	mmc->caps |= MMC_CAP_4_BIT_DATA;
-+	tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
- 
--	mmc->max_hw_segs = 64;
--	mmc->max_phys_segs = 64;
--	mmc->max_req_size = 32768 * 512;
--	mmc->max_blk_size = 32768;
--	mmc->max_blk_count = 512;
--
--	tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
--
--	ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, mmc);
-+	ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, host);
- 	if (ret)
- 		goto err_request_irq;
- 
--	/* Assume card is present if we don't have a detect pin */
--	host->present = 1;
--	if (gpio_is_valid(host->detect_pin)) {
--		if (gpio_request(host->detect_pin, "mmc_detect")) {
--			dev_dbg(&mmc->class_dev, "no detect pin available\n");
--			host->detect_pin = -1;
--		} else {
--			host->present = !gpio_get_value(host->detect_pin);
--		}
--	}
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	if (pdata->dma_slave) {
-+		struct dma_slave *slave = pdata->dma_slave;
- 
--	if (!gpio_is_valid(host->detect_pin))
--		mmc->caps |= MMC_CAP_NEEDS_POLL;
-+		slave->tx_reg = regs->start + MCI_TDR;
-+		slave->rx_reg = regs->start + MCI_RDR;
- 
--	if (gpio_is_valid(host->wp_pin)) {
--		if (gpio_request(host->wp_pin, "mmc_wp")) {
--			dev_dbg(&mmc->class_dev, "no WP pin available\n");
--			host->wp_pin = -1;
--		}
-+		/* Try to grab a DMA channel */
-+		host->dma.client.event_callback = atmci_dma_event;
-+		dma_cap_set(DMA_SLAVE, host->dma.client.cap_mask);
-+		host->dma.client.slave = slave;
-+
-+		dma_async_client_register(&host->dma.client);
-+		dma_async_client_chan_request(&host->dma.client);
-+	} else {
-+		dev_notice(&pdev->dev, "DMA not available, using PIO\n");
- 	}
-+#endif /* CONFIG_MMC_ATMELMCI_DMA */
- 
- 	platform_set_drvdata(pdev, host);
- 
--	mmc_add_host(mmc);
--
--	if (gpio_is_valid(host->detect_pin)) {
--		setup_timer(&host->detect_timer, atmci_detect_change,
--				(unsigned long)host);
--
--		ret = request_irq(gpio_to_irq(host->detect_pin),
--				atmci_detect_interrupt,
--				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
--				"mmc-detect", mmc);
--		if (ret) {
--			dev_dbg(&mmc->class_dev,
--				"could not request IRQ %d for detect pin\n",
--				gpio_to_irq(host->detect_pin));
--			gpio_free(host->detect_pin);
--			host->detect_pin = -1;
--		}
-+	/* We need at least one slot to succeed */
-+	nr_slots = 0;
-+	ret = -ENODEV;
-+	if (pdata->slot[0].bus_width) {
-+		ret = atmci_init_slot(host, &pdata->slot[0],
-+				MCI_SDCSEL_SLOT_A, 0);
-+		if (!ret)
-+			nr_slots++;
-+	}
-+	if (pdata->slot[1].bus_width) {
-+		ret = atmci_init_slot(host, &pdata->slot[1],
-+				MCI_SDCSEL_SLOT_B, 1);
-+		if (!ret)
-+			nr_slots++;
- 	}
- 
--	dev_info(&mmc->class_dev,
--			"Atmel MCI controller at 0x%08lx irq %d\n",
--			host->mapbase, irq);
-+	if (!nr_slots)
-+		goto err_init_slot;
- 
--	atmci_init_debugfs(host);
-+	dev_info(&pdev->dev,
-+			"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
-+			host->mapbase, irq, nr_slots);
- 
- 	return 0;
- 
-+err_init_slot:
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	if (pdata->dma_slave)
-+		dma_async_client_unregister(&host->dma.client);
-+#endif
-+	free_irq(irq, host);
- err_request_irq:
- 	iounmap(host->regs);
- err_ioremap:
- 	clk_put(host->mck);
- err_clk_get:
--	mmc_free_host(mmc);
-+	kfree(host);
- 	return ret;
- }
- 
- static int __exit atmci_remove(struct platform_device *pdev)
- {
--	struct atmel_mci *host = platform_get_drvdata(pdev);
-+	struct atmel_mci	*host = platform_get_drvdata(pdev);
-+	unsigned int		i;
- 
- 	platform_set_drvdata(pdev, NULL);
- 
--	if (host) {
--		/* Debugfs stuff is cleaned up by mmc core */
--
--		if (gpio_is_valid(host->detect_pin)) {
--			int pin = host->detect_pin;
--
--			/* Make sure the timer doesn't enable the interrupt */
--			host->detect_pin = -1;
--			smp_wmb();
--
--			free_irq(gpio_to_irq(pin), host->mmc);
--			del_timer_sync(&host->detect_timer);
--			gpio_free(pin);
--		}
--
--		mmc_remove_host(host->mmc);
-+	for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
-+		if (host->slot[i])
-+			atmci_cleanup_slot(host->slot[i], i);
-+	}
- 
--		clk_enable(host->mck);
--		mci_writel(host, IDR, ~0UL);
--		mci_writel(host, CR, MCI_CR_MCIDIS);
--		mci_readl(host, SR);
--		clk_disable(host->mck);
-+	clk_enable(host->mck);
-+	mci_writel(host, IDR, ~0UL);
-+	mci_writel(host, CR, MCI_CR_MCIDIS);
-+	mci_readl(host, SR);
-+	clk_disable(host->mck);
- 
--		if (gpio_is_valid(host->wp_pin))
--			gpio_free(host->wp_pin);
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	if (host->dma.client.slave)
-+		dma_async_client_unregister(&host->dma.client);
-+#endif
- 
--		free_irq(platform_get_irq(pdev, 0), host->mmc);
--		iounmap(host->regs);
-+	free_irq(platform_get_irq(pdev, 0), host);
-+	iounmap(host->regs);
- 
--		clk_put(host->mck);
-+	clk_put(host->mck);
-+	kfree(host);
- 
--		mmc_free_host(host->mmc);
--	}
- 	return 0;
- }
- 
-diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
-index 9e7a236..6033e74 100644
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -178,10 +178,18 @@ static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
- 	if (atmel_pri.Features & 0x02)
- 		extp->EraseSuspend = 2;
- 
--	if (atmel_pri.BottomBoot)
--		extp->TopBottom = 2;
--	else
--		extp->TopBottom = 3;
-+	/* Some chips got it backwards... */
-+	if (cfi->id == AT49BV6416) {
-+		if (atmel_pri.BottomBoot)
-+			extp->TopBottom = 3;
-+		else
-+			extp->TopBottom = 2;
-+	} else {
-+		if (atmel_pri.BottomBoot)
-+			extp->TopBottom = 2;
-+		else
-+			extp->TopBottom = 3;
-+	}
- 
- 	/* burst write mode not supported */
- 	cfi->cfiq->BufWriteTimeoutTyp = 0;
-diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
-index 3387e0d..4af80c0 100644
---- a/drivers/mtd/nand/atmel_nand.c
-+++ b/drivers/mtd/nand/atmel_nand.c
-@@ -500,7 +500,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
- 	platform_set_drvdata(pdev, host);
- 	atmel_nand_enable(host);
- 
--	if (host->board->det_pin) {
-+	if (gpio_is_valid(host->board->det_pin)) {
- 		if (gpio_get_value(host->board->det_pin)) {
- 			printk("No SmartMedia card inserted.\n");
- 			res = ENXIO;
-diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
-index 9a9755c..13f4fb0 100644
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -559,6 +559,22 @@ config RTC_DRV_AT91SAM9_GPBR
- 	  will be used.  The default of zero is normally OK to use, but
- 	  on some systems other software needs to use that register.
- 
-+config RTC_DRV_AVR32_AST
-+	tristate "AVR32 Asynchronous Timer"
-+	depends on AVR32
-+	help
-+	  RTC driver for the AVR32 Asynchronous Timers. The AST is a
-+	  simple and flexible timer that can be used both as a
-+	  high-resolution system timer and an RTC, depending on what
-+	  clock source it is running from.
-+
-+	  If you say yes here, and add one or more platform_device
-+	  called "rtc-ast", those devices will be clocked from a
-+	  32.768 kHz crystal oscillator and used as RTCs.
-+
-+	  This driver can also be built as a module. If so, the module
-+	  will be called rtc-ast.
-+
- config RTC_DRV_BFIN
- 	tristate "Blackfin On-Chip RTC"
- 	depends on BLACKFIN && !BF561
-diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
-index 18622ef..5ad1266 100644
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -20,6 +20,7 @@ rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o
- obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
- obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
- obj-$(CONFIG_RTC_DRV_AT91SAM9)	+= rtc-at91sam9.o
-+obj-$(CONFIG_RTC_DRV_AVR32_AST)	+= rtc-ast.o
- obj-$(CONFIG_RTC_DRV_BFIN)	+= rtc-bfin.o
- obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
- obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
-diff --git a/drivers/rtc/rtc-ast.c b/drivers/rtc/rtc-ast.c
-new file mode 100644
-index 0000000..be7db91
---- /dev/null
-+++ b/drivers/rtc/rtc-ast.c
-@@ -0,0 +1,546 @@
-+/*
-+ * An RTC driver for the AVR32 Asynchronous Timer
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/rtc.h>
-+
-+#include <asm/ast_regs.h>
-+
-+/*
-+ * The AST - ASynchronous Timer - is built around a simple cycle
-+ * counter that can be driven from one of four selectable clocks with
-+ * a selectable power-of-two prescaler. It also has two alarms (ALARM0
-+ * and ALARM1) and two periodic event generators (PER0 and PER1). The
-+ * latter can be driven by different tappings of the same prescaler
-+ * that drives the counter.
-+ *
-+ * This driver uses the 32.768 kHz crystal oscillator as a clock
-+ * source and a prescaler that gives a 1 Hz counter frequency. It uses
-+ * ALARM0 to support both "old-school" and "wake" alarms, PER0 to
-+ * support periodic interrupts (PIE) up to 16.384 kHz (at power-of-two
-+ * intervals), and PER1 to support a 1 Hz update interrupt (UIE).
-+ *
-+ * Watchdog interrupts seem to be undocumented and unsupported by
-+ * everyone else, so those are not supported for now.
-+ *
-+ * The AST can wake the system from any sleep mode given that the
-+ * source clock is running. On AT32AP720x, the 32.768 kHz crystal
-+ * oscillator runs in all sleep modes except "static" and "shutdown".
-+ */
-+
-+/* 32768 Hz means up to 60 us for synchronization + a bit of slack */
-+#define AST_SYNC_TIMEOUT_US	100
-+
-+#define AST_CLK_RATE		32768
-+#define AST_1S_PRESCALER	14	/* log2(32768) - 1 */
-+
-+struct rtc_ast {
-+	/* Protects I/O registers */
-+	spinlock_t		lock;
-+
-+	struct rtc_device	*rtc;
-+	void __iomem		*regs;
-+	struct clk		*osc32;
-+	struct clk		*pclk;
-+};
-+
-+/*
-+ * Because the AST is, well, asynchronous, we must make sure we don't
-+ * write to certain registers while the previous write is being
-+ * synchronized between clock domains. This affects writes to CR, CV,
-+ * SCR, WER, PIRx and ARx. To keep the delays minimal, we always
-+ * synchronize _before_ writes to these registers.
-+ *
-+ * This function is also used to synchronize when changing the clock
-+ * source, using a different bit in the status register.
-+ */
-+static int ast_wait_ready(void __iomem *regs, unsigned int busy_mask)
-+{
-+	unsigned long	timeout = AST_SYNC_TIMEOUT_US;
-+
-+	while (ast_readl(regs, SR) & busy_mask) {
-+		udelay(1);
-+		if (--timeout == 0)
-+			return -ETIMEDOUT;
-+		cpu_relax();
-+	}
-+
-+	return 0;
-+}
-+
-+static void rtc_ast_release(struct device *dev)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	/* Disable all interrupts */
-+	clk_enable(ast->pclk);
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	clk_disable(ast->pclk);
-+}
-+
-+static int rtc_ast_ioctl(struct device *dev, unsigned int cmd,
-+		unsigned long arg)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret = 0;
-+
-+	clk_enable(ast->pclk);
-+
-+	switch (cmd) {
-+		/* REVISIT: Should perhaps verify that irq_task is NULL */
-+	case RTC_AIE_ON:
-+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
-+		break;
-+	case RTC_AIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(ALARM0));
-+		break;
-+	case RTC_UIE_ON:
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (!ret) {
-+			ast_writel(ast->regs, SCR, AST_BIT(PER1));
-+			ast_writel(ast->regs, IER, AST_BIT(PER1));
-+		}
-+		spin_unlock_irq(&ast->lock);
-+
-+		break;
-+	case RTC_UIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+		break;
-+#if 0
-+	case RTC_PIE_ON:
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (ret)
-+			break;
-+		ast_writel(ast->regs, SCR, AST_BIT(PER0));
-+		spin_unlock_irq(&ast->lock);
-+
-+		ast_writel(ast->regs, IER, AST_BIT(PER0));
-+		break;
-+	case RTC_PIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+		break;
-+#endif
-+	default:
-+		ret = -ENOIOCTLCMD;
-+		break;
-+	}
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_read_time(struct device *dev, struct rtc_time *tm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	clk_enable(ast->pclk);
-+	rtc_time_to_tm(ast_readl(ast->regs, CV), tm);
-+	clk_disable(ast->pclk);
-+
-+	return 0;
-+}
-+
-+static int rtc_ast_set_mmss(struct device *dev, unsigned long secs)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret;
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (!ret)
-+		ast_writel(ast->regs, CV, secs);
-+	spin_unlock_irq(&ast->lock);
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_set_time(struct device *dev, struct rtc_time *tm)
-+{
-+	unsigned long	secs;
-+	int		ret;
-+
-+	ret = rtc_tm_to_time(tm, &secs);
-+	if (!ret)
-+		ret = rtc_ast_set_mmss(dev, secs);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	rtc_time_to_tm(ast_readl(ast->regs, AR0), &alrm->time);
-+	alrm->enabled = !!(ast_readl(ast->regs, IMR) & AST_BIT(ALARM0));
-+	alrm->pending = !!(ast_readl(ast->regs, SR) & AST_BIT(ALARM0));
-+	spin_unlock_irq(&ast->lock);
-+
-+	clk_disable(ast->pclk);
-+
-+	return 0;
-+}
-+
-+static int rtc_ast_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	unsigned long	seconds;
-+	int		ret;
-+
-+	ret = rtc_tm_to_time(&alrm->time, &seconds);
-+	if (ret)
-+		return ret;
-+
-+	clk_enable(ast->pclk);
-+
-+	/*
-+	 * REVISIT: The alarm may trigger before we are done here.
-+	 * Who's responsible for handling that?
-+	 *
-+	 * We don't want to clear the ALARM0 flag before we update AR0
-+	 * because the previous value of AR0 might trigger an alarm
-+	 * right after we clear the flag.
-+	 */
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (ret)
-+		goto unlock;
-+	ast_writel(ast->regs, AR0, seconds);
-+
-+	/* Try to avoid synchronization penalty */
-+	if (ast_readl(ast->regs, SR) & AST_BIT(ALARM0)) {
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (ret)
-+			goto unlock;
-+		ast_writel(ast->regs, SCR, AST_BIT(ALARM0));
-+	}
-+
-+	if (alrm->enabled)
-+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
-+
-+unlock:
-+	spin_unlock_irq(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_proc(struct device *dev, struct seq_file *seq)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	u32		imr;
-+
-+	clk_enable(ast->pclk);
-+	imr = ast_readl(ast->regs, IMR);
-+	clk_disable(ast->pclk);
-+
-+	return seq_printf(seq,
-+			"periodic_IRQ\t: %s\n"
-+			"update_IRQ\t: %s\n"
-+			"periodic_freq\t: %d\n",
-+			(imr & AST_BIT(PER0)) ? "yes" : "no",
-+			(imr & AST_BIT(PER1)) ? "yes" : "no",
-+			ast->rtc->irq_freq);
-+}
-+
-+static int rtc_ast_irq_set_freq(struct device *dev, int freq)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	unsigned int	pres_bit;
-+	int		ret;
-+
-+	/* RTC core currently ensures this. */
-+	BUG_ON(!freq);
-+
-+	pres_bit = __ffs(freq);
-+	if (pres_bit > AST_1S_PRESCALER)
-+		return -EINVAL;
-+	pres_bit = AST_1S_PRESCALER - pres_bit;
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (ret)
-+		goto unlock;
-+
-+	ast_writel(ast->regs, PIR0, pres_bit);
-+
-+unlock:
-+	spin_unlock_irq(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_irq_set_state(struct device *dev, int enabled)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret = 0;
-+
-+	clk_enable(ast->pclk);
-+
-+	if (enabled) {
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (!ret) {
-+			ast_writel(ast->regs, SCR, AST_BIT(PER0));
-+			ast_writel(ast->regs, IER, AST_BIT(PER0));
-+		}
-+		spin_unlock_irq(&ast->lock);
-+	} else {
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+	}
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static const struct rtc_class_ops rtc_ast_ops = {
-+	.release	= rtc_ast_release,
-+	.ioctl		= rtc_ast_ioctl,
-+	.read_time	= rtc_ast_read_time,
-+	.set_time	= rtc_ast_set_time,
-+	.read_alarm	= rtc_ast_read_alarm,
-+	.set_alarm	= rtc_ast_set_alarm,
-+	.proc		= rtc_ast_proc,
-+	.set_mmss	= rtc_ast_set_mmss,
-+	.irq_set_freq	= rtc_ast_irq_set_freq,
-+	.irq_set_state	= rtc_ast_irq_set_state,
-+};
-+
-+static irqreturn_t rtc_ast_interrupt(int irq, void *dev_id)
-+{
-+	struct rtc_ast	*ast = dev_id;
-+	unsigned long	events;
-+	unsigned long	num;
-+	u32		status;
-+	u32		pending;
-+	irqreturn_t	ret = IRQ_NONE;
-+
-+	clk_enable(ast->pclk);
-+	spin_lock(&ast->lock);
-+
-+	status = ast_readl(ast->regs, SR);
-+	pending = status & ast_readl(ast->regs, IMR);
-+	if (unlikely(!pending))
-+		goto out;
-+
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, SCR, pending);
-+
-+	events = RTC_IRQF;
-+	num = 0;
-+	if (pending & AST_BIT(ALARM0)) {
-+		num++;
-+		events |= RTC_AF;
-+	}
-+	if (pending & AST_BIT(PER0)) {
-+		num++;
-+		events |= RTC_PF;
-+	}
-+	if (pending & AST_BIT(PER1)) {
-+		num++;
-+		events |= RTC_UF;
-+	}
-+
-+	rtc_update_irq(ast->rtc, num, events);
-+	ret = IRQ_HANDLED;
-+
-+out:
-+	spin_unlock(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __init rtc_ast_probe(struct platform_device *pdev)
-+{
-+	struct resource	*regs;
-+	struct rtc_ast	*ast;
-+	int		irq;
-+	int		ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "no mmio resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no irq\n");
-+		return -ENXIO;
-+	}
-+
-+	ast = kzalloc(sizeof(struct rtc_ast), GFP_KERNEL);
-+	if (!ast) {
-+		dev_dbg(&pdev->dev, "out of memory\n");
-+		return -ENOMEM;
-+	}
-+
-+	ast->osc32 = clk_get(NULL, "osc32k");
-+	if (IS_ERR(ast->osc32)) {
-+		ret = PTR_ERR(ast->osc32);
-+		dev_dbg(&pdev->dev, "no 32 kHz oscillator\n");
-+		goto err_osc32;
-+	}
-+
-+	ast->pclk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(ast->pclk)) {
-+		ret = PTR_ERR(ast->pclk);
-+		dev_dbg(&pdev->dev, "no peripheral clock\n");
-+		goto err_pclk;
-+	}
-+
-+	spin_lock_init(&ast->lock);
-+
-+	ast->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+	if (!ast->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		ret = -ENOMEM;
-+		goto err_ioremap;
-+	}
-+
-+	clk_enable(ast->osc32);
-+	clk_enable(ast->pclk);
-+
-+	/* Initialize the AST if it isn't running already */
-+	if (!(ast_readl(ast->regs, CR) & AST_BIT(CR_EN))) {
-+		ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
-+		ast_writel(ast->regs, CLOCK,
-+				AST_BF(CLOCK_CSSEL, AST_CLOCK_OSC32)
-+				| AST_BIT(CLOCK_CEN));
-+		ret = ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
-+		if (ret) {
-+			dev_dbg(&pdev->dev,
-+				"timed out selecting clock source\n");
-+			goto err_clksel;
-+		}
-+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		ast_writel(ast->regs, CV, 0);
-+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		ast_writel(ast->regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR)
-+				| AST_BF(CR_PSEL, AST_1S_PRESCALER));
-+	}
-+
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, WER, 0);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, PIR0, AST_1S_PRESCALER);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, PIR1, AST_1S_PRESCALER);
-+
-+	ret = request_irq(irq, rtc_ast_interrupt, 0, "rtc-ast", ast);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
-+		goto err_request_irq;
-+	}
-+
-+	ast->rtc = rtc_device_register("rtc-ast", &pdev->dev,
-+			&rtc_ast_ops, THIS_MODULE);
-+	if (IS_ERR(ast->rtc)) {
-+		dev_dbg(&pdev->dev, "could not register rtc device\n");
-+		ret = PTR_ERR(ast->rtc);
-+		goto err_register;
-+	}
-+
-+	ast->rtc->max_user_freq = AST_CLK_RATE / 2;
-+	ast->rtc->irq_freq = 1;
-+
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	clk_disable(ast->pclk);
-+	platform_set_drvdata(pdev, ast);
-+	device_init_wakeup(&pdev->dev, 1);
-+
-+	dev_info(&pdev->dev, "AVR32 Asynchronous Timer at %08lx irq %d\n",
-+			(unsigned long)regs->start, irq);
-+
-+	return 0;
-+
-+err_register:
-+	free_irq(irq, ast);
-+err_request_irq:
-+err_clksel:
-+	clk_disable(ast->pclk);
-+	clk_disable(ast->osc32);
-+	iounmap(ast->regs);
-+err_ioremap:
-+	clk_put(ast->pclk);
-+err_pclk:
-+	clk_put(ast->osc32);
-+err_osc32:
-+	kfree(ast);
-+	return ret;
-+}
-+
-+static int __exit rtc_ast_remove(struct platform_device *pdev)
-+{
-+	struct rtc_ast *ast = platform_get_drvdata(pdev);
-+
-+	device_init_wakeup(&pdev->dev, 0);
-+
-+	clk_enable(ast->pclk);
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	ast_readl(ast->regs, IMR);
-+	clk_disable(ast->pclk);
-+
-+	free_irq(platform_get_irq(pdev, 0), ast);
-+	rtc_device_unregister(ast->rtc);
-+	clk_disable(ast->osc32);
-+	iounmap(ast->regs);
-+	clk_put(ast->pclk);
-+	clk_put(ast->osc32);
-+	kfree(ast);
-+
-+	platform_set_drvdata(pdev, NULL);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver rtc_ast_driver = {
-+	.remove		= __exit_p(rtc_ast_remove),
-+	.driver		= {
-+		.name	= "rtc-ast",
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+static int __init rtc_ast_init(void)
-+{
-+	return platform_driver_probe(&rtc_ast_driver, rtc_ast_probe);
-+}
-+module_init(rtc_ast_init);
-+
-+static void __exit rtc_ast_exit(void)
-+{
-+	platform_driver_unregister(&rtc_ast_driver);
-+}
-+module_exit(rtc_ast_exit);
-+
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
-+MODULE_DESCRIPTION("AVR32 Asynchronous Timer RTC");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index b9d0efb..ebfb883 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -53,9 +53,14 @@ if SPI_MASTER
- 
- comment "SPI Master Controller Drivers"
- 
-+config SPI_ATMEL_HAVE_PDC
-+	def_bool y
-+	depends on (ARCH_AT91 || CPU_AT32AP700X)
-+
- config SPI_ATMEL
- 	tristate "Atmel SPI Controller"
- 	depends on (ARCH_AT91 || AVR32)
-+	depends on SPI_ATMEL_HAVE_PDC || DMA_ENGINE
- 	help
- 	  This selects a driver for the Atmel SPI Controller, present on
- 	  many AT32 (AVR32) and AT91 (ARM) chips.
-diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
-index 02f9320..5afae71 100644
---- a/drivers/spi/atmel_spi.c
-+++ b/drivers/spi/atmel_spi.c
-@@ -1,306 +1,445 @@
- /*
-  * Driver for Atmel AT32 and AT91 SPI Controllers
-  *
-- * Copyright (C) 2006 Atmel Corporation
-+ * Copyright (C) 2006-2008 Atmel Corporation
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License version 2 as
-  * published by the Free Software Foundation.
-  */
- 
--#include <linux/kernel.h>
--#include <linux/init.h>
- #include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/platform_device.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
- #include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/init.h>
- #include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/wait.h>
-+#include <linux/workqueue.h>
-+#include <linux/spi/atmel_spi.h>
- #include <linux/spi/spi.h>
- 
--#include <asm/io.h>
--#include <mach/board.h>
--#include <mach/gpio.h>
- #include <mach/cpu.h>
- 
- #include "atmel_spi.h"
- 
--/*
-- * The core SPI transfer engine just talks to a register bank to set up
-- * DMA transfers; transfer queue progress is driven by IRQs.  The clock
-- * framework provides the base clock, subdivided for each spi_device.
-- *
-- * Newer controllers, marked with "new_1" flag, have:
-- *  - CR.LASTXFER
-- *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
-- *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
-- *  - SPI_CSRx.CSAAT
-- *  - SPI_CSRx.SBCR allows faster clocking
-+#define BUFFER_SIZE		PAGE_SIZE
-+#define INVALID_DMA_ADDRESS	0xffffffff
-+#define MAX_SG_SEGS		8
-+
-+/**
-+ * struct atmel_spi - SPI master controller state
-+ * @lock: Spinlock protecting the @queue, @stay and @stopping fields
-+ *	as well as the hardware registers.
-+ * @regs: Base address of the hardware registers.
-+ * @wait: Waitqueue used to wait for DMA completion or errors.
-+ * @pending: Number of DMA transfers currently pending.
-+ * @pending_bytes: Number of bytes submitted for DMA but not yet
-+ *	accounted for.
-+ * @error: Data transfer error detected by interrupt handler. When this
-+ *	is set to a nonzero value, the DMA engine is stopped, @pending
-+ *	is set to 0 and @wait is triggered.
-+ * @buffer: Scratch buffer for use when the upper layers didn't provide
-+ *	a TX or RX buffer.
-+ * @buffer_dma: DMA address of @buffer.
-+ * @buffer_size: Length of @buffer in bytes.
-+ * @queue: SPI messages queued for transfer.
-+ * @workqueue: Per-controller workqueue.
-+ * @work: Queue processing work struct.
-+ * @stay: If the last SPI message caused the SPI device to stay active,
-+ *	this points to the SPI device associated with that message. NULL
-+ *	otherwise.
-+ * @clk: Bus clock connected to the controller.
-+ * @base_hz: Base clock rate in Hz used for baud rate calculations.
-+ * @stopping: Queue is being stopped. No new messages are started.
-+ * @always_bounce: Always do transfers to/from bounce buffer.
-+ * @pdev: Platform device associated with the controller.
-  */
- struct atmel_spi {
- 	spinlock_t		lock;
--
- 	void __iomem		*regs;
--	int			irq;
--	struct clk		*clk;
--	struct platform_device	*pdev;
--	unsigned		new_1:1;
--	struct spi_device	*stay;
- 
--	u8			stopping;
--	struct list_head	queue;
--	struct spi_transfer	*current_transfer;
--	unsigned long		current_remaining_bytes;
--	struct spi_transfer	*next_transfer;
--	unsigned long		next_remaining_bytes;
-+	wait_queue_head_t	wait;
-+	int			pending;
-+	size_t			pending_bytes;
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	struct scatterlist	tx_sg[MAX_SG_SEGS];
-+	struct scatterlist	rx_sg[MAX_SG_SEGS];
-+	unsigned int		sg_len;
-+	struct dma_async_tx_descriptor *tx_desc;
-+	struct dma_async_tx_descriptor *rx_desc;
-+	struct dma_chan		*tx_chan;
-+	struct dma_chan		*rx_chan;
-+	struct dma_client	rx_client;
-+	struct dma_client	tx_client;
-+#endif
-+	int			error;
- 
- 	void			*buffer;
- 	dma_addr_t		buffer_dma;
-+	size_t			buffer_size;
-+
-+	struct list_head	queue;
-+	struct workqueue_struct	*workqueue;
-+	struct work_struct	work;
-+	struct spi_device	*stay;
-+	struct clk		*clk;
-+	unsigned long		base_hz;
-+	bool			stopping;
-+	bool			always_bounce;
-+
-+	struct platform_device	*pdev;
-+#ifdef CONFIG_DEBUG_FS
-+	struct dentry		*debugfs_root;
-+#endif
- };
- 
--#define BUFFER_SIZE		PAGE_SIZE
--#define INVALID_DMA_ADDRESS	0xffffffff
-+/**
-+ * struct atmel_spi_device - Controller-specific per-slave state
-+ * @npcs_pin: GPIO pin ID hooked up to this SPI slave.
-+ * @csr: CSRn register value used when talking to this SPI slave.
-+ */
-+struct atmel_spi_device {
-+	unsigned int		npcs_pin;
-+	u32			csr;
-+};
- 
- /*
-- * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
-- * they assume that spi slave device state will not change on deselect, so
-- * that automagic deselection is OK.  ("NPCSx rises if no data is to be
-- * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
-- * controllers have CSAAT and friends.
-- *
-- * Since the CSAAT functionality is a bit weird on newer controllers as
-- * well, we use GPIO to control nCSx pins on all controllers, updating
-- * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
-- * support active-high chipselects despite the controller's belief that
-- * only active-low devices/systems exists.
-+ * Version 2 of the SPI controller has
-+ *  - CR.LASTXFER
-+ *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
-+ *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
-+ *  - SPI_CSRx.CSAAT
-+ *  - SPI_CSRx.SBCR allows faster clocking
-  *
-- * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
-- * right when driven with GPIO.  ("Mode Fault does not allow more than one
-- * Master on Chip Select 0.")  No workaround exists for that ... so for
-- * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
-- * and (c) will trigger that first erratum in some cases.
-+ * We can determine the controller version by reading the VERSION
-+ * register, but I haven't checked that it exists on all chips, and
-+ * this is cheaper anyway.
-  */
--
--static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
-+static bool atmel_spi_is_v2(void)
- {
--	unsigned gpio = (unsigned) spi->controller_data;
--	unsigned active = spi->mode & SPI_CS_HIGH;
--	u32 mr;
--	int i;
--	u32 csr;
--	u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-+	return !cpu_is_at91rm9200();
-+}
- 
--	/* Make sure clock polarity is correct */
--	for (i = 0; i < spi->master->num_chipselect; i++) {
--		csr = spi_readl(as, CSR0 + 4 * i);
--		if ((csr ^ cpol) & SPI_BIT(CPOL))
--			spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
--	}
-+static bool atmel_spi_xfer_is_last(struct spi_message *msg,
-+		struct spi_transfer *xfer)
-+{
-+	return &xfer->transfer_list == msg->transfers.prev;
-+}
- 
--	mr = spi_readl(as, MR);
--	mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
-+/*-------------------------------------------------------------------------*/
- 
--	dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
--			gpio, active ? " (high)" : "",
--			mr);
-+/*
-+ * GCC doesn't eliminate _all_ the dead code, only some of it. In
-+ * particular, the file operations appear to be difficult even if the
-+ * file operations struct itself gets eliminated.
-+ *
-+ * So let's do the CPP dance.
-+ */
-+#ifdef CONFIG_DEBUG_FS
- 
--	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
--		gpio_set_value(gpio, active);
--	spi_writel(as, MR, mr);
--}
-+#include <linux/debugfs.h>
-+#include <linux/seq_file.h>
- 
--static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
-+static int atmel_spi_queue_show(struct seq_file *s, void *v)
- {
--	unsigned gpio = (unsigned) spi->controller_data;
--	unsigned active = spi->mode & SPI_CS_HIGH;
--	u32 mr;
-+	struct atmel_spi	*as = s->private;
-+	struct spi_message	*msg;
-+	struct spi_transfer	*xfer;
- 
--	/* only deactivate *this* device; sometimes transfers to
--	 * another device may be active when this routine is called.
--	 */
--	mr = spi_readl(as, MR);
--	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
--		mr = SPI_BFINS(PCS, 0xf, mr);
--		spi_writel(as, MR, mr);
-+	spin_lock_irq(&as->lock);
-+	list_for_each_entry(msg, &as->queue, queue) {
-+		seq_printf(s, "msg to %s:%s DMA mapped, status %d actual %u\n",
-+				msg->spi->dev.bus_id,
-+				msg->is_dma_mapped ? "" : " Not",
-+				msg->status, msg->actual_length);
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+			seq_printf(s, "  t%p r%p l%u%s %u bits %u us %u Hz\n",
-+					xfer->tx_buf, xfer->rx_buf, xfer->len,
-+					xfer->cs_change ? "cs_change" : "",
-+					xfer->bits_per_word,
-+					xfer->delay_usecs,
-+					xfer->speed_hz);
-+		}
- 	}
-+	spin_unlock_irq(&as->lock);
- 
--	dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
--			gpio, active ? " (low)" : "",
--			mr);
--
--	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
--		gpio_set_value(gpio, !active);
-+	return 0;
- }
- 
--static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
--					struct spi_transfer *xfer)
-+static int atmel_spi_queue_open(struct inode *inode, struct file *file)
- {
--	return msg->transfers.prev == &xfer->transfer_list;
-+	return single_open(file, atmel_spi_queue_show, inode->i_private);
- }
- 
--static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
-+static const struct file_operations atmel_spi_queue_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= atmel_spi_queue_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
-+
-+static void atmel_spi_show_status_reg(struct seq_file *s,
-+		const char *regname, u32 value)
- {
--	return xfer->delay_usecs == 0 && !xfer->cs_change;
-+	static const char	*sr_bit[] = {
-+		[0]	= "RDRF",
-+		[1]	= "TDRE",
-+		[2]	= "MODF",
-+		[3]	= "OVRES",
-+		[4]	= "ENDRX",
-+		[5]	= "ENDTX",
-+		[6]	= "RXBUFF",
-+		[7]	= "TXBUFE",
-+		[8]	= "NSSR",
-+		[9]	= "TXEMPTY",
-+		[16]	= "SPIENS",
-+	};
-+	unsigned int		i;
-+
-+	seq_printf(s, "%s:\t0x%08x", regname, value);
-+	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
-+		if (value & (1 << i)) {
-+			if (sr_bit[i])
-+				seq_printf(s, " %s", sr_bit[i]);
-+			else
-+				seq_printf(s, " UNKNOWN(%u)", i);
-+		}
-+	}
-+	seq_putc(s, '\n');
- }
- 
--static void atmel_spi_next_xfer_data(struct spi_master *master,
--				struct spi_transfer *xfer,
--				dma_addr_t *tx_dma,
--				dma_addr_t *rx_dma,
--				u32 *plen)
-+static int atmel_spi_regs_show(struct seq_file *s, void *v)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	u32			len = *plen;
-+	struct atmel_spi	*as = s->private;
-+	unsigned int		i;
-+	u32			value;
-+	u32			*buf;
- 
--	/* use scratch buffer only when rx or tx data is unspecified */
--	if (xfer->rx_buf)
--		*rx_dma = xfer->rx_dma + xfer->len - len;
--	else {
--		*rx_dma = as->buffer_dma;
--		if (len > BUFFER_SIZE)
--			len = BUFFER_SIZE;
--	}
--	if (xfer->tx_buf)
--		*tx_dma = xfer->tx_dma + xfer->len - len;
--	else {
--		*tx_dma = as->buffer_dma;
--		if (len > BUFFER_SIZE)
--			len = BUFFER_SIZE;
--		memset(as->buffer, 0, len);
--		dma_sync_single_for_device(&as->pdev->dev,
--				as->buffer_dma, len, DMA_TO_DEVICE);
--	}
-+	buf = kmalloc(0x200, GFP_KERNEL);
-+	if (!buf)
-+		return -ENOMEM;
- 
--	*plen = len;
--}
-+	/* Grab a more or less consistent snapshot */
-+	spin_lock_irq(&as->lock);
-+	memcpy_fromio(buf, as->regs, 0x200);
-+	spin_unlock_irq(&as->lock);
- 
--/*
-- * Submit next transfer for DMA.
-- * lock is held, spi irq is blocked
-- */
--static void atmel_spi_next_xfer(struct spi_master *master,
--				struct spi_message *msg)
--{
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_transfer	*xfer;
--	u32			len, remaining;
--	u32			ieval;
--	dma_addr_t		tx_dma, rx_dma;
--
--	if (!as->current_transfer)
--		xfer = list_entry(msg->transfers.next,
--				struct spi_transfer, transfer_list);
--	else if (!as->next_transfer)
--		xfer = list_entry(as->current_transfer->transfer_list.next,
--				struct spi_transfer, transfer_list);
--	else
--		xfer = NULL;
-+	value = buf[SPI_MR / 4];
-+	seq_printf(s, "MR:\t0x%08x%s%s%s%s%s%s PCS=%x DLYBCS=%u\n",
-+			value,
-+			(value & SPI_BIT(MSTR)) ? " MSTR" : "",
-+			(value & SPI_BIT(PS)) ? " PS" : "",
-+			(value & SPI_BIT(PCSDEC)) ? " PCSDEC" : "",
-+			(value & SPI_BIT(FDIV)) ? " FDIV" : "",
-+			(value & SPI_BIT(MODFDIS)) ? " MODFDIS" : "",
-+			(value & SPI_BIT(LLB)) ? " LLB" : "",
-+			SPI_BFEXT(PCS, value),
-+			SPI_BFEXT(DLYBCS, value));
-+
-+	atmel_spi_show_status_reg(s, "SR", buf[SPI_SR / 4]);
-+	atmel_spi_show_status_reg(s, "IMR", buf[SPI_IMR / 4]);
-+
-+	for (i = 0; i < 4; i++) {
-+		value = buf[SPI_CSR0 / 4 + i];
-+		seq_printf(s, "CSR%u:\t0x%08x%s%s%s\n",
-+				i, value,
-+				(value & SPI_BIT(CPOL)) ? " CPOL" : "",
-+				(value & SPI_BIT(NCPHA)) ? " NCPHA" : "",
-+				(value & SPI_BIT(CSAAT)) ? " CSAAT" : "");
-+		seq_printf(s, "\t\tBITS=%u SCBR=%u DLYBS=%u DLYBCT=%u\n",
-+				SPI_BFEXT(BITS, value) + 8,
-+				SPI_BFEXT(SCBR, value),
-+				SPI_BFEXT(DLYBS, value),
-+				SPI_BFEXT(DLYBCT, value));
-+	}
- 
--	if (xfer) {
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-+	seq_printf(s, "RPR:\t0x%08x\n", buf[SPI_RPR / 4]);
-+	seq_printf(s, "RCR:\t0x%08x\n", buf[SPI_RCR / 4]);
-+	seq_printf(s, "TPR:\t0x%08x\n", buf[SPI_TPR / 4]);
-+	seq_printf(s, "TCR:\t0x%08x\n", buf[SPI_TCR / 4]);
-+	seq_printf(s, "RNPR:\t0x%08x\n", buf[SPI_RNPR / 4]);
-+	seq_printf(s, "RNCR:\t0x%08x\n", buf[SPI_RNCR / 4]);
-+	seq_printf(s, "TNPR:\t0x%08x\n", buf[SPI_TNPR / 4]);
-+	seq_printf(s, "TNCR:\t0x%08x\n", buf[SPI_TNCR / 4]);
- 
--		len = xfer->len;
--		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
--		remaining = xfer->len - len;
-+	value = buf[SPI_PTSR / 4];
-+	seq_printf(s, "PTSR:\t0x%08x%s%s\n", value,
-+			(value & SPI_BIT(RXTEN)) ? " RXTEN" : "",
-+			(value & SPI_BIT(TXTEN)) ? " TXTEN" : "");
- 
--		spi_writel(as, RPR, rx_dma);
--		spi_writel(as, TPR, tx_dma);
-+	kfree(buf);
- 
--		if (msg->spi->bits_per_word > 8)
--			len >>= 1;
--		spi_writel(as, RCR, len);
--		spi_writel(as, TCR, len);
-+	return 0;
-+}
- 
--		dev_dbg(&msg->spi->dev,
--			"  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--	} else {
--		xfer = as->next_transfer;
--		remaining = as->next_remaining_bytes;
--	}
-+static int atmel_spi_regs_open(struct inode *inode, struct file *file)
-+{
-+	return single_open(file, atmel_spi_regs_show, inode->i_private);
-+}
- 
--	as->current_transfer = xfer;
--	as->current_remaining_bytes = remaining;
-+static const struct file_operations atmel_spi_regs_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= atmel_spi_regs_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
- 
--	if (remaining > 0)
--		len = remaining;
--	else if (!atmel_spi_xfer_is_last(msg, xfer)
--			&& atmel_spi_xfer_can_be_chained(xfer)) {
--		xfer = list_entry(xfer->transfer_list.next,
--				struct spi_transfer, transfer_list);
--		len = xfer->len;
--	} else
--		xfer = NULL;
-+static void atmel_spi_init_debugfs(struct atmel_spi *as)
-+{
-+	struct dentry	*root;
-+	struct dentry	*node;
- 
--	as->next_transfer = xfer;
-+	root = debugfs_create_dir(as->pdev->dev.bus_id, NULL);
-+	if (IS_ERR(root))
-+		/* Debugfs not enabled */
-+		return;
-+	if (!root)
-+		/* Debugfs enabled, but failed to create directory */
-+		goto err_root;
-+
-+	node = debugfs_create_file("regs", S_IRUSR, root, as,
-+			&atmel_spi_regs_fops);
-+	if (!node)
-+		goto err;
-+	node = debugfs_create_file("queue", S_IRUSR, root, as,
-+			&atmel_spi_queue_fops);
-+	if (!node)
-+		goto err;
-+
-+	as->debugfs_root = root;
-+	return;
-+
-+err:
-+	debugfs_remove_recursive(root);
-+err_root:
-+	dev_err(&as->pdev->dev, "failed to initialize debugfs\n");
-+}
- 
--	if (xfer) {
--		u32	total;
-+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
-+{
-+	debugfs_remove_recursive(as->debugfs_root);
-+}
- 
--		total = len;
--		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
--		as->next_remaining_bytes = total - len;
-+#else
-+static void atmel_spi_init_debugfs(struct atmel_spi *as)
-+{
- 
--		spi_writel(as, RNPR, rx_dma);
--		spi_writel(as, TNPR, tx_dma);
-+}
-+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
-+{
- 
--		if (msg->spi->bits_per_word > 8)
--			len >>= 1;
--		spi_writel(as, RNCR, len);
--		spi_writel(as, TNCR, len);
-+}
-+#endif
- 
--		dev_dbg(&msg->spi->dev,
--			"  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--		ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
--	} else {
--		spi_writel(as, RNCR, 0);
--		spi_writel(as, TNCR, 0);
--		ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
--	}
-+/*
-+ * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
-+ * they assume that spi slave device state will not change on deselect, so
-+ * that automagic deselection is OK.  ("NPCSx rises if no data is to be
-+ * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
-+ * controllers have CSAAT and friends.
-+ *
-+ * Since the CSAAT functionality is a bit weird on newer controllers as
-+ * well, we use GPIO to control nCSx pins on all controllers, updating
-+ * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
-+ * support active-high chipselects despite the controller's belief that
-+ * only active-low devices/systems exists.
-+ *
-+ * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
-+ * right when driven with GPIO.  ("Mode Fault does not allow more than one
-+ * Master on Chip Select 0.")  No workaround exists for that ... so for
-+ * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
-+ * and (c) will trigger that first erratum in some cases.
-+ *
-+ * TODO: Test if the atmel_spi_is_v2() branch below works on
-+ * AT91RM9200 if we use some other register than CSR0. However, don't
-+ * do this unconditionally since AP7000 has an errata where the BITS
-+ * field in CSR0 overrides all other CSRs.
-+ */
- 
--	/* REVISIT: We're waiting for ENDRX before we start the next
--	 * transfer because we need to handle some difficult timing
--	 * issues otherwise. If we wait for ENDTX in one transfer and
--	 * then starts waiting for ENDRX in the next, it's difficult
--	 * to tell the difference between the ENDRX interrupt we're
--	 * actually waiting for and the ENDRX interrupt of the
--	 * previous transfer.
--	 *
--	 * It should be doable, though. Just not now...
--	 */
--	spi_writel(as, IER, ieval);
--	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
-+static void atmel_spi_set_csr(struct atmel_spi *as,
-+		struct spi_device *spi, u32 csr)
-+{
-+	if (atmel_spi_is_v2())
-+		spi_writel(as, CSR0, csr);
-+	else
-+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
- }
- 
--static void atmel_spi_next_message(struct spi_master *master)
-+static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
--	struct spi_device	*spi;
-+	struct atmel_spi_device *asd = spi->controller_state;
-+	unsigned active = spi->mode & SPI_CS_HIGH;
-+
-+	if (atmel_spi_is_v2()) {
-+		/*
-+		 * Always use CSR0. This ensures that the clock
-+		 * switches to the correct idle polarity before we
-+		 * toggle the CS.
-+		 */
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
-+				| SPI_BIT(MSTR));
-+		spi_readl(as, MR);
-+		dev_vdbg(&spi->dev, "activate %u%s, csr0: %08x\n",
-+				asd->npcs_pin, active ? " (low)" : "",
-+				asd->csr);
-+
-+		gpio_set_value(asd->npcs_pin, active);
-+	} else {
-+		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-+		int i;
-+		u32 mr;
-+		u32 csr;
-+
-+		/* Make sure clock polarity is correct */
-+		for (i = 0; i < spi->master->num_chipselect; i++) {
-+			csr = spi_readl(as, CSR0 + 4 * i);
-+			if ((csr ^ cpol) & SPI_BIT(CPOL))
-+				spi_writel(as, CSR0 + 4 * i,
-+						csr ^ SPI_BIT(CPOL));
-+		}
- 
--	BUG_ON(as->current_transfer);
-+		mr = spi_readl(as, MR);
-+		mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
-+		dev_vdbg(&spi->dev, "activate %u%s, mr: %08x csr: %08x\n",
-+				asd->npcs_pin, active ? " (low)" : "",
-+				mr, csr);
-+		if (spi->chip_select != 0)
-+			gpio_set_value(asd->npcs_pin, active);
-+		spi_writel(as, MR, mr);
-+	}
-+}
- 
--	msg = list_entry(as->queue.next, struct spi_message, queue);
--	spi = msg->spi;
-+static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
-+{
-+	struct atmel_spi_device *asd = spi->controller_state;
-+	unsigned active = spi->mode & SPI_CS_HIGH;
-+	u32 mr;
- 
--	dev_dbg(master->dev.parent, "start message %p for %s\n",
--			msg, spi->dev.bus_id);
-+	/* only deactivate *this* device; sometimes transfers to
-+	 * another device may be active when this routine is called.
-+	 */
-+	mr = spi_readl(as, MR);
-+	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
-+		mr = SPI_BFINS(PCS, 0xf, mr);
-+		spi_writel(as, MR, mr);
-+	}
- 
--	/* select chip if it's not still active */
--	if (as->stay) {
--		if (as->stay != spi) {
--			cs_deactivate(as, as->stay);
--			cs_activate(as, spi);
--		}
--		as->stay = NULL;
--	} else
--		cs_activate(as, spi);
-+	dev_vdbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
-+			asd->npcs_pin, active ? " (low)" : "",
-+			mr);
- 
--	atmel_spi_next_xfer(master, msg);
-+	if (atmel_spi_is_v2() || spi->chip_select != 0)
-+		gpio_set_value(asd->npcs_pin, !active);
- }
- 
- /*
-@@ -338,162 +477,460 @@ atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
- 	return 0;
- }
- 
--static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
-+static void atmel_spi_dma_unmap_xfer(struct atmel_spi *as,
- 				     struct spi_transfer *xfer)
- {
- 	if (xfer->tx_dma != INVALID_DMA_ADDRESS)
--		dma_unmap_single(master->dev.parent, xfer->tx_dma,
-+		dma_unmap_single(&as->pdev->dev, xfer->tx_dma,
- 				 xfer->len, DMA_TO_DEVICE);
- 	if (xfer->rx_dma != INVALID_DMA_ADDRESS)
--		dma_unmap_single(master->dev.parent, xfer->rx_dma,
-+		dma_unmap_single(&as->pdev->dev, xfer->rx_dma,
- 				 xfer->len, DMA_FROM_DEVICE);
- }
- 
--static void
--atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
--		struct spi_message *msg, int status, int stay)
-+static void atmel_spi_dma_unmap_msg(struct atmel_spi *as, struct spi_message *msg)
- {
--	if (!stay || status < 0)
--		cs_deactivate(as, msg->spi);
--	else
--		as->stay = msg->spi;
--
--	list_del(&msg->queue);
--	msg->status = status;
--
--	dev_dbg(master->dev.parent,
--		"xfer complete: %u bytes transferred\n",
--		msg->actual_length);
-+	struct spi_transfer	*xfer;
- 
--	spin_unlock(&as->lock);
--	msg->complete(msg->context);
--	spin_lock(&as->lock);
-+	if (!msg->is_dma_mapped)
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list)
-+			atmel_spi_dma_unmap_xfer(as, xfer);
-+}
- 
--	as->current_transfer = NULL;
--	as->next_transfer = NULL;
-+static void atmel_spi_handle_error(struct atmel_spi *as,
-+		struct spi_message *msg, int err)
-+{
-+	unsigned int timeout;
-+
-+	/* Drain the buffers so that the hardware is ready for a new message */
-+	for (timeout = 1000; timeout; timeout--)
-+		if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
-+			break;
-+	if (!timeout)
-+		dev_warn(&msg->spi->dev,
-+			 "timeout waiting for TXEMPTY");
-+	while (spi_readl(as, SR) & SPI_BIT(RDRF))
-+		spi_readl(as, RDR);
-+
-+	/* Clear any overrun happening while cleaning up */
-+	spi_readl(as, SR);
- 
--	/* continue if needed */
--	if (list_empty(&as->queue) || as->stopping)
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
--	else
--		atmel_spi_next_message(master);
-+	msg->status = err;
-+	as->error = 0;
- }
- 
--static irqreturn_t
--atmel_spi_interrupt(int irq, void *dev_id)
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
- {
--	struct spi_master	*master = dev_id;
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
--	struct spi_transfer	*xfer;
--	u32			status, pending, imr;
--	int			ret = IRQ_NONE;
-+	int err;
- 
--	spin_lock(&as->lock);
-+	wait_event(as->wait, as->pending == 0);
-+	err = as->error;
-+	if (err) {
-+		dev_warn(&msg->spi->dev,
-+				"transfer error %d (%u/%u remaining)\n",
-+				err, spi_readl(as, TCR), spi_readl(as, RCR));
-+
-+		spi_writel(as, TNCR, 0);
-+		spi_writel(as, RNCR, 0);
-+		spi_writel(as, TCR, 0);
-+		spi_writel(as, RCR, 0);
- 
--	xfer = as->current_transfer;
--	msg = list_entry(as->queue.next, struct spi_message, queue);
-+		atmel_spi_handle_error(as, msg, err);
- 
--	imr = spi_readl(as, IMR);
--	status = spi_readl(as, SR);
--	pending = status & imr;
-+		return err;
-+	}
- 
--	if (pending & SPI_BIT(OVRES)) {
--		int timeout;
-+	msg->actual_length += as->pending_bytes;
-+	as->pending_bytes = 0;
-+
-+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
-+			msg->actual_length);
-+
-+	return 0;
-+}
-+
-+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
-+		struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+	unsigned int	bits = xfer->bits_per_word;
-+	unsigned int	speed_hz = xfer->speed_hz;
-+	unsigned int	submitted = 0;
-+	dma_addr_t	rx_dma;
-+	dma_addr_t	tx_dma;
-+
-+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
-+			xfer->len, xfer->rx_buf, xfer->tx_buf);
-+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
-+			xfer->cs_change, xfer->bits_per_word,
-+			xfer->delay_usecs, xfer->speed_hz);
-+
-+	if (bits || speed_hz) {
-+		struct atmel_spi_device *asd;
-+		u32 csr;
-+
-+		if (atmel_spi_wait_idle(as, msg))
-+			return 0;
-+
-+		asd = spi->controller_state;
-+		csr = asd->csr;
-+
-+		if (bits)
-+			csr = SPI_BFINS(BITS, csr, bits - 8);
-+		if (speed_hz) {
-+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
-+			csr = SPI_BFINS(SCBR, csr, scbr);
-+		}
-+
-+		atmel_spi_set_csr(as, spi, csr);
-+	}
- 
--		ret = IRQ_HANDLED;
-+	if (!bits)
-+		bits = spi->bits_per_word;
- 
--		spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
--				     | SPI_BIT(OVRES)));
-+	/* PDC stuff starts here */
-+	while (submitted < xfer->len) {
-+		unsigned long len;
-+
-+		wait_event(as->wait, as->pending < 2);
- 
- 		/*
--		 * When we get an overrun, we disregard the current
--		 * transfer. Data will not be copied back from any
--		 * bounce buffer and msg->actual_len will not be
--		 * updated with the last xfer.
--		 *
--		 * We will also not process any remaning transfers in
--		 * the message.
--		 *
--		 * First, stop the transfer and unmap the DMA buffers.
-+		 * This gives the RX side a slight advantage, making
-+		 * overruns less likely.
- 		 */
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
--		if (!msg->is_dma_mapped)
--			atmel_spi_dma_unmap_xfer(master, xfer);
-+		spi_writel(as, PTCR, SPI_BIT(TXTDIS));
-+
-+		len = xfer->len - submitted;
-+		if (xfer->rx_buf) {
-+			rx_dma = xfer->rx_dma + submitted;
-+		} else {
-+			rx_dma = as->buffer_dma;
-+			len = min(len, BUFFER_SIZE);
-+		}
-+		if (xfer->tx_buf) {
-+			tx_dma = xfer->tx_dma + submitted;
-+		} else {
-+			tx_dma = as->buffer_dma;
-+			len = min(len, BUFFER_SIZE);
-+			memset(as->buffer, 0, len);
-+		}
-+
-+		submitted += len;
-+		if (bits > 8)
-+			len >>= 1;
-+
-+		spin_lock_irq(&as->lock);
-+		if (as->error) {
-+			spin_unlock_irq(&as->lock);
-+			atmel_spi_wait_idle(as, msg);
-+			return 0;
-+		}
-+
-+		spi_writel(as, RNPR, rx_dma);
-+		spi_writel(as, RNCR, len);
-+		spi_writel(as, TNPR, tx_dma);
-+		spi_writel(as, TNCR, len);
-+		spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
-+				| SPI_BIT(OVRES));
-+		spi_writel(as, PTCR, SPI_BIT(RXTEN) | SPI_BIT(TXTEN));
-+		as->pending++;
-+		spin_unlock_irq(&as->lock);
-+	}
-+
-+	as->pending_bytes += submitted;
- 
--		/* REVISIT: udelay in irq is unfriendly */
-+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
-+			|| xfer->speed_hz) {
-+		struct atmel_spi_device	*asd = spi->controller_state;
-+		int			err;
-+
-+		err = atmel_spi_wait_idle(as, msg);
- 		if (xfer->delay_usecs)
- 			udelay(xfer->delay_usecs);
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		if (err)
-+			return 0;
- 
--		dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
--			 spi_readl(as, TCR), spi_readl(as, RCR));
-+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
-+			cs_deactivate(as, spi);
-+			udelay(1);
-+			cs_activate(as, spi);
-+		}
-+	}
- 
--		/*
--		 * Clean up DMA registers and make sure the data
--		 * registers are empty.
--		 */
--		spi_writel(as, RNCR, 0);
--		spi_writel(as, TNCR, 0);
--		spi_writel(as, RCR, 0);
--		spi_writel(as, TCR, 0);
--		for (timeout = 1000; timeout; timeout--)
--			if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
--				break;
--		if (!timeout)
--			dev_warn(master->dev.parent,
--				 "timeout waiting for TXEMPTY");
--		while (spi_readl(as, SR) & SPI_BIT(RDRF))
--			spi_readl(as, RDR);
-+	return xfer->cs_change;
-+}
- 
--		/* Clear any overrun happening while cleaning up */
--		spi_readl(as, SR);
-+#else /* Use DMA engine framework, not PDC */
- 
--		atmel_spi_msg_done(master, as, msg, -EIO, 0);
--	} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
--		ret = IRQ_HANDLED;
-+static void atmel_spi_dma_complete(void *param)
-+{
-+	struct atmel_spi	*as = param;
- 
--		spi_writel(as, IDR, pending);
-+	as->pending = 0;
-+	as->sg_len = 0;
-+	wake_up(&as->wait);
-+}
- 
--		if (as->current_remaining_bytes == 0) {
--			msg->actual_length += xfer->len;
--
--			if (!msg->is_dma_mapped)
--				atmel_spi_dma_unmap_xfer(master, xfer);
--
--			/* REVISIT: udelay in irq is unfriendly */
--			if (xfer->delay_usecs)
--				udelay(xfer->delay_usecs);
--
--			if (atmel_spi_xfer_is_last(msg, xfer)) {
--				/* report completed message */
--				atmel_spi_msg_done(master, as, msg, 0,
--						xfer->cs_change);
--			} else {
--				if (xfer->cs_change) {
--					cs_deactivate(as, msg->spi);
--					udelay(1);
--					cs_activate(as, msg->spi);
--				}
-+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
-+{
-+	struct dma_chan			*tx_chan = as->tx_chan;
-+	struct dma_chan			*rx_chan = as->rx_chan;
-+	struct dma_device		*dma = rx_chan->device;
-+	struct dma_async_tx_descriptor	*tx_desc;
-+	struct dma_async_tx_descriptor	*rx_desc;
-+	int				err;
-+
-+	dev_vdbg(&msg->spi->dev, "wait_idle: sg_len=%u\n", as->sg_len);
-+
-+	if (!as->sg_len)
-+		return 0;
-+
-+	sg_mark_end(as->tx_sg + (as->sg_len - 1));
-+	sg_mark_end(as->rx_sg + (as->sg_len - 1));
-+	as->pending = 1;
-+	smp_wmb();
-+
-+	tx_desc = dma->device_prep_slave_sg(tx_chan,
-+			as->tx_sg, as->sg_len, DMA_TO_DEVICE,
-+			DMA_COMPL_SKIP_SRC_UNMAP | DMA_CTRL_ACK);
-+	rx_desc = dma->device_prep_slave_sg(rx_chan,
-+			as->rx_sg, as->sg_len, DMA_FROM_DEVICE,
-+			DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP
-+			| DMA_CTRL_ACK);
-+	rx_desc->callback = atmel_spi_dma_complete;
-+	rx_desc->callback_param = as;
-+	rx_desc->tx_submit(rx_desc);
-+	tx_desc->tx_submit(tx_desc);
-+	dma->device_issue_pending(rx_chan);
-+	dma->device_issue_pending(tx_chan);
-+
-+	spi_writel(as, IER, SPI_BIT(OVRES));
-+	wait_event(as->wait, !as->pending);
-+	spi_writel(as, IDR, SPI_BIT(OVRES));
-+	err = as->error;
-+	if (err) {
-+		dev_warn(&msg->spi->dev, "transfer error %d\n", err);
-+
-+		dma->device_terminate_all(tx_chan);
-+		dma->device_terminate_all(rx_chan);
-+
-+		atmel_spi_handle_error(as, msg, err);
-+
-+		return err;
-+	}
-+
-+	msg->actual_length += as->pending_bytes;
-+	as->pending_bytes = 0;
-+	sg_init_table(as->rx_sg, MAX_SG_SEGS);
-+	sg_init_table(as->tx_sg, MAX_SG_SEGS);
-+
-+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
-+			msg->actual_length);
-+
-+	return 0;
-+}
-+
-+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
-+		struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+	unsigned int	bits = xfer->bits_per_word;
-+	unsigned int	speed_hz = xfer->speed_hz;
-+	unsigned int	submitted = 0;
-+	unsigned int	i;
-+
-+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
-+			xfer->len, xfer->rx_buf, xfer->tx_buf);
-+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
-+			xfer->cs_change, xfer->bits_per_word,
-+			xfer->delay_usecs, xfer->speed_hz);
-+
-+	if (bits || speed_hz) {
-+		struct atmel_spi_device *asd;
-+		u32 csr;
-+
-+		if (atmel_spi_wait_idle(as, msg))
-+			return 0;
-+
-+		asd = spi->controller_state;
-+		csr = asd->csr;
-+
-+		if (bits)
-+			csr = SPI_BFINS(BITS, csr, bits - 8);
-+		if (speed_hz) {
-+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
-+			csr = SPI_BFINS(SCBR, csr, scbr);
-+		}
-+
-+		atmel_spi_set_csr(as, spi, csr);
-+	}
-+
-+	if (!bits)
-+		bits = spi->bits_per_word;
-+
-+	i = as->sg_len;
-+	while (submitted < xfer->len) {
-+		unsigned long len;
-+
-+		if (i == MAX_SG_SEGS) {
-+			if (atmel_spi_wait_idle(as, msg))
-+				return 0;
-+			i = 0;
-+		}
-+
-+		len = xfer->len - submitted;
-+		if (!xfer->rx_buf || !xfer->tx_buf)
-+			len = min(len, BUFFER_SIZE);
-+
-+		if (xfer->rx_buf) {
-+			sg_set_buf(&as->rx_sg[i], xfer->rx_buf + submitted, len);
-+			as->rx_sg[i].dma_address = xfer->rx_dma + submitted;
-+		} else {
-+			sg_set_buf(&as->rx_sg[i], as->buffer, len);
-+			as->rx_sg[i].dma_address = as->buffer_dma;
-+		}
-+		if (xfer->tx_buf) {
-+			sg_set_buf(&as->tx_sg[i], xfer->tx_buf + submitted, len);
-+			as->tx_sg[i].dma_address = xfer->tx_dma + submitted;
-+		} else {
-+			sg_set_buf(&as->tx_sg[i], as->buffer, len);
-+			as->tx_sg[i].dma_address = as->buffer_dma;
-+			memset(as->buffer, 0, len);
-+		}
- 
--				/*
--				 * Not done yet. Submit the next transfer.
--				 *
--				 * FIXME handle protocol options for xfer
--				 */
--				atmel_spi_next_xfer(master, msg);
-+		submitted += len;
-+		as->sg_len = ++i;
-+	}
-+
-+	as->pending_bytes += submitted;
-+
-+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
-+			|| xfer->speed_hz) {
-+		struct atmel_spi_device	*asd = spi->controller_state;
-+		int			err;
-+
-+		err = atmel_spi_wait_idle(as, msg);
-+		if (xfer->delay_usecs)
-+			udelay(xfer->delay_usecs);
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		if (err)
-+			return 0;
-+
-+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
-+			cs_deactivate(as, spi);
-+			udelay(1);
-+			cs_activate(as, spi);
-+		}
-+	}
-+
-+	return xfer->cs_change;
-+}
-+
-+#endif /* PDC vs. DMA engine */
-+
-+static void atmel_spi_work(struct work_struct *work)
-+{
-+	struct atmel_spi	*as;
-+
-+	as = container_of(work, struct atmel_spi, work);
-+
-+	spin_lock_irq(&as->lock);
-+	while (!list_empty(&as->queue)) {
-+		struct spi_message	*msg;
-+		struct spi_transfer	*xfer;
-+		struct spi_device	*spi;
-+		int			cs_change = 0;
-+
-+		if (as->stopping)
-+			break;
-+
-+		msg = list_entry(as->queue.next, struct spi_message, queue);
-+		spin_unlock_irq(&as->lock);
-+
-+		spi = msg->spi;
-+
-+		if (as->stay) {
-+			if (as->stay != spi) {
-+				cs_deactivate(as, as->stay);
-+				cs_activate(as, spi);
- 			}
-+			as->stay = NULL;
- 		} else {
--			/*
--			 * Keep going, we still have data to send in
--			 * the current transfer.
--			 */
--			atmel_spi_next_xfer(master, msg);
-+			cs_activate(as, spi);
-+		}
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+		sg_init_table(as->rx_sg, MAX_SG_SEGS);
-+		sg_init_table(as->tx_sg, MAX_SG_SEGS);
-+#endif
-+
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+			if (msg->status != -EINPROGRESS)
-+				break;
-+			cs_change = atmel_spi_submit_xfer(as, spi, msg, xfer);
-+		}
-+
-+		if (msg->status == -EINPROGRESS) {
-+			if (atmel_spi_wait_idle(as, msg))
-+				cs_change = 1;
-+			else
-+				msg->status = 0;
- 		}
-+		if (!cs_change)
-+			cs_deactivate(as, spi);
-+		else
-+			as->stay = spi;
-+
-+		atmel_spi_dma_unmap_msg(as, msg);
-+
-+		msg->complete(msg->context);
-+		spin_lock_irq(&as->lock);
-+		list_del(&msg->queue);
-+	}
-+	spin_unlock_irq(&as->lock);
-+}
-+
-+static irqreturn_t atmel_spi_interrupt(int irq, void *dev_id)
-+{
-+	struct atmel_spi	*as = dev_id;
-+	u32			status;
-+	u32			mask;
-+	u32			pending;
-+
-+	spin_lock(&as->lock);
-+
-+	status = spi_readl(as, SR);
-+	mask = spi_readl(as, IMR);
-+	pending = status & mask;
-+
-+	if (pending & SPI_BIT(OVRES)) {
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-+#endif
-+		spi_writel(as, IDR, ~0UL);
-+		as->error = -EIO;
-+		as->pending = 0;
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+	} else if (pending & SPI_BIT(RXBUFF)) {
-+		spi_writel(as, IDR, ~0UL);
-+		as->pending = 0;
-+	} else if (pending & SPI_BIT(ENDRX)) {
-+		spi_writel(as, IDR, SPI_BIT(ENDRX));
-+		as->pending--;
-+#endif
-+	} else {
-+		dev_err(&as->pdev->dev,
-+			"unexpected interrupt: SR=0x%08x MR=0x%08x\n",
-+				status, mask);
-+		spi_writel(as, IDR, pending);
- 	}
- 
-+	spi_readl(as, IMR);
-+	wake_up(&as->wait);
-+
- 	spin_unlock(&as->lock);
- 
--	return ret;
-+	return IRQ_HANDLED;
- }
- 
- /* the spi->mode bits understood by this driver: */
-@@ -502,6 +939,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
- static int atmel_spi_setup(struct spi_device *spi)
- {
- 	struct atmel_spi	*as;
-+	struct atmel_spi_device	*asd;
- 	u32			scbr, csr;
- 	unsigned int		bits = spi->bits_per_word;
- 	unsigned long		bus_hz;
-@@ -536,21 +974,14 @@ static int atmel_spi_setup(struct spi_device *spi)
- 	}
- 
- 	/* see notes above re chipselect */
--	if (cpu_is_at91rm9200()
-+	if (!atmel_spi_is_v2()
- 			&& spi->chip_select == 0
- 			&& (spi->mode & SPI_CS_HIGH)) {
- 		dev_dbg(&spi->dev, "setup: can't be active-high\n");
- 		return -EINVAL;
- 	}
- 
--	/*
--	 * Pre-new_1 chips start out at half the peripheral
--	 * bus speed.
--	 */
--	bus_hz = clk_get_rate(as->clk);
--	if (!as->new_1)
--		bus_hz /= 2;
--
-+	bus_hz = as->base_hz;
- 	if (spi->max_speed_hz) {
- 		/*
- 		 * Calculate the lowest divider that satisfies the
-@@ -589,11 +1020,20 @@ static int atmel_spi_setup(struct spi_device *spi)
- 
- 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
- 	npcs_pin = (unsigned int)spi->controller_data;
--	if (!spi->controller_state) {
-+	asd = spi->controller_state;
-+	if (!asd) {
-+		asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
-+		if (!asd)
-+			return -ENOMEM;
-+
- 		ret = gpio_request(npcs_pin, spi->dev.bus_id);
--		if (ret)
-+		if (ret) {
-+			kfree(asd);
- 			return ret;
--		spi->controller_state = (void *)npcs_pin;
-+		}
-+
-+		asd->npcs_pin = npcs_pin;
-+		spi->controller_state = asd;
- 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
- 	} else {
- 		unsigned long		flags;
-@@ -605,11 +1045,14 @@ static int atmel_spi_setup(struct spi_device *spi)
- 		spin_unlock_irqrestore(&as->lock, flags);
- 	}
- 
-+	asd->csr = csr;
-+
- 	dev_dbg(&spi->dev,
- 		"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
- 		bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
- 
--	spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
-+	if (!atmel_spi_is_v2())
-+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
- 
- 	return 0;
- }
-@@ -620,74 +1063,81 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
- 	struct spi_transfer	*xfer;
- 	unsigned long		flags;
- 	struct device		*controller = spi->master->dev.parent;
-+	int			ret;
- 
- 	as = spi_master_get_devdata(spi->master);
- 
--	dev_dbg(controller, "new message %p submitted for %s\n",
-+	dev_vdbg(controller, "new message %p submitted for %s\n",
- 			msg, spi->dev.bus_id);
- 
- 	if (unlikely(list_empty(&msg->transfers)
- 			|| !spi->max_speed_hz))
- 		return -EINVAL;
- 
--	if (as->stopping)
--		return -ESHUTDOWN;
--
- 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- 		if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
- 			dev_dbg(&spi->dev, "missing rx or tx buf\n");
- 			return -EINVAL;
- 		}
- 
--		/* FIXME implement these protocol options!! */
--		if (xfer->bits_per_word || xfer->speed_hz) {
--			dev_dbg(&spi->dev, "no protocol options yet\n");
--			return -ENOPROTOOPT;
-+		if (xfer->bits_per_word && (xfer->bits_per_word < 8
-+					|| xfer->bits_per_word > 16)) {
-+			dev_dbg(&spi->dev, "unsupported bits_per_word\n");
-+			return -EINVAL;
-+		}
-+		if (xfer->speed_hz) {
-+			unsigned long divider;
-+			divider = DIV_ROUND_UP(as->base_hz, xfer->speed_hz);
-+
-+			if (divider > 255) {
-+				dev_dbg(&spi->dev, "speed_hz too low\n");
-+				return -EINVAL;
-+			}
- 		}
- 
- 		/*
- 		 * DMA map early, for performance (empties dcache ASAP) and
- 		 * better fault reporting.  This is a DMA-only driver.
--		 *
--		 * NOTE that if dma_unmap_single() ever starts to do work on
--		 * platforms supported by this driver, we would need to clean
--		 * up mappings for previously-mapped transfers.
- 		 */
- 		if (!msg->is_dma_mapped) {
--			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
-+			if (atmel_spi_dma_map_xfer(as, xfer) < 0) {
-+				/* Ick */
-+				while (xfer->transfer_list.prev != &msg->transfers) {
-+					xfer = list_entry(xfer->transfer_list.prev,
-+							struct spi_transfer,
-+							transfer_list);
-+					atmel_spi_dma_unmap_xfer(as, xfer);
-+				}
-+
- 				return -ENOMEM;
-+			}
- 		}
- 	}
- 
--#ifdef VERBOSE
--	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
--		dev_dbg(controller,
--			"  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len,
--			xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--	}
--#endif
--
- 	msg->status = -EINPROGRESS;
- 	msg->actual_length = 0;
- 
- 	spin_lock_irqsave(&as->lock, flags);
--	list_add_tail(&msg->queue, &as->queue);
--	if (!as->current_transfer)
--		atmel_spi_next_message(spi->master);
-+	if (as->stopping) {
-+		ret = -ESHUTDOWN;
-+	} else {
-+		list_add_tail(&msg->queue, &as->queue);
-+		queue_work(as->workqueue, &as->work);
-+		ret = 0;
-+	}
- 	spin_unlock_irqrestore(&as->lock, flags);
- 
--	return 0;
-+	return ret;
- }
- 
- static void atmel_spi_cleanup(struct spi_device *spi)
- {
- 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
-+	struct atmel_spi_device	*asd = spi->controller_state;
- 	unsigned		gpio = (unsigned) spi->controller_data;
- 	unsigned long		flags;
- 
--	if (!spi->controller_state)
-+	if (!asd)
- 		return;
- 
- 	spin_lock_irqsave(&as->lock, flags);
-@@ -697,14 +1147,131 @@ static void atmel_spi_cleanup(struct spi_device *spi)
- 	}
- 	spin_unlock_irqrestore(&as->lock, flags);
- 
-+	spi->controller_state = NULL;
- 	gpio_free(gpio);
-+	kfree(asd);
-+}
-+
-+static void atmel_spi_stop_queue(struct atmel_spi *as)
-+{
-+	struct spi_message	*msg;
-+
-+	/*
-+	 * Prevent any new messages from being submitted, cancel any
-+	 * submitted but not-yet-started messages, and wait for any
-+	 * ongoing messages to complete.
-+	 */
-+	as->stopping = true;
-+	smp_wmb();
-+	cancel_work_sync(&as->work);
-+
-+	/* Terminate anything that was left over */
-+	list_for_each_entry(msg, &as->queue, queue) {
-+		atmel_spi_dma_unmap_msg(as, msg);
-+		msg->status = -ESHUTDOWN;
-+		msg->complete(msg->context);
-+	}
-+}
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+static enum dma_state_client atmel_spi_dma_chan_avail(struct atmel_spi *as,
-+		struct dma_chan *chan, struct dma_chan **pchan)
-+{
-+	enum dma_state_client ret = DMA_NAK;
-+
-+	if (!*pchan) {
-+		as->stopping = false;
-+		*pchan = chan;
-+		ret = DMA_ACK;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_chan_removed(struct atmel_spi *as,
-+		struct dma_chan *chan, struct dma_chan **pchan)
-+{
-+	enum dma_state_client ret = DMA_NAK;
-+
-+	if (chan == *pchan) {
-+		atmel_spi_stop_queue(as);
-+		*pchan = NULL;
-+		ret = DMA_ACK;
-+	}
-+
-+	return ret;
- }
- 
-+static enum dma_state_client atmel_spi_dma_rx_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_spi	*as;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	as = container_of(client, struct atmel_spi, rx_client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		ret = atmel_spi_dma_chan_avail(as, chan, &as->rx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev,
-+					"Using %s for DMA RX transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		ret = atmel_spi_dma_chan_removed(as, chan, &as->rx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_tx_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_spi	*as;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	as = container_of(client, struct atmel_spi, tx_client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		ret = atmel_spi_dma_chan_avail(as, chan, &as->tx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev,
-+					"Using %s for DMA TX transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		ret = atmel_spi_dma_chan_removed(as, chan, &as->tx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+#endif
-+
- /*-------------------------------------------------------------------------*/
- 
- static int __init atmel_spi_probe(struct platform_device *pdev)
- {
- 	struct resource		*regs;
-+	struct resource		*buf;
-+	struct atmel_spi_pdata	*pdata;
- 	int			irq;
- 	struct clk		*clk;
- 	int			ret;
-@@ -719,6 +1286,14 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 	if (irq < 0)
- 		return irq;
- 
-+	pdata = pdev->dev.platform_data;
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	if (!pdata) {
-+		dev_dbg(&pdev->dev, "no platform data\n");
-+		return -ENXIO;
-+	}
-+#endif
-+
- 	clk = clk_get(&pdev->dev, "spi_clk");
- 	if (IS_ERR(clk))
- 		return PTR_ERR(clk);
-@@ -738,31 +1313,65 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 
- 	as = spi_master_get_devdata(master);
- 
--	/*
--	 * Scratch buffer is used for throwaway rx and tx data.
--	 * It's coherent to minimize dcache pollution.
--	 */
--	as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
--					&as->buffer_dma, GFP_KERNEL);
--	if (!as->buffer)
--		goto out_free;
-+	buf = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (buf) {
-+		as->buffer_dma = buf->start;
-+		as->buffer_size
-+			= rounddown_pow_of_two(buf->end - buf->start + 1);
-+		if (as->buffer_size) {
-+			as->buffer = (void __force *)ioremap(buf->start,
-+					as->buffer_size);
-+			if (as->buffer)
-+				as->always_bounce = true;
-+		}
-+	}
-+
-+	if (!as->buffer) {
-+		/*
-+		 * Scratch buffer is used for throwaway rx and tx data.
-+		 * It's coherent to minimize dcache pollution.
-+		 */
-+		as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
-+						&as->buffer_dma, GFP_KERNEL);
-+		if (!as->buffer)
-+			goto out_free;
-+	}
- 
- 	spin_lock_init(&as->lock);
-+	init_waitqueue_head(&as->wait);
- 	INIT_LIST_HEAD(&as->queue);
-+	INIT_WORK(&as->work, atmel_spi_work);
- 	as->pdev = pdev;
-+	as->clk = clk;
- 	as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
- 	if (!as->regs)
- 		goto out_free_buffer;
--	as->irq = irq;
--	as->clk = clk;
--	if (!cpu_is_at91rm9200())
--		as->new_1 = 1;
- 
--	ret = request_irq(irq, atmel_spi_interrupt, 0,
--			pdev->dev.bus_id, master);
-+	ret = request_irq(irq, atmel_spi_interrupt, 0, pdev->dev.bus_id, as);
- 	if (ret)
- 		goto out_unmap_regs;
- 
-+	as->workqueue = create_singlethread_workqueue(pdev->dev.bus_id);
-+	if (!as->workqueue)
-+		goto out_free_irq;
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	as->rx_client.event_callback = atmel_spi_dma_rx_event;
-+	dma_cap_set(DMA_SLAVE, as->rx_client.cap_mask);
-+	as->rx_client.slave = pdata->rx_dma_slave;
-+	pdata->rx_dma_slave->rx_reg = regs->start + SPI_RDR + 3;
-+
-+	as->tx_client.event_callback = atmel_spi_dma_tx_event;
-+	dma_cap_set(DMA_SLAVE, as->tx_client.cap_mask);
-+	as->tx_client.slave = pdata->tx_dma_slave;
-+	pdata->tx_dma_slave->tx_reg = regs->start + SPI_TDR + 3;
-+
-+	dma_async_client_register(&as->rx_client);
-+	dma_async_client_register(&as->tx_client);
-+	dma_async_client_chan_request(&as->rx_client);
-+	dma_async_client_chan_request(&as->tx_client);
-+#endif
-+
- 	/* Initialize the hardware */
- 	clk_enable(clk);
- 	spi_writel(as, CR, SPI_BIT(SWRST));
-@@ -770,9 +1379,19 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
- 	spi_writel(as, CR, SPI_BIT(SPIEN));
- 
-+	/* v1 chips start out at half the peripheral bus speed. */
-+	as->base_hz = clk_get_rate(clk);
-+	if (!atmel_spi_is_v2())
-+		as->base_hz /= 2;
-+
- 	/* go! */
- 	dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
- 			(unsigned long)regs->start, irq);
-+	if (as->always_bounce)
-+		dev_info(&pdev->dev, "Using bounce buffer at 0x%08x len %zu\n",
-+				as->buffer_dma, as->buffer_size);
-+
-+	atmel_spi_init_debugfs(as);
- 
- 	ret = spi_register_master(master);
- 	if (ret)
-@@ -781,9 +1400,16 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 	return 0;
- 
- out_reset_hw:
-+	atmel_spi_cleanup_debugfs(as);
- 	spi_writel(as, CR, SPI_BIT(SWRST));
- 	clk_disable(clk);
--	free_irq(irq, master);
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	dma_async_client_unregister(&as->tx_client);
-+	dma_async_client_unregister(&as->rx_client);
-+#endif
-+	destroy_workqueue(as->workqueue);
-+out_free_irq:
-+	free_irq(irq, as);
- out_unmap_regs:
- 	iounmap(as->regs);
- out_free_buffer:
-@@ -799,33 +1425,34 @@ static int __exit atmel_spi_remove(struct platform_device *pdev)
- {
- 	struct spi_master	*master = platform_get_drvdata(pdev);
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
- 
--	/* reset the hardware and block queue progress */
--	spin_lock_irq(&as->lock);
--	as->stopping = 1;
--	spi_writel(as, CR, SPI_BIT(SWRST));
--	spi_readl(as, SR);
--	spin_unlock_irq(&as->lock);
-+	/* Stop the queue */
-+	atmel_spi_stop_queue(as);
- 
--	/* Terminate remaining queued transfers */
--	list_for_each_entry(msg, &as->queue, queue) {
--		/* REVISIT unmapping the dma is a NOP on ARM and AVR32
--		 * but we shouldn't depend on that...
--		 */
--		msg->status = -ESHUTDOWN;
--		msg->complete(msg->context);
--	}
-+	atmel_spi_cleanup_debugfs(as);
- 
--	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
--			as->buffer_dma);
-+	/* Shut down the hardware */
-+	spi_writel(as, CR, SPI_BIT(SWRST));
-+	spi_readl(as, SR);
- 
-+	/* Clean up */
-+	spi_unregister_master(master);
-+	free_irq(platform_get_irq(pdev, 0), as);
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	dma_async_client_unregister(&as->tx_client);
-+	dma_async_client_unregister(&as->rx_client);
-+#endif
-+	destroy_workqueue(as->workqueue);
-+	if (as->always_bounce)
-+		iounmap((void __iomem __force *)as->buffer);
-+	else
-+		dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
-+				as->buffer_dma);
-+	iounmap(as->regs);
- 	clk_disable(as->clk);
- 	clk_put(as->clk);
--	free_irq(as->irq, master);
--	iounmap(as->regs);
- 
--	spi_unregister_master(master);
-+	spi_master_put(master);
- 
- 	return 0;
- }
-@@ -837,7 +1464,9 @@ static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
- 	struct spi_master	*master = platform_get_drvdata(pdev);
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
- 
-+	atmel_spi_stop_queue(as);
- 	clk_disable(as->clk);
-+
- 	return 0;
- }
- 
-@@ -847,6 +1476,9 @@ static int atmel_spi_resume(struct platform_device *pdev)
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
- 
- 	clk_enable(as->clk);
-+	as->stopping = false;
-+	smp_wmb();
-+
- 	return 0;
- }
- 
-@@ -868,7 +1500,12 @@ static struct platform_driver atmel_spi_driver = {
- 
- static int __init atmel_spi_init(void)
- {
--	return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
-+	int ret;
-+
-+	ret = platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
-+	if (ret)
-+		pr_notice("atmel_spi probe failed: %d\n", ret);
-+	return ret;
- }
- module_init(atmel_spi_init);
- 
-@@ -879,6 +1516,6 @@ static void __exit atmel_spi_exit(void)
- module_exit(atmel_spi_exit);
- 
- MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
--MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
--MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
-+MODULE_LICENSE("GPL v2");
- MODULE_ALIAS("platform:atmel_spi");
-diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
-index bcefbdd..6882a7d 100644
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -37,6 +37,8 @@ config USB_ARCH_HAS_OHCI
- 	default y if ARCH_EP93XX
- 	default y if ARCH_AT91
- 	default y if ARCH_PNX4008
-+	# AVR32
-+	default y if AVR32
- 	# PPC:
- 	default y if STB03xxx
- 	default y if PPC_MPC52xx
-@@ -55,6 +57,7 @@ config USB_ARCH_HAS_EHCI
- 	default y if PPC_83xx
- 	default y if SOC_AU1200
- 	default y if ARCH_IXP4XX
-+	default y if AVR32
- 	default PCI
- 
- # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index 228797e..8c48773 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -73,12 +73,12 @@ config USB_EHCI_TT_NEWSCHED
- 
- config USB_EHCI_BIG_ENDIAN_MMIO
- 	bool
--	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX)
-+	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || AVR32)
- 	default y
- 
- config USB_EHCI_BIG_ENDIAN_DESC
- 	bool
--	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
-+	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || AVR32)
- 	default y
- 
- config USB_EHCI_FSL
-@@ -208,17 +208,19 @@ config USB_OHCI_HCD_SSB
- config USB_OHCI_BIG_ENDIAN_DESC
- 	bool
- 	depends on USB_OHCI_HCD
-+	default y if AVR32
- 	default n
- 
- config USB_OHCI_BIG_ENDIAN_MMIO
- 	bool
- 	depends on USB_OHCI_HCD
-+	default y if AVR32
- 	default n
- 
- config USB_OHCI_LITTLE_ENDIAN
- 	bool
- 	depends on USB_OHCI_HCD
--	default n if STB03xxx || PPC_MPC52xx
-+	default n if STB03xxx || PPC_MPC52xx || AVR32
- 	default y
- 
- config USB_UHCI_HCD
-diff --git a/drivers/usb/host/ehci-avr32.c b/drivers/usb/host/ehci-avr32.c
-new file mode 100644
-index 0000000..7cd0591
---- /dev/null
-+++ b/drivers/usb/host/ehci-avr32.c
-@@ -0,0 +1,213 @@
-+/*
-+ * AVR32 EHCI bus and power management glue
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+
-+static struct clk	*utmi_clk;
-+static struct clk	*hclk;
-+
-+static void ehci_avr32_start_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "starting clocks...\n");
-+
-+	clk_enable(utmi_clk);
-+	clk_enable(hclk);
-+}
-+
-+static void ehci_avr32_stop_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "stopping clocks...\n");
-+
-+	clk_disable(hclk);
-+	clk_disable(utmi_clk);
-+}
-+
-+static int ehci_avr32_setup(struct usb_hcd *hcd)
-+{
-+	struct device	*dev = hcd->self.controller;
-+	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
-+	int		ret;
-+
-+	ehci_avr32_start_clocks(dev);
-+
-+	ehci->caps = hcd->regs;
-+	ehci->regs = hcd->regs
-+		+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
-+	dbg_hcs_params(ehci, "reset");
-+	dbg_hcc_params(ehci, "reset");
-+
-+	/* cache this readonly data; minimize chip reads */
-+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-+
-+	ret = ehci_halt(ehci);
-+	if (ret)
-+		goto err;
-+
-+	/* data structure init */
-+	ret = ehci_init(hcd);
-+	if (ret)
-+		goto err;
-+
-+	ehci->sbrn = 0x20;
-+	ehci_port_power(ehci, 0);
-+
-+	return 0;
-+
-+err:
-+	ehci_avr32_stop_clocks(dev);
-+	return ret;
-+}
-+
-+static void ehci_avr32_shutdown(struct usb_hcd *hcd)
-+{
-+	ehci_shutdown(hcd);
-+	ehci_avr32_stop_clocks(hcd->self.controller);
-+}
-+
-+static const struct hc_driver ehci_avr32_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "AVR32 USBH (EHCI)",
-+	.hcd_priv_size		= sizeof(struct ehci_hcd),
-+
-+	.irq			= ehci_irq,
-+	.flags			= HCD_MEMORY | HCD_USB2,
-+
-+	.reset			= ehci_avr32_setup,
-+	.start			= ehci_run,
-+	.stop			= ehci_stop,
-+	.shutdown		= ehci_avr32_shutdown,
-+
-+	.urb_enqueue		= ehci_urb_enqueue,
-+	.urb_dequeue		= ehci_urb_dequeue,
-+	.endpoint_disable	= ehci_endpoint_disable,
-+
-+	.get_frame_number	= ehci_get_frame,
-+
-+	.hub_status_data	= ehci_hub_status_data,
-+	.hub_control		= ehci_hub_control,
-+	.bus_suspend		= ehci_bus_suspend,
-+	.bus_resume		= ehci_bus_resume,
-+	.relinquish_port	= ehci_relinquish_port,
-+	.port_handed_over	= ehci_port_handed_over,
-+};
-+
-+static int ehci_avr32_probe(struct platform_device *pdev)
-+{
-+	struct resource		*reg_res;
-+	struct usb_hcd		*hcd;
-+	struct ehci_hcd		*ehci;
-+	int			irq;
-+	int			ret;
-+
-+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!reg_res) {
-+		dev_dbg(&pdev->dev, "no MMIO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no IRQ resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		return -ENXIO;
-+	}
-+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
-+	if (IS_ERR(utmi_clk)) {
-+		dev_dbg(&pdev->dev, "no UTMI clock\n");
-+		ret = -ENXIO;
-+		goto err_utmi_clk;
-+	}
-+
-+	if (!request_mem_region(reg_res->start,
-+				reg_res->end - reg_res->start + 1,
-+				hcd_name)) {
-+		dev_dbg(&pdev->dev, "config regs busy\n");
-+		ret = -EBUSY;
-+		goto err_request_mmio;
-+	}
-+
-+	ret = -ENOMEM;
-+
-+	hcd = usb_create_hcd(&ehci_avr32_hc_driver, &pdev->dev, "ehci-avr32");
-+	if (!hcd) {
-+		dev_dbg(&pdev->dev, "failed to create hcd\n");
-+		goto err_create_hcd;
-+	}
-+
-+	hcd->rsrc_start = reg_res->start;
-+	hcd->rsrc_len = reg_res->end - reg_res->start + 1;
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		goto err_ioremap;
-+	}
-+
-+	ehci = hcd_to_ehci(hcd);
-+	ehci->big_endian_mmio = 1;
-+	ehci->big_endian_desc = 1;
-+
-+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
-+	if (ret)
-+		goto err_add_hcd;
-+
-+	return 0;
-+
-+err_add_hcd:
-+	iounmap(hcd->regs);
-+err_ioremap:
-+	usb_put_hcd(hcd);
-+err_create_hcd:
-+	release_mem_region(reg_res->start, reg_res->end - reg_res->start + 1);
-+err_request_mmio:
-+	clk_put(utmi_clk);
-+err_utmi_clk:
-+	clk_put(hclk);
-+
-+	return ret;
-+}
-+
-+static int ehci_avr32_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	usb_remove_hcd(hcd);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+	clk_put(utmi_clk);
-+	clk_put(hclk);
-+
-+	return 0;
-+}
-+
-+/* FIXME */
-+#define ehci_avr32_suspend	NULL
-+#define ehci_avr32_resume	NULL
-+
-+static struct platform_driver ehci_hcd_avr32_driver = {
-+	.probe		= ehci_avr32_probe,
-+	.remove		= ehci_avr32_remove,
-+	.suspend	= ehci_avr32_suspend,
-+	.resume		= ehci_avr32_resume,
-+	.shutdown	= usb_hcd_platform_shutdown,
-+	.driver		= {
-+		.name	= "ehci",
-+	},
-+};
-diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
-index 86e38b0..15e3956 100644
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -1015,6 +1015,11 @@ MODULE_LICENSE ("GPL");
- #define	PLATFORM_DRIVER		ehci_hcd_au1xxx_driver
- #endif
- 
-+#ifdef CONFIG_AVR32
-+#include "ehci-avr32.c"
-+#define PLATFORM_DRIVER		ehci_hcd_avr32_driver
-+#endif
-+
- #ifdef CONFIG_PPC_PS3
- #include "ehci-ps3.c"
- #define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
-diff --git a/drivers/usb/host/ohci-avr32.c b/drivers/usb/host/ohci-avr32.c
-new file mode 100644
-index 0000000..67f25d6
---- /dev/null
-+++ b/drivers/usb/host/ohci-avr32.c
-@@ -0,0 +1,208 @@
-+/*
-+ * AVR32 OHCI bus and power management glue
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+
-+/* Grr! The core layer doesn't let us keep private data anywhere! */
-+static struct clk	*ohci_clk;
-+static struct clk	*utmi_clk;
-+static struct clk	*hclk;
-+
-+static void ohci_avr32_start_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "starting clocks...\n");
-+
-+	clk_enable(ohci_clk);
-+	clk_enable(utmi_clk);
-+	clk_enable(hclk);
-+}
-+
-+static void ohci_avr32_stop_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "stopping clocks...\n");
-+
-+	clk_disable(hclk);
-+	clk_disable(utmi_clk);
-+	clk_disable(ohci_clk);
-+}
-+
-+static int ohci_avr32_start(struct usb_hcd *hcd)
-+{
-+	struct device	*dev = hcd->self.controller;
-+	struct ohci_hcd	*ohci = hcd_to_ohci(hcd);
-+	int		ret;
-+
-+	ohci_avr32_start_clocks(dev);
-+
-+	ret = ohci_init(ohci);
-+	if (ret)
-+		goto err_ohci_init;
-+
-+	ret = ohci_run(ohci);
-+	if (likely(!ret))
-+		return 0;
-+
-+	ohci_stop(hcd);
-+
-+err_ohci_init:
-+	ohci_avr32_stop_clocks(dev);
-+	return ret;
-+}
-+
-+static void ohci_avr32_stop(struct usb_hcd *hcd)
-+{
-+	ohci_stop(hcd);
-+	ohci_avr32_stop_clocks(hcd->self.controller);
-+}
-+
-+static const struct hc_driver ohci_avr32_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "AVR32 USBH (OHCI)",
-+	.hcd_priv_size		= sizeof(struct ohci_hcd),
-+
-+	.irq			= ohci_irq,
-+	.flags			= HCD_USB11 | HCD_MEMORY,
-+
-+	.start			= ohci_avr32_start,
-+	.stop			= ohci_avr32_stop,
-+	.shutdown		= ohci_shutdown,
-+
-+	.urb_enqueue		= ohci_urb_enqueue,
-+	.urb_dequeue		= ohci_urb_dequeue,
-+	.endpoint_disable	= ohci_endpoint_disable,
-+	.get_frame_number	= ohci_get_frame,
-+	.hub_status_data	= ohci_hub_status_data,
-+	.hub_control		= ohci_hub_control,
-+#ifdef CONFIG_PM
-+	.bus_suspend		= ohci_bus_suspend,
-+	.bus_resume		= ohci_bus_resume,
-+#endif
-+	.start_port_reset	= ohci_start_port_reset,
-+};
-+
-+static int ohci_avr32_probe(struct platform_device *pdev)
-+{
-+	struct resource		*regs;
-+	struct usb_hcd		*hcd;
-+	int			irq;
-+	int			ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "no MMIO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no IRQ resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		return -ENXIO;
-+	}
-+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
-+	if (IS_ERR(utmi_clk)) {
-+		dev_dbg(&pdev->dev, "no UTMI clock\n");
-+		ret = -ENXIO;
-+		goto err_utmi_clk;
-+	}
-+	ohci_clk = clk_get(&pdev->dev, "ohci_clk");
-+	if (IS_ERR(ohci_clk)) {
-+		dev_dbg(&pdev->dev, "no OHCI clock\n");
-+		ret = -ENXIO;
-+		goto err_ohci_clk;
-+	}
-+
-+	if (!request_mem_region(regs->start, regs->end - regs->start + 1,
-+				hcd_name)) {
-+		dev_dbg(&pdev->dev, "config regs busy\n");
-+		ret = -EBUSY;
-+		goto err_request_mmio;
-+	}
-+
-+	ret = -ENOMEM;
-+	hcd = usb_create_hcd(&ohci_avr32_hc_driver, &pdev->dev, "ohci-avr32");
-+	if (!hcd) {
-+		dev_dbg(&pdev->dev, "failed to create hcd\n");
-+		goto err_create_hcd;
-+	}
-+
-+	hcd->rsrc_start = regs->start;
-+	hcd->rsrc_len = regs->end - regs->start + 1;
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		goto err_ioremap;
-+	}
-+
-+	ohci_hcd_init(hcd_to_ohci(hcd));
-+
-+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
-+	if (ret)
-+		goto err_add_hcd;
-+
-+	return 0;
-+
-+err_add_hcd:
-+	iounmap(hcd->regs);
-+err_ioremap:
-+	usb_put_hcd(hcd);
-+err_create_hcd:
-+	release_mem_region(regs->start, regs->end - regs->start + 1);
-+err_request_mmio:
-+	clk_put(ohci_clk);
-+err_ohci_clk:
-+	clk_put(utmi_clk);
-+err_utmi_clk:
-+	clk_put(hclk);
-+
-+	return ret;
-+}
-+
-+static int ohci_avr32_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	usb_remove_hcd(hcd);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+	clk_put(utmi_clk);
-+	clk_put(ohci_clk);
-+	clk_put(hclk);
-+
-+	return 0;
-+}
-+
-+/* FIXME */
-+#define ohci_avr32_suspend	NULL
-+#define ohci_avr32_resume	NULL
-+
-+static struct platform_driver ohci_hcd_avr32_driver = {
-+	.probe		= ohci_avr32_probe,
-+	.remove		= ohci_avr32_remove,
-+	.shutdown	= usb_hcd_platform_shutdown,
-+	.suspend	= ohci_avr32_suspend,
-+	.resume		= ohci_avr32_resume,
-+	.driver		= {
-+		.owner	= THIS_MODULE,
-+		.name	= "ohci",
-+	},
-+};
-+MODULE_ALIAS("platform:ohci");
-diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
-index 8bec02c..43bed29 100644
---- a/drivers/usb/host/ohci-hcd.c
-+++ b/drivers/usb/host/ohci-hcd.c
-@@ -1045,6 +1045,11 @@ MODULE_LICENSE ("GPL");
- #define PLATFORM_DRIVER		ohci_hcd_at91_driver
- #endif
- 
-+#ifdef CONFIG_AVR32
-+#include "ohci-avr32.c"
-+#define PLATFORM_DRIVER		ohci_hcd_avr32_driver
-+#endif
-+
- #ifdef CONFIG_ARCH_PNX4008
- #include "ohci-pnx4008.c"
- #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
-diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
-index faf622e..d77ea5c 100644
---- a/drivers/usb/host/ohci.h
-+++ b/drivers/usb/host/ohci.h
-@@ -654,8 +654,10 @@ static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
-  * some big-endian SOC implementations.  Same thing happens with PSW access.
-  */
- 
--#ifdef CONFIG_PPC_MPC52xx
-+#if defined(CONFIG_PPC_MPC52xx)
- #define big_endian_frame_no_quirk(ohci)	(ohci->flags & OHCI_QUIRK_FRAME_NO)
-+#elif defined(CONFIG_AVR32)
-+#define big_endian_frame_no_quirk(ohci)	1
- #else
- #define big_endian_frame_no_quirk(ohci)	0
- #endif
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index 70d135e..9f8e70b 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -938,6 +938,15 @@ config FB_ATMEL
- 	help
- 	  This enables support for the AT91/AT32 LCD Controller.
- 
-+config FB_ATMEL_MPOP
-+	tristate "AT32 MPOP support"
-+	depends on FB && AVR32 && FB_ATMEL
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	help
-+	  This enables support for the AT32 MPOP module.
-+
- config FB_INTSRAM
- 	bool "Frame Buffer in internal SRAM"
- 	depends on FB_ATMEL && ARCH_AT91SAM9261
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index a6b5529..edc0656 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -89,6 +89,7 @@ obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
- obj-$(CONFIG_FB_HIT)              += hitfb.o
- obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
- obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
-+obj-$(CONFIG_FB_ATMEL_MPOP)	  += atmel_mpopfb.o
- obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
- obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
- obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
-diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
-index 75dac57..993d79e 100644
---- a/drivers/video/atmel_lcdfb.c
-+++ b/drivers/video/atmel_lcdfb.c
-@@ -178,7 +178,7 @@ static void init_contrast(struct atmel_lcdfb_info *sinfo)
- static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
- 	.type		= FB_TYPE_PACKED_PIXELS,
- 	.visual		= FB_VISUAL_TRUECOLOR,
--	.xpanstep	= 0,
-+	.xpanstep	= 1,
- 	.ypanstep	= 1,
- 	.ywrapstep	= 0,
- 	.accel		= FB_ACCEL_NONE,
-@@ -239,7 +239,7 @@ static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
- }
- 
- static void atmel_lcdfb_update_dma(struct fb_info *info,
--			       struct fb_var_screeninfo *var)
-+                                   struct fb_var_screeninfo *var)
- {
- 	struct atmel_lcdfb_info *sinfo = info->par;
- 	struct fb_fix_screeninfo *fix = &info->fix;
-@@ -251,6 +251,8 @@ static void atmel_lcdfb_update_dma(struct fb_info *info,
- 	dma_addr &= ~3UL;
- 
- 	/* Set framebuffer DMA base address and pixel offset */
-+	dev_dbg(info->device, "%s:\n", __func__);
-+        dev_dbg(info->device, "  *setting dma addr: 0x%lx \n", dma_addr); 
- 	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
- 
- 	atmel_lcdfb_update_dma2d(sinfo, var);
-@@ -482,6 +484,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
- 	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
- 		 info->var.xres, info->var.yres,
- 		 info->var.xres_virtual, info->var.yres_virtual);
-+	dev_dbg(info->device, "  * bpp:        %u\n", info->var.bits_per_pixel);
- 
- 	atmel_lcdfb_stop_nowait(sinfo);
- 
-@@ -583,7 +586,12 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
- 	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
- 	/* Enable FIFO & DMA errors */
- 	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
--
-+        
-+        /* !!!HACK for logging end of frame and underruns 
-+           when connected to MPOP. */
-+        if( info->var.bits_per_pixel == 32 )
-+          lcdc_writel(sinfo, ATMEL_LCDC_IER, 0x70);
-+        
- 	/* ...wait for DMA engine to become idle... */
- 	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
- 		msleep(10);
-@@ -684,7 +692,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
- }
- 
- static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
--			       struct fb_info *info)
-+                                   struct fb_info *info)
- {
- 	dev_dbg(info->device, "%s\n", __func__);
- 
-@@ -816,7 +824,8 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
- 	info->fix = atmel_lcdfb_fix;
- 
- 	/* Enable LCDC Clocks */
--	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
-+	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()
-+			|| cpu_is_at32ap7200()) {
- 		sinfo->bus_clk = clk_get(dev, "hck1");
- 		if (IS_ERR(sinfo->bus_clk)) {
- 			ret = PTR_ERR(sinfo->bus_clk);
-diff --git a/drivers/video/atmel_mpopfb.c b/drivers/video/atmel_mpopfb.c
-new file mode 100644
-index 0000000..0a07f7b
---- /dev/null
-+++ b/drivers/video/atmel_mpopfb.c
-@@ -0,0 +1,1127 @@
-+/*
-+ *  Driver for AT91/AT32 LCD Controller
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file COPYING in the main directory of this archive for
-+ * more details.
-+ */
-+
-+#define DEBUG
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+
-+#include <mach/board.h>
-+#include <mach/cpu.h>
-+
-+#include <video/atmel_lcdc.h>
-+#include <video/atmel_mpop.h>
-+
-+#define mpop_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
-+#define mpop_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
-+
-+#define	ATMEL_MPOPFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
-+                                         | FBINFO_PARTIAL_PAN_OK        \
-+                                         | FBINFO_HWACCEL_XPAN          \
-+                                         | FBINFO_HWACCEL_YPAN)
-+
-+static struct atmel_mpopfb_rgbconv_coeffs atmel_mpop_ycrcb2rgb_coeffs = {
-+	.r1 = 298,
-+	.r2 = 0,
-+	.r3 = 409,
-+	.r4 = -56992,
-+	.g1 = 298,
-+	.g2 = -100,
-+	.g3 = -208,
-+	.g4 = 34784,
-+	.b1 = 298,
-+	.b2 = 516,
-+	.b3 = 0,
-+	.b4 = -70688,
-+};
-+
-+static struct fb_fix_screeninfo atmel_mpopfb_fix __initdata = {
-+	.type		= FB_TYPE_PLANES,
-+	.visual		= FB_VISUAL_TRUECOLOR,
-+	.xpanstep	= 16,
-+	.ypanstep	= 1,
-+	.ywrapstep	= 1,
-+	.accel		= FB_ACCEL_NONE,
-+};
-+
-+static void atmel_mpopfb_update_sar(struct fb_info *info,
-+		struct fb_var_screeninfo *var)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_fix_screeninfo *fix = &info->fix;
-+	u32 y_sar, u_sar, v_sar, o1_sar, o2_sar, cursor_sar, next_sar;
-+
-+	u32 chroma_xres_virtual;
-+	u32 chroma_yres_virtual;
-+	u32 chroma_xres;
-+	u32 chroma_yres;
-+	u32 chroma_xoffset;
-+	u32 chroma_yoffset;
-+
-+	switch (var->bits_per_pixel) {
-+	default:
-+	case 12:
-+		chroma_xres_virtual = var->xres_virtual / 2;
-+		chroma_yres_virtual = var->yres_virtual / 2;
-+		chroma_xres = var->xres / 2;
-+		chroma_yres = var->yres / 2;
-+		chroma_xoffset = var->xoffset / 2;
-+		chroma_yoffset = var->yoffset / 2;
-+		break;
-+	case 16:
-+		chroma_xres_virtual = var->xres_virtual / 2;
-+		chroma_yres_virtual = var->yres_virtual;
-+		chroma_xres = var->xres / 2;
-+		chroma_yres = var->yres;
-+		chroma_xoffset = var->xoffset / 2;
-+		chroma_yoffset = var->yoffset;
-+		break;
-+	case 24:
-+		chroma_xres_virtual = var->xres_virtual;
-+		chroma_yres_virtual = var->yres_virtual;
-+		chroma_xres = var->xres;
-+		chroma_yres = var->yres;
-+		chroma_xoffset = var->xoffset;
-+		chroma_yoffset = var->yoffset;
-+		break;
-+	}
-+
-+	/* Setup pointer to YUV planes in YUV framebuffer. */
-+	y_sar = fix->smem_start + var->xoffset
-+		+ var->yoffset * var->xres_virtual;
-+	u_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
-+		+ chroma_xoffset + chroma_yoffset * chroma_xres_virtual;
-+	v_sar = u_sar + chroma_xres_virtual * chroma_yres_virtual;
-+	next_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
-+		+ 2 * chroma_xres_virtual * chroma_yres_virtual;
-+	o1_sar = next_sar;
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
-+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
-+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize;
-+	o2_sar = next_sar;
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
-+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize
-+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize;
-+	cursor_sar = next_sar;
-+
-+	if (sinfo->baseimg_info.flip) {
-+		/* If we flip we must start with the last line in the frame. */
-+		y_sar += var->xres_virtual * (var->yres - 1);
-+		u_sar += chroma_xres_virtual * (chroma_yres - 1);
-+		v_sar += chroma_xres_virtual * (chroma_yres - 1);
-+	}
-+
-+	dev_dbg(info->device, "%s:\n", __func__);
-+	dev_dbg(info->device, "  * y_sar = 0x%x\n", y_sar);
-+	dev_dbg(info->device, "  * u_sar = 0x%x\n", u_sar);
-+	dev_dbg(info->device, "  * v_sar = 0x%x\n", v_sar);
-+	dev_dbg(info->device, "  * o1_sar = 0x%x\n", o1_sar);
-+	dev_dbg(info->device, "  * o2_sar = 0x%x\n", o2_sar);
-+	dev_dbg(info->device, "  * cursor_sar = 0x%x\n", cursor_sar);
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_Y_SAR, y_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_U_SAR, u_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_V_SAR, v_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_SAR, o1_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_SAR, o2_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SAR, cursor_sar);
-+}
-+
-+static void atmel_mpopfb_free_video_memory(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+
-+	dma_free_writecombine(info->device, info->fix.smem_len,
-+			(void __force *)info->screen_base,
-+			info->fix.smem_start);
-+}
-+
-+/**
-+ *	atmel_mpopfb_alloc_video_memory - Allocate framebuffer memory
-+ *	@sinfo: the frame buffer to allocate memory for
-+ */
-+static int atmel_mpopfb_alloc_video_memory(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+	struct fb_var_screeninfo *var = &info->var;
-+
-+	info->fix.smem_len = (var->xres_virtual * var->yres_virtual
-+			* ((var->bits_per_pixel + 7) / 8));
-+
-+	info->screen_base
-+		= (void __iomem __force *)dma_alloc_writecombine(info->device,
-+				info->fix.smem_len,
-+				(dma_addr_t *)&info->fix.smem_start,
-+				GFP_KERNEL);
-+
-+	if (!info->screen_base)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+/**
-+ *      atmel_mpopfb_check_var - Validates a var passed in.
-+ *      @var: frame buffer variable screen structure
-+ *      @info: frame buffer structure that represents a single frame buffer
-+ *
-+ *	Checks to see if the hardware supports the state requested by
-+ *	var passed in. This function does not alter the hardware
-+ *	state!!!  This means the data stored in struct fb_info and
-+ *	struct atmel_mpopfb_info do not change. This includes the var
-+ *	inside of struct fb_info.  Do NOT change these. This function
-+ *	can be called on its own if we intent to only test a mode and
-+ *	not actually set it. The stuff in modedb.c is a example of
-+ *	this. If the var passed in is slightly off by what the
-+ *	hardware can support then we alter the var PASSED in to what
-+ *	we can do. If the hardware doesn't support mode change a
-+ *	-EINVAL will be returned by the upper layers. You don't need
-+ *	to implement this function then. If you hardware doesn't
-+ *	support changing the resolution then this function is not
-+ *	needed. In this case the driver would just provide a var that
-+ *	represents the static state the screen is in.
-+ *
-+ *	Returns negative errno on error, or zero on success.
-+ */
-+static int atmel_mpopfb_check_var(struct fb_var_screeninfo *var,
-+		struct fb_info *info)
-+{
-+	struct device *dev = info->device;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(dev, "%s:\n", __func__);
-+	dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
-+	dev_dbg(dev, "  offset: (%u,%u)\n", var->xoffset, var->yoffset);
-+	dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
-+
-+	/*
-+	 *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
-+	 *  as FB_VMODE_SMOOTH_XPAN is only used internally
-+	 */
-+
-+	if (var->vmode & FB_VMODE_CONUPDATE) {
-+		var->vmode |= FB_VMODE_YWRAP;
-+		var->xoffset = info->var.xoffset;
-+		var->yoffset = info->var.yoffset;
-+	}
-+
-+	/* Horizontal size must be a multiple of 16 pixels */
-+
-+	/*
-+	 *  Some very basic checks
-+	 */
-+	if (!var->xres)
-+		var->xres = 1;
-+	if (!var->yres)
-+		var->yres = 1;
-+	if (var->xres > var->xres_virtual)
-+		var->xres_virtual = var->xres;
-+	if (var->yres > var->yres_virtual)
-+		var->yres_virtual = var->yres;
-+	if (var->bits_per_pixel > 16)
-+		var->bits_per_pixel = 24;
-+	else if (var->bits_per_pixel > 12)
-+		var->bits_per_pixel = 16;
-+	else
-+		var->bits_per_pixel = 12;
-+
-+	/* Horizontal size and offset must be a multiple of 16 pixels */
-+	var->xres = (var->xres + 15) & ~15UL;
-+	var->xres_virtual = (var->xres_virtual + 15) & ~15UL;
-+	var->xoffset = (var->xoffset + 15) & ~15UL;
-+
-+	if (var->xres_virtual < var->xoffset + var->xres)
-+		var->xres_virtual = var->xoffset + var->xres;
-+	if (var->yres_virtual < var->yoffset + var->yres)
-+		var->yres_virtual = var->yoffset + var->yres;
-+
-+	/* Check that the scaled image will fit into the LCD display. */
-+	if (sinfo->baseimg_info.xsize > lcdc_info->var.xres) {
-+		dev_err(dev, "baseimage is wider than screen: %d > %d\n",
-+			sinfo->baseimg_info.xsize, lcdc_info->var.xres);
-+		return -EINVAL;
-+	}
-+
-+	if (sinfo->baseimg_info.ysize > lcdc_info->var.yres) {
-+		dev_err(dev, "baseimage is higher than screen: %d > %d\n",
-+			sinfo->baseimg_info.ysize, lcdc_info->var.yres);
-+		return -EINVAL;
-+	}
-+
-+	/* Check that it is possible to scale to given size. */
-+	if (ATMEL_MPOP_CALC_SCALE(var->xres, sinfo->baseimg_info.xsize) == 0
-+			|| (ATMEL_MPOP_CALC_SCALE(var->xres,
-+					sinfo->baseimg_info.xsize)
-+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
-+		dev_err(dev, "cannot scale from width %d to %d Max %s\n",
-+			var->xres, sinfo->baseimg_info.xsize,
-+			ATMEL_MPOP_CALC_SCALE(var->xres,
-+					      sinfo->baseimg_info.xsize)
-+			? "downscale factor is 4!"
-+			: "upscale factor is 32");
-+		return -EINVAL;
-+	}
-+
-+	if (ATMEL_MPOP_CALC_SCALE(var->yres, sinfo->baseimg_info.ysize) == 0
-+			|| (ATMEL_MPOP_CALC_SCALE(var->yres,
-+					sinfo->baseimg_info.ysize)
-+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
-+		dev_err(dev, "cannot scale from height %d to %d Max %s\n",
-+			var->yres, sinfo->baseimg_info.ysize,
-+			ATMEL_MPOP_CALC_SCALE(var->yres,
-+					      sinfo->baseimg_info.ysize)
-+			? "downscale factor is 4!"
-+			: "upscale factor is 32");
-+		return -EINVAL;
-+	}
-+
-+	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
-+	var->transp.msb_right = 0;
-+	var->transp.offset = var->transp.length = 0;
-+
-+	switch (var->bits_per_pixel) {
-+	case 12:
-+	case 16:
-+	case 24:
-+		var->red.offset = 0;
-+		var->green.offset = 8;
-+		var->blue.offset = 16;
-+		var->red.length = var->green.length = var->blue.length = 8;
-+		break;
-+	default:
-+		dev_err(dev, "color depth %d not supported\n",
-+			var->bits_per_pixel);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
-+{
-+	if (!sinfo->running) {
-+		dev_dbg(sinfo->info->device, "  * Starting MPOP.\n");
-+
-+		/* Enable all error interrupts. */
-+		mpop_writel(sinfo, ATMEL_MPOP_INTEN, 0x7);
-+
-+		/*
-+		 * Enable the MPOP. When the LCD controller starts
-+		 * reading from the slave interface it will start
-+		 * generating a frame.
-+		 */
-+		mpop_writel(sinfo, ATMEL_MPOP_CR,
-+			    ATMEL_MPOP_CR_EN_MASK
-+			    /*| ATMEL_MPOP_CR_OUT_BGR_MASK */ );
-+
-+		sinfo->running = 1;
-+	}
-+}
-+
-+static void atmel_mpopfb_stop(struct atmel_mpopfb_info *sinfo)
-+{
-+	if (!sinfo->running)
-+		/* Not running. Already stopped. */
-+		return;
-+
-+	dev_dbg(sinfo->info->device, "Stopping MPOP.\n");
-+
-+	/* Disable the MPOP. This will force the MPOP to be reset. */
-+	mpop_writel(sinfo, ATMEL_MPOP_CR, 0);
-+
-+	/* Disable all interrupts. */
-+	mpop_writel(sinfo, ATMEL_MPOP_INTDIS, ~0UL);
-+
-+	/* Looks like we stopped the MPOP... */
-+	dev_dbg(sinfo->info->device, "MPOP stopped.\n");
-+
-+	sinfo->running = 0;
-+}
-+
-+static void atmel_mpopfb_connect_to_lcdc(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(sinfo->info->device, "Connecting MPOP to LCDC:\n");
-+
-+	/* Start the mpop if it is not running. */
-+	atmel_mpopfb_start(sinfo);
-+
-+	if (sinfo->connected_to_lcdc)
-+		/* Already connected. */
-+		return;
-+
-+	/*
-+	 * Set framebuffer pointer in LCDC to point to the slave
-+	 * interface of the MPOP.
-+	 */
-+	dev_dbg(sinfo->info->device, "  * Attaching to LCDC.\n");
-+	sinfo->lcdc_old_smem_start = lcdc_info->fix.smem_start;
-+	lcdc_info->fix.smem_start = (unsigned long)sinfo->slave_base;
-+	sinfo->lcdc_old_bits_per_pixel = lcdc_info->var.bits_per_pixel;
-+	lcdc_info->var.bits_per_pixel = 32;
-+
-+	/* Force the LCDC to change the configuration. */
-+	lcdc_info->fbops->fb_set_par(lcdc_info);
-+
-+	sinfo->connected_to_lcdc = 1;
-+}
-+
-+static void atmel_mpopfb_disconnect_from_lcdc(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(sinfo->info->device, "Disconnecting MPOP from LCDC:\n");
-+
-+	if (!sinfo->connected_to_lcdc)
-+		/* Already disconnected. */
-+		return;
-+
-+	/* Restore lcdc's old framebuffer pointer and pixel-format. */
-+	lcdc_info->fix.smem_start = sinfo->lcdc_old_smem_start;
-+	lcdc_info->var.bits_per_pixel = sinfo->lcdc_old_bits_per_pixel;
-+
-+	/* Force the LCDC to change the configuration. */
-+	lcdc_info->fbops->fb_set_par(lcdc_info);
-+
-+	sinfo->connected_to_lcdc = 0;
-+
-+	/* We must stop the mpop to reset it. */
-+	atmel_mpopfb_stop(sinfo);
-+}
-+
-+static void atmel_mpopfb_put_overlay_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_overlay_palette *palette)
-+{
-+	int i;
-+
-+	dev_dbg(sinfo->info->device, "Overlay palette = :\n");
-+	for (i = 0; i < 256; i++) {
-+		dev_dbg(sinfo->info->device, "%d -> 0x%x\n", i,
-+			*((int *)&palette->entry[i]));
-+		mpop_writel(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i,
-+			    *((int *)&palette->entry[i]));
-+	}
-+}
-+
-+static void atmel_mpopfb_get_overlay_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_overlay_palette *palette)
-+{
-+	int i;
-+
-+	for (i = 0; i < 256; i++)
-+		*((int *)&palette->entry[i]) =
-+		    mpop_readl(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i);
-+}
-+
-+static void atmel_mpopfb_put_cursor_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_cursor_palette *palette)
-+{
-+	int i;
-+	for (i = 0; i < 4; i++)
-+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i,
-+				*((int *)&palette->entry[i]));
-+}
-+
-+static void atmel_mpopfb_get_cursor_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_cursor_palette *palette)
-+{
-+	int i;
-+	for (i = 0; i < 4; i++)
-+		*((int *)&palette->entry[i])
-+			= mpop_readl(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i);
-+}
-+
-+/**
-+ *      atmel_mpopfb_set_par - Alters the hardware state.
-+ *      @info: frame buffer structure that represents a single frame buffer
-+ *
-+ *	Using the fb_var_screeninfo in fb_info we set the resolution
-+ *	of the this particular framebuffer. This function alters the
-+ *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
-+ *	not alter var in fb_info since we are using that data. This
-+ *	means we depend on the data in var inside fb_info to be
-+ *	supported by the hardware.  atmel_lcdfb_check_var is always called
-+ *	before atmel_lcdfb_set_par to ensure this.  Again if you can't
-+ *	change the resolution you don't need this function.
-+ *
-+ */
-+static int atmel_mpopfb_set_par(struct fb_info *info)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+	struct fb_var_screeninfo *var = &info->var;
-+
-+	u32 yuv_format;
-+	u32 xscale, yscale;
-+
-+	dev_dbg(info->device, "%s:\n", __func__);
-+	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
-+			info->var.xres, info->var.yres,
-+			info->var.xres_virtual, info->var.yres_virtual);
-+	dev_dbg(info->device, "  * offset: (%u,%u)\n",
-+			info->var.xoffset, info->var.yoffset);
-+	dev_dbg(info->device, "  * bpp: %u\n", info->var.bits_per_pixel);
-+
-+	/* Setup the output picture size. We must use the size of the lcdcfb. */
-+	dev_dbg(info->device, "  * output frame resolution: %ux%u \n",
-+			lcdc_info->var.xres, lcdc_info->var.yres);
-+	mpop_writel(sinfo, ATMEL_MPOP_DISP_MAX_COORD,
-+			((lcdc_info->var.xres - 1) << ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET)
-+			| ((lcdc_info->var.yres - 1) << ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET));
-+
-+	/* Setup base picture. */
-+
-+	switch (var->bits_per_pixel) {
-+	default:
-+	case 12:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_420;
-+		break;
-+	case 16:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_422;
-+		break;
-+	case 24:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_444;
-+		break;
-+	}
-+
-+	xscale = ATMEL_MPOP_CALC_SCALE(info->var.xres, sinfo->baseimg_info.xsize);
-+	yscale = ATMEL_MPOP_CALC_SCALE(info->var.yres, sinfo->baseimg_info.ysize);
-+
-+	dev_dbg(info->device, "  * baseimg output size = %ux%u \n",
-+			sinfo->baseimg_info.xsize, sinfo->baseimg_info.ysize);
-+	dev_dbg(info->device, "  * resize scales = %ux%u \n", xscale, yscale);
-+	dev_dbg(info->device, "  * yuv format = %u \n", yuv_format);
-+	mpop_writel(sinfo, ATMEL_MPOP_YCR,
-+			yuv_format << ATMEL_MPOP_YCR_YUVFORMAT_OFFSET
-+			| xscale << ATMEL_MPOP_YCR_XRESIZE_OFFSET
-+			| yscale << ATMEL_MPOP_YCR_YRESIZE_OFFSET);
-+
-+	/* Setup conversion coefficients. */
-+	mpop_writel(sinfo, ATMEL_MPOP_R2R1,
-+			((sinfo->rgbconv_coeffs.r1 << ATMEL_MPOP_R1_OFFSET) & ATMEL_MPOP_R1_MASK)
-+			| ((sinfo->rgbconv_coeffs.r2 << ATMEL_MPOP_R2_OFFSET) & ATMEL_MPOP_R2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_R4R3,
-+			((sinfo->rgbconv_coeffs.r3 << ATMEL_MPOP_R3_OFFSET) & ATMEL_MPOP_R3_MASK)
-+			| ((sinfo->rgbconv_coeffs.r4 << ATMEL_MPOP_R4_OFFSET) & ATMEL_MPOP_R4_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_G2G1,
-+			((sinfo->rgbconv_coeffs.g1 << ATMEL_MPOP_G1_OFFSET) & ATMEL_MPOP_G1_MASK)
-+			| ((sinfo->rgbconv_coeffs.g2 << ATMEL_MPOP_G2_OFFSET) & ATMEL_MPOP_G2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_G4G3,
-+			((sinfo->rgbconv_coeffs.g3 << ATMEL_MPOP_G3_OFFSET) & ATMEL_MPOP_G3_MASK)
-+			| ((sinfo->rgbconv_coeffs.g4 << ATMEL_MPOP_G4_OFFSET) & ATMEL_MPOP_G4_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_B2B1,
-+			((sinfo->rgbconv_coeffs.b1 << ATMEL_MPOP_B1_OFFSET) & ATMEL_MPOP_B1_MASK)
-+			| ((sinfo->rgbconv_coeffs.b2 << ATMEL_MPOP_B2_OFFSET) & ATMEL_MPOP_B2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_B4B3,
-+			((sinfo->rgbconv_coeffs.b3 << ATMEL_MPOP_B3_OFFSET) & ATMEL_MPOP_B3_MASK)
-+			| ((sinfo->rgbconv_coeffs.b4 << ATMEL_MPOP_B4_OFFSET) & ATMEL_MPOP_B4_MASK));
-+
-+	info->fix.line_length = info->var.xres_virtual;
-+	info->fix.visual = FB_VISUAL_TRUECOLOR;
-+
-+	/* Setup stride. We can flip the image by negating the 
-+	   stride, but we must then set the SAR registers to point
-+	   to the last line in the image. */
-+	if (sinfo->baseimg_info.flip) {
-+		dev_dbg(info->device, "  * flip \n");
-+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, -info->var.xres_virtual);
-+	} else
-+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, info->var.xres_virtual);
-+
-+	/* Setup input image size. */
-+	mpop_writel(sinfo, ATMEL_MPOP_YUV_MAX_COORD,
-+			((info->var.xres - 1) << ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET)
-+			| ((info->var.yres - 1) << ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET));
-+
-+	/* Setup size and position of output base image after scaling. */
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_SIZE,
-+			sinfo->baseimg_info.xsize << ATMEL_MPOP_RGB_SIZE_X_OFFSET
-+			| sinfo->baseimg_info.ysize << ATMEL_MPOP_RGB_SIZE_Y_OFFSET);
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_POS,
-+			(sinfo->baseimg_info.xpos << ATMEL_MPOP_RGB_POS_X_OFFSET)
-+			| (sinfo->baseimg_info.ypos << ATMEL_MPOP_RGB_POS_Y_OFFSET));
-+
-+	dev_dbg(info->device, "  * baseimg pos: (%u,%u) \n",
-+			sinfo->baseimg_info.xpos, sinfo->baseimg_info.ypos);
-+
-+	/* Setup Word Transfer Count. */
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_WTC,
-+			DIV_ROUND_UP(info->var.xres * info->var.yres
-+				* var->bits_per_pixel, 32));
-+
-+	/* Set overlay parameters. */
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize << ATMEL_MPOP_O1_SIZE_O1_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize << ATMEL_MPOP_O1_SIZE_O1_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
-+			 * sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize, 4));
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize << ATMEL_MPOP_O2_SIZE_O2_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize << ATMEL_MPOP_O2_SIZE_O2_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize *
-+				sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize, 4));
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize
-+				* sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize, 16));
-+
-+	/* Enable base overlay + any other enabled overlays. */
-+	mpop_writel(sinfo, ATMEL_MPOP_OCR, ATMEL_MPOP_OCR_RGBEN_MASK);
-+
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_CURSOREN_MASK);
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_O1EN_MASK);
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_O2EN_MASK);
-+
-+	/* Set background to black. */
-+	mpop_writel(sinfo, ATMEL_MPOP_BGCOLOR, 0);
-+
-+	/* Setup source address registers */
-+	atmel_mpopfb_update_sar(info, &info->var);
-+
-+	dev_dbg(info->device, "  * DONE\n");
-+
-+	return 0;
-+}
-+
-+static int atmel_mpopfb_pan_display(struct fb_var_screeninfo *var,
-+		struct fb_info *info)
-+{
-+	dev_dbg(info->device, "%s\n", __func__);
-+
-+	/* Change source address registers to reflect the panning. */
-+	atmel_mpopfb_update_sar(info, var);
-+
-+	return 0;
-+}
-+
-+static void atmel_mpopfb_put_overlay_info(struct fb_info *info,
-+		struct atmel_mpopfb_overlay_info overlay_info)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+
-+	/* We can update the position now since it is double buffered. */
-+	switch (overlay_info.overlay) {
-+	case ATMEL_MPOPFB_OVERLAY1:
-+		mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
-+		break;
-+	case ATMEL_MPOPFB_OVERLAY2:
-+		mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
-+		break;
-+	case ATMEL_MPOPFB_CURSOR:
-+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
-+		break;
-+	default:
-+		dev_warn(info->device, "Unknown overlay type: %d\n",
-+				overlay_info.overlay);
-+		return;
-+	}
-+
-+	/* Copy the overlay info to the mpopfb info structure. */
-+	sinfo->overlay_info[overlay_info.overlay] = overlay_info;
-+}
-+
-+static int atmel_mpopfb_ioctl(struct fb_info *info,
-+		unsigned int cmd, unsigned long arg)
-+{
-+	void __user *argp = (void __user *)arg;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct atmel_mpopfb_overlay_info overlay_info;
-+
-+	switch (cmd) {
-+	case ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE:{
-+			struct atmel_mpopfb_overlay_palette palette;
-+			if (copy_from_user(&palette, argp, sizeof(palette)))
-+				return -EFAULT;
-+			atmel_mpopfb_put_overlay_palette(sinfo, &palette);
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE:{
-+			struct atmel_mpopfb_overlay_palette palette;
-+			atmel_mpopfb_get_overlay_palette(sinfo, &palette);
-+			if (copy_to_user(argp, &palette, sizeof(palette)))
-+				return -EFAULT;
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE:{
-+			struct atmel_mpopfb_cursor_palette palette;
-+			if (copy_from_user(&palette, argp, sizeof(palette)))
-+				return -EFAULT;
-+			atmel_mpopfb_put_cursor_palette(sinfo, &palette);
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOGET_CURSOR_PALETTE:{
-+			struct atmel_mpopfb_cursor_palette palette;
-+			atmel_mpopfb_get_cursor_palette(sinfo, &palette);
-+			if (copy_to_user(argp, &palette, sizeof(palette)))
-+				return -EFAULT;
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOPUT_OVERLAY_INFO:
-+		if (copy_from_user(&overlay_info, argp, sizeof(overlay_info)))
-+			return -EFAULT;
-+		atmel_mpopfb_put_overlay_info(info, overlay_info);
-+		return 0;
-+	case ATMEL_MPOP_FBIOPUT_BASEIMG_INFO:
-+		if (copy_from_user(&sinfo->baseimg_info, argp,
-+					sizeof(sinfo->baseimg_info)))
-+			return -EFAULT;
-+
-+		/* Check that new baseimg parameters are sane. */
-+		if (atmel_mpopfb_check_var(&info->var, info))
-+			return -EFAULT;
-+
-+		/* Update hardware configuration. */
-+		atmel_mpopfb_set_par(info);
-+		return 0;
-+	case ATMEL_MPOP_FBIOGET_BASEIMG_INFO:
-+		return copy_to_user(argp, &sinfo->baseimg_info,
-+				sizeof(sinfo->baseimg_info)) ? -EFAULT : 0;
-+	case ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS:
-+		if (copy_from_user(&sinfo->rgbconv_coeffs, argp,
-+					sizeof(sinfo->rgbconv_coeffs)))
-+			return -EFAULT;
-+
-+		/* Update hardware configuration. */
-+		if (atmel_mpopfb_set_par(info))
-+			return -EFAULT;
-+
-+		return 0;
-+	case ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS:
-+		return copy_to_user(argp, &sinfo->rgbconv_coeffs,
-+				sizeof(sinfo->rgbconv_coeffs)) ? -EFAULT : 0;
-+	case ATMEL_MPOP_FBIO_CONNECT_TO_LCDC:
-+		atmel_mpopfb_connect_to_lcdc(sinfo);
-+		return 0;
-+	case ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC:
-+		atmel_mpopfb_disconnect_from_lcdc(sinfo);
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	/* Force MPOP to be updated with any new parameters. */
-+	atmel_mpopfb_set_par(info);
-+}
-+
-+static int atmel_mpopfb_setcolreg(unsigned int regno, unsigned int red,
-+				  unsigned int green, unsigned int blue,
-+				  unsigned int transp, struct fb_info *info)
-+{
-+	return 0;
-+}
-+
-+static struct fb_ops atmel_mpopfb_ops = {
-+	.owner		= THIS_MODULE,
-+	.fb_check_var	= atmel_mpopfb_check_var,
-+	.fb_set_par	= atmel_mpopfb_set_par,
-+	.fb_setcolreg	= atmel_mpopfb_setcolreg,
-+	.fb_pan_display	= atmel_mpopfb_pan_display,
-+	.fb_imageblit	= cfb_imageblit,
-+	.fb_ioctl	= atmel_mpopfb_ioctl,
-+	.fb_fillrect	= cfb_fillrect,
-+	.fb_copyarea	= cfb_copyarea,
-+};
-+
-+static irqreturn_t atmel_mpopfb_interrupt(int irq, void *dev_id)
-+{
-+	struct fb_info *info = dev_id;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	u32 status;
-+
-+	/* Check which interrupt we have. */
-+	status = mpop_readl(sinfo, ATMEL_MPOP_INTSTATUS);
-+
-+	/* Clear interrupts. */
-+	mpop_writel(sinfo, ATMEL_MPOP_INTCLEAR, status);
-+
-+	if (status & ATMEL_MPOP_EOP) {
-+		/* End Of Picture. Start new picture. */
-+		mpop_writel(sinfo, ATMEL_MPOP_CR,
-+				ATMEL_MPOP_CR_START_MASK
-+				| mpop_readl(sinfo, ATMEL_MPOP_CR));
-+	} else if (status & ATMEL_MPOP_OUT) {
-+		dev_err(info->dev,
-+			"MPOP Output DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_OUT_BEAR));
-+	} else if (status & ATMEL_MPOP_YUV) {
-+		dev_err(info->dev,
-+			"MPOP YUV Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_YUV_BEAR));
-+	} else if (status & ATMEL_MPOP_OVERLAY) {
-+		dev_err(info->dev,
-+			"MPOP Overlay Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_OVERLAY_BEAR));
-+	}
-+
-+	dev_dbg(info->device, "%s\n", __func__);
-+	dev_dbg(info->device, "  * status: 0x%x \n", status);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __init atmel_mpopfb_init_fbinfo(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+	int ret = 0;
-+
-+	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
-+
-+	dev_info(info->device,
-+			"%luKiB frame buffer at %08lx (mapped at %p)\n",
-+			(unsigned long)info->fix.smem_len / 1024,
-+			(unsigned long)info->fix.smem_start, info->screen_base);
-+
-+	return ret;
-+}
-+
-+static void atmel_mpopfb_start_clock(struct atmel_mpopfb_info *sinfo)
-+{
-+	clk_enable(sinfo->mpop_hclk);
-+	clk_enable(sinfo->mpop_pclk);
-+}
-+
-+static void atmel_mpopfb_stop_clock(struct atmel_mpopfb_info *sinfo)
-+{
-+	clk_disable(sinfo->mpop_hclk);
-+	clk_disable(sinfo->mpop_pclk);
-+}
-+
-+static int __init atmel_mpopfb_probe(struct platform_device *pdev)
-+{
-+	struct device			*dev = &pdev->dev;
-+	struct fb_info			*info;
-+	struct fb_info			*lcdc_info;
-+	struct atmel_mpopfb_info	*sinfo;
-+	struct atmel_mpopfb_info	*pdata_sinfo;
-+	struct resource			*regs = NULL;
-+	struct resource			*slave = NULL;
-+	struct resource			*map = NULL;
-+	int				ret;
-+
-+	dev_dbg(dev, "%s BEGIN\n", __func__);
-+
-+	ret = -ENOMEM;
-+	info = framebuffer_alloc(sizeof(struct atmel_mpopfb_info), dev);
-+	if (!info) {
-+		dev_err(dev, "cannot allocate memory\n");
-+		goto out;
-+	}
-+
-+	sinfo = info->par;
-+
-+	if (dev->platform_data) {
-+		pdata_sinfo = dev->platform_data;
-+		sinfo->lcdc_pdev = pdata_sinfo->lcdc_pdev;
-+		if (!sinfo->lcdc_pdev) {
-+			dev_err(dev, "cannot get hold of lcdcfb device\n");
-+			goto free_info;
-+		}
-+	} else {
-+		dev_err(dev, "cannot get default configuration\n");
-+		goto free_info;
-+	}
-+
-+	sinfo->info = info;
-+	sinfo->pdev = pdev;
-+	sinfo->running = 0;
-+	sinfo->connected_to_lcdc = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled = 0;
-+
-+	/* Setup default info */
-+
-+	/* Set fb_var_screeninfo equal to that of the lcdcfb driver. */
-+	lcdc_info = (struct fb_info *)platform_get_drvdata(sinfo->lcdc_pdev);
-+	memcpy(&info->var, &lcdc_info->var, sizeof(struct fb_var_screeninfo));
-+
-+	/* Set default position of the image on the screen to (0,0) and
-+	   no scaling */
-+	sinfo->baseimg_info.xpos = 0;
-+	sinfo->baseimg_info.ypos = 0;
-+	sinfo->baseimg_info.xsize = info->var.xres;
-+	sinfo->baseimg_info.ysize = info->var.yres;
-+
-+	/* Use YCbCr --> RGB converion per default. */
-+	memcpy(&sinfo->rgbconv_coeffs, &atmel_mpop_ycrcb2rgb_coeffs,
-+	       sizeof(struct atmel_mpopfb_rgbconv_coeffs));
-+
-+	strcpy(info->fix.id, sinfo->pdev->name);
-+	info->flags = ATMEL_MPOPFB_FBINFO_DEFAULT;
-+	info->fbops = &atmel_mpopfb_ops;
-+
-+	//memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
-+	info->fix = atmel_mpopfb_fix;
-+
-+	/* Enable MPOP Clocks */
-+	sinfo->mpop_hclk = clk_get(dev, "hclk");
-+	sinfo->mpop_pclk = clk_get(dev, "pclk");
-+	if (IS_ERR(sinfo->mpop_hclk)) {
-+		ret = PTR_ERR(sinfo->mpop_hclk);
-+		goto put_bus_clk;
-+	}
-+	if (IS_ERR(sinfo->mpop_pclk)) {
-+		ret = PTR_ERR(sinfo->mpop_pclk);
-+		goto stop_clk;
-+	}
-+	atmel_mpopfb_start_clock(sinfo);
-+
-+	//ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
-+	//                   info->monspecs.modedb_len, info->monspecs.modedb,
-+	//                   sinfo->default_bpp);
-+	//if (!ret) {
-+	//      dev_err(dev, "no suitable video mode found\n");
-+	//      goto stop_clk;
-+	//}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(dev, "resources unusable\n");
-+		ret = -ENXIO;
-+		goto stop_clk;
-+	}
-+
-+	slave = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (!slave) {
-+		dev_err(dev, "slave interface memory resource unusable\n");
-+		ret = -ENXIO;
-+		goto stop_clk;
-+	}
-+	sinfo->slave_base = (void *)slave->start;
-+
-+	sinfo->irq_base = platform_get_irq(pdev, 0);
-+	if (sinfo->irq_base < 0) {
-+		dev_err(dev, "unable to get irq\n");
-+		ret = sinfo->irq_base;
-+		goto stop_clk;
-+	}
-+
-+	/* Initialize video memory */
-+	map = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-+	if (map) {
-+		/* use a pre-allocated memory buffer */
-+		info->fix.smem_start = map->start;
-+		info->fix.smem_len = map->end - map->start + 1;
-+		if (!request_mem_region(info->fix.smem_start,
-+					info->fix.smem_len, pdev->name)) {
-+			//ret = -EBUSY;
-+			//goto stop_clk;
-+			/* Probably in use by LCD controller. */
-+			info->screen_base = lcdc_info->screen_base;
-+		} else {
-+			info->screen_base =
-+			    ioremap(info->fix.smem_start, info->fix.smem_len);
-+			if (!info->screen_base)
-+				goto release_intmem;
-+		}
-+	} else {
-+		/* alocate memory buffer */
-+		ret = atmel_mpopfb_alloc_video_memory(sinfo);
-+		if (ret < 0) {
-+			dev_err(dev, "cannot allocate mpop framebuffer: %d\n",
-+				ret);
-+			goto stop_clk;
-+		}
-+	}
-+
-+	/* MPOP registers */
-+	info->fix.mmio_start = regs->start;
-+	info->fix.mmio_len = regs->end - regs->start + 1;
-+
-+	if (!request_mem_region(info->fix.mmio_start,
-+				info->fix.mmio_len, pdev->name)) {
-+		ret = -EBUSY;
-+		goto free_fb;
-+	}
-+
-+	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
-+	if (!sinfo->mmio) {
-+		dev_err(dev, "cannot map MPOP registers\n");
-+		goto release_mem;
-+	}
-+
-+	/* MPOP slave interface */
-+	if (!request_mem_region(slave->start,
-+				slave->end - slave->start + 1, pdev->name)) {
-+		dev_err(dev,
-+			"error requesting memory region for MPOP slave interface\n");
-+		ret = -EBUSY;
-+		goto unmap_mmio;
-+	}
-+
-+	/* interrupt */
-+	ret =
-+	    request_irq(sinfo->irq_base, atmel_mpopfb_interrupt, 0, pdev->name,
-+			info);
-+	if (ret) {
-+		dev_err(dev, "request_irq failed: %d\n", ret);
-+		goto release_mem_slave;
-+	}
-+
-+	ret = atmel_mpopfb_init_fbinfo(sinfo);
-+	if (ret < 0) {
-+		dev_err(dev, "init fbinfo failed: %d\n", ret);
-+		goto unregister_irqs;
-+	}
-+
-+	/*
-+	 * This makes sure that our colour bitfield
-+	 * descriptors are correctly initialised.
-+	 */
-+	atmel_mpopfb_check_var(&info->var, info);
-+
-+	ret = fb_set_var(info, &info->var);
-+	if (ret) {
-+		dev_warn(dev, "unable to set display parameters\n");
-+		goto free_cmap;
-+	}
-+
-+	dev_set_drvdata(dev, info);
-+
-+	/*
-+	 * Tell the world that we're ready to go
-+	 */
-+	ret = register_framebuffer(info);
-+	if (ret < 0) {
-+		dev_err(dev, "failed to register framebuffer device: %d\n",
-+			ret);
-+		goto free_cmap;
-+	}
-+
-+	dev_info(dev, "fb%d: Atmel MPOP at 0x%08lx (mapped at %p), irq %lu\n",
-+		 info->node, info->fix.mmio_start, sinfo->mmio,
-+		 sinfo->irq_base);
-+
-+	return 0;
-+
-+free_cmap:
-+	fb_dealloc_cmap(&info->cmap);
-+unregister_irqs:
-+	free_irq(sinfo->irq_base, info);
-+release_mem_slave:
-+	release_mem_region(slave->start, slave->end - slave->start + 1);
-+unmap_mmio:
-+	iounmap(sinfo->mmio);
-+release_mem:
-+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-+free_fb:
-+	if (map)
-+		iounmap(info->screen_base);
-+	else
-+		atmel_mpopfb_free_video_memory(sinfo);
-+
-+release_intmem:
-+	if (map)
-+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
-+stop_clk:
-+	atmel_mpopfb_stop_clock(sinfo);
-+	clk_put(sinfo->mpop_hclk);
-+put_bus_clk:
-+	if (sinfo->mpop_pclk)
-+		clk_put(sinfo->mpop_pclk);
-+free_info:
-+	framebuffer_release(info);
-+out:
-+	dev_dbg(dev, "%s FAILED\n", __func__);
-+	return ret;
-+}
-+
-+static int __exit atmel_mpopfb_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct fb_info *info = dev_get_drvdata(dev);
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+
-+	if (!sinfo)
-+		return 0;
-+
-+	unregister_framebuffer(info);
-+	atmel_mpopfb_stop_clock(sinfo);
-+	clk_put(sinfo->mpop_hclk);
-+	clk_put(sinfo->mpop_pclk);
-+	fb_dealloc_cmap(&info->cmap);
-+	free_irq(sinfo->irq_base, info);
-+	iounmap(sinfo->mmio);
-+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-+	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
-+		iounmap(info->screen_base);
-+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
-+	} else {
-+		atmel_mpopfb_free_video_memory(sinfo);
-+	}
-+
-+	dev_set_drvdata(dev, NULL);
-+	framebuffer_release(info);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver atmel_mpopfb_driver = {
-+	.remove = __exit_p(atmel_mpopfb_remove),
-+	.driver.name = "atmel_mpopfb",
-+	.driver.owner = THIS_MODULE,
-+};
-+
-+static int __init atmel_mpopfb_init(void)
-+{
-+	return platform_driver_probe(&atmel_mpopfb_driver, atmel_mpopfb_probe);
-+}
-+
-+static void __exit atmel_mpopfb_exit(void)
-+{
-+	platform_driver_unregister(&atmel_mpopfb_driver);
-+}
-+
-+module_init(atmel_mpopfb_init);
-+module_exit(atmel_mpopfb_exit);
-+
-+MODULE_DESCRIPTION("AT32 MPOP framebuffer driver");
-+MODULE_AUTHOR("Ronny Pedersen <rpedersen@atmel.com>");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
-index c510367..55a3a34 100644
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -221,12 +221,12 @@ config DAVINCI_WATCHDOG
- 
- # AVR32 Architecture
- 
--config AT32AP700X_WDT
--	tristate "AT32AP700x watchdog"
--	depends on CPU_AT32AP700X
-+config AT32_WDT
-+	tristate "AVR32 On-Chip Watchdog Timer"
-+	depends on AVR32
- 	help
--	  Watchdog timer embedded into AT32AP700x devices. This will reboot
--	  your system when the timeout is reached.
-+	  Watchdog timer embedded into AT32AP700x and similar devices.
-+	  This will reboot your system when the timeout is reached.
- 
- # BLACKFIN Architecture
- 
-diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
-index e0ef123..7db92cd 100644
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -43,7 +43,7 @@ obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
- # ARM26 Architecture
- 
- # AVR32 Architecture
--obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
-+obj-$(CONFIG_AT32_WDT) += at32_wdt.o
- 
- # BLACKFIN Architecture
- obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
-diff --git a/drivers/watchdog/at32_wdt.c b/drivers/watchdog/at32_wdt.c
-new file mode 100644
-index 0000000..bbdb997
---- /dev/null
-+++ b/drivers/watchdog/at32_wdt.c
-@@ -0,0 +1,620 @@
-+/*
-+ * Watchdog driver for Atmel AVR32 devices
-+ *
-+ * Copyright (C) 2005-2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ *
-+ * AT32AP700x Errata: WDT Clear is blocked after WDT Reset
-+ *
-+ * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
-+ * register, preventing the program to clear the next Watchdog Timer Reset.
-+ *
-+ * If you still want to use the WDT after a WDT reset a small code can be
-+ * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
-+ * and use a GPIO pin to reset the system. This method requires that one of the
-+ * GPIO pins are available and connected externally to the RESET_N pin. After
-+ * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
-+ * the pin tristated with pullup.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/miscdevice.h>
-+#include <linux/fs.h>
-+#include <linux/platform_device.h>
-+#include <linux/watchdog.h>
-+#include <linux/uaccess.h>
-+#include <linux/io.h>
-+#include <linux/log2.h>
-+#include <linux/spinlock.h>
-+
-+#include <mach/cpu.h>
-+#include <mach/pm.h>
-+
-+/*
-+ * AT32AP700x uses a 16-bit prescaler. This limits the timeout range
-+ * somewhat. Later chips use a 32-bit prescaler.
-+ */
-+#define TIMEOUT_MIN		1
-+#ifdef CONFIG_CPU_AT32AP700X
-+# define TIMEOUT_MAX		2
-+# define TIMEOUT_DEFAULT	TIMEOUT_MAX
-+#else
-+# define TIMEOUT_MAX		131072
-+# define TIMEOUT_DEFAULT	64
-+#endif
-+
-+/* module parameters */
-+static int timeout =  TIMEOUT_DEFAULT;
-+module_param(timeout, int, 0);
-+MODULE_PARM_DESC(timeout,
-+		"Timeout value. Any power of two between 1 and "
-+		__MODULE_STRING(TIMEOUT_MAX) " seconds. (default="
-+		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
-+
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
-+		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-+
-+/* Watchdog registers and write/read macro */
-+#define WDT_CTRL		0x00
-+#define WDT_CTRL_EN		   0
-+#define WDT_CTRL_PSEL		   8
-+#define WDT_CTRL_CEN		  16
-+#define WDT_CTRL_CSEL		  17
-+#define WDT_CTRL_KEY		  24
-+
-+#define WDT_CLR			0x04
-+
-+#define WDT_BIT(name)		(1 << WDT_##name)
-+#define WDT_BF(name, value)	((value) << WDT_##name)
-+
-+#define wdt_readl(dev, reg)				\
-+	__raw_readl((dev)->regs + WDT_##reg)
-+#define wdt_writel(dev, reg, value)			\
-+	__raw_writel((value), (dev)->regs + WDT_##reg)
-+
-+struct wdt_at32 {
-+	void __iomem		*regs;
-+	struct clk		*pclk;
-+	struct clk		*src_clk;
-+	spinlock_t		io_lock;
-+	int			timeout;
-+	int			boot_status;
-+	unsigned long		users;
-+	struct miscdevice	miscdev;
-+};
-+
-+static struct wdt_at32 *wdt;
-+static char expect_release;
-+
-+static inline void wdt_clk_enable(struct wdt_at32 *w)
-+{
-+	if (!cpu_is_at32ap7000())
-+		clk_enable(w->pclk);
-+}
-+
-+static inline void wdt_clk_disable(struct wdt_at32 *w)
-+{
-+	if (!cpu_is_at32ap7000())
-+		clk_disable(w->pclk);
-+}
-+
-+static inline int at32_wdt_version(void)
-+{
-+	if (cpu_is_at32ap7000())
-+		return 1;
-+	if (cpu_is_at32ap7200())
-+		return 3;
-+
-+	BUG();
-+}
-+
-+static unsigned long at32_wdt_calc_psel(int timeout)
-+{
-+	if (at32_wdt_version() == 1)
-+		/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
-+		return (timeout > 1) ? 0xf : 0xe;
-+
-+	return order_base_2(timeout) + 14;
-+}
-+
-+/*
-+ * Disable the watchdog.
-+ */
-+static inline void at32_wdt_stop(void)
-+{
-+	unsigned long ctrl;
-+	unsigned long ctrl_mask = 0;
-+
-+	switch (at32_wdt_version()) {
-+	case 3:
-+		ctrl_mask |= (1 << WDT_CTRL_CEN) | (1 << WDT_CTRL_CSEL);
-+		/* fall through */
-+	case 2:
-+		ctrl_mask |= 0x1f << WDT_CTRL_PSEL;
-+		break;
-+	case 1:
-+		ctrl_mask |= 0x0f << WDT_CTRL_PSEL;
-+		break;
-+	}
-+
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	ctrl = wdt_readl(wdt, CTRL);
-+	ctrl &= ctrl_mask;
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Enable and reset the watchdog.
-+ */
-+static inline void at32_wdt_start(void)
-+{
-+	unsigned long psel;
-+	unsigned long ctrl;
-+
-+	psel = at32_wdt_calc_psel(wdt->timeout);
-+	ctrl = WDT_BIT(CTRL_EN) | WDT_BF(CTRL_PSEL, psel);
-+
-+	if (at32_wdt_version() >= 3)
-+		ctrl |= wdt_readl(wdt, CTRL)
-+			& (WDT_BIT(CTRL_CSEL) | WDT_BIT(CTRL_CEN));
-+
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Pat the watchdog timer.
-+ */
-+static inline void at32_wdt_pat(void)
-+{
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	wdt_writel(wdt, CLR, 0x42);
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Watchdog device is opened, and watchdog starts running.
-+ */
-+static int at32_wdt_open(struct inode *inode, struct file *file)
-+{
-+	if (test_and_set_bit(1, &wdt->users))
-+		return -EBUSY;
-+
-+	at32_wdt_start();
-+	return nonseekable_open(inode, file);
-+}
-+
-+/*
-+ * Close the watchdog device.
-+ */
-+static int at32_wdt_close(struct inode *inode, struct file *file)
-+{
-+	if (expect_release == 42) {
-+		at32_wdt_stop();
-+	} else {
-+		dev_dbg(wdt->miscdev.parent,
-+			"unexpected close, not stopping watchdog!\n");
-+		at32_wdt_pat();
-+	}
-+	clear_bit(1, &wdt->users);
-+	expect_release = 0;
-+	return 0;
-+}
-+
-+/*
-+ * Change the watchdog time interval.
-+ */
-+static int at32_wdt_settimeout(int time)
-+{
-+	/*
-+	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max
-+	 * prescaler is 2 ^ 16 (or 2 ^ 32) allowing up to TIMEOUT_MAX
-+	 * seconds timeout.
-+	 */
-+	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX)
-+			|| !is_power_of_2(time))
-+		return -EINVAL;
-+
-+	/*
-+	 * Set new watchdog time. It will be used when at32_wdt_start() is
-+	 * called.
-+	 */
-+	wdt->timeout = time;
-+	return 0;
-+}
-+
-+/*
-+ * Get the watchdog status.
-+ */
-+static int at32_wdt_get_status(void)
-+{
-+	int rcause;
-+	int status = 0;
-+
-+	rcause = at32_get_reset_cause();
-+
-+	switch (rcause) {
-+	case AT32_RCAUSE_BOD:
-+		status = WDIOF_POWERUNDER;
-+		break;
-+	case AT32_RCAUSE_EXT:
-+		status = WDIOF_EXTERN1;
-+		break;
-+	case AT32_RCAUSE_JTAG:
-+	case AT32_RCAUSE_JTAGHARD:
-+	case AT32_RCAUSE_OCDRST:
-+		status = WDIOF_EXTERN2;
-+		break;
-+	case AT32_RCAUSE_WDT:
-+		status = WDIOF_CARDRESET;
-+		break;
-+	case AT32_RCAUSE_POR:
-+	case AT32_RCAUSE_NTAE:
-+	case AT32_RCAUSE_SLEEP:
-+	case AT32_RCAUSE_CPUERR:
-+	default:
-+		break;
-+	}
-+
-+	return status;
-+}
-+
-+static struct watchdog_info at32_wdt_info = {
-+	.identity	= "at32 watchdog",
-+	.options	= WDIOF_SETTIMEOUT |
-+			  WDIOF_KEEPALIVEPING |
-+			  WDIOF_MAGICCLOSE,
-+};
-+
-+/*
-+ * Handle commands from user-space.
-+ */
-+static long at32_wdt_ioctl(struct file *file,
-+				unsigned int cmd, unsigned long arg)
-+{
-+	int ret = -ENOTTY;
-+	int time;
-+	void __user *argp = (void __user *)arg;
-+	int __user *p = argp;
-+
-+	switch (cmd) {
-+	case WDIOC_GETSUPPORT:
-+		ret = copy_to_user(argp, &at32_wdt_info,
-+				sizeof(at32_wdt_info)) ? -EFAULT : 0;
-+		break;
-+	case WDIOC_GETSTATUS:
-+		ret = put_user(0, p);
-+		break;
-+	case WDIOC_GETBOOTSTATUS:
-+		ret = put_user(wdt->boot_status, p);
-+		break;
-+	case WDIOC_SETOPTIONS:
-+		ret = get_user(time, p);
-+		if (ret)
-+			break;
-+		if (time & WDIOS_DISABLECARD)
-+			at32_wdt_stop();
-+		if (time & WDIOS_ENABLECARD)
-+			at32_wdt_start();
-+		ret = 0;
-+		break;
-+	case WDIOC_KEEPALIVE:
-+		at32_wdt_pat();
-+		ret = 0;
-+		break;
-+	case WDIOC_SETTIMEOUT:
-+		ret = get_user(time, p);
-+		if (ret)
-+			break;
-+		ret = at32_wdt_settimeout(time);
-+		if (ret)
-+			break;
-+		/* Enable new time value */
-+		at32_wdt_start();
-+		/* fall through */
-+	case WDIOC_GETTIMEOUT:
-+		ret = put_user(wdt->timeout, p);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static ssize_t at32_wdt_write(struct file *file, const char __user *data,
-+				size_t len, loff_t *ppos)
-+{
-+	/* See if we got the magic character 'V' and reload the timer */
-+	if (len) {
-+		if (!nowayout) {
-+			size_t i;
-+
-+			/*
-+			 * note: just in case someone wrote the magic
-+			 * character five months ago...
-+			 */
-+			expect_release = 0;
-+
-+			/*
-+			 * scan to see whether or not we got the magic
-+			 * character
-+			 */
-+			for (i = 0; i != len; i++) {
-+				char c;
-+				if (get_user(c, data + i))
-+					return -EFAULT;
-+				if (c == 'V')
-+					expect_release = 42;
-+			}
-+		}
-+		/* someone wrote to us, we should pat the watchdog */
-+		at32_wdt_pat();
-+	}
-+	return len;
-+}
-+
-+static const struct file_operations at32_wdt_fops = {
-+	.owner		= THIS_MODULE,
-+	.llseek		= no_llseek,
-+	.unlocked_ioctl	= at32_wdt_ioctl,
-+	.open		= at32_wdt_open,
-+	.release	= at32_wdt_close,
-+	.write		= at32_wdt_write,
-+};
-+
-+static int __init at32_wdt_enable_source_clock(struct platform_device *pdev)
-+{
-+	struct clk	*clk;
-+	unsigned int	csel;
-+	u32		ctrl;
-+
-+	/* Only v3+ have selectable source clock */
-+	if (at32_wdt_version() < 3)
-+		return 0;
-+
-+	csel = 1;
-+
-+	/*
-+	 * Prefer the much more accurate crystal oscillator in favor
-+	 * of the RC oscillator.
-+	 */
-+	clk = clk_get(NULL, "osc32");
-+	if (IS_ERR(clk)) {
-+		csel = 0;
-+		clk = clk_get(NULL, "rcosc");
-+	}
-+	if (IS_ERR(clk)) {
-+		dev_dbg(&pdev->dev, "No source clock\n");
-+		return -ENXIO;
-+	}
-+
-+	clk_enable(clk);
-+
-+	dev_info(&pdev->dev, "Using 32 kHz %s oscillator\n",
-+			csel ? "crystal" : "RC");
-+
-+	wdt_clk_enable(wdt);
-+	ctrl = (csel << WDT_CTRL_CSEL) | (1 << WDT_CTRL_CEN);
-+
-+	/*
-+	 * Make sure the WDT is disabled, and disable any clocks that
-+	 * may have been selected earlier.
-+	 */
-+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
-+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
-+
-+	/* Wait for the clock to become properly deselected */
-+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
-+		cpu_relax();
-+
-+	/* Select the new clock */
-+	wdt_writel(wdt, CTRL, ctrl | (0x55 << WDT_CTRL_KEY));
-+	wdt_writel(wdt, CTRL, ctrl | (0xaa << WDT_CTRL_KEY));
-+
-+	/* Wait for the new clock to become usable */
-+	while (!(wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN)))
-+		cpu_relax();
-+
-+	wdt_clk_disable(wdt);
-+	return 0;
-+}
-+
-+static void at32_wdt_disable_source_clock(void)
-+{
-+	wdt_clk_enable(wdt);
-+
-+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
-+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
-+
-+	/* Wait for the clock to become properly deselected */
-+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
-+		cpu_relax();
-+
-+	wdt_clk_disable(wdt);
-+}
-+
-+static int __init at32_wdt_probe(struct platform_device *pdev)
-+{
-+	struct resource	*regs;
-+	int ret;
-+
-+	if (wdt) {
-+		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
-+		return -EBUSY;
-+	}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "missing mmio resource\n");
-+		return -ENXIO;
-+	}
-+
-+	wdt = kzalloc(sizeof(struct wdt_at32), GFP_KERNEL);
-+	if (!wdt) {
-+		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
-+		return -ENOMEM;
-+	}
-+
-+	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+	if (!wdt->regs) {
-+		ret = -ENOMEM;
-+		dev_dbg(&pdev->dev, "could not map I/O memory\n");
-+		goto err_free;
-+	}
-+
-+	if (!cpu_is_at32ap7000()) {
-+		wdt->pclk = clk_get(&pdev->dev, "pclk");
-+		if (IS_ERR(wdt->pclk)) {
-+			dev_dbg(&pdev->dev, "no peripheral clock\n");
-+			ret = -ENXIO;
-+			goto err_iounmap;
-+		}
-+	}
-+
-+	ret = at32_wdt_enable_source_clock(pdev);
-+	if (ret)
-+		goto err_put_clk;
-+
-+	spin_lock_init(&wdt->io_lock);
-+	wdt->boot_status = at32_wdt_get_status();
-+
-+	/* Work-around for watchdog silicon errata. */
-+	if (cpu_is_at32ap7000()
-+			&& (wdt->boot_status & WDIOF_CARDRESET)) {
-+		dev_info(&pdev->dev, "CPU must be reset with external "
-+				"reset or POR due to silicon errata.\n");
-+		ret = -EIO;
-+		goto err_disable_source_clock;
-+	} else {
-+		wdt->users = 0;
-+	}
-+	wdt->miscdev.minor = WATCHDOG_MINOR;
-+	wdt->miscdev.name = "watchdog";
-+	wdt->miscdev.fops = &at32_wdt_fops;
-+
-+	if (at32_wdt_settimeout(timeout)) {
-+		at32_wdt_settimeout(TIMEOUT_DEFAULT);
-+		dev_dbg(&pdev->dev,
-+			"default timeout invalid, set to %d sec.\n",
-+			TIMEOUT_DEFAULT);
-+	}
-+
-+	ret = misc_register(&wdt->miscdev);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
-+		goto err_iounmap;
-+	}
-+
-+	platform_set_drvdata(pdev, wdt);
-+	wdt->miscdev.parent = &pdev->dev;
-+	dev_info(&pdev->dev,
-+		"AT32 WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
-+		wdt->regs, wdt->timeout, nowayout);
-+
-+	return 0;
-+
-+err_disable_source_clock:
-+	at32_wdt_disable_source_clock();
-+err_put_clk:
-+	if (!cpu_is_at32ap7000())
-+		clk_put(wdt->pclk);
-+err_iounmap:
-+	iounmap(wdt->regs);
-+err_free:
-+	kfree(wdt);
-+	wdt = NULL;
-+	return ret;
-+}
-+
-+static int __exit at32_wdt_remove(struct platform_device *pdev)
-+{
-+	if (wdt && platform_get_drvdata(pdev) == wdt) {
-+		/* Stop the timer before we leave */
-+		if (!nowayout) {
-+			at32_wdt_stop();
-+			at32_wdt_disable_source_clock();
-+		}
-+
-+		misc_deregister(&wdt->miscdev);
-+		if (!cpu_is_at32ap7000())
-+			clk_put(wdt->pclk);
-+		iounmap(wdt->regs);
-+		kfree(wdt);
-+		wdt = NULL;
-+		platform_set_drvdata(pdev, NULL);
-+	}
-+	return 0;
-+}
-+
-+static void at32_wdt_shutdown(struct platform_device *pdev)
-+{
-+	at32_wdt_stop();
-+}
-+
-+#ifdef CONFIG_PM
-+static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-+{
-+	at32_wdt_stop();
-+	return 0;
-+}
-+
-+static int at32_wdt_resume(struct platform_device *pdev)
-+{
-+	if (wdt->users)
-+		at32_wdt_start();
-+	return 0;
-+}
-+#else
-+#define at32_wdt_suspend NULL
-+#define at32_wdt_resume NULL
-+#endif
-+
-+/* work with hotplug and coldplug */
-+MODULE_ALIAS("platform:at32_wdt");
-+
-+static struct platform_driver at32_wdt_driver = {
-+	.remove		= __exit_p(at32_wdt_remove),
-+	.suspend	= at32_wdt_suspend,
-+	.resume		= at32_wdt_resume,
-+	.driver		= {
-+		.name	= "at32_wdt",
-+		.owner	= THIS_MODULE,
-+	},
-+	.shutdown	= at32_wdt_shutdown,
-+};
-+
-+static int __init at32_wdt_init(void)
-+{
-+	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
-+}
-+module_init(at32_wdt_init);
-+
-+static void __exit at32_wdt_exit(void)
-+{
-+	platform_driver_unregister(&at32_wdt_driver);
-+}
-+module_exit(at32_wdt_exit);
-+
-+MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
-+MODULE_DESCRIPTION("Watchdog driver for Atmel AVR32 devices");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c
-deleted file mode 100644
-index e8ae638..0000000
---- a/drivers/watchdog/at32ap700x_wdt.c
-+++ /dev/null
-@@ -1,449 +0,0 @@
--/*
-- * Watchdog driver for Atmel AT32AP700X devices
-- *
-- * Copyright (C) 2005-2006 Atmel Corporation
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- *
-- * Errata: WDT Clear is blocked after WDT Reset
-- *
-- * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
-- * register, preventing the program to clear the next Watchdog Timer Reset.
-- *
-- * If you still want to use the WDT after a WDT reset a small code can be
-- * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
-- * and use a GPIO pin to reset the system. This method requires that one of the
-- * GPIO pins are available and connected externally to the RESET_N pin. After
-- * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
-- * the pin tristated with pullup.
-- */
--
--#include <linux/init.h>
--#include <linux/kernel.h>
--#include <linux/module.h>
--#include <linux/moduleparam.h>
--#include <linux/miscdevice.h>
--#include <linux/fs.h>
--#include <linux/platform_device.h>
--#include <linux/watchdog.h>
--#include <linux/uaccess.h>
--#include <linux/io.h>
--#include <linux/spinlock.h>
--
--#define TIMEOUT_MIN		1
--#define TIMEOUT_MAX		2
--#define TIMEOUT_DEFAULT		TIMEOUT_MAX
--
--/* module parameters */
--static int timeout =  TIMEOUT_DEFAULT;
--module_param(timeout, int, 0);
--MODULE_PARM_DESC(timeout,
--		"Timeout value. Limited to be 1 or 2 seconds. (default="
--		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
--
--static int nowayout = WATCHDOG_NOWAYOUT;
--module_param(nowayout, int, 0);
--MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
--		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
--
--/* Watchdog registers and write/read macro */
--#define WDT_CTRL		0x00
--#define WDT_CTRL_EN		   0
--#define WDT_CTRL_PSEL		   8
--#define WDT_CTRL_KEY		  24
--
--#define WDT_CLR			0x04
--
--#define WDT_RCAUSE		0x10
--#define WDT_RCAUSE_POR		   0
--#define WDT_RCAUSE_EXT		   2
--#define WDT_RCAUSE_WDT		   3
--#define WDT_RCAUSE_JTAG		   4
--#define WDT_RCAUSE_SERP		   5
--
--#define WDT_BIT(name)		(1 << WDT_##name)
--#define WDT_BF(name, value)	((value) << WDT_##name)
--
--#define wdt_readl(dev, reg)				\
--	__raw_readl((dev)->regs + WDT_##reg)
--#define wdt_writel(dev, reg, value)			\
--	__raw_writel((value), (dev)->regs + WDT_##reg)
--
--struct wdt_at32ap700x {
--	void __iomem		*regs;
--	spinlock_t		io_lock;
--	int			timeout;
--	int			boot_status;
--	unsigned long		users;
--	struct miscdevice	miscdev;
--};
--
--static struct wdt_at32ap700x *wdt;
--static char expect_release;
--
--/*
-- * Disable the watchdog.
-- */
--static inline void at32_wdt_stop(void)
--{
--	unsigned long psel;
--
--	spin_lock(&wdt->io_lock);
--	psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
--	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
--	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Enable and reset the watchdog.
-- */
--static inline void at32_wdt_start(void)
--{
--	/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
--	unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
--
--	spin_lock(&wdt->io_lock);
--	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
--			| WDT_BF(CTRL_PSEL, psel)
--			| WDT_BF(CTRL_KEY, 0x55));
--	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
--			| WDT_BF(CTRL_PSEL, psel)
--			| WDT_BF(CTRL_KEY, 0xaa));
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Pat the watchdog timer.
-- */
--static inline void at32_wdt_pat(void)
--{
--	spin_lock(&wdt->io_lock);
--	wdt_writel(wdt, CLR, 0x42);
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Watchdog device is opened, and watchdog starts running.
-- */
--static int at32_wdt_open(struct inode *inode, struct file *file)
--{
--	if (test_and_set_bit(1, &wdt->users))
--		return -EBUSY;
--
--	at32_wdt_start();
--	return nonseekable_open(inode, file);
--}
--
--/*
-- * Close the watchdog device.
-- */
--static int at32_wdt_close(struct inode *inode, struct file *file)
--{
--	if (expect_release == 42) {
--		at32_wdt_stop();
--	} else {
--		dev_dbg(wdt->miscdev.parent,
--			"unexpected close, not stopping watchdog!\n");
--		at32_wdt_pat();
--	}
--	clear_bit(1, &wdt->users);
--	expect_release = 0;
--	return 0;
--}
--
--/*
-- * Change the watchdog time interval.
-- */
--static int at32_wdt_settimeout(int time)
--{
--	/*
--	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max prescaler is
--	 * 2 ^ 16 allowing up to 2 seconds timeout.
--	 */
--	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX))
--		return -EINVAL;
--
--	/*
--	 * Set new watchdog time. It will be used when at32_wdt_start() is
--	 * called.
--	 */
--	wdt->timeout = time;
--	return 0;
--}
--
--/*
-- * Get the watchdog status.
-- */
--static int at32_wdt_get_status(void)
--{
--	int rcause;
--	int status = 0;
--
--	rcause = wdt_readl(wdt, RCAUSE);
--
--	switch (rcause) {
--	case WDT_BIT(RCAUSE_EXT):
--		status = WDIOF_EXTERN1;
--		break;
--	case WDT_BIT(RCAUSE_WDT):
--		status = WDIOF_CARDRESET;
--		break;
--	case WDT_BIT(RCAUSE_POR):  /* fall through */
--	case WDT_BIT(RCAUSE_JTAG): /* fall through */
--	case WDT_BIT(RCAUSE_SERP): /* fall through */
--	default:
--		break;
--	}
--
--	return status;
--}
--
--static struct watchdog_info at32_wdt_info = {
--	.identity	= "at32ap700x watchdog",
--	.options	= WDIOF_SETTIMEOUT |
--			  WDIOF_KEEPALIVEPING |
--			  WDIOF_MAGICCLOSE,
--};
--
--/*
-- * Handle commands from user-space.
-- */
--static long at32_wdt_ioctl(struct file *file,
--				unsigned int cmd, unsigned long arg)
--{
--	int ret = -ENOTTY;
--	int time;
--	void __user *argp = (void __user *)arg;
--	int __user *p = argp;
--
--	switch (cmd) {
--	case WDIOC_GETSUPPORT:
--		ret = copy_to_user(argp, &at32_wdt_info,
--				sizeof(at32_wdt_info)) ? -EFAULT : 0;
--		break;
--	case WDIOC_GETSTATUS:
--		ret = put_user(0, p);
--		break;
--	case WDIOC_GETBOOTSTATUS:
--		ret = put_user(wdt->boot_status, p);
--		break;
--	case WDIOC_SETOPTIONS:
--		ret = get_user(time, p);
--		if (ret)
--			break;
--		if (time & WDIOS_DISABLECARD)
--			at32_wdt_stop();
--		if (time & WDIOS_ENABLECARD)
--			at32_wdt_start();
--		ret = 0;
--		break;
--	case WDIOC_KEEPALIVE:
--		at32_wdt_pat();
--		ret = 0;
--		break;
--	case WDIOC_SETTIMEOUT:
--		ret = get_user(time, p);
--		if (ret)
--			break;
--		ret = at32_wdt_settimeout(time);
--		if (ret)
--			break;
--		/* Enable new time value */
--		at32_wdt_start();
--		/* fall through */
--	case WDIOC_GETTIMEOUT:
--		ret = put_user(wdt->timeout, p);
--		break;
--	}
--
--	return ret;
--}
--
--static ssize_t at32_wdt_write(struct file *file, const char __user *data,
--				size_t len, loff_t *ppos)
--{
--	/* See if we got the magic character 'V' and reload the timer */
--	if (len) {
--		if (!nowayout) {
--			size_t i;
--
--			/*
--			 * note: just in case someone wrote the magic
--			 * character five months ago...
--			 */
--			expect_release = 0;
--
--			/*
--			 * scan to see whether or not we got the magic
--			 * character
--			 */
--			for (i = 0; i != len; i++) {
--				char c;
--				if (get_user(c, data + i))
--					return -EFAULT;
--				if (c == 'V')
--					expect_release = 42;
--			}
--		}
--		/* someone wrote to us, we should pat the watchdog */
--		at32_wdt_pat();
--	}
--	return len;
--}
--
--static const struct file_operations at32_wdt_fops = {
--	.owner		= THIS_MODULE,
--	.llseek		= no_llseek,
--	.unlocked_ioctl	= at32_wdt_ioctl,
--	.open		= at32_wdt_open,
--	.release	= at32_wdt_close,
--	.write		= at32_wdt_write,
--};
--
--static int __init at32_wdt_probe(struct platform_device *pdev)
--{
--	struct resource	*regs;
--	int ret;
--
--	if (wdt) {
--		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
--		return -EBUSY;
--	}
--
--	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	if (!regs) {
--		dev_dbg(&pdev->dev, "missing mmio resource\n");
--		return -ENXIO;
--	}
--
--	wdt = kzalloc(sizeof(struct wdt_at32ap700x), GFP_KERNEL);
--	if (!wdt) {
--		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
--		return -ENOMEM;
--	}
--
--	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
--	if (!wdt->regs) {
--		ret = -ENOMEM;
--		dev_dbg(&pdev->dev, "could not map I/O memory\n");
--		goto err_free;
--	}
--
--	spin_lock_init(&wdt->io_lock);
--	wdt->boot_status = at32_wdt_get_status();
--
--	/* Work-around for watchdog silicon errata. */
--	if (wdt->boot_status & WDIOF_CARDRESET) {
--		dev_info(&pdev->dev, "CPU must be reset with external "
--				"reset or POR due to silicon errata.\n");
--		ret = -EIO;
--		goto err_iounmap;
--	} else {
--		wdt->users = 0;
--	}
--	wdt->miscdev.minor = WATCHDOG_MINOR;
--	wdt->miscdev.name = "watchdog";
--	wdt->miscdev.fops = &at32_wdt_fops;
--
--	if (at32_wdt_settimeout(timeout)) {
--		at32_wdt_settimeout(TIMEOUT_DEFAULT);
--		dev_dbg(&pdev->dev,
--			"default timeout invalid, set to %d sec.\n",
--			TIMEOUT_DEFAULT);
--	}
--
--	ret = misc_register(&wdt->miscdev);
--	if (ret) {
--		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
--		goto err_iounmap;
--	}
--
--	platform_set_drvdata(pdev, wdt);
--	wdt->miscdev.parent = &pdev->dev;
--	dev_info(&pdev->dev,
--		"AT32AP700X WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
--		wdt->regs, wdt->timeout, nowayout);
--
--	return 0;
--
--err_iounmap:
--	iounmap(wdt->regs);
--err_free:
--	kfree(wdt);
--	wdt = NULL;
--	return ret;
--}
--
--static int __exit at32_wdt_remove(struct platform_device *pdev)
--{
--	if (wdt && platform_get_drvdata(pdev) == wdt) {
--		/* Stop the timer before we leave */
--		if (!nowayout)
--			at32_wdt_stop();
--
--		misc_deregister(&wdt->miscdev);
--		iounmap(wdt->regs);
--		kfree(wdt);
--		wdt = NULL;
--		platform_set_drvdata(pdev, NULL);
--	}
--	return 0;
--}
--
--static void at32_wdt_shutdown(struct platform_device *pdev)
--{
--	at32_wdt_stop();
--}
--
--#ifdef CONFIG_PM
--static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
--{
--	at32_wdt_stop();
--	return 0;
--}
--
--static int at32_wdt_resume(struct platform_device *pdev)
--{
--	if (wdt->users)
--		at32_wdt_start();
--	return 0;
--}
--#else
--#define at32_wdt_suspend NULL
--#define at32_wdt_resume NULL
--#endif
--
--/* work with hotplug and coldplug */
--MODULE_ALIAS("platform:at32_wdt");
--
--static struct platform_driver at32_wdt_driver = {
--	.remove		= __exit_p(at32_wdt_remove),
--	.suspend	= at32_wdt_suspend,
--	.resume		= at32_wdt_resume,
--	.driver		= {
--		.name	= "at32_wdt",
--		.owner	= THIS_MODULE,
--	},
--	.shutdown	= at32_wdt_shutdown,
--};
--
--static int __init at32_wdt_init(void)
--{
--	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
--}
--module_init(at32_wdt_init);
--
--static void __exit at32_wdt_exit(void)
--{
--	platform_driver_unregister(&at32_wdt_driver);
--}
--module_exit(at32_wdt_exit);
--
--MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
--MODULE_DESCRIPTION("Watchdog driver for Atmel AT32AP700X");
--MODULE_LICENSE("GPL");
--MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-diff --git a/include/linux/Kbuild b/include/linux/Kbuild
-index b68ec09..e69646d 100644
---- a/include/linux/Kbuild
-+++ b/include/linux/Kbuild
-@@ -23,6 +23,7 @@ header-y += atmapi.h
- header-y += atmarp.h
- header-y += atmbr2684.h
- header-y += atmclip.h
-+header-y += atmel_mpopfb.h
- header-y += atm_eni.h
- header-y += atm_he.h
- header-y += atm_idt77105.h
-diff --git a/include/linux/atmel_mpopfb.h b/include/linux/atmel_mpopfb.h
-new file mode 100644
-index 0000000..cd12e16
---- /dev/null
-+++ b/include/linux/atmel_mpopfb.h
-@@ -0,0 +1,112 @@
-+/*
-+ *  Header file for AT32 MPOP FB Driver
-+ *
-+ *  Data structure and register user interface
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ATMEL_MPOPFB_H__
-+#define __ATMEL_MPOPFB_H__
-+
-+#include <linux/fb.h>
-+#include <linux/ioctl.h>
-+
-+/* Coefficients for conversion to rgb. */
-+struct atmel_mpopfb_rgbconv_coeffs {
-+	int r1, r2, r3, r4;
-+	int g1, g2, g3, g4;
-+	int b1, b2, b3, b4;
-+};
-+
-+struct atmel_mpopfb_baseimg_info {
-+	/* Position of the mpop base image
-+	   in the image sent to the LCD. */
-+	unsigned xpos;
-+	unsigned ypos;
-+
-+	/* The size of the base image after scaling. */
-+	unsigned xsize;
-+	unsigned ysize;
-+
-+	/* Signal that we should flip the video. */
-+	int flip;
-+
-+};
-+
-+enum atmel_mpopfb_overlay_type {
-+	ATMEL_MPOPFB_OVERLAY1 = 0,
-+	ATMEL_MPOPFB_OVERLAY2 = 1,
-+	ATMEL_MPOPFB_CURSOR = 2
-+};
-+
-+struct atmel_mpopfb_overlay_info {
-+	/* Position of the mpop overlay image
-+	   in the image sent to the LCD. */
-+	unsigned xpos;
-+	unsigned ypos;
-+	/* The size of the overlay image. */
-+	unsigned xsize;
-+	unsigned ysize;
-+	/* Signal which overlay this info is for. */
-+	enum atmel_mpopfb_overlay_type overlay;
-+	/* Signal if the overlay is enabled. */
-+	unsigned enabled;
-+};
-+
-+struct atmel_mpopfb_overlay_palette_entry {
-+	unsigned char alpha;
-+	unsigned char red;
-+	unsigned char green;
-+	unsigned char blue;
-+};
-+
-+struct atmel_mpopfb_cursor_palette_entry {
-+	unsigned char:6;
-+	unsigned char invert:1;
-+	unsigned char visible:1;
-+	unsigned char red;
-+	unsigned char green;
-+	unsigned char blue;
-+};
-+
-+struct atmel_mpopfb_overlay_palette {
-+	struct atmel_mpopfb_overlay_palette_entry entry[256];
-+};
-+
-+struct atmel_mpopfb_cursor_palette {
-+	struct atmel_mpopfb_cursor_palette_entry entry[4];
-+};
-+
-+#define ATMEL_MPOP_FBIOPUT_BASEIMG_INFO        _IOW('x',0,struct atmel_mpopfb_baseimg_info)
-+#define ATMEL_MPOP_FBIOGET_BASEIMG_INFO        _IOR('x',1,struct atmel_mpopfb_baseimg_info)
-+#define ATMEL_MPOP_FBIOPUT_OVERLAY_INFO        _IOW('x',2,struct atmel_mpopfb_overlay_info)
-+#define ATMEL_MPOP_FBIO_CONNECT_TO_LCDC        _IO( 'x',4)
-+#define ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC   _IO( 'x',5)
-+#define ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS      _IOW('x',6,struct atmel_mpopfb_rgbconv_coeffs)
-+#define ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS      _IOR('x',7,struct atmel_mpopfb_rgbconv_coeffs)
-+#define ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE     _IOW('x',8,struct atmel_mpopfb_overlay_palette)
-+#define ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE     _IOR('x',9,struct atmel_mpopfb_overlay_palette)
-+#define ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE      _IOW('x',10,struct atmel_mpopfb_cursor_palette)
-+#define ATMEL_MPOP_FBIOGET_CURSOR_PALETTE      _IOR('x',11,struct atmel_mpopfb_cursor_palette)
-+
-+#define ATMEL_MPOP_RESIZE_FRAC_BITS 5
-+#define ATMEL_MPOP_SCALE_FRAC_DIV(a,b)  ((((a) << ATMEL_MPOP_RESIZE_FRAC_BITS))/(b))
-+#define ATMEL_MPOP_CALC_SCALE(from_res,to_res)  ATMEL_MPOP_SCALE_FRAC_DIV(from_res, to_res)
-+
-+#define ATMEL_MPOP_COEFF_FRAC_BITS 8
-+
-+#endif
-diff --git a/include/linux/atmel_pdca.h b/include/linux/atmel_pdca.h
-new file mode 100644
-index 0000000..a2ee314
---- /dev/null
-+++ b/include/linux/atmel_pdca.h
-@@ -0,0 +1,120 @@
-+/*
-+ * Driver for the Atmel PDCA Peripheral DMA Controller
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ATMEL_PDCA_H
-+#define __ATMEL_PDCA_H
-+
-+#include <linux/dmaengine.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+
-+struct pdca_pdata {
-+	unsigned int		nr_channels;
-+};
-+
-+struct pdca_slave {
-+	struct dma_slave	slave;
-+	u8			tx_periph_id;
-+	u8			rx_periph_id;
-+};
-+
-+struct pdca_desc {
-+	/* This controller does not support hardware descriptors */
-+	struct scatterlist	*sg;
-+	int			sg_len;
-+	u8			reg_width;
-+	u8			periph_id;
-+
-+	struct list_head	desc_node;
-+	struct dma_async_tx_descriptor txd;
-+};
-+
-+struct pdca_chan {
-+	struct list_head	freelist;
-+	struct list_head	queue;
-+
-+	spinlock_t		lock;
-+	void __iomem		*regs;
-+
-+	struct scatterlist	*cur_sg;
-+	struct scatterlist	*next_sg;
-+
-+	struct tasklet_struct	tasklet;
-+
-+	dma_cookie_t		completed;
-+	struct dma_chan		chan;
-+	struct pdca_slave	*pslave;
-+	unsigned int		descs_allocated;
-+	bool			enabled;
-+};
-+
-+struct pdca_dev {
-+	struct clk		*hclk;
-+	struct clk		*pclk;
-+	struct dma_device	dma;
-+	void __iomem		*regs;
-+
-+	struct pdca_chan	chan[];
-+};
-+
-+static inline struct pdca_slave *dma_to_pdca_slave(struct dma_slave *slave)
-+{
-+	return container_of(slave, struct pdca_slave, slave);
-+}
-+
-+static inline struct pdca_desc *txd_to_pdca_desc(
-+		struct dma_async_tx_descriptor *txd)
-+{
-+	return container_of(txd, struct pdca_desc, txd);
-+}
-+
-+static inline struct pdca_chan *dma_to_pdca_chan(struct dma_chan *chan)
-+{
-+	return container_of(chan, struct pdca_chan, chan);
-+}
-+
-+static inline struct pdca_dev *dma_to_pdca_dev(struct dma_device *dma)
-+{
-+	return container_of(dma, struct pdca_dev, dma);
-+}
-+
-+/* PDCA per-channel register definitions */
-+#define PDCA_MAR		0x0000	/* Memory Address */
-+#define PDCA_PSR		0x0004	/* Peripheral Select */
-+#define PDCA_TCR		0x0008	/* Transfer Counter */
-+#define PDCA_MARR		0x000c	/* Memory Address Reload */
-+#define PDCA_TCRR		0x0010	/* Transfer Counter Reload */
-+#define PDCA_CR			0x0014	/* Control */
-+# define PDCA_CR_TEN		(  1 <<  0)	/* Transfer Enable */
-+# define PDCA_CR_TDIS		(  1 <<  1)	/* Transfer Disable */
-+# define PDCA_CR_ECLR		(  1 <<  8)	/* Error Clear */
-+#define PDCA_MR			0x0018	/* Mode */
-+# define PDCA_SIZE_BYTE		(  0 <<  0)	/* 8 bits per transfer */
-+# define PDCA_SIZE_HWORD	(  1 <<  0)	/* 16 bits per transfer */
-+# define PDCA_SIZE_WORD		(  2 <<  0)	/* 32 bits per transfer */
-+#define PDCA_SR			0x001c	/* Status */
-+# define PDCA_SR_TEN		(  1 <<  0)	/* Transfer Enabled */
-+#define PDCA_IER		0x0020	/* Interrupt Enable */
-+#define PDCA_IDR		0x0024	/* Interrupt Disable */
-+#define PDCA_IMR		0x0028	/* Interrupt Mask */
-+#define PDCA_ISR		0x002c	/* Interrupt Status */
-+# define PDCA_RCZ		(  1 <<  0)	/* Reload Counter Zero */
-+# define PDCA_TRC		(  1 <<  1)	/* Transfer Complete */
-+# define PDCA_TERR		(  1 <<  2)	/* Transfer Error */
-+
-+/* Address space occupied by one channel */
-+#define PDCA_CHAN_SIZE		0x40
-+
-+#define pdca_readl(base, reg)				\
-+	__raw_readl((base) + PDCA_##reg)
-+#define pdca_writel(base, reg, value)			\
-+	__raw_writel((value), (base) + PDCA_##reg)
-+
-+#endif /* __ATMEL_PDCA_H */
-diff --git a/include/linux/spi/atmel_spi.h b/include/linux/spi/atmel_spi.h
-new file mode 100644
-index 0000000..88ae568
---- /dev/null
-+++ b/include/linux/spi/atmel_spi.h
-@@ -0,0 +1,20 @@
-+/*
-+ * Driver for Atmel AT32 and AT91 SPI Controllers
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __LINUX_SPI_ATMEL_SPI_H
-+#define __LINUX_SPI_ATMEL_SPI_H
-+
-+struct atmel_spi_pdata {
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	struct dma_slave	*rx_dma_slave;
-+	struct dma_slave	*tx_dma_slave;
-+#endif
-+};
-+
-+#endif /* __LINUX_SPI_ATMEL_SPI_H */
-diff --git a/include/video/atmel_mpop.h b/include/video/atmel_mpop.h
-new file mode 100644
-index 0000000..60270b8
---- /dev/null
-+++ b/include/video/atmel_mpop.h
-@@ -0,0 +1,820 @@
-+/*
-+ *  Header file for AT32 MPOP Controller
-+ *
-+ *  Data structure and register user interface
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ATMEL_MPOP_H__
-+#define __ATMEL_MPOP_H__
-+
-+#include <linux/atmel_mpopfb.h>
-+
-+/* MPOP Controller info data structure */
-+struct atmel_mpopfb_info {
-+	spinlock_t lock;
-+	struct fb_info *info;
-+	void __iomem *mmio;
-+	unsigned long irq_base;
-+	void *slave_base;
-+
-+	struct platform_device *pdev;
-+	struct platform_device *lcdc_pdev;
-+	struct clk *mpop_hclk;
-+	struct clk *mpop_pclk;
-+	unsigned int running;
-+	unsigned int connected_to_lcdc;
-+	unsigned long lcdc_old_smem_start;
-+	unsigned long lcdc_old_bits_per_pixel;
-+	struct atmel_mpopfb_baseimg_info baseimg_info;
-+	struct atmel_mpopfb_overlay_info overlay_info[3];
-+	struct atmel_mpopfb_rgbconv_coeffs rgbconv_coeffs;
-+};
-+
-+/* TODO! Clean up these defines.... */
-+#define ATMEL_MPOP_B                                                 0
-+#define ATMEL_MPOP_B1                                                0
-+#define ATMEL_MPOP_B1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_B1_OFFSET                                         0
-+#define ATMEL_MPOP_B1_SIZE                                          12
-+#define ATMEL_MPOP_B2                                               12
-+#define ATMEL_MPOP_B2B1                                     0x00000024
-+#define ATMEL_MPOP_B2B1_B1                                           0
-+#define ATMEL_MPOP_B2B1_B1_MASK                             0x00000fff
-+#define ATMEL_MPOP_B2B1_B1_OFFSET                                    0
-+#define ATMEL_MPOP_B2B1_B1_SIZE                                     12
-+#define ATMEL_MPOP_B2B1_B2                                          12
-+#define ATMEL_MPOP_B2B1_B2_MASK                             0x00fff000
-+#define ATMEL_MPOP_B2B1_B2_OFFSET                                   12
-+#define ATMEL_MPOP_B2B1_B2_SIZE                                     12
-+#define ATMEL_MPOP_B2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_B2_OFFSET                                        12
-+#define ATMEL_MPOP_B2_SIZE                                          12
-+#define ATMEL_MPOP_B3                                                0
-+#define ATMEL_MPOP_B3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_B3_OFFSET                                         0
-+#define ATMEL_MPOP_B3_SIZE                                          12
-+#define ATMEL_MPOP_B4                                               12
-+#define ATMEL_MPOP_B4B3                                     0x00000028
-+#define ATMEL_MPOP_B4B3_B3                                           0
-+#define ATMEL_MPOP_B4B3_B3_MASK                             0x00000fff
-+#define ATMEL_MPOP_B4B3_B3_OFFSET                                    0
-+#define ATMEL_MPOP_B4B3_B3_SIZE                                     12
-+#define ATMEL_MPOP_B4B3_B4                                          12
-+#define ATMEL_MPOP_B4B3_B4_MASK                             0xfffff000
-+#define ATMEL_MPOP_B4B3_B4_OFFSET                                   12
-+#define ATMEL_MPOP_B4B3_B4_SIZE                                     20
-+#define ATMEL_MPOP_B4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_B4_OFFSET                                        12
-+#define ATMEL_MPOP_B4_SIZE                                          20
-+#define ATMEL_MPOP_BGCOLOR                                  0x00000090
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR                                   0
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_MASK                     0xffffffff
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_OFFSET                            0
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_SIZE                             32
-+#define ATMEL_MPOP_BGCOLOR_MASK                             0xffffffff
-+#define ATMEL_MPOP_BGCOLOR_OFFSET                                    0
-+#define ATMEL_MPOP_BGCOLOR_SIZE                                     32
-+#define ATMEL_MPOP_BGR                                               6
-+#define ATMEL_MPOP_BGR_MASK                                 0x00000040
-+#define ATMEL_MPOP_BGR_OFFSET                                        6
-+#define ATMEL_MPOP_BGR_SIZE                                          1
-+#define ATMEL_MPOP_B_MASK                                   0x000000ff
-+#define ATMEL_MPOP_B_OFFSET                                          0
-+#define ATMEL_MPOP_B_SIZE                                            8
-+#define ATMEL_MPOP_CACHEDIS                                          8
-+#define ATMEL_MPOP_CACHEDIS_MASK                            0x00000100
-+#define ATMEL_MPOP_CACHEDIS_OFFSET                                   8
-+#define ATMEL_MPOP_CACHEDIS_SIZE                                     1
-+#define ATMEL_MPOP_CR                                       0x00000000
-+#define ATMEL_MPOP_CR_CACHEDIS                                       8
-+#define ATMEL_MPOP_CR_CACHEDIS_MASK                         0x00000100
-+#define ATMEL_MPOP_CR_CACHEDIS_OFFSET                                8
-+#define ATMEL_MPOP_CR_CACHEDIS_SIZE                                  1
-+#define ATMEL_MPOP_CR_EN                                             0
-+#define ATMEL_MPOP_CR_EN_MASK                               0x00000001
-+#define ATMEL_MPOP_CR_EN_OFFSET                                      0
-+#define ATMEL_MPOP_CR_EN_SIZE                                        1
-+#define ATMEL_MPOP_CR_OUT_BGR                                        3
-+#define ATMEL_MPOP_CR_OUT_BGR_MASK                          0x00000008
-+#define ATMEL_MPOP_CR_OUT_BGR_OFFSET                                 3
-+#define ATMEL_MPOP_CR_OUT_BGR_SIZE                                   1
-+#define ATMEL_MPOP_CR_OUT_CTRL                                       2
-+#define ATMEL_MPOP_CR_OUT_CTRL_MASK                         0x00000004
-+#define ATMEL_MPOP_CR_OUT_CTRL_OFFSET                                2
-+#define ATMEL_MPOP_CR_OUT_CTRL_SIZE                                  1
-+#define ATMEL_MPOP_CR_START                                          1
-+#define ATMEL_MPOP_CR_START_MASK                            0x00000002
-+#define ATMEL_MPOP_CR_START_OFFSET                                   1
-+#define ATMEL_MPOP_CR_START_SIZE                                     1
-+#define ATMEL_MPOP_CURSOREN                                          0
-+#define ATMEL_MPOP_CURSOREN_MASK                            0x00000001
-+#define ATMEL_MPOP_CURSOREN_OFFSET                                   0
-+#define ATMEL_MPOP_CURSOREN_SIZE                                     1
-+#define ATMEL_MPOP_CURSOR_P0                                0x00000080
-+#define ATMEL_MPOP_CURSOR_P0_B                                       0
-+#define ATMEL_MPOP_CURSOR_P0_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P0_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P0_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_G                                       8
-+#define ATMEL_MPOP_CURSOR_P0_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P0_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P0_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P0_R                                      16
-+#define ATMEL_MPOP_CURSOR_P0_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P0_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P0_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P1                                0x00000084
-+#define ATMEL_MPOP_CURSOR_P1_B                                       0
-+#define ATMEL_MPOP_CURSOR_P1_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P1_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P1_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_G                                       8
-+#define ATMEL_MPOP_CURSOR_P1_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P1_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P1_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P1_R                                      16
-+#define ATMEL_MPOP_CURSOR_P1_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P1_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P1_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P2                                0x00000088
-+#define ATMEL_MPOP_CURSOR_P2_B                                       0
-+#define ATMEL_MPOP_CURSOR_P2_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P2_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P2_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_G                                       8
-+#define ATMEL_MPOP_CURSOR_P2_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P2_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P2_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P2_R                                      16
-+#define ATMEL_MPOP_CURSOR_P2_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P2_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P2_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P3                                0x0000008c
-+#define ATMEL_MPOP_CURSOR_P3_B                                       0
-+#define ATMEL_MPOP_CURSOR_P3_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P3_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P3_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_G                                       8
-+#define ATMEL_MPOP_CURSOR_P3_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P3_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P3_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P3_R                                      16
-+#define ATMEL_MPOP_CURSOR_P3_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P3_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P3_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_POS                               0x00000058
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X                          11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_MASK             0x003ff800
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_OFFSET                   11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_SIZE                     11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y                           0
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_MASK             0x000007ff
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_OFFSET                    0
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_SIZE                     11
-+#define ATMEL_MPOP_CURSOR_POS_X                                     11
-+#define ATMEL_MPOP_CURSOR_POS_X_MASK                        0x003ff800
-+#define ATMEL_MPOP_CURSOR_POS_X_OFFSET                              11
-+#define ATMEL_MPOP_CURSOR_POS_X_SIZE                                11
-+#define ATMEL_MPOP_CURSOR_POS_Y                                      0
-+#define ATMEL_MPOP_CURSOR_POS_Y_MASK                        0x000007ff
-+#define ATMEL_MPOP_CURSOR_POS_Y_OFFSET                               0
-+#define ATMEL_MPOP_CURSOR_POS_Y_SIZE                                11
-+#define ATMEL_MPOP_CURSOR_SAR                               0x00000048
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR                             0
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_MASK               0xffffffff
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_OFFSET                      0
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_SIZE                       32
-+#define ATMEL_MPOP_CURSOR_SAR_MASK                          0xffffffff
-+#define ATMEL_MPOP_CURSOR_SAR_OFFSET                                 0
-+#define ATMEL_MPOP_CURSOR_SAR_SIZE                                  32
-+#define ATMEL_MPOP_CURSOR_SIZE                              0x0000006c
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X                        11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_MASK           0x003ff800
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_OFFSET                 11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_SIZE                   11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y                         0
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_MASK           0x000007ff
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_OFFSET                  0
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_SIZE                   11
-+#define ATMEL_MPOP_CURSOR_SIZE_X                                    11
-+#define ATMEL_MPOP_CURSOR_SIZE_X_MASK                       0x003ff800
-+#define ATMEL_MPOP_CURSOR_SIZE_X_OFFSET                             11
-+#define ATMEL_MPOP_CURSOR_SIZE_X_SIZE                               11
-+#define ATMEL_MPOP_CURSOR_SIZE_Y                                     0
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_MASK                       0x000007ff
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_OFFSET                              0
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_SIZE                               11
-+#define ATMEL_MPOP_CURSOR_WTC                               0x0000007c
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC                             0
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_MASK               0xffffffff
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_OFFSET                      0
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_SIZE                       32
-+#define ATMEL_MPOP_CURSOR_WTC_MASK                          0xffffffff
-+#define ATMEL_MPOP_CURSOR_WTC_OFFSET                                 0
-+#define ATMEL_MPOP_CURSOR_WTC_SIZE                                  32
-+#define ATMEL_MPOP_DISP_MAX_COORD                           0x00000010
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X                  11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_MASK     0x003ff800
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_OFFSET           11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_SIZE             11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y                   0
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_MASK     0x000007ff
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_OFFSET            0
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_SIZE             11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X                                 11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_MASK                    0x003ff800
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET                          11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_SIZE                            11
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y                                  0
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_MASK                    0x000007ff
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET                           0
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_SIZE                            11
-+#define ATMEL_MPOP_EN                                                0
-+#define ATMEL_MPOP_EN_MASK                                  0x00000001
-+#define ATMEL_MPOP_EN_OFFSET                                         0
-+#define ATMEL_MPOP_EN_SIZE                                           1
-+#define ATMEL_MPOP_EOP                                               3
-+#define ATMEL_MPOP_EOP_MASK                                 0x00000008
-+#define ATMEL_MPOP_EOP_OFFSET                                        3
-+#define ATMEL_MPOP_EOP_SIZE                                          1
-+#define ATMEL_MPOP_G                                                 8
-+#define ATMEL_MPOP_G1                                                0
-+#define ATMEL_MPOP_G1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_G1_OFFSET                                         0
-+#define ATMEL_MPOP_G1_SIZE                                          12
-+#define ATMEL_MPOP_G2                                               12
-+#define ATMEL_MPOP_G2G1                                     0x0000001c
-+#define ATMEL_MPOP_G2G1_G1                                           0
-+#define ATMEL_MPOP_G2G1_G1_MASK                             0x00000fff
-+#define ATMEL_MPOP_G2G1_G1_OFFSET                                    0
-+#define ATMEL_MPOP_G2G1_G1_SIZE                                     12
-+#define ATMEL_MPOP_G2G1_G2                                          12
-+#define ATMEL_MPOP_G2G1_G2_MASK                             0x00fff000
-+#define ATMEL_MPOP_G2G1_G2_OFFSET                                   12
-+#define ATMEL_MPOP_G2G1_G2_SIZE                                     12
-+#define ATMEL_MPOP_G2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_G2_OFFSET                                        12
-+#define ATMEL_MPOP_G2_SIZE                                          12
-+#define ATMEL_MPOP_G3                                                0
-+#define ATMEL_MPOP_G3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_G3_OFFSET                                         0
-+#define ATMEL_MPOP_G3_SIZE                                          12
-+#define ATMEL_MPOP_G4                                               12
-+#define ATMEL_MPOP_G4G3                                     0x00000020
-+#define ATMEL_MPOP_G4G3_G3                                           0
-+#define ATMEL_MPOP_G4G3_G3_MASK                             0x00000fff
-+#define ATMEL_MPOP_G4G3_G3_OFFSET                                    0
-+#define ATMEL_MPOP_G4G3_G3_SIZE                                     12
-+#define ATMEL_MPOP_G4G3_G4                                          12
-+#define ATMEL_MPOP_G4G3_G4_MASK                             0xfffff000
-+#define ATMEL_MPOP_G4G3_G4_OFFSET                                   12
-+#define ATMEL_MPOP_G4G3_G4_SIZE                                     20
-+#define ATMEL_MPOP_G4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_G4_OFFSET                                        12
-+#define ATMEL_MPOP_G4_SIZE                                          20
-+#define ATMEL_MPOP_G_MASK                                   0x0000ff00
-+#define ATMEL_MPOP_G_OFFSET                                          8
-+#define ATMEL_MPOP_G_SIZE                                            8
-+#define ATMEL_MPOP_INTCLEAR                                 0x000000b0
-+#define ATMEL_MPOP_INTCLEAR_EOP                                      3
-+#define ATMEL_MPOP_INTCLEAR_EOP_MASK                        0x00000008
-+#define ATMEL_MPOP_INTCLEAR_EOP_OFFSET                               3
-+#define ATMEL_MPOP_INTCLEAR_EOP_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_OUT                                      2
-+#define ATMEL_MPOP_INTCLEAR_OUT_MASK                        0x00000004
-+#define ATMEL_MPOP_INTCLEAR_OUT_OFFSET                               2
-+#define ATMEL_MPOP_INTCLEAR_OUT_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY                                  1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_MASK                    0x00000002
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_OFFSET                           1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_SIZE                             1
-+#define ATMEL_MPOP_INTCLEAR_SOP                                      4
-+#define ATMEL_MPOP_INTCLEAR_SOP_MASK                        0x00000010
-+#define ATMEL_MPOP_INTCLEAR_SOP_OFFSET                               4
-+#define ATMEL_MPOP_INTCLEAR_SOP_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_YUV                                      0
-+#define ATMEL_MPOP_INTCLEAR_YUV_MASK                        0x00000001
-+#define ATMEL_MPOP_INTCLEAR_YUV_OFFSET                               0
-+#define ATMEL_MPOP_INTCLEAR_YUV_SIZE                                 1
-+#define ATMEL_MPOP_INTDIS                                   0x000000a4
-+#define ATMEL_MPOP_INTDIS_EOP                                        3
-+#define ATMEL_MPOP_INTDIS_EOP_MASK                          0x00000008
-+#define ATMEL_MPOP_INTDIS_EOP_OFFSET                                 3
-+#define ATMEL_MPOP_INTDIS_EOP_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_OUT                                        2
-+#define ATMEL_MPOP_INTDIS_OUT_MASK                          0x00000004
-+#define ATMEL_MPOP_INTDIS_OUT_OFFSET                                 2
-+#define ATMEL_MPOP_INTDIS_OUT_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_OVERLAY                                    1
-+#define ATMEL_MPOP_INTDIS_OVERLAY_MASK                      0x00000002
-+#define ATMEL_MPOP_INTDIS_OVERLAY_OFFSET                             1
-+#define ATMEL_MPOP_INTDIS_OVERLAY_SIZE                               1
-+#define ATMEL_MPOP_INTDIS_SOP                                        4
-+#define ATMEL_MPOP_INTDIS_SOP_MASK                          0x00000010
-+#define ATMEL_MPOP_INTDIS_SOP_OFFSET                                 4
-+#define ATMEL_MPOP_INTDIS_SOP_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_YUV                                        0
-+#define ATMEL_MPOP_INTDIS_YUV_MASK                          0x00000001
-+#define ATMEL_MPOP_INTDIS_YUV_OFFSET                                 0
-+#define ATMEL_MPOP_INTDIS_YUV_SIZE                                   1
-+#define ATMEL_MPOP_INTEN                                    0x000000a0
-+#define ATMEL_MPOP_INTEN_EOP                                         3
-+#define ATMEL_MPOP_INTEN_EOP_MASK                           0x00000008
-+#define ATMEL_MPOP_INTEN_EOP_OFFSET                                  3
-+#define ATMEL_MPOP_INTEN_EOP_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_OUT                                         2
-+#define ATMEL_MPOP_INTEN_OUT_MASK                           0x00000004
-+#define ATMEL_MPOP_INTEN_OUT_OFFSET                                  2
-+#define ATMEL_MPOP_INTEN_OUT_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_OVERLAY                                     1
-+#define ATMEL_MPOP_INTEN_OVERLAY_MASK                       0x00000002
-+#define ATMEL_MPOP_INTEN_OVERLAY_OFFSET                              1
-+#define ATMEL_MPOP_INTEN_OVERLAY_SIZE                                1
-+#define ATMEL_MPOP_INTEN_SOP                                         4
-+#define ATMEL_MPOP_INTEN_SOP_MASK                           0x00000010
-+#define ATMEL_MPOP_INTEN_SOP_OFFSET                                  4
-+#define ATMEL_MPOP_INTEN_SOP_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_YUV                                         0
-+#define ATMEL_MPOP_INTEN_YUV_MASK                           0x00000001
-+#define ATMEL_MPOP_INTEN_YUV_OFFSET                                  0
-+#define ATMEL_MPOP_INTEN_YUV_SIZE                                    1
-+#define ATMEL_MPOP_INTMASK                                  0x000000a8
-+#define ATMEL_MPOP_INTMASK_EOP                                       3
-+#define ATMEL_MPOP_INTMASK_EOP_MASK                         0x00000008
-+#define ATMEL_MPOP_INTMASK_EOP_OFFSET                                3
-+#define ATMEL_MPOP_INTMASK_EOP_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_OUT                                       2
-+#define ATMEL_MPOP_INTMASK_OUT_MASK                         0x00000004
-+#define ATMEL_MPOP_INTMASK_OUT_OFFSET                                2
-+#define ATMEL_MPOP_INTMASK_OUT_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_OVERLAY                                   1
-+#define ATMEL_MPOP_INTMASK_OVERLAY_MASK                     0x00000002
-+#define ATMEL_MPOP_INTMASK_OVERLAY_OFFSET                            1
-+#define ATMEL_MPOP_INTMASK_OVERLAY_SIZE                              1
-+#define ATMEL_MPOP_INTMASK_SOP                                       4
-+#define ATMEL_MPOP_INTMASK_SOP_MASK                         0x00000010
-+#define ATMEL_MPOP_INTMASK_SOP_OFFSET                                4
-+#define ATMEL_MPOP_INTMASK_SOP_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_YUV                                       0
-+#define ATMEL_MPOP_INTMASK_YUV_MASK                         0x00000001
-+#define ATMEL_MPOP_INTMASK_YUV_OFFSET                                0
-+#define ATMEL_MPOP_INTMASK_YUV_SIZE                                  1
-+#define ATMEL_MPOP_INTSTATUS                                0x000000ac
-+#define ATMEL_MPOP_INTSTATUS_EOP                                     3
-+#define ATMEL_MPOP_INTSTATUS_EOP_MASK                       0x00000008
-+#define ATMEL_MPOP_INTSTATUS_EOP_OFFSET                              3
-+#define ATMEL_MPOP_INTSTATUS_EOP_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_OUT                                     2
-+#define ATMEL_MPOP_INTSTATUS_OUT_MASK                       0x00000004
-+#define ATMEL_MPOP_INTSTATUS_OUT_OFFSET                              2
-+#define ATMEL_MPOP_INTSTATUS_OUT_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY                                 1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_MASK                   0x00000002
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_OFFSET                          1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_SIZE                            1
-+#define ATMEL_MPOP_INTSTATUS_SOP                                     4
-+#define ATMEL_MPOP_INTSTATUS_SOP_MASK                       0x00000010
-+#define ATMEL_MPOP_INTSTATUS_SOP_OFFSET                              4
-+#define ATMEL_MPOP_INTSTATUS_SOP_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_YUV                                     0
-+#define ATMEL_MPOP_INTSTATUS_YUV_MASK                       0x00000001
-+#define ATMEL_MPOP_INTSTATUS_YUV_OFFSET                              0
-+#define ATMEL_MPOP_INTSTATUS_YUV_SIZE                                1
-+#define ATMEL_MPOP_INVERT                                           25
-+#define ATMEL_MPOP_INVERT_MASK                              0x02000000
-+#define ATMEL_MPOP_INVERT_OFFSET                                    25
-+#define ATMEL_MPOP_INVERT_SIZE                                       1
-+#define ATMEL_MPOP_MSTR_PTR                                 0x0000000c
-+#define ATMEL_MPOP_MSTR_PTR_MASK                            0xffffffff
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR                                 0
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_MASK                   0xffffffff
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_OFFSET                          0
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_SIZE                           32
-+#define ATMEL_MPOP_MSTR_PTR_OFFSET                                   0
-+#define ATMEL_MPOP_MSTR_PTR_SIZE                                    32
-+#define ATMEL_MPOP_O1EN                                              1
-+#define ATMEL_MPOP_O1EN_MASK                                0x00000002
-+#define ATMEL_MPOP_O1EN_OFFSET                                       1
-+#define ATMEL_MPOP_O1EN_SIZE                                         1
-+#define ATMEL_MPOP_O1_POS                                   0x00000050
-+#define ATMEL_MPOP_O1_POS_O1_POS_X                                  11
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_OFFSET                           11
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_SIZE                             11
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y                                   0
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_OFFSET                            0
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_SIZE                             11
-+#define ATMEL_MPOP_O1_POS_X                                         11
-+#define ATMEL_MPOP_O1_POS_X_MASK                            0x003ff800
-+#define ATMEL_MPOP_O1_POS_X_OFFSET                                  11
-+#define ATMEL_MPOP_O1_POS_X_SIZE                                    11
-+#define ATMEL_MPOP_O1_POS_Y                                          0
-+#define ATMEL_MPOP_O1_POS_Y_MASK                            0x000007ff
-+#define ATMEL_MPOP_O1_POS_Y_OFFSET                                   0
-+#define ATMEL_MPOP_O1_POS_Y_SIZE                                    11
-+#define ATMEL_MPOP_O1_SAR                                   0x00000040
-+#define ATMEL_MPOP_O1_SAR_MASK                              0xffffffff
-+#define ATMEL_MPOP_O1_SAR_O1_SAR                                     0
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_MASK                       0xffffffff
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_OFFSET                              0
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_SIZE                               32
-+#define ATMEL_MPOP_O1_SAR_OFFSET                                     0
-+#define ATMEL_MPOP_O1_SAR_SIZE                                      32
-+#define ATMEL_MPOP_O1_SIZE                                  0x00000064
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X                                11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_OFFSET                         11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_SIZE                           11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y                                 0
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_OFFSET                          0
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_SIZE                           11
-+#define ATMEL_MPOP_O1_SIZE_X                                        11
-+#define ATMEL_MPOP_O1_SIZE_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_O1_SIZE_X_OFFSET                                 11
-+#define ATMEL_MPOP_O1_SIZE_X_SIZE                                   11
-+#define ATMEL_MPOP_O1_SIZE_Y                                         0
-+#define ATMEL_MPOP_O1_SIZE_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_O1_SIZE_Y_OFFSET                                  0
-+#define ATMEL_MPOP_O1_SIZE_Y_SIZE                                   11
-+#define ATMEL_MPOP_O1_WTC                                   0x00000074
-+#define ATMEL_MPOP_O1_WTC_MASK                              0xffffffff
-+#define ATMEL_MPOP_O1_WTC_O1_WTC                                     0
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_MASK                       0xffffffff
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_OFFSET                              0
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_SIZE                               32
-+#define ATMEL_MPOP_O1_WTC_OFFSET                                     0
-+#define ATMEL_MPOP_O1_WTC_SIZE                                      32
-+#define ATMEL_MPOP_O2EN                                              2
-+#define ATMEL_MPOP_O2EN_MASK                                0x00000004
-+#define ATMEL_MPOP_O2EN_OFFSET                                       2
-+#define ATMEL_MPOP_O2EN_SIZE                                         1
-+#define ATMEL_MPOP_O2_POS                                   0x00000054
-+#define ATMEL_MPOP_O2_POS_O2_POS_X                                  11
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_OFFSET                           11
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_SIZE                             11
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y                                   0
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_OFFSET                            0
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_SIZE                             11
-+#define ATMEL_MPOP_O2_POS_X                                         11
-+#define ATMEL_MPOP_O2_POS_X_MASK                            0x003ff800
-+#define ATMEL_MPOP_O2_POS_X_OFFSET                                  11
-+#define ATMEL_MPOP_O2_POS_X_SIZE                                    11
-+#define ATMEL_MPOP_O2_POS_Y                                          0
-+#define ATMEL_MPOP_O2_POS_Y_MASK                            0x000007ff
-+#define ATMEL_MPOP_O2_POS_Y_OFFSET                                   0
-+#define ATMEL_MPOP_O2_POS_Y_SIZE                                    11
-+#define ATMEL_MPOP_O2_SAR                                   0x00000044
-+#define ATMEL_MPOP_O2_SAR_MASK                              0xffffffff
-+#define ATMEL_MPOP_O2_SAR_O2_SAR                                     0
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_MASK                       0xffffffff
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_OFFSET                              0
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_SIZE                               32
-+#define ATMEL_MPOP_O2_SAR_OFFSET                                     0
-+#define ATMEL_MPOP_O2_SAR_SIZE                                      32
-+#define ATMEL_MPOP_O2_SIZE                                  0x00000068
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X                                11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_OFFSET                         11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_SIZE                           11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y                                 0
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_OFFSET                          0
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_SIZE                           11
-+#define ATMEL_MPOP_O2_SIZE_X                                        11
-+#define ATMEL_MPOP_O2_SIZE_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_O2_SIZE_X_OFFSET                                 11
-+#define ATMEL_MPOP_O2_SIZE_X_SIZE                                   11
-+#define ATMEL_MPOP_O2_SIZE_Y                                         0
-+#define ATMEL_MPOP_O2_SIZE_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_O2_SIZE_Y_OFFSET                                  0
-+#define ATMEL_MPOP_O2_SIZE_Y_SIZE                                   11
-+#define ATMEL_MPOP_O2_WTC                                   0x00000078
-+#define ATMEL_MPOP_O2_WTC_MASK                              0xffffffff
-+#define ATMEL_MPOP_O2_WTC_O2_WTC                                     0
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_MASK                       0xffffffff
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_OFFSET                              0
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_SIZE                               32
-+#define ATMEL_MPOP_O2_WTC_OFFSET                                     0
-+#define ATMEL_MPOP_O2_WTC_SIZE                                      32
-+#define ATMEL_MPOP_OCR                                      0x00000008
-+#define ATMEL_MPOP_OCR_BGR                                           6
-+#define ATMEL_MPOP_OCR_BGR_MASK                             0x00000040
-+#define ATMEL_MPOP_OCR_BGR_OFFSET                                    6
-+#define ATMEL_MPOP_OCR_BGR_SIZE                                      1
-+#define ATMEL_MPOP_OCR_CURSOREN                                      0
-+#define ATMEL_MPOP_OCR_CURSOREN_MASK                        0x00000001
-+#define ATMEL_MPOP_OCR_CURSOREN_OFFSET                               0
-+#define ATMEL_MPOP_OCR_CURSOREN_SIZE                                 1
-+#define ATMEL_MPOP_OCR_O1EN                                          1
-+#define ATMEL_MPOP_OCR_O1EN_MASK                            0x00000002
-+#define ATMEL_MPOP_OCR_O1EN_OFFSET                                   1
-+#define ATMEL_MPOP_OCR_O1EN_SIZE                                     1
-+#define ATMEL_MPOP_OCR_O2EN                                          2
-+#define ATMEL_MPOP_OCR_O2EN_MASK                            0x00000004
-+#define ATMEL_MPOP_OCR_O2EN_OFFSET                                   2
-+#define ATMEL_MPOP_OCR_O2EN_SIZE                                     1
-+#define ATMEL_MPOP_OCR_RGBEN                                         3
-+#define ATMEL_MPOP_OCR_RGBEN_MASK                           0x00000008
-+#define ATMEL_MPOP_OCR_RGBEN_OFFSET                                  3
-+#define ATMEL_MPOP_OCR_RGBEN_SIZE                                    1
-+#define ATMEL_MPOP_OCR_RGBFORM                                       5
-+#define ATMEL_MPOP_OCR_RGBFORM_MASK                         0x00000020
-+#define ATMEL_MPOP_OCR_RGBFORM_OFFSET                                5
-+#define ATMEL_MPOP_OCR_RGBFORM_SIZE                                  1
-+#define ATMEL_MPOP_OCR_RGBSRC                                        4
-+#define ATMEL_MPOP_OCR_RGBSRC_MASK                          0x00000010
-+#define ATMEL_MPOP_OCR_RGBSRC_OFFSET                                 4
-+#define ATMEL_MPOP_OCR_RGBSRC_SIZE                                   1
-+#define ATMEL_MPOP_OUT                                               2
-+#define ATMEL_MPOP_OUT_BEAR                                 0x0000009c
-+#define ATMEL_MPOP_OUT_BEAR_MASK                            0xffffffff
-+#define ATMEL_MPOP_OUT_BEAR_OFFSET                                   0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR                                 0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_MASK                   0xffffffff
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_OFFSET                          0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_SIZE                           32
-+#define ATMEL_MPOP_OUT_BEAR_SIZE                                    32
-+#define ATMEL_MPOP_OUT_BGR                                           3
-+#define ATMEL_MPOP_OUT_BGR_MASK                             0x00000008
-+#define ATMEL_MPOP_OUT_BGR_OFFSET                                    3
-+#define ATMEL_MPOP_OUT_BGR_SIZE                                      1
-+#define ATMEL_MPOP_OUT_CTRL                                          2
-+#define ATMEL_MPOP_OUT_CTRL_MASK                            0x00000004
-+#define ATMEL_MPOP_OUT_CTRL_OFFSET                                   2
-+#define ATMEL_MPOP_OUT_CTRL_SIZE                                     1
-+#define ATMEL_MPOP_OUT_MASK                                 0x00000004
-+#define ATMEL_MPOP_OUT_OFFSET                                        2
-+#define ATMEL_MPOP_OUT_SIZE                                          1
-+#define ATMEL_MPOP_OVERLAY                                           1
-+#define ATMEL_MPOP_OVERLAY_BEAR                             0x00000098
-+#define ATMEL_MPOP_OVERLAY_BEAR_MASK                        0xffffffff
-+#define ATMEL_MPOP_OVERLAY_BEAR_OFFSET                               0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR                         0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_MASK           0xffffffff
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_OFFSET                  0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_SIZE                   32
-+#define ATMEL_MPOP_OVERLAY_BEAR_SIZE                                32
-+#define ATMEL_MPOP_OVERLAY_MASK                             0x00000002
-+#define ATMEL_MPOP_OVERLAY_OFFSET                                    1
-+#define ATMEL_MPOP_OVERLAY_SIZE                                      1
-+#define ATMEL_MPOP_PALETTEDATA                              0x00000400
-+#define ATMEL_MPOP_R                                                16
-+#define ATMEL_MPOP_R1                                                0
-+#define ATMEL_MPOP_R1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_R1_OFFSET                                         0
-+#define ATMEL_MPOP_R1_SIZE                                          12
-+#define ATMEL_MPOP_R2                                               12
-+#define ATMEL_MPOP_R2R1                                     0x00000014
-+#define ATMEL_MPOP_R2R1_R1                                           0
-+#define ATMEL_MPOP_R2R1_R1_MASK                             0x00000fff
-+#define ATMEL_MPOP_R2R1_R1_OFFSET                                    0
-+#define ATMEL_MPOP_R2R1_R1_SIZE                                     12
-+#define ATMEL_MPOP_R2R1_R2                                          12
-+#define ATMEL_MPOP_R2R1_R2_MASK                             0x00fff000
-+#define ATMEL_MPOP_R2R1_R2_OFFSET                                   12
-+#define ATMEL_MPOP_R2R1_R2_SIZE                                     12
-+#define ATMEL_MPOP_R2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_R2_OFFSET                                        12
-+#define ATMEL_MPOP_R2_SIZE                                          12
-+#define ATMEL_MPOP_R3                                                0
-+#define ATMEL_MPOP_R3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_R3_OFFSET                                         0
-+#define ATMEL_MPOP_R3_SIZE                                          12
-+#define ATMEL_MPOP_R4                                               12
-+#define ATMEL_MPOP_R4R3                                     0x00000018
-+#define ATMEL_MPOP_R4R3_R3                                           0
-+#define ATMEL_MPOP_R4R3_R3_MASK                             0x00000fff
-+#define ATMEL_MPOP_R4R3_R3_OFFSET                                    0
-+#define ATMEL_MPOP_R4R3_R3_SIZE                                     12
-+#define ATMEL_MPOP_R4R3_R4                                          12
-+#define ATMEL_MPOP_R4R3_R4_MASK                             0xfffff000
-+#define ATMEL_MPOP_R4R3_R4_OFFSET                                   12
-+#define ATMEL_MPOP_R4R3_R4_SIZE                                     20
-+#define ATMEL_MPOP_R4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_R4_OFFSET                                        12
-+#define ATMEL_MPOP_R4_SIZE                                          20
-+#define ATMEL_MPOP_RGBEN                                             3
-+#define ATMEL_MPOP_RGBEN_MASK                               0x00000008
-+#define ATMEL_MPOP_RGBEN_OFFSET                                      3
-+#define ATMEL_MPOP_RGBEN_SIZE                                        1
-+#define ATMEL_MPOP_RGBFORM                                           5
-+#define ATMEL_MPOP_RGBFORM_MASK                             0x00000020
-+#define ATMEL_MPOP_RGBFORM_OFFSET                                    5
-+#define ATMEL_MPOP_RGBFORM_SIZE                                      1
-+#define ATMEL_MPOP_RGBSRC                                            4
-+#define ATMEL_MPOP_RGBSRC_MASK                              0x00000010
-+#define ATMEL_MPOP_RGBSRC_OFFSET                                     4
-+#define ATMEL_MPOP_RGBSRC_SIZE                                       1
-+#define ATMEL_MPOP_RGB_POS                                  0x0000004c
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X                                11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_OFFSET                         11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_SIZE                           11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y                                 0
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_OFFSET                          0
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_SIZE                           11
-+#define ATMEL_MPOP_RGB_POS_X                                        11
-+#define ATMEL_MPOP_RGB_POS_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_RGB_POS_X_OFFSET                                 11
-+#define ATMEL_MPOP_RGB_POS_X_SIZE                                   11
-+#define ATMEL_MPOP_RGB_POS_Y                                         0
-+#define ATMEL_MPOP_RGB_POS_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_RGB_POS_Y_OFFSET                                  0
-+#define ATMEL_MPOP_RGB_POS_Y_SIZE                                   11
-+#define ATMEL_MPOP_RGB_SAR                                  0x0000003c
-+#define ATMEL_MPOP_RGB_SAR_MASK                             0xffffffff
-+#define ATMEL_MPOP_RGB_SAR_OFFSET                                    0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR                                   0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_MASK                     0xffffffff
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_OFFSET                            0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_SIZE                             32
-+#define ATMEL_MPOP_RGB_SAR_SIZE                                     32
-+#define ATMEL_MPOP_RGB_SIZE                                 0x00000060
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X                              11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_MASK                 0x003ff800
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_OFFSET                       11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_SIZE                         11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y                               0
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_MASK                 0x000007ff
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_OFFSET                        0
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_SIZE                         11
-+#define ATMEL_MPOP_RGB_SIZE_X                                       11
-+#define ATMEL_MPOP_RGB_SIZE_X_MASK                          0x003ff800
-+#define ATMEL_MPOP_RGB_SIZE_X_OFFSET                                11
-+#define ATMEL_MPOP_RGB_SIZE_X_SIZE                                  11
-+#define ATMEL_MPOP_RGB_SIZE_Y                                        0
-+#define ATMEL_MPOP_RGB_SIZE_Y_MASK                          0x000007ff
-+#define ATMEL_MPOP_RGB_SIZE_Y_OFFSET                                 0
-+#define ATMEL_MPOP_RGB_SIZE_Y_SIZE                                  11
-+#define ATMEL_MPOP_RGB_WTC                                  0x00000070
-+#define ATMEL_MPOP_RGB_WTC_MASK                             0xffffffff
-+#define ATMEL_MPOP_RGB_WTC_OFFSET                                    0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC                                   0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_MASK                     0xffffffff
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_OFFSET                            0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_SIZE                             32
-+#define ATMEL_MPOP_RGB_WTC_SIZE                                     32
-+#define ATMEL_MPOP_R_MASK                                   0x00ff0000
-+#define ATMEL_MPOP_R_OFFSET                                         16
-+#define ATMEL_MPOP_R_SIZE                                            8
-+#define ATMEL_MPOP_SOP                                               4
-+#define ATMEL_MPOP_SOP_MASK                                 0x00000010
-+#define ATMEL_MPOP_SOP_OFFSET                                        4
-+#define ATMEL_MPOP_SOP_SIZE                                          1
-+#define ATMEL_MPOP_START                                             1
-+#define ATMEL_MPOP_START_MASK                               0x00000002
-+#define ATMEL_MPOP_START_OFFSET                                      1
-+#define ATMEL_MPOP_START_SIZE                                        1
-+#define ATMEL_MPOP_STRIDE                                   0x0000002c
-+#define ATMEL_MPOP_STRIDE_MASK                              0xffffffff
-+#define ATMEL_MPOP_STRIDE_OFFSET                                     0
-+#define ATMEL_MPOP_STRIDE_SIZE                                      32
-+#define ATMEL_MPOP_STRIDE_STRIDE                                     0
-+#define ATMEL_MPOP_STRIDE_STRIDE_MASK                       0xffffffff
-+#define ATMEL_MPOP_STRIDE_STRIDE_OFFSET                              0
-+#define ATMEL_MPOP_STRIDE_STRIDE_SIZE                               32
-+#define ATMEL_MPOP_U_SAR                                    0x00000034
-+#define ATMEL_MPOP_U_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_U_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_U_SAR_SIZE                                       32
-+#define ATMEL_MPOP_U_SAR_U_SAR                                       0
-+#define ATMEL_MPOP_U_SAR_U_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_U_SAR_U_SAR_OFFSET                                0
-+#define ATMEL_MPOP_U_SAR_U_SAR_SIZE                                 32
-+#define ATMEL_MPOP_VISIBLE                                          24
-+#define ATMEL_MPOP_VISIBLE_MASK                             0x01000000
-+#define ATMEL_MPOP_VISIBLE_OFFSET                                   24
-+#define ATMEL_MPOP_VISIBLE_SIZE                                      1
-+#define ATMEL_MPOP_V_SAR                                    0x00000038
-+#define ATMEL_MPOP_V_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_V_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_V_SAR_SIZE                                       32
-+#define ATMEL_MPOP_V_SAR_V_SAR                                       0
-+#define ATMEL_MPOP_V_SAR_V_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_V_SAR_V_SAR_OFFSET                                0
-+#define ATMEL_MPOP_V_SAR_V_SAR_SIZE                                 32
-+#define ATMEL_MPOP_XRESIZE                                          16
-+#define ATMEL_MPOP_XRESIZE_MASK                             0x00ff0000
-+#define ATMEL_MPOP_XRESIZE_OFFSET                                   16
-+#define ATMEL_MPOP_XRESIZE_SIZE                                      8
-+#define ATMEL_MPOP_YCR                                      0x00000004
-+#define ATMEL_MPOP_YCR_XRESIZE                                      16
-+#define ATMEL_MPOP_YCR_XRESIZE_MASK                         0x00ff0000
-+#define ATMEL_MPOP_YCR_XRESIZE_OFFSET                               16
-+#define ATMEL_MPOP_YCR_XRESIZE_SIZE                                  8
-+#define ATMEL_MPOP_YCR_YRESIZE                                       8
-+#define ATMEL_MPOP_YCR_YRESIZE_MASK                         0x0000ff00
-+#define ATMEL_MPOP_YCR_YRESIZE_OFFSET                                8
-+#define ATMEL_MPOP_YCR_YRESIZE_SIZE                                  8
-+#define ATMEL_MPOP_YCR_YUVFORMAT                                     0
-+#define ATMEL_MPOP_YCR_YUVFORMAT_MASK                       0x00000003
-+#define ATMEL_MPOP_YCR_YUVFORMAT_OFFSET                              0
-+#define ATMEL_MPOP_YCR_YUVFORMAT_SIZE                                2
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_420              0x00000002
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_422              0x00000001
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_444              0x00000000
-+#define ATMEL_MPOP_YRESIZE                                           8
-+#define ATMEL_MPOP_YRESIZE_MASK                             0x0000ff00
-+#define ATMEL_MPOP_YRESIZE_OFFSET                                    8
-+#define ATMEL_MPOP_YRESIZE_SIZE                                      8
-+#define ATMEL_MPOP_YUV                                               0
-+#define ATMEL_MPOP_YUVFORMAT                                         0
-+#define ATMEL_MPOP_YUVFORMAT_420                            0x00000002
-+#define ATMEL_MPOP_YUVFORMAT_422                            0x00000001
-+#define ATMEL_MPOP_YUVFORMAT_444                            0x00000000
-+#define ATMEL_MPOP_YUVFORMAT_MASK                           0x00000003
-+#define ATMEL_MPOP_YUVFORMAT_OFFSET                                  0
-+#define ATMEL_MPOP_YUVFORMAT_SIZE                                    2
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_420                  0x00000002
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_422                  0x00000001
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_444                  0x00000000
-+#define ATMEL_MPOP_YUV_BEAR                                 0x00000094
-+#define ATMEL_MPOP_YUV_BEAR_MASK                            0xffffffff
-+#define ATMEL_MPOP_YUV_BEAR_OFFSET                                   0
-+#define ATMEL_MPOP_YUV_BEAR_SIZE                                    32
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR                                 0
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_MASK                   0xffffffff
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_OFFSET                          0
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_SIZE                           32
-+#define ATMEL_MPOP_YUV_MASK                                 0x00000001
-+#define ATMEL_MPOP_YUV_MAX_COORD                            0x0000005c
-+#define ATMEL_MPOP_YUV_MAX_COORD_X                                  11
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET                           11
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_SIZE                             11
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y                                   0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X                    11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_MASK       0x003ff800
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_OFFSET             11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_SIZE               11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y                     0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_MASK       0x000007ff
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_OFFSET              0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_SIZE               11
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET                            0
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_SIZE                             11
-+#define ATMEL_MPOP_YUV_OFFSET                                        0
-+#define ATMEL_MPOP_YUV_SIZE                                          1
-+#define ATMEL_MPOP_Y_SAR                                    0x00000030
-+#define ATMEL_MPOP_Y_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_Y_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_Y_SAR_SIZE                                       32
-+#define ATMEL_MPOP_Y_SAR_Y_SAR                                       0
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_OFFSET                                0
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_SIZE                                 32
-+
-+#endif /* __ATMEL_MPOP_H__ */
-diff --git a/localversion-atmel b/localversion-atmel
-new file mode 100644
-index 0000000..b90deba
---- /dev/null
-+++ b/localversion-atmel
-@@ -0,0 +1 @@
-+.atmel.1
-- 
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