Support AT91 in vanilla U-Boot

14 files changed, 2160 insertions, 15 deletions

diff --git a/target/device/Atmel/AT91_Config.in b/target/device/Atmel/AT91_Config.in
index 9d9b8d50e..83021badc 100644
--- a/target/device/Atmel/AT91_Config.in
+++ b/target/device/Atmel/AT91_Config.in
@@ -188,96 +188,132 @@ choice
 config BR2_TARGET_AT91RM9200DF
 	bool "Atmel AT91RM9200 Generic Dataflash(Card) Board Support"
 	depends on BR2_TARGET_AT91RM9200
+	select BR2_BOOTSOURCE_DATAFLASHCARD
 	help
 	  The Atmel AT91RM9200EK Development Board using Dataflashcard
 
 config BR2_TARGET_AT91RM9200SE
 	bool "Atmel AT91RM9200 Generic Dataflash(Card) Board Support (SE)"
 	depends on BR2_TARGET_AT91RM9200
+	select BR2_BOOTSOURCE_DATAFLASHCARD
 	help
 	  The Atmel AT91RM9200EK Development Board using Dataflashcard (SE)
 
 config BR2_TARGET_AT91RM9200EK
 	bool "Atmel AT91RM9200EK Development Board Support"
 	depends on BR2_TARGET_AT91RM9200
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_FLASH
 	help
 	  The Atmel AT91RM9200EK Development Board
 
 config BR2_TARGET_AT91RM9200DK
 	bool "Atmel AT91RM9200DK Development Board Support"
 	depends on BR2_TARGET_AT91RM9200
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_FLASH
 	help
 	  The Atmel AT91RM9200DK Development Board
 
 config BR2_TARGET_AT91SAM9260DFC
 	bool "Atmel AT91SAM9260DFC"
 	depends on BR2_TARGET_AT91SAM9260 || BR2_TARGET_AT91SAM9XE
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
 	help
 	  The Atmel AT91SAM9260 Development Board booting from Dataflashcard
 
 config BR2_TARGET_AT91SAM9260EK
 	bool "Atmel AT91SAM9260EK"
 	depends on BR2_TARGET_AT91SAM9260 || BR2_TARGET_AT91SAM9XE
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91SAM9260 Development Board booting from dataflash
 
 config BR2_TARGET_AT91SAM9G20DFC
 	bool "Atmel AT91SAM9G20DFC"
 	depends on BR2_TARGET_AT91SAM9G20
+	select BR2_BOOTSOURCE_DATAFLASHCARD
 	help
 	  The Atmel AT91SAM9G20 Development Board booting from Dataflashcard
 
 config BR2_TARGET_AT91SAM9G20EK
 	bool "Atmel AT91SAM9G20EK"
 	depends on BR2_TARGET_AT91SAM9G20
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91SAM9G20 Development Board booting from dataflash
 
 config BR2_TARGET_AT91SAM9XEEK
 	bool "Atmel AT91SAM9XE-EK"
 	depends on BR2_TARGET_AT91SAM9260 || BR2_TARGET_AT91SAM9XE
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91SAM9xe Development Board (Not Yet Implemented)
 
 config BR2_TARGET_AT91SAM9261EK
 	bool "Atmel AT91SAM9261EK"
 	depends on BR2_TARGET_AT91SAM9261 || BR2_TARGET_AT91SAM9261S
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91SAM9261 Development Board
 
 config BR2_TARGET_AT91SAM9RL64EK
 	bool "Atmel AT91SAM9RL64EK"
 	depends on BR2_TARGET_AT91SAM9RL64
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
+	select BR2_BOOTSOURCE_SDCARD
 	help
 	  The Atmel AT91SAM9RL64 Development Board
 
 config BR2_TARGET_AT91SAM9262EK
 	bool "Atmel AT91SAM9262EK"
 	depends on BR2_TARGET_AT91SAM9262
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91SAM9262 Development Board (Not Yet Implemented)
 
 config BR2_TARGET_AT91SAM9263EK
 	bool "Atmel AT91SAM9263EK"
 	depends on BR2_TARGET_AT91SAM9263
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91SAM9263 Development Board (Not Yet Implemented)
 
 config BR2_TARGET_AT572D940DCM
 	bool "Atmel AT572D940 Diopsis Computer Module"
 	depends on BR2_TARGET_AT572D940HF
+	select BR2_BOOTSOURCE_FLASH
+	select BR2_BOOTSOURCE_SDCARD
 	help
 	  The Atmel Diopsis CPU Module (Not Yet Implemented)
 
 config BR2_TARGET_AT91CAP9DK
 	bool "Atmel AT91CAP9DK"
 	depends on BR2_TARGET_AT91CAP9
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91CAP9 Development Kit (Not Yet Implemented)
 
 config BR2_TARGET_AT91CAP9STK
 	bool "Atmel AT91CAP9STK"
 	depends on BR2_TARGET_AT91CAP9
+	select BR2_BOOTSOURCE_DATAFLASHCARD
+	select BR2_BOOTSOURCE_DATAFLASH
+	select BR2_BOOTSOURCE_NANDFLASH
 	help
 	  The Atmel AT91CAP9 Starter Kit (Not Yet Implemented)
 
@@ -304,3 +340,4 @@ config BR2_TARGET_AT91SAM9261EK_SPIMODE3
 
 endchoice
 
+
diff --git a/target/device/Atmel/Makefile.in b/target/device/Atmel/Makefile.in
index 117a7c252..342b129de 100644
--- a/target/device/Atmel/Makefile.in
+++ b/target/device/Atmel/Makefile.in
@@ -49,7 +49,7 @@ LINUX26_COPYTO:=/tftpboot
 
 # The board specific Makefile.in can redefine BOARD_NAME's
 LINUX_BOARD_NAME:=$(BOARD_NAME)
-UBOOT_BOARD_NAME:=$(BOARD_NAME)
+#UBOOT_BOARD_NAME:=$(BOARD_NAME)
 DFB_BOARD_NAME:=$(BOARD_NAME)
 
 #BR2_PACKAGE_BUSYBOX_CONFIG:=$(BR2_BOARD_PATH)/busybox-$(BR2_BUSYBOX_VERSION).config
@@ -84,6 +84,8 @@ atmel_status:
 	@echo DOWNLOAD_LINUX26_VERSION=$(DOWNLOAD_LINUX26_VERSION)
 	@echo LINUX_SOURCE=$(LINUX_SOURCE)
 	@echo TARGETS=$(TARGETS)
+	@echo ALLAN=$(ALLAN)
+
 
 #TARGETS+=atmel_status
 endif
diff --git a/target/device/Atmel/at91rm9200df/Makefile.in b/target/device/Atmel/at91rm9200df/Makefile.in
index 95b5ba7a2..12219c8d7 100644
--- a/target/device/Atmel/at91rm9200df/Makefile.in
+++ b/target/device/Atmel/at91rm9200df/Makefile.in
@@ -1,6 +1,7 @@
-ifeq ($(strip$(BOARD_NAME)),at91rm9200df)
+ifeq ($(strip $(BOARD_NAME)),at91rm9200df)
 LINUX_BOARD_NAME=at91rm9200ek
 BR2_PACKAGE_BUSYBOX_CONFIG:=$(BOARD_PATH)/busybox-1.7.1.config
+UBOOT_BOARD_NAME:=at91rm9200df
 endif
 
 
diff --git a/target/device/Atmel/at91sam9260dfc/Makefile.in b/target/device/Atmel/at91sam9260dfc/Makefile.in
index e10b007b6..50b8e3ca5 100644
--- a/target/device/Atmel/at91sam9260dfc/Makefile.in
+++ b/target/device/Atmel/at91sam9260dfc/Makefile.in
@@ -1,4 +1,20 @@
-ifeq ($(strip$(BOARD_NAME)),at91sam9260dfc)
+ifeq ($(strip $(BOARD_NAME)),at91sam9260dfc)
 LINUX26_BOARD_NAME=at91sam9260ek
 BR2_PACKAGE_BUSYBOX_CONFIG:=$(BOARD_PATH)/busybox-1.9.1.config
+
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD),)
+UBOOT_BOARD_NAME:=at91sam9260ek_dataflash_cs0
+else
+UBOOT_BOARD_NAME:=at91sam9260ek_dataflash_cs0x
 endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH),)
+UBOOT_BOARD_NAME:=at91sam9260ek_dataflash_cs1
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH),)
+UBOOT_BOARD_NAME:=at91sam9260ek_nandflash
+endif
+ALLAN=1
+else
+ALLAN=2
+endif
+
diff --git a/target/device/Atmel/at91sam9261ek/Makefile.in b/target/device/Atmel/at91sam9261ek/Makefile.in
index 7bd61a423..e9074485f 100644
--- a/target/device/Atmel/at91sam9261ek/Makefile.in
+++ b/target/device/Atmel/at91sam9261ek/Makefile.in
@@ -1,3 +1,12 @@
 ifeq ($(strip $(BOARD_NAME)),at91sam9261ek)
 BR2_PACKAGE_BUSYBOX_CONFIG:=$(BOARD_PATH)/busybox-1.6.0.config
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD),)
+UBOOT_BOARD_NAME:=at91sam9261ek_dataflash_cs0
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH),)
+UBOOT_BOARD_NAME:=at91sam9261ek_dataflash_cs0
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH),)
+UBOOT_BOARD_NAME:=at91sam9261ek_nandflash
+endif
 endif
diff --git a/target/device/Atmel/at91sam9263ek/Makefile.in b/target/device/Atmel/at91sam9263ek/Makefile.in
index e10adb4b1..dce340765 100644
--- a/target/device/Atmel/at91sam9263ek/Makefile.in
+++ b/target/device/Atmel/at91sam9263ek/Makefile.in
@@ -1,3 +1,12 @@
 ifeq ($(strip $(BOARD_NAME)),at91sam9263ek)
 BR2_PACKAGE_BUSYBOX_CONFIG:=$(BOARD_PATH)/busybox-1.6.0.config
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD),)
+UBOOT_BOARD_NAME:=at91sam9263ek_dataflash_cs0
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH),)
+UBOOT_BOARD_NAME:=at91sam9263ek_dataflash_cs0
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH),)
+UBOOT_BOARD_NAME:=at91sam9263ek_nandflash
+endif
 endif
diff --git a/target/device/Atmel/at91sam9g20dfc/Makefile.in b/target/device/Atmel/at91sam9g20dfc/Makefile.in
index bcd9e58f1..79135c876 100644
--- a/target/device/Atmel/at91sam9g20dfc/Makefile.in
+++ b/target/device/Atmel/at91sam9g20dfc/Makefile.in
@@ -1,4 +1,13 @@
-ifeq ($(strip$(BOARD_NAME)),at91sam9g20dfc)
+ifeq ($(strip $(BOARD_NAME)),at91sam9g20dfc)
 LINUX26_BOARD_NAME=at91sam9g20ek
 BR2_PACKAGE_BUSYBOX_CONFIG:=$(BOARD_PATH)/busybox-1.9.1.config
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD),)
+UBOOT_BOARD_NAME:=at91sam9g20ek_dataflash_cs0
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH),)
+UBOOT_BOARD_NAME:=at91sam9g20ek_dataflash_cs0
+endif
+ifneq ($(BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH),)
+UBOOT_BOARD_NAME:=at91sam9g20ek_nandflash
+endif
 endif
diff --git a/target/device/Atmel/u-boot/Config.in b/target/device/Atmel/u-boot/Config.in
index 40764512a..ca1398169 100644
--- a/target/device/Atmel/u-boot/Config.in
+++ b/target/device/Atmel/u-boot/Config.in
@@ -2,9 +2,11 @@ config BR2_TARGET_UBOOT_AT91
 	bool "Das U-Boot Boot Monitor"
 	depends on BR2_TARGET_AT91 && !BR2_TARGET_AT91SAM9G20
 	depends on !BR2_TARGET_AT91SAM9260PF
+	select BR2_TARGET_CUSTOM_UBOOT
 	help
-	  Build "Das U-Boot" Boot Monitor
+	  Build "Das U-Boot" Boot Monitor for AT91
 
+if BR2_TARGET_UBOOT_AT91
 config BR2_TARGET_UBOOT_SERVERIP_AT91
 	string "server ip"
 	depends on BR2_TARGET_UBOOT_AT91
@@ -40,4 +42,5 @@ config BR2_TARGET_UBOOT_ETHADDR_AT91
 	help
 	  Target ip address, this should be changed for production units
 
+endif
 
diff --git a/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-001-at91rm9200.patch b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-001-at91rm9200.patch
new file mode 100644
index 000000000..0445b2329
--- /dev/null
+++ b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-001-at91rm9200.patch
@@ -0,0 +1,723 @@
+diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pio.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pio.h
+--- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pio.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pio.h	2009-01-01 14:02:28.000000000 +0100
+@@ -0,0 +1,49 @@
++/*
++ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Parallel I/O Controller (PIO) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PIO_H
++#define AT91_PIO_H
++
++#define PIO_PER		0x00	/* Enable Register */
++#define PIO_PDR		0x04	/* Disable Register */
++#define PIO_PSR		0x08	/* Status Register */
++#define PIO_OER		0x10	/* Output Enable Register */
++#define PIO_ODR		0x14	/* Output Disable Register */
++#define PIO_OSR		0x18	/* Output Status Register */
++#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
++#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
++#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
++#define PIO_SODR	0x30	/* Set Output Data Register */
++#define PIO_CODR	0x34	/* Clear Output Data Register */
++#define PIO_ODSR	0x38	/* Output Data Status Register */
++#define PIO_PDSR	0x3c	/* Pin Data Status Register */
++#define PIO_IER		0x40	/* Interrupt Enable Register */
++#define PIO_IDR		0x44	/* Interrupt Disable Register */
++#define PIO_IMR		0x48	/* Interrupt Mask Register */
++#define PIO_ISR		0x4c	/* Interrupt Status Register */
++#define PIO_MDER	0x50	/* Multi-driver Enable Register */
++#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
++#define PIO_MDSR	0x58	/* Multi-driver Status Register */
++#define PIO_PUDR	0x60	/* Pull-up Disable Register */
++#define PIO_PUER	0x64	/* Pull-up Enable Register */
++#define PIO_PUSR	0x68	/* Pull-up Status Register */
++#define PIO_ASR		0x70	/* Peripheral A Select Register */
++#define PIO_BSR		0x74	/* Peripheral B Select Register */
++#define PIO_ABSR	0x78	/* AB Status Register */
++#define PIO_OWER	0xa0	/* Output Write Enable Register */
++#define PIO_OWDR	0xa4	/* Output Write Disable Register */
++#define PIO_OWSR	0xa8	/* Output Write Status Register */
++
++#endif
+diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pmc.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pmc.h
+--- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/at91_pmc.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/at91_pmc.h	2009-01-01 15:51:28.000000000 +0100
+@@ -0,0 +1,116 @@
++/*
++ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h]
++ *
++ * Copyright (C) 2005 Ivan Kokshaysky
++ * Copyright (C) SAN People
++ *
++ * Copyright (C) 2008 Ulf Samuelsson
++ *
++ * Power Management Controller (PMC) - System peripherals registers.
++ * Based on AT91RM9200 datasheet revision E.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef AT91_PMC_H
++#define AT91_PMC_H
++
++#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
++#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
++
++#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
++#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
++#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
++#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
++#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
++#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
++#define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
++#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
++#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
++#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
++#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
++#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
++#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
++#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
++#define	AT91_PMC_RES_0C		(AT91_PMC + 0x0c)	/* Reserved */
++
++#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
++#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
++#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
++#define	AT91_PMC_RES_1C		(AT91_PMC + 0x1c)	/* Reserved */
++
++
++#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
++#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
++#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [AT91SAM926x only] */
++#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
++
++#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
++#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
++#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
++
++#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
++#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
++#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
++#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
++#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
++#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
++#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
++#define			AT91_PMC_USBDIV_1		(0 << 28)
++#define			AT91_PMC_USBDIV_2		(1 << 28)
++#define			AT91_PMC_USBDIV_4		(2 << 28)
++#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
++
++#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
++#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
++#define			AT91_PMC_CSS_SLOW		(0 << 0)
++#define			AT91_PMC_CSS_MAIN		(1 << 0)
++#define			AT91_PMC_CSS_PLLA		(2 << 0)
++#define			AT91_PMC_CSS_PLLB		(3 << 0)
++#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
++#define			AT91_PMC_PRES_1			(0 << 2)
++#define			AT91_PMC_PRES_2			(1 << 2)
++#define			AT91_PMC_PRES_4			(2 << 2)
++#define			AT91_PMC_PRES_8			(3 << 2)
++#define			AT91_PMC_PRES_16		(4 << 2)
++#define			AT91_PMC_PRES_32		(5 << 2)
++#define			AT91_PMC_PRES_64		(6 << 2)
++#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
++#define			AT91_PMC_MDIV_1			(0 << 8)
++#define			AT91_PMC_MDIV_2			(1 << 8)
++#define			AT91_PMC_MDIV_3			(2 << 8)
++#define			AT91_PMC_MDIV_4			(3 << 8)
++
++#define	AT91_PMC_RES_34		(AT91_PMC + 0x34)	/* Reserved */
++#define	AT91_PMC_RES_38		(AT91_PMC + 0x38)	/* Reserved */
++#define	AT91_PMC_RES_3C		(AT91_PMC + 0x3c)	/* Reserved */
++
++#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
++
++#define	AT91_PMC_RES_50		(AT91_PMC + 0x50)	/* Reserved */
++#define	AT91_PMC_RES_54		(AT91_PMC + 0x54)	/* Reserved */
++#define	AT91_PMC_RES_58		(AT91_PMC + 0x58)	/* Reserved */
++#define	AT91_PMC_RES_5C		(AT91_PMC + 0x5c)	/* Reserved */
++
++#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
++#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
++#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
++#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
++#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
++#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
++#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
++#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
++#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
++#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
++#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
++#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
++
++#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
++#define		AT91_PMC_PROTKEY	0x504d4301		/* Activation Code */
++
++#define AT91_PMC_VER	(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
++
++#endif
+diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/AT91RM9200.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+--- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/AT91RM9200.h	2009-01-01 13:09:34.000000000 +0100
++++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/AT91RM9200.h	2009-01-01 15:52:00.000000000 +0100
+@@ -28,6 +28,114 @@
+ #ifndef __ASSEMBLY__
+ typedef volatile unsigned int AT91_REG;		/* Hardware register definition */
+ 
++/*
++ * Peripheral identifiers/interrupts.
++ */
++#define AT91RM9200_ID_AIC	0	/* Advanced Interrupt Controller (FIQ) */
++#define AT91RM9200_ID_SYSIRQ	1	/* System Peripherals */
++#define AT91RM9200_ID_PIOA	2	/* Parallel IO Controller A */
++#define AT91RM9200_ID_PIOB	3	/* Parallel IO Controller B */
++#define AT91RM9200_ID_PIOC	4	/* Parallel IO Controller C */
++#define AT91RM9200_ID_PIOD	5	/* Parallel IO Controller D */
++#define AT91RM9200_ID_US0	6	/* USART 0 */
++#define AT91RM9200_ID_US1	7	/* USART 1 */
++#define AT91RM9200_ID_US2	8	/* USART 2 */
++#define AT91RM9200_ID_US3	9	/* USART 2 */
++#define AT91RM9200_ID_MCI	10	/* Multimedia Card Interface */
++#define AT91RM9200_ID_UDP	11	/* USB Device Port */
++#define AT91RM9200_ID_TWI	12	/* Two-Wire Interface */
++#define AT91RM9200_ID_SPI0	13	/* Serial Peripheral Interface 0 */
++#define AT91RM9200_ID_SSC0	14	/* Serial Synchronous Controller */
++#define AT91RM9200_ID_SSC1	15	/* Serial Synchronous Controller */
++#define AT91RM9200_ID_SSC2	16	/* Serial Synchronous Controller */
++#define AT91RM9200_ID_TC0	17	/* Timer Counter 0 */
++#define AT91RM9200_ID_TC1	18	/* Timer Counter 1 */
++#define AT91RM9200_ID_TC2	19	/* Timer Counter 2 */
++#define AT91RM9200_ID_TC3	20	/* Timer Counter 3 */
++#define AT91RM9200_ID_TC4	21	/* Timer Counter 4 */
++#define AT91RM9200_ID_TC5	22	/* Timer Counter 5 */
++#define AT91RM9200_ID_UHP	23	/* USB Host port */
++#define AT91RM9200_ID_EMAC	24	/* Ethernet */
++#define AT91RM9200_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */
++#define AT91RM9200_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */
++#define AT91RM9200_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */
++#define AT91RM9200_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */
++#define AT91RM9200_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */
++#define AT91RM9200_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */
++#define AT91RM9200_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */
++/*
++ * User Peripheral physical base addresses.
++ */
++
++
++
++#define AT91RM9200_BASE_TC0	0xFFFA0000 /* (TC0) Base Address */
++#define AT91RM9200_BASE_TC1	0xFFFA4000 /* (TC0) Base Address */
++#define AT91RM9200_BASE_UDP	0xFFFB0000 /* (TC0) Base Address */
++#define AT91RM9200_BASE_MCI	0xFFFB4000 /* (TC0) Base Address */
++#define AT91RM9200_BASE_TWI	0xFFFB8000 /* (TC0) Base Address */
++#define AT91RM9200_BASE_EMAC	0xFFFBC000 /* (EMAC) Base Address */
++#define AT91RM9200_BASE_US0	0xFFFC0000 /* (US0) Base Address */
++#define AT91RM9200_BASE_US1	0xFFFC4000 /* (US1) Base Address */
++#define AT91RM9200_BASE_US2	0xFFFC8000 /* (US1) Base Address */
++#define AT91RM9200_BASE_US3	0xFFFCC000 /* (US1) Base Address */
++#define AT91RM9200_BASE_SPI	0xFFFE0000 /* (SPI) Base Address */
++
++#define AT91RM9200_BASE_AIC	0xFFFFF000 /* (AIC) Base Address */
++#define AT91RM9200_BASE_DBGU	0xFFFFF200 /* (DBGU) Base Address */
++#define AT91RM9200_BASE_PIOA	0xFFFFF400 /* (PIOA) Base Address */
++#define AT91RM9200_BASE_PIOB	0xFFFFF600 /* (PIOB) Base Address */
++#define AT91RM9200_BASE_PIOC	0xFFFFF800 /* (PIOC) Base Address */
++#define AT91RM9200_BASE_PIOD	0xFFFFFA00 /* (PIOC) Base Address */
++#define AT91RM9200_BASE_PMC	0xFFFFFC00 /* (PMC) Base Address */
++#define AT91RM9200_BASE_CKGR	0xFFFFFC20 /* (CKGR) Base Address */
++#define AT91RM9200_BASE_ST	0xFFFFFD00 /* (PMC) Base Address */
++#define AT91RM9200_BASE_RTC	0xFFFFFE00 /* (PMC) Base Address */
++#define AT91RM9200_BASE_MC	0xFFFFFF00 /* (PMC) Base Address */
++#define AT91RM9200_BASE_EBI	0xFFFFFF60 /* (PMC) Base Address */
++#define AT91RM9200_BASE_SMC2	0xFFFFFF70 /* (SMC2) Base Address */
++#define AT91RM9200_BASE_SDRAMC	0xFFFFFF90 /* (SMC2) Base Address */
++#define AT91RM9200_BASE_BFC	0xFFFFFFC0 /* (SMC2) Base Address */
++
++/*
++ * System Peripherals (offset from AT91_BASE_SYS)
++ */
++#define AT91_BASE_SYS		AT91RM9200_BASE_AIC
++
++#define AT91_AIC		(AT91RM9200_BASE_AIC	- AT91_BASE_SYS)
++#define AT91_DBGU		(AT91RM9200_BASE_DBGU	- AT91_BASE_SYS)
++#define AT91_PIOA		(AT91RM9200_BASE_PIOA	- AT91_BASE_SYS)
++#define AT91_PIOB		(AT91RM9200_BASE_PIOB	- AT91_BASE_SYS)
++#define AT91_PIOC		(AT91RM9200_BASE_PIOC	- AT91_BASE_SYS)
++#define AT91_PIOD		(AT91RM9200_BASE_PIOD	- AT91_BASE_SYS)
++#define AT91_PMC		(AT91RM9200_BASE_PMC	- AT91_BASE_SYS)
++#define AT91_PMC		(AT91RM9200_BASE_PMC	- AT91_BASE_SYS)
++#define AT91_PMC		(AT91RM9200_BASE_PMC	- AT91_BASE_SYS)
++#define AT91_PMC		(AT91RM9200_BASE_PMC	- AT91_BASE_SYS)
++#define AT91_PMC		(AT91RM9200_BASE_PMC	- AT91_BASE_SYS)
++
++#define AT91_CKGR		(AT91RM9200_BASE_CKGR	- AT91_BASE_SYS)
++#define AT91_ST			(AT91RM9200_BASE_ST	- AT91_BASE_SYS)
++#define AT91_RTC		(AT91RM9200_BASE_RTC	- AT91_BASE_SYS)
++#define AT91_MC			(AT91RM9200_BASE_MC	- AT91_BASE_SYS)
++#define AT91_EBI		(AT91RM9200_BASE_EBI	- AT91_BASE_SYS)
++#define 	AT91_EBI_CSA		((AT91RM9200_BASE_EBI +0x00)	- AT91_BASE_SYS)
++#define AT91_SMC2		(AT91RM9200_BASE_SMC2	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR0		((AT91RM9200_BASE_SMC2+0x00)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR1		((AT91RM9200_BASE_SMC2+0x04)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR2		((AT91RM9200_BASE_SMC2+0x08)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR3		((AT91RM9200_BASE_SMC2+0x0c)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR4		((AT91RM9200_BASE_SMC2+0x10)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR5		((AT91RM9200_BASE_SMC2+0x14)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR6		((AT91RM9200_BASE_SMC2+0x18)	- AT91_BASE_SYS)
++#define		AT91_SMC2_CSR7		((AT91RM9200_BASE_SMC2+0x1c)	- AT91_BASE_SYS)
++
++
++#define AT91_USART0		AT91RM9200_BASE_US0
++#define AT91_USART1		AT91RM9200_BASE_US1
++#define AT91_USART2		AT91RM9200_BASE_US2
++#define AT91_USART3		AT91RM9200_BASE_US3
++
+ /*****************************************************************************/
+ /*        SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface       */
+ /*****************************************************************************/
+diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/gpio.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/gpio.h
+--- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/gpio.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/gpio.h	2009-01-01 14:02:11.000000000 +0100
+@@ -0,0 +1,367 @@
++/*
++ * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
++ *
++ *  Copyright (C) 2005 HP Labs
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#ifndef __ASM_ARCH_AT91_GPIO_H
++#define __ASM_ARCH_AT91_GPIO_H
++
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/arch/at91_pio.h>
++#include <asm/arch/hardware.h>
++
++#define PIN_BASE		32
++
++#define MAX_GPIO_BANKS		5
++
++/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
++
++#define	AT91_PIN_PA0	(PIN_BASE + 0x00 + 0)
++#define	AT91_PIN_PA1	(PIN_BASE + 0x00 + 1)
++#define	AT91_PIN_PA2	(PIN_BASE + 0x00 + 2)
++#define	AT91_PIN_PA3	(PIN_BASE + 0x00 + 3)
++#define	AT91_PIN_PA4	(PIN_BASE + 0x00 + 4)
++#define	AT91_PIN_PA5	(PIN_BASE + 0x00 + 5)
++#define	AT91_PIN_PA6	(PIN_BASE + 0x00 + 6)
++#define	AT91_PIN_PA7	(PIN_BASE + 0x00 + 7)
++#define	AT91_PIN_PA8	(PIN_BASE + 0x00 + 8)
++#define	AT91_PIN_PA9	(PIN_BASE + 0x00 + 9)
++#define	AT91_PIN_PA10	(PIN_BASE + 0x00 + 10)
++#define	AT91_PIN_PA11	(PIN_BASE + 0x00 + 11)
++#define	AT91_PIN_PA12	(PIN_BASE + 0x00 + 12)
++#define	AT91_PIN_PA13	(PIN_BASE + 0x00 + 13)
++#define	AT91_PIN_PA14	(PIN_BASE + 0x00 + 14)
++#define	AT91_PIN_PA15	(PIN_BASE + 0x00 + 15)
++#define	AT91_PIN_PA16	(PIN_BASE + 0x00 + 16)
++#define	AT91_PIN_PA17	(PIN_BASE + 0x00 + 17)
++#define	AT91_PIN_PA18	(PIN_BASE + 0x00 + 18)
++#define	AT91_PIN_PA19	(PIN_BASE + 0x00 + 19)
++#define	AT91_PIN_PA20	(PIN_BASE + 0x00 + 20)
++#define	AT91_PIN_PA21	(PIN_BASE + 0x00 + 21)
++#define	AT91_PIN_PA22	(PIN_BASE + 0x00 + 22)
++#define	AT91_PIN_PA23	(PIN_BASE + 0x00 + 23)
++#define	AT91_PIN_PA24	(PIN_BASE + 0x00 + 24)
++#define	AT91_PIN_PA25	(PIN_BASE + 0x00 + 25)
++#define	AT91_PIN_PA26	(PIN_BASE + 0x00 + 26)
++#define	AT91_PIN_PA27	(PIN_BASE + 0x00 + 27)
++#define	AT91_PIN_PA28	(PIN_BASE + 0x00 + 28)
++#define	AT91_PIN_PA29	(PIN_BASE + 0x00 + 29)
++#define	AT91_PIN_PA30	(PIN_BASE + 0x00 + 30)
++#define	AT91_PIN_PA31	(PIN_BASE + 0x00 + 31)
++
++#define	AT91_PIN_PB0	(PIN_BASE + 0x20 + 0)
++#define	AT91_PIN_PB1	(PIN_BASE + 0x20 + 1)
++#define	AT91_PIN_PB2	(PIN_BASE + 0x20 + 2)
++#define	AT91_PIN_PB3	(PIN_BASE + 0x20 + 3)
++#define	AT91_PIN_PB4	(PIN_BASE + 0x20 + 4)
++#define	AT91_PIN_PB5	(PIN_BASE + 0x20 + 5)
++#define	AT91_PIN_PB6	(PIN_BASE + 0x20 + 6)
++#define	AT91_PIN_PB7	(PIN_BASE + 0x20 + 7)
++#define	AT91_PIN_PB8	(PIN_BASE + 0x20 + 8)
++#define	AT91_PIN_PB9	(PIN_BASE + 0x20 + 9)
++#define	AT91_PIN_PB10	(PIN_BASE + 0x20 + 10)
++#define	AT91_PIN_PB11	(PIN_BASE + 0x20 + 11)
++#define	AT91_PIN_PB12	(PIN_BASE + 0x20 + 12)
++#define	AT91_PIN_PB13	(PIN_BASE + 0x20 + 13)
++#define	AT91_PIN_PB14	(PIN_BASE + 0x20 + 14)
++#define	AT91_PIN_PB15	(PIN_BASE + 0x20 + 15)
++#define	AT91_PIN_PB16	(PIN_BASE + 0x20 + 16)
++#define	AT91_PIN_PB17	(PIN_BASE + 0x20 + 17)
++#define	AT91_PIN_PB18	(PIN_BASE + 0x20 + 18)
++#define	AT91_PIN_PB19	(PIN_BASE + 0x20 + 19)
++#define	AT91_PIN_PB20	(PIN_BASE + 0x20 + 20)
++#define	AT91_PIN_PB21	(PIN_BASE + 0x20 + 21)
++#define	AT91_PIN_PB22	(PIN_BASE + 0x20 + 22)
++#define	AT91_PIN_PB23	(PIN_BASE + 0x20 + 23)
++#define	AT91_PIN_PB24	(PIN_BASE + 0x20 + 24)
++#define	AT91_PIN_PB25	(PIN_BASE + 0x20 + 25)
++#define	AT91_PIN_PB26	(PIN_BASE + 0x20 + 26)
++#define	AT91_PIN_PB27	(PIN_BASE + 0x20 + 27)
++#define	AT91_PIN_PB28	(PIN_BASE + 0x20 + 28)
++#define	AT91_PIN_PB29	(PIN_BASE + 0x20 + 29)
++#define	AT91_PIN_PB30	(PIN_BASE + 0x20 + 30)
++#define	AT91_PIN_PB31	(PIN_BASE + 0x20 + 31)
++
++#define	AT91_PIN_PC0	(PIN_BASE + 0x40 + 0)
++#define	AT91_PIN_PC1	(PIN_BASE + 0x40 + 1)
++#define	AT91_PIN_PC2	(PIN_BASE + 0x40 + 2)
++#define	AT91_PIN_PC3	(PIN_BASE + 0x40 + 3)
++#define	AT91_PIN_PC4	(PIN_BASE + 0x40 + 4)
++#define	AT91_PIN_PC5	(PIN_BASE + 0x40 + 5)
++#define	AT91_PIN_PC6	(PIN_BASE + 0x40 + 6)
++#define	AT91_PIN_PC7	(PIN_BASE + 0x40 + 7)
++#define	AT91_PIN_PC8	(PIN_BASE + 0x40 + 8)
++#define	AT91_PIN_PC9	(PIN_BASE + 0x40 + 9)
++#define	AT91_PIN_PC10	(PIN_BASE + 0x40 + 10)
++#define	AT91_PIN_PC11	(PIN_BASE + 0x40 + 11)
++#define	AT91_PIN_PC12	(PIN_BASE + 0x40 + 12)
++#define	AT91_PIN_PC13	(PIN_BASE + 0x40 + 13)
++#define	AT91_PIN_PC14	(PIN_BASE + 0x40 + 14)
++#define	AT91_PIN_PC15	(PIN_BASE + 0x40 + 15)
++#define	AT91_PIN_PC16	(PIN_BASE + 0x40 + 16)
++#define	AT91_PIN_PC17	(PIN_BASE + 0x40 + 17)
++#define	AT91_PIN_PC18	(PIN_BASE + 0x40 + 18)
++#define	AT91_PIN_PC19	(PIN_BASE + 0x40 + 19)
++#define	AT91_PIN_PC20	(PIN_BASE + 0x40 + 20)
++#define	AT91_PIN_PC21	(PIN_BASE + 0x40 + 21)
++#define	AT91_PIN_PC22	(PIN_BASE + 0x40 + 22)
++#define	AT91_PIN_PC23	(PIN_BASE + 0x40 + 23)
++#define	AT91_PIN_PC24	(PIN_BASE + 0x40 + 24)
++#define	AT91_PIN_PC25	(PIN_BASE + 0x40 + 25)
++#define	AT91_PIN_PC26	(PIN_BASE + 0x40 + 26)
++#define	AT91_PIN_PC27	(PIN_BASE + 0x40 + 27)
++#define	AT91_PIN_PC28	(PIN_BASE + 0x40 + 28)
++#define	AT91_PIN_PC29	(PIN_BASE + 0x40 + 29)
++#define	AT91_PIN_PC30	(PIN_BASE + 0x40 + 30)
++#define	AT91_PIN_PC31	(PIN_BASE + 0x40 + 31)
++
++#define	AT91_PIN_PD0	(PIN_BASE + 0x60 + 0)
++#define	AT91_PIN_PD1	(PIN_BASE + 0x60 + 1)
++#define	AT91_PIN_PD2	(PIN_BASE + 0x60 + 2)
++#define	AT91_PIN_PD3	(PIN_BASE + 0x60 + 3)
++#define	AT91_PIN_PD4	(PIN_BASE + 0x60 + 4)
++#define	AT91_PIN_PD5	(PIN_BASE + 0x60 + 5)
++#define	AT91_PIN_PD6	(PIN_BASE + 0x60 + 6)
++#define	AT91_PIN_PD7	(PIN_BASE + 0x60 + 7)
++#define	AT91_PIN_PD8	(PIN_BASE + 0x60 + 8)
++#define	AT91_PIN_PD9	(PIN_BASE + 0x60 + 9)
++#define	AT91_PIN_PD10	(PIN_BASE + 0x60 + 10)
++#define	AT91_PIN_PD11	(PIN_BASE + 0x60 + 11)
++#define	AT91_PIN_PD12	(PIN_BASE + 0x60 + 12)
++#define	AT91_PIN_PD13	(PIN_BASE + 0x60 + 13)
++#define	AT91_PIN_PD14	(PIN_BASE + 0x60 + 14)
++#define	AT91_PIN_PD15	(PIN_BASE + 0x60 + 15)
++#define	AT91_PIN_PD16	(PIN_BASE + 0x60 + 16)
++#define	AT91_PIN_PD17	(PIN_BASE + 0x60 + 17)
++#define	AT91_PIN_PD18	(PIN_BASE + 0x60 + 18)
++#define	AT91_PIN_PD19	(PIN_BASE + 0x60 + 19)
++#define	AT91_PIN_PD20	(PIN_BASE + 0x60 + 20)
++#define	AT91_PIN_PD21	(PIN_BASE + 0x60 + 21)
++#define	AT91_PIN_PD22	(PIN_BASE + 0x60 + 22)
++#define	AT91_PIN_PD23	(PIN_BASE + 0x60 + 23)
++#define	AT91_PIN_PD24	(PIN_BASE + 0x60 + 24)
++#define	AT91_PIN_PD25	(PIN_BASE + 0x60 + 25)
++#define	AT91_PIN_PD26	(PIN_BASE + 0x60 + 26)
++#define	AT91_PIN_PD27	(PIN_BASE + 0x60 + 27)
++#define	AT91_PIN_PD28	(PIN_BASE + 0x60 + 28)
++#define	AT91_PIN_PD29	(PIN_BASE + 0x60 + 29)
++#define	AT91_PIN_PD30	(PIN_BASE + 0x60 + 30)
++#define	AT91_PIN_PD31	(PIN_BASE + 0x60 + 31)
++
++#define	AT91_PIN_PE0	(PIN_BASE + 0x80 + 0)
++#define	AT91_PIN_PE1	(PIN_BASE + 0x80 + 1)
++#define	AT91_PIN_PE2	(PIN_BASE + 0x80 + 2)
++#define	AT91_PIN_PE3	(PIN_BASE + 0x80 + 3)
++#define	AT91_PIN_PE4	(PIN_BASE + 0x80 + 4)
++#define	AT91_PIN_PE5	(PIN_BASE + 0x80 + 5)
++#define	AT91_PIN_PE6	(PIN_BASE + 0x80 + 6)
++#define	AT91_PIN_PE7	(PIN_BASE + 0x80 + 7)
++#define	AT91_PIN_PE8	(PIN_BASE + 0x80 + 8)
++#define	AT91_PIN_PE9	(PIN_BASE + 0x80 + 9)
++#define	AT91_PIN_PE10	(PIN_BASE + 0x80 + 10)
++#define	AT91_PIN_PE11	(PIN_BASE + 0x80 + 11)
++#define	AT91_PIN_PE12	(PIN_BASE + 0x80 + 12)
++#define	AT91_PIN_PE13	(PIN_BASE + 0x80 + 13)
++#define	AT91_PIN_PE14	(PIN_BASE + 0x80 + 14)
++#define	AT91_PIN_PE15	(PIN_BASE + 0x80 + 15)
++#define	AT91_PIN_PE16	(PIN_BASE + 0x80 + 16)
++#define	AT91_PIN_PE17	(PIN_BASE + 0x80 + 17)
++#define	AT91_PIN_PE18	(PIN_BASE + 0x80 + 18)
++#define	AT91_PIN_PE19	(PIN_BASE + 0x80 + 19)
++#define	AT91_PIN_PE20	(PIN_BASE + 0x80 + 20)
++#define	AT91_PIN_PE21	(PIN_BASE + 0x80 + 21)
++#define	AT91_PIN_PE22	(PIN_BASE + 0x80 + 22)
++#define	AT91_PIN_PE23	(PIN_BASE + 0x80 + 23)
++#define	AT91_PIN_PE24	(PIN_BASE + 0x80 + 24)
++#define	AT91_PIN_PE25	(PIN_BASE + 0x80 + 25)
++#define	AT91_PIN_PE26	(PIN_BASE + 0x80 + 26)
++#define	AT91_PIN_PE27	(PIN_BASE + 0x80 + 27)
++#define	AT91_PIN_PE28	(PIN_BASE + 0x80 + 28)
++#define	AT91_PIN_PE29	(PIN_BASE + 0x80 + 29)
++#define	AT91_PIN_PE30	(PIN_BASE + 0x80 + 30)
++#define	AT91_PIN_PE31	(PIN_BASE + 0x80 + 31)
++
++static unsigned long at91_pios[] = {
++	AT91_PIOA,
++	AT91_PIOB,
++	AT91_PIOC,
++#ifdef AT91_PIOD
++	AT91_PIOD,
++#ifdef AT91_PIOE
++	AT91_PIOE
++#endif
++#endif
++};
++
++static inline void *pin_to_controller(unsigned pin)
++{
++	pin -= PIN_BASE;
++	pin /= 32;
++	return (void *)(AT91_BASE_SYS + at91_pios[pin]);
++}
++
++static inline unsigned pin_to_mask(unsigned pin)
++{
++	pin -= PIN_BASE;
++	return 1 << (pin % 32);
++}
++
++/*
++ * mux the pin to the "GPIO" peripheral role.
++ */
++static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(mask, pio + PIO_PER);
++	return 0;
++}
++
++/*
++ * mux the pin to the "A" internal peripheral role.
++ */
++static inline int at91_set_A_periph(unsigned pin, int use_pullup)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(mask, pio + PIO_ASR);
++	__raw_writel(mask, pio + PIO_PDR);
++	return 0;
++}
++
++/*
++ * mux the pin to the "B" internal peripheral role.
++ */
++static inline int at91_set_B_periph(unsigned pin, int use_pullup)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(mask, pio + PIO_BSR);
++	__raw_writel(mask, pio + PIO_PDR);
++	return 0;
++}
++
++/*
++ * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
++ * configure it for an input.
++ */
++static inline int at91_set_gpio_input(unsigned pin, int use_pullup)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
++	__raw_writel(mask, pio + PIO_ODR);
++	__raw_writel(mask, pio + PIO_PER);
++	return 0;
++}
++
++/*
++ * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
++ * and configure it for an output.
++ */
++static inline int at91_set_gpio_output(unsigned pin, int value)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + PIO_IDR);
++	__raw_writel(mask, pio + PIO_PUDR);
++	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
++	__raw_writel(mask, pio + PIO_OER);
++	__raw_writel(mask, pio + PIO_PER);
++	return 0;
++}
++
++/*
++ * enable/disable the glitch filter; mostly used with IRQ handling.
++ */
++static inline int at91_set_deglitch(unsigned pin, int is_on)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
++	return 0;
++}
++
++/*
++ * enable/disable the multi-driver; This is only valid for output and
++ * allows the output pin to run as an open collector output.
++ */
++static inline int at91_set_multi_drive(unsigned pin, int is_on)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
++	return 0;
++}
++
++static inline int gpio_direction_input(unsigned pin)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!(__raw_readl(pio + PIO_PSR) & mask))
++		return -EINVAL;
++	__raw_writel(mask, pio + PIO_ODR);
++	return 0;
++}
++
++static inline int gpio_direction_output(unsigned pin, int value)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	if (!(__raw_readl(pio + PIO_PSR) & mask))
++		return -EINVAL;
++	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
++	__raw_writel(mask, pio + PIO_OER);
++	return 0;
++}
++
++/*
++ * assuming the pin is muxed as a gpio output, set its value.
++ */
++static inline int at91_set_gpio_value(unsigned pin, int value)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++
++	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
++	return 0;
++}
++
++/*
++ * read the pin's value (works even if it's not muxed as a gpio).
++ */
++static inline int at91_get_gpio_value(unsigned pin)
++{
++	void		*pio = pin_to_controller(pin);
++	unsigned	mask = pin_to_mask(pin);
++	u32		pdsr;
++
++	pdsr = __raw_readl(pio + PIO_PDSR);
++	return (pdsr & mask) != 0;
++}
++
++#endif
+diff -urN u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/io.h u-boot-2009.01/include/asm-arm/arch-at91rm9200/io.h
+--- u-boot-2009.01-rc1-0rig//include/asm-arm/arch-at91rm9200/io.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/asm-arm/arch-at91rm9200/io.h	2009-01-01 15:59:51.000000000 +0100
+@@ -0,0 +1,56 @@
++/*
++ * [origin: Linux kernel include/asm-arm/arch-at91/io.h]
++ *
++ *  Copyright (C) 2003 SAN People
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#ifndef __ASM_ARCH_IO_H
++#define __ASM_ARCH_IO_H
++
++#include <asm/io.h>
++
++static inline unsigned int at91_sys_read(unsigned int reg_offset)
++{
++	void *addr = (void *)AT91_BASE_SYS;
++
++	return __raw_readl(addr + reg_offset);
++}
++
++static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
++{
++	void *addr = (void *)AT91_BASE_SYS;
++
++	__raw_writel(value, addr + reg_offset);
++}
++
++static inline void at91_sys_setbit(unsigned long value, unsigned int reg_offset)
++{
++	void *addr = (void *)(AT91_BASE_SYS  + reg_offset);
++	value |= __raw_readl(addr);
++	__raw_writel(value, addr);
++}
++
++static inline void at91_sys_clrbit(unsigned long value, unsigned int reg_offset)
++{
++	void *addr = (void *)(AT91_BASE_SYS  + reg_offset);
++	unsigned long data;
++	data = __raw_readl(addr);
++	data &= ~value;
++	__raw_writel(data, addr);
++}
++
++#endif
+
diff --git a/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-002-at91rm9200dk.h.patch b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-002-at91rm9200dk.h.patch
new file mode 100644
index 000000000..c86dcdea9
--- /dev/null
+++ b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-002-at91rm9200dk.h.patch
@@ -0,0 +1,309 @@
+diff -urN u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk_df.h u-boot-2009.01/include/configs/at91rm9200dk_df.h
+--- u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk_df.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/configs/at91rm9200dk_df.h	2009-01-01 21:19:30.000000000 +0100
+@@ -0,0 +1,251 @@
++/*
++ * Rick Bronson <rick@efn.org>
++ *
++ * Configuration settings for the AT91RM9200DK board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++#define	AT91RM9200_BOARD	MACH_TYPE_AT91RM9200DK
++#define	CONFIG_HOSTNAME		at91rm9200dk
++
++/* ARM asynchronous clock */
++#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
++#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
++/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */
++
++#define AT91_SLOW_CLOCK		32768	/* slow clock */
++
++#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
++#define	CONFIG_AT91		1	/* THis is an ARM from the AT91 family */
++#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
++#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
++#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
++#define USE_920T_MMU		1
++
++#define CONFIG_SKIP_LOWLEVEL_INIT	/* Already done by dataflashboot */
++
++#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG	1
++
++#ifndef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
++/* flash */
++#define MC_PUIA_VAL	0x00000000
++#define MC_PUP_VAL	0x00000000
++#define MC_PUER_VAL	0x00000000
++#define MC_ASR_VAL	0x00000000
++#define MC_AASR_VAL	0x00000000
++#define EBI_CFGR_VAL	0x00000000
++#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
++
++/* clocks */
++#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
++#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
++#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
++
++/* sdram */
++#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
++#define PIOC_BSR_VAL	0x00000000
++#define PIOC_PDR_VAL	0xFFFF0000
++#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
++#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
++#define SDRAM		0x20000000 /* address of the SDRAM */
++#define SDRAM1		0x20000080 /* address of the SDRAM */
++#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
++#define SDRC_MR_VAL	0x00000002 /* Precharge All */
++#define SDRC_MR_VAL1	0x00000004 /* refresh */
++#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
++#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
++#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
++#else
++#define CONFIG_SKIP_RELOCATE_UBOOT
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++/*
++ * Size of malloc() pool
++ */
++#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
++#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
++
++#define CONFIG_BAUDRATE 115200
++
++/*
++ * Hardware drivers
++ */
++
++/* define one of these to choose the DBGU, USART0  or USART1 as console */
++#define CONFIG_DBGU
++#undef CONFIG_USART0
++#undef CONFIG_USART1
++
++#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
++
++#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
++
++#define CONFIG_BOOTDELAY      3
++/* #define CONFIG_ENV_OVERWRITE	1 */
++
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE
++#define CONFIG_BOOTP_BOOTPATH
++#define CONFIG_BOOTP_GATEWAY
++#define CONFIG_BOOTP_HOSTNAME
++
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_NAND
++#define CONFIG_CMD_AT91_SPIMUX
++
++#define CONFIG_NAND_LEGACY
++
++#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
++#define SECTORSIZE 512
++
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++
++#define NAND_ChipID_UNKNOWN	0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++
++#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
++#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
++
++#include <asm/arch/AT91RM9200.h>	/* needed for port definitions */
++#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
++#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
++
++#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
++
++#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
++#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
++#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
++/* the following are NOP's in our implementation */
++#define NAND_CTL_CLRALE(nandptr)
++#define NAND_CTL_SETALE(nandptr)
++#define NAND_CTL_CLRCLE(nandptr)
++#define NAND_CTL_SETCLE(nandptr)
++
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM 0x20000000
++#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
++
++#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
++#define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
++
++#define CONFIG_DRIVER_ETHER
++#define CONFIG_NET_RETRY_COUNT		20
++#define CONFIG_AT91C_USE_RMII
++
++/* AC Characteristics */
++/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS	(0xC << 16)
++#define DATAFLASH_TCHS	(0x1 << 24)
++
++#define CONFIG_HAS_DATAFLASH		1
++#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
++#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
++#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
++#define	CFG_SUPPORT_BLOCK_ERASE		1
++
++
++#define PHYS_FLASH_1			0x10000000
++#define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
++#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
++#define CONFIG_SYS_MAX_FLASH_BANKS		1
++#define CONFIG_SYS_MAX_FLASH_SECT		256
++#define CONFIG_SYS_FLASH_ERASE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
++#define CONFIG_SYS_FLASH_WRITE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
++
++#define	CONFIG_ENV_IS_IN_DATAFLASH	1
++#define	CONFIG_NEW_PARTITION		1
++
++#ifdef CONFIG_ENV_IS_IN_DATAFLASH
++#ifdef	CONFIG_NEW_PARTITION		
++#define CONFIG_ENV_OFFSET		0x4200
++#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
++#define CONFIG_ENV_SIZE			0x2000  /* 8 * 1056 really , but start.s is not OK with this*/
++#else
++#define CONFIG_ENV_OFFSET		0x20000
++#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
++#define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
++#endif
++#else
++#define CONFIG_ENV_IS_IN_FLASH		1
++#ifdef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
++#define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
++#else
++#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
++#define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++#endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
++
++#if defined(CONFIG_AT91RM9200DK)
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB7
++#else
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB22
++#endif
++
++#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
++
++#ifdef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
++#define CONFIG_SYS_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
++#define CONFIG_SYS_U_BOOT_SIZE		0x10000 /* 64 KBytes */
++#else
++#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
++#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
++#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++
++#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
++
++#define CONFIG_SYS_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
++#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
++#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
++#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
++
++#define CONFIG_SYS_HZ 1000
++#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
++						/* AT91C_TC_TIMER_DIV1_CLOCK */
++
++#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
++
++#ifdef CONFIG_USE_IRQ
++#error CONFIG_USE_IRQ not supported
++#endif
++
++#endif
+diff -urN u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk.h u-boot-2009.01/include/configs/at91rm9200dk.h
+--- u-boot-2009.01-rc1-0rig//include/configs/at91rm9200dk.h	2009-01-01 13:09:35.000000000 +0100
++++ u-boot-2009.01/include/configs/at91rm9200dk.h	2009-01-01 17:06:32.000000000 +0100
+@@ -24,6 +24,8 @@
+ 
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
++#define	AT91RM9200_BOARD	MACH_TYPE_AT91RM9200DK
++#define	CONFIG_HOSTNAME		at91rm9200dk
+ 
+ /* ARM asynchronous clock */
+ #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
+@@ -33,6 +35,7 @@
+ #define AT91_SLOW_CLOCK		32768	/* slow clock */
+ 
+ #define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
++#define	CONFIG_AT91		1	/* THis is an ARM from the AT91 family */
+ #define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+ #define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+ #undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+@@ -117,6 +120,7 @@
+ #define CONFIG_CMD_DHCP
+ #define CONFIG_CMD_MII
+ #define CONFIG_CMD_NAND
++#define CONFIG_CMD_AT91_SPIMUX
+ 
+ #define CONFIG_NAND_LEGACY
+ 
+@@ -198,6 +202,11 @@
+ #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+ #endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
+ 
++#if defined(CONFIG_AT91RM9200DK)
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB7
++#else
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB22
++#endif
+ 
+ #define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+ 
+diff -urN u-boot-2009.01-rc1-0rig//Makefile u-boot-2009.01/Makefile
+--- u-boot-2009.01-rc1-0rig//Makefile	2009-01-01 13:09:30.000000000 +0100
++++ u-boot-2009.01/Makefile	2009-01-01 21:35:24.000000000 +0100
+@@ -2562,6 +2562,9 @@
+ ## Atmel AT91RM9200 Systems
+ #########################################################################
+ 
++at91rm9200dk_df_config	:	unconfig
++	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
++
+ at91rm9200dk_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
+ 
+
diff --git a/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-003-at91rm9200dk.patch b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-003-at91rm9200dk.patch
new file mode 100644
index 000000000..8f14170fa
--- /dev/null
+++ b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-003-at91rm9200dk.patch
@@ -0,0 +1,324 @@
+diff -urN u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/at91rm9200dk.c u-boot-2009.01/board/atmel/at91rm9200dk/at91rm9200dk.c
+--- u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/at91rm9200dk.c	2009-01-01 13:09:31.000000000 +0100
++++ u-boot-2009.01/board/atmel/at91rm9200dk/at91rm9200dk.c	2009-01-01 16:11:36.000000000 +0100
+@@ -3,6 +3,9 @@
+  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+  * Marius Groeger <mgroeger@sysgo.de>
+  *
++ * (C) Copyright 2008
++ * Ulf Samuelsson <ulf.samuelsson@atmel.com>
++ *
+  * See file CREDITS for list of people who contributed to this
+  * project.
+  *
+@@ -24,6 +27,10 @@
+ 
+ #include <common.h>
+ #include <asm/arch/AT91RM9200.h>
++#include <asm/arch/at91_pmc.h>
++#include <asm/arch/at91_pio.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
+ #include <at91rm9200_net.h>
+ #include <dm9161.h>
+ 
+@@ -41,13 +48,13 @@
+ 
+ 	/* Correct IRDA resistor problem */
+ 	/* Set PA23_TXD in Output */
+-	((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2;
++	at91_set_gpio_output(AT91_PIN_PA23, 1);
+ 
+ 	/* memory and cpu-speed are setup before relocation */
+ 	/* so we do _nothing_ here */
+ 
+ 	/* arch number of AT91RM9200DK-Board */
+-	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK;
++	gd->bd->bi_arch_number = AT91RM9200_BOARD;
+ 	/* adress of boot parameters */
+ 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ 
+@@ -91,46 +98,58 @@
+  */
+ #if defined(CONFIG_CMD_NAND)
+ extern ulong nand_probe (ulong physadr);
++/* set the bus interface characteristics based on
++ * tDS Data Set up Time 30 - ns
++ * tDH Data Hold Time 20 - ns
++ * tALS ALE Set up Time 20 - ns
++ * 16ns at 60 MHz ~= 3
++ */
+ 
+-#define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
+-void nand_init (void)
+-{
+-	/* Setup Smart Media, fitst enable the address range of CS3 */
+-	*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
+-	/* set the bus interface characteristics based on
+-	   tDS Data Set up Time 30 - ns
+-	   tDH Data Hold Time 20 - ns
+-	   tALS ALE Set up Time 20 - ns
+-	   16ns at 60 MHz ~= 3  */
+ /*memory mapping structures */
+ #define SM_ID_RWH	(5 << 28)
+ #define SM_RWH		(1 << 28)
+ #define SM_RWS		(0 << 24)
+ #define SM_TDF		(1 << 8)
+ #define SM_NWS		(3)
+-	AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
+-		AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
+-		SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
++
++#define	SMARTMEDIA_INIT	(			\
++		SM_RWH |			\
++		SM_RWS |			\
++		AT91C_SMC2_ACSS_STANDARD |	\
++		AT91C_SMC2_DBW_8 |		\
++		SM_TDF |			\
++		AT91C_SMC2_WSEN |		\
++		SM_NWS				\
++		)
++
++
++
++#define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
++void nand_init (void)
++{
++	/* Setup Smart Media, fitst enable the address range of CS3 */
++	/* *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; */
++	at91_sys_setbit(AT91C_EBI_CS3A_SMC_SmartMedia, AT91_EBI_CSA);
++
++	/* Init Smartmedia Interface */
++	at91_sys_write(AT91_SMC2_CSR3, SMARTMEDIA_INIT);
+ 
+ 	/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
+-	*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+-		AT91C_PC3_BFBAA_SMWE;
+-	*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+-		AT91C_PC3_BFBAA_SMWE;
++	at91_set_A_periph(AT91_PIN_PC0, 0);	/* BFCK	*/
++	at91_set_A_periph(AT91_PIN_PC1, 0);	/* BFRDY/SMOE */
++	at91_set_A_periph(AT91_PIN_PC3, 0);	/* BFBAA/SMWE */
+ 
+ 	/* Configure PC2 as input (signal READY of the SmartMedia) */
+-	*AT91C_PIOC_PER = AT91C_PC2_BFAVD;	/* enable direct output enable */
+-	*AT91C_PIOC_ODR = AT91C_PC2_BFAVD;	/* disable output */
++	at91_set_gpio_input(AT91_PIN_PC2, 0);
+ 
+ 	/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+-	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
+-	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
++	at91_set_gpio_input(AT91_PIN_PB1, 0);
+ 
+ 	/* PIOB and PIOC clock enabling */
+-	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+-	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91RM9200_ID_PIOB);
++	at91_sys_write(AT91_PMC_PCER, 1 << AT91RM9200_ID_PIOC);
+ 
+-	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
++	if (at91_get_gpio_value(AT91_PIN_PB1))
+ 		printf ("  No SmartMedia card inserted\n");
+ #ifdef DEBUG
+ 	printf ("  SmartMedia card inserted\n");
+@@ -140,3 +159,4 @@
+ 	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
+ }
+ #endif
++
+diff -urN u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/led.c u-boot-2009.01/board/atmel/at91rm9200dk/led.c
+--- u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/led.c	2009-01-01 13:09:31.000000000 +0100
++++ u-boot-2009.01/board/atmel/at91rm9200dk/led.c	2009-01-01 15:53:56.000000000 +0100
+@@ -24,57 +24,105 @@
+ 
+ #include <common.h>
+ #include <asm/arch/AT91RM9200.h>
++/*#include <asm/arch/at91_pmc.h>*/
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
+ 
+-#define	GREEN_LED	AT91C_PIO_PB0
+-#define	YELLOW_LED	AT91C_PIO_PB1
+-#define	RED_LED	AT91C_PIO_PB2
++#define	GREEN_LED			AT91_PIN_PB0
++#define	YELLOW_LED			AT91_PIN_PB1
++#define	RED_LED				AT91_PIN_PB2
+ 
+-void	green_LED_on(void)
++
++#define	GREEN_LED_ON			0
++#define	GREEN_LED_OFF			1
++#define	YELLOW_LED_ON			0
++#define	YELLOW_LED_OFF			1
++#define	RED_LED_ON			0
++#define	RED_LED_OFF			1
++
++#define	TIME_SLICE			500000
++
++void yellow_LED_on(void)
++{
++	at91_set_gpio_value(YELLOW_LED, YELLOW_LED_ON);
++}
++
++void yellow_LED_off(void)
++{
++	at91_set_gpio_value(YELLOW_LED, YELLOW_LED_OFF);
++}
++
++void red_LED_on(void)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	PIOB->PIO_CODR		= GREEN_LED;
++	at91_set_gpio_value(RED_LED, RED_LED_ON);
+ }
+ 
+-void	 yellow_LED_on(void)
++void red_LED_off(void)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	PIOB->PIO_CODR		= YELLOW_LED;
++	at91_set_gpio_value(RED_LED, RED_LED_OFF);
+ }
+ 
+-void	 red_LED_on(void)
++void green_LED_on(void)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	PIOB->PIO_CODR		= RED_LED;
++	at91_set_gpio_value(GREEN_LED, GREEN_LED_ON);
+ }
+ 
+-void	green_LED_off(void)
++void green_LED_off(void)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	PIOB->PIO_SODR		= GREEN_LED;
++	at91_set_gpio_value(GREEN_LED, GREEN_LED_OFF);
+ }
+ 
+-void	yellow_LED_off(void)
++static void	delay(unsigned int	time)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	PIOB->PIO_SODR		= YELLOW_LED;
++	volatile unsigned int	counter = time;
++	while(counter > 0) counter--;
+ }
+ 
+-void	red_LED_off(void)
++void	green_LED_blink(unsigned int time)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	PIOB->PIO_SODR		= RED_LED;
++	while(time > 0) {
++		green_LED_on();
++		delay(TIME_SLICE);
++		green_LED_off();
++		delay(TIME_SLICE);
++		time--;
++	}
+ }
+ 
++void	yellow_LED_blink(unsigned int time)
++{
++	while(time > 0) {
++		yellow_LED_on();
++		delay(TIME_SLICE);
++		yellow_LED_off();
++		delay(TIME_SLICE);
++		time--;
++	}
++}
+ 
+-void coloured_LED_init (void)
++void	red_LED_blink(unsigned int time)
+ {
+-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
+-	AT91PS_PMC	PMC	= AT91C_BASE_PMC;
+-	PMC->PMC_PCER		= (1 << AT91C_ID_PIOB);	/* Enable PIOB clock */
+-	/* Disable peripherals on LEDs */
+-	PIOB->PIO_PER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+-	/* Enable pins as outputs */
+-	PIOB->PIO_OER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
+-	/* Turn all LEDs OFF */
+-	PIOB->PIO_SODR		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
++	while(time > 0) {
++		red_LED_on();
++		delay(TIME_SLICE);
++		red_LED_off();
++		delay(TIME_SLICE);
++		time--;
++	}
+ }
++
++void coloured_LED_init(void)
++{
++	/* Enable clock */
++	at91_sys_write(AT91C_PMC_PCER, 1 << AT91RM9200_ID_PIOB);
++
++	at91_set_gpio_output(GREEN_LED, 1);
++	at91_set_gpio_output(YELLOW_LED, 1);
++	at91_set_gpio_output(RED_LED, 1);
++
++	at91_set_gpio_value(GREEN_LED,	GREEN_LED_OFF);
++	at91_set_gpio_value(YELLOW_LED, YELLOW_LED_OFF);
++	at91_set_gpio_value(RED_LED,	RED_LED_ON);
++}
++
++
+diff -urN u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/mux.c u-boot-2009.01/board/atmel/at91rm9200dk/mux.c
+--- u-boot-2009.01-rc1-0rig//board/atmel/at91rm9200dk/mux.c	2009-01-01 13:09:31.000000000 +0100
++++ u-boot-2009.01/board/atmel/at91rm9200dk/mux.c	2009-01-01 16:38:01.000000000 +0100
+@@ -1,37 +1,29 @@
+ #include <config.h>
+ #include <common.h>
+ #include <asm/hardware.h>
++#include <asm/arch/at91_pio.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/io.h>
+ #include <dataflash.h>
+ 
+ int AT91F_GetMuxStatus(void) {
+-#ifdef	DATAFLASH_MMC_SELECT
+-	AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
+-	AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
+-
+-
+-	if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) {
+-		return 1;
+-	} else {
+-		return 0;
+-	}
+-#endif
++#ifdef	CONFIG_CMD_AT91_SPIMUX
++	return at91_get_gpio_value(DATAFLASH_MMC_SELECT);
++#else
+ 	return 0;
++#endif
+ }
+ 
+-void AT91F_SelectMMC(void) {
+-#ifdef	DATAFLASH_MMC_SELECT
+-	AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT;	/* Set in PIO mode */
+-	AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT;	/* Configure in output */
+-	/* Set Output */
+-	AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT;
++void AT91F_SelectMMC(void) 
++{
++#ifdef	CONFIG_CMD_AT91_SPIMUX
++	at91_set_gpio_output(DATAFLASH_MMC_SELECT, 1);	/* Set in PIO mode and select SD-Card*/
+ #endif
+ }
+ 
+ void AT91F_SelectSPI(void) {
+-#ifdef	DATAFLASH_MMC_SELECT
+-	AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT;	/* Set in PIO mode */
+-	AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT;	/* Configure in output */
+-	/* Clear Output */
+-	AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT;
++#ifdef	CONFIG_CMD_AT91_SPIMUX
++	at91_set_gpio_output(DATAFLASH_MMC_SELECT, 0);	/* Set in PIO mode and select SPI */
+ #endif
+ }
++
+
diff --git a/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-004-at91rm9200ek.patch b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-004-at91rm9200ek.patch
new file mode 100644
index 000000000..f979dd3d6
--- /dev/null
+++ b/target/u-boot/2009.01-rc1/u-boot-2009.01-rc1-004-at91rm9200ek.patch
@@ -0,0 +1,536 @@
+diff -urN u-boot-2009.01-0rig/include/configs/at91rm9200df.h u-boot-2009.01/include/configs/at91rm9200df.h
+--- u-boot-2009.01-0rig/include/configs/at91rm9200df.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/configs/at91rm9200df.h	2009-01-01 21:19:17.000000000 +0100
+@@ -0,0 +1,261 @@
++/*
++ * Rick Bronson <rick@efn.org>
++ *
++ * Ulf Samuelsson <ulf.samuelsson@atmel.com>
++ *
++ * Configuration settings for the AT91RM9200EK board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++#define	AT91RM9200_BOARD	MACH_TYPE_AT91RM9200DF
++#define	CONFIG_HOSTNAME		at91rm9200df
++/* ARM asynchronous clock */
++#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
++#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
++/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */
++
++#define AT91_SLOW_CLOCK		32768	/* slow clock */
++
++#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
++#define	CONFIG_AT91		1	/* THis is an ARM from the AT91 family */
++#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
++#define CONFIG_AT91RM9200DF	1	/* Generic AT91RM9200 Board running from Dataflashcard	*/
++#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
++#define USE_920T_MMU		1
++
++#define CONFIG_SKIP_LOWLEVEL_INIT	/* Already done by dataflashboot */
++
++#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG	1
++
++#ifndef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
++/* flash */
++#define MC_PUIA_VAL	0x00000000
++#define MC_PUP_VAL	0x00000000
++#define MC_PUER_VAL	0x00000000
++#define MC_ASR_VAL	0x00000000
++#define MC_AASR_VAL	0x00000000
++#define EBI_CFGR_VAL	0x00000000
++#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
++
++/* clocks */
++#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
++#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
++#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
++
++/* sdram */
++#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
++#define PIOC_BSR_VAL	0x00000000
++#define PIOC_PDR_VAL	0xFFFF0000
++#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
++#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
++#define SDRAM		0x20000000 /* address of the SDRAM */
++#define SDRAM1		0x20000080 /* address of the SDRAM */
++#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
++#define SDRC_MR_VAL	0x00000002 /* Precharge All */
++#define SDRC_MR_VAL1	0x00000004 /* refresh */
++#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
++#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
++#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
++#else
++#define CONFIG_SKIP_RELOCATE_UBOOT
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++/*
++ * Size of malloc() pool
++ */
++#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
++#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
++
++#define CONFIG_BAUDRATE 115200
++
++/*
++ * Hardware drivers
++ */
++
++/* define one of these to choose the DBGU, USART0  or USART1 as console */
++#define CONFIG_DBGU
++#undef CONFIG_USART0
++#undef CONFIG_USART1
++
++#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
++
++#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
++
++#define CONFIG_BOOTDELAY      3
++/* #define CONFIG_ENV_OVERWRITE	1 */
++
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE
++#define CONFIG_BOOTP_BOOTPATH
++#define CONFIG_BOOTP_GATEWAY
++#define CONFIG_BOOTP_HOSTNAME
++
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_NAND
++#define CONFIG_CMD_AT91_SPIMUX
++#define CONFIG_CMD_ETHINIT
++
++#define CONFIG_DOS_PARTITION		1
++#define CONFIG_MMC			1
++#define CONFIG_SUPPORT_VFAT		1
++#define CFG_MMC_BASE			0xFFFB4000	/* From AT91RM9200.h*/
++#define CFG_MMC_BLOCKSIZE		512
++
++#define CONFIG_NAND_LEGACY
++
++#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
++#define SECTORSIZE 512
++
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++
++#define NAND_ChipID_UNKNOWN	0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++
++#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
++#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
++
++#include <asm/arch/AT91RM9200.h>	/* needed for port definitions */
++#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
++#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
++
++#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
++
++#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
++#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
++#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
++/* the following are NOP's in our implementation */
++#define NAND_CTL_CLRALE(nandptr)
++#define NAND_CTL_SETALE(nandptr)
++#define NAND_CTL_CLRCLE(nandptr)
++#define NAND_CTL_SETCLE(nandptr)
++
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM 0x20000000
++#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
++
++#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
++#define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
++
++#define CONFIG_DRIVER_ETHER
++#define CONFIG_NET_RETRY_COUNT		20
++#define CONFIG_AT91C_USE_RMII
++
++/* AC Characteristics */
++/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS	(0xC << 16)
++#define DATAFLASH_TCHS	(0x1 << 24)
++
++#define CONFIG_HAS_DATAFLASH		1
++#define BOARD_LATE_INIT			1
++
++#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
++#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
++#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
++#define	CFG_SUPPORT_BLOCK_ERASE		1
++
++#define PHYS_FLASH_1			0x10000000
++#define PHYS_FLASH_SIZE			0x800000  /* 2 megs main flash */
++#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
++#define CONFIG_SYS_MAX_FLASH_BANKS		1
++#define CONFIG_SYS_MAX_FLASH_SECT		256
++#define CONFIG_SYS_FLASH_ERASE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
++#define CONFIG_SYS_FLASH_WRITE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
++
++#define	CONFIG_ENV_IS_IN_DATAFLASH
++#define	CONFIG_NEW_PARTITION		1
++
++#ifdef CONFIG_ENV_IS_IN_DATAFLASH
++#ifdef	CONFIG_NEW_PARTITION		
++#define CONFIG_ENV_OFFSET		0x21000
++#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
++#define CONFIG_ENV_SIZE			0x2000  /* 8 * 1056 really , but start.s is not OK with this*/
++#else
++#define CONFIG_ENV_OFFSET		0x20000
++#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
++#define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
++#endif
++#else
++#define CONFIG_ENV_IS_IN_FLASH		1
++#ifdef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
++#define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
++#else
++#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
++#define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++#endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
++
++#if defined(CONFIG_AT91RM9200DK)
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB7
++#else
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB22
++#endif
++
++#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
++
++#ifdef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
++#define CONFIG_SYS_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
++#define CONFIG_SYS_U_BOOT_SIZE		0x10000 /* 64 KBytes */
++#else
++#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
++#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
++#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++
++#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
++
++#define CONFIG_SYS_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
++#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
++#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
++#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
++
++#define CONFIG_SYS_HZ 1000
++#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
++						/* AT91C_TC_TIMER_DIV1_CLOCK */
++
++#define CONFIG_STACKSIZE		(32*1024)	/* regular stack */
++#define CONFIG_STACKSIZE_IRQ  		(4*1024)        /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ  		(4*1024) 
++
++#ifdef CONFIG_USE_IRQ
++#error CONFIG_USE_IRQ not supported
++#endif
++#endif
+diff -urN u-boot-2009.01-0rig/include/configs/at91rm9200ek.h u-boot-2009.01/include/configs/at91rm9200ek.h
+--- u-boot-2009.01-0rig/include/configs/at91rm9200ek.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2009.01/include/configs/at91rm9200ek.h	2009-01-01 17:13:31.000000000 +0100
+@@ -0,0 +1,251 @@
++/*
++ * Rick Bronson <rick@efn.org>
++ *
++ * Ulf Samuelsson <ulf.samuelsson@atmel.com>
++ *
++ * Configuration settings for the AT91RM9200EK board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++#define	AT91RM9200_BOARD	MACH_TYPE_AT91RM9200EK
++#define	CONFIG_HOSTNAME		at91rm9200ek
++/* ARM asynchronous clock */
++#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
++#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
++/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */
++
++#define AT91_SLOW_CLOCK		32768	/* slow clock */
++
++#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
++#define	CONFIG_AT91		1	/* THis is an ARM from the AT91 family */
++#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
++#define CONFIG_AT91RM9200EK	1	/* on an AT91RM9200EK Board	*/
++#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
++#define USE_920T_MMU		1
++
++#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG	1
++
++#ifndef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
++/* flash */
++#define MC_PUIA_VAL	0x00000000
++#define MC_PUP_VAL	0x00000000
++#define MC_PUER_VAL	0x00000000
++#define MC_ASR_VAL	0x00000000
++#define MC_AASR_VAL	0x00000000
++#define EBI_CFGR_VAL	0x00000000
++#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
++
++/* clocks */
++#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
++#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
++#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
++
++/* sdram */
++#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
++#define PIOC_BSR_VAL	0x00000000
++#define PIOC_PDR_VAL	0xFFFF0000
++#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
++#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
++#define SDRAM		0x20000000 /* address of the SDRAM */
++#define SDRAM1		0x20000080 /* address of the SDRAM */
++#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
++#define SDRC_MR_VAL	0x00000002 /* Precharge All */
++#define SDRC_MR_VAL1	0x00000004 /* refresh */
++#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
++#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
++#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
++#else
++#define CONFIG_SKIP_RELOCATE_UBOOT
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++/*
++ * Size of malloc() pool
++ */
++#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
++#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
++
++#define CONFIG_BAUDRATE 115200
++
++/*
++ * Hardware drivers
++ */
++
++/* define one of these to choose the DBGU, USART0  or USART1 as console */
++#define CONFIG_DBGU
++#undef CONFIG_USART0
++#undef CONFIG_USART1
++
++#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
++
++#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
++
++#define CONFIG_BOOTDELAY      3
++/* #define CONFIG_ENV_OVERWRITE	1 */
++
++
++/*
++ * BOOTP options
++ */
++#define CONFIG_BOOTP_BOOTFILESIZE
++#define CONFIG_BOOTP_BOOTPATH
++#define CONFIG_BOOTP_GATEWAY
++#define CONFIG_BOOTP_HOSTNAME
++
++
++/*
++ * Command line configuration.
++ */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_NAND
++#define CONFIG_CMD_AT91_SPIMUX
++#define CONFIG_CMD_ETHINIT
++
++#define CONFIG_NAND_LEGACY
++
++#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
++#define SECTORSIZE 512
++
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++
++#define NAND_ChipID_UNKNOWN	0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++
++#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
++#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
++
++#include <asm/arch/AT91RM9200.h>	/* needed for port definitions */
++#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
++#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
++
++#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
++
++#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
++#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
++#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
++#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
++/* the following are NOP's in our implementation */
++#define NAND_CTL_CLRALE(nandptr)
++#define NAND_CTL_SETALE(nandptr)
++#define NAND_CTL_CLRCLE(nandptr)
++#define NAND_CTL_SETCLE(nandptr)
++
++#define CONFIG_NR_DRAM_BANKS 1
++#define PHYS_SDRAM 0x20000000
++#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
++
++#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
++#define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
++
++#define CONFIG_DRIVER_ETHER
++#define CONFIG_NET_RETRY_COUNT		20
++#define CONFIG_AT91C_USE_RMII
++
++/* AC Characteristics */
++/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
++#define DATAFLASH_TCSS	(0xC << 16)
++#define DATAFLASH_TCHS	(0x1 << 24)
++
++#define CONFIG_HAS_DATAFLASH		1
++#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
++#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
++#define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
++#define	CFG_SUPPORT_BLOCK_ERASE		1
++
++#define PHYS_FLASH_1			0x10000000
++#define PHYS_FLASH_SIZE			0x800000  /* 2 megs main flash */
++#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
++#define CONFIG_SYS_MAX_FLASH_BANKS		1
++#define CONFIG_SYS_MAX_FLASH_SECT		256
++#define CONFIG_SYS_FLASH_ERASE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
++#define CONFIG_SYS_FLASH_WRITE_TOUT		(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
++
++#undef	CONFIG_ENV_IS_IN_DATAFLASH
++#define	CONFIG_NEW_PARTITION		1
++
++#ifdef CONFIG_ENV_IS_IN_DATAFLASH
++#ifdef	CONFIG_NEW_PARTITION		
++#define CFG_ENV_OFFSET			0x21000
++#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
++#define CFG_ENV_SIZE			0x2000  /* 8 * 1056 really , but start.s is not OK with this*/
++> #else
++#define CONFIG_ENV_OFFSET		0x20000
++#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
++#define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
++#endif
++#else
++#define CONFIG_ENV_IS_IN_FLASH		1
++#ifdef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
++#define CONFIG_ENV_SIZE			0x2000  /* 0x8000 */
++#else
++#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
++#define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++#endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
++
++#if defined(CONFIG_AT91RM9200DK)
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB7
++#else
++#define	DATAFLASH_MMC_SELECT		AT91_PIN_PB22
++#endif
++
++#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
++
++#ifdef CONFIG_SKIP_LOWLEVEL_INIT
++#define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
++#define CONFIG_SYS_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
++#define CONFIG_SYS_U_BOOT_SIZE		0x10000 /* 64 KBytes */
++#else
++#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
++#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
++#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
++#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
++
++#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
++
++#define CONFIG_SYS_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
++#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
++#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
++#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
++
++#define CONFIG_SYS_HZ 1000
++#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
++						/* AT91C_TC_TIMER_DIV1_CLOCK */
++
++#define CONFIG_STACKSIZE		(32*1024)	/* regular stack */
++#define CONFIG_STACKSIZE_IRQ  		(4*1024)        /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ  		(4*1024) 
++
++#ifdef CONFIG_USE_IRQ
++#error CONFIG_USE_IRQ not supported
++#endif
++#endif
+diff -urN u-boot-2009.01-0rig/Makefile u-boot-2009.01/Makefile
+--- u-boot-2009.01-0rig/Makefile	2009-01-02 10:03:11.000000000 +0100
++++ u-boot-2009.01/Makefile	2009-01-01 21:31:34.000000000 +0100
+@@ -2568,6 +2568,12 @@
+ at91rm9200dk_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
+ 
++at91rm9200df_config	:	unconfig
++	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
++
++at91rm9200ek_config	:	unconfig
++	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
++
+ cmc_pu2_config	:	unconfig
+ 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+ 
diff --git a/target/u-boot/Config.in b/target/u-boot/Config.in
index 815948524..a91820cf8 100644
--- a/target/u-boot/Config.in
+++ b/target/u-boot/Config.in
@@ -1,9 +1,56 @@
-config BR2_TARGET_UBOOT
+config BR2_TARGET_CUSTOM_UBOOT
+	bool
+	help
+	  A target can "select" this to disable
+	  the build of vanilla u-boot.
+
+menuconfig BR2_TARGET_UBOOT
 	bool "Das U-Boot Boot Monitor"
-	depends on !BR2_TARGET_AT91
+	depends on !BR2_TARGET_CUSTOM_UBOOT
 	help
 	  Build "Das U-Boot" Boot Monitor
 
+if BR2_TARGET_UBOOT
+choice
+	prompt "U-Boot Version"
+	default BR2_TARGET_UBOOT_2009_01_RC1
+	help
+	  Select the specific Linux version you want to use
+	
+config BR2_TARGET_UBOOT_2009_01_RC1
+	bool "u-boot-2009.01-rc1"
+	depends on BR2_TARGET_UBOOT
+	help
+	  Use u-boot from December 2008 (RC1)
+
+config BR2_TARGET_UBOOT_2008_10
+	bool "u-boot-2008.10"
+	depends on BR2_TARGET_UBOOT
+	help
+	  Use u-boot from October 2008
+	
+config BR2_TARGET_UBOOT_1_3_4
+	bool "u-boot-1.3.4"
+	depends on BR2_TARGET_UBOOT
+	help
+	  Use u-boot from mid 2008
+	
+config BR2_TARGET_UBOOT_2009_01
+	bool "u-boot-2009.01"
+	depends on BR2_TARGET_UBOOT
+	help
+	  Use u-boot from January 2009
+	  Release date 2009-01-17
+
+endchoice
+
+config BR2_UBOOT_VERSION
+	string
+	default "2009.01-rc1"	if BR2_TARGET_UBOOT_2009_01_RC1
+	default "2008.10"	if BR2_TARGET_UBOOT_2008_10
+	default "1.3.4"		if BR2_TARGET_UBOOT_1_3_4
+	default "2009.01"	if BR2_TARGET_UBOOT_2009_01
+
 config BR2_TARGET_UBOOT_BOARDNAME
 	string "board name"
 	depends on BR2_TARGET_UBOOT
@@ -19,6 +66,62 @@ config BR2_TARGET_UBOOT_CUSTOM_PATCH
 	  If your board requires a custom patch, add the path to the file here.
 	  Most users may leave this empty
 
+choice
+	prompt "Bootsource"
+	depends on BR2_BOOTSOURCE
+	default BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD
+
+	config BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD
+	bool "Boot from dataflashcard"
+	depends on BR2_BOOTSOURCE_DATAFLASHCARD
+	help
+	  
+
+	config BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH
+	bool "Boot from dataflash
+	depends on BR2_BOOTSOURCE_DATAFLASH
+	help
+	  
+
+	config BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH
+	bool "Boot from a NAND flash"
+	depends on BR2_BOOTSOURCE_NANDFLASH
+	help
+	  Build u-boot with environment in the NAND flash
+
+	config BR2_TARGET_UBOOT_BOOTSOURCE_FLASH
+	bool "Boot from a parallell flash"
+	depends on BR2_BOOTSOURCE_FLASH
+	help
+	  Build u-boot with environment in a flash RAM
+
+	config BR2_TARGET_UBOOT_BOOTSOURCE_SDCARD
+	bool "Boot from a NAND flash"
+	depends on BR2_BOOTSOURCE_SDCARD
+	help
+	  Build u-boot with environment on an SD-Card
+	  Not yet supported
+
+	config BR2_TARGET_UBOOT_BOOTSOURCE_EEPROM
+	bool "Boot from a serial EEPROM"
+	depends on BR2_BOOTSOURCE_EEPROM
+	help
+	  Build u-boot with environment in a serial EEPROM
+	  Not yet supported
+
+
+endchoice
+
+config BR2_TARGET_UBOOT_BOOTSOURCE
+	string
+	depends on BR2_BOOTSOURCE
+	default "dataflash"	if BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD
+	default "dataflash"	if BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH
+	default "nandflash"	if BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH
+	default "flash"		if BR2_TARGET_UBOOT_BOOTSOURCE_FLASH
+	default "sdcard"	if BR2_TARGET_UBOOT_BOOTSOURCE_SDCARD
+	default "eeprom"	if BR2_TARGET_UBOOT_BOOTSOURCE_EEPROM
+
 config BR2_TARGET_UBOOT_SERVERIP
 	string "server ip"
 	depends on BR2_TARGET_UBOOT
@@ -80,3 +183,45 @@ config BR2_TARGET_UBOOT_TOOL_ENV
 	depends on BR2_TARGET_UBOOT
 	help
 	  Install fw_printenv / fw_setenv tools in target.
+endif
+
+config BR2_BOOTSOURCE_DATAFLASHCARD
+	bool
+	help
+	  Allow use of a dataflashcard as a boot source
+
+config BR2_BOOTSOURCE_DATAFLASH
+	bool
+	help
+	  Allow use of a dataflash as a boot source
+
+config BR2_BOOTSOURCE_NANDFLASH
+	bool
+	help
+	  Allow use of a NAND flash as a boot source
+
+config BR2_BOOTSOURCE_FLASH
+	bool
+	help
+	  Allow use of a flash RAM as a boot source
+
+config BR2_BOOTSOURCE_SDCARD
+	bool
+	help
+	  Allow use of an SD-card as a boot source
+
+config BR2_BOOTSOURCE_EEPROM
+	bool
+	help
+	  Allow use of a serial eeprom as a boot source
+
+config	BR2_BOOTSOURCE
+	bool
+	default y if BR2_BOOTSOURCE_DATAFLASHCARD
+	default y if BR2_BOOTSOURCE_DATAFLASH
+	default y if BR2_BOOTSOURCE_NANDFLASH
+	default y if BR2_BOOTSOURCE_FLASH
+	default y if BR2_BOOTSOURCE_SDCARD
+	default y if BR2_BOOTSOURCE_EEPROM
+	default n
+
diff --git a/target/u-boot/Makefile.in b/target/u-boot/Makefile.in
index 001bc8881..8565f2e9d 100644
--- a/target/u-boot/Makefile.in
+++ b/target/u-boot/Makefile.in
@@ -3,16 +3,24 @@
 # U-Boot
 #
 #############################################################
-U_BOOT_VERSION:=1.3.4
+U_BOOT_VERSION:=$(strip $(subst ",,$(BR2_UBOOT_VERSION)))
+#"))
+
 U_BOOT_SOURCE:=u-boot-$(U_BOOT_VERSION).tar.bz2
 U_BOOT_SITE:=ftp://ftp.denx.de/pub/u-boot
 U_BOOT_DIR:=$(PROJECT_BUILD_DIR)/u-boot-$(U_BOOT_VERSION)
 U_BOOT_PATCH_DIR:=$(PROJECT_BUILD_DIR)/u-boot-patches
 U_BOOT_CAT:=$(BZCAT)
 U_BOOT_BIN:=u-boot.bin
+U_BOOT_TARGET:=$(BOARD_NAME)-u-boot-$(U_BOOT_VERSION)-$(DATE).bin
 U_BOOT_TOOLS_BIN:=mkimage
+U_BOOT_TOOLS:=$(STAGING_DIR)/usr/bin/$(U_BOOT_TOOLS_BIN)
 # u-boot still uses arch=ppc for powerpc
 U_BOOT_ARCH=$(KERNEL_ARCH:powerpc=ppc)
+ifeq ($(UBOOT_BOARD_NAME),"")
+UBOOT_BOARD_NAME:=$(strip $(subst ",,$(BR2_TARGET_UBOOT_BOARDNAME)))
+#"))
+endif
 
 ifneq ($(BR2_TARGET_U_BOOT_CONFIG_BOARD),)
 U_BOOT_INC_CONF_FILE:=$(U_BOOT_DIR)/include/configs/$(subst _config,,$(BR2_TARGET_U_BOOT_CONFIG_BOARD)).h
@@ -46,7 +54,7 @@ $(U_BOOT_DIR)/.unpacked: $(DL_DIR)/$(U_BOOT_SOURCE)
 	touch $@
 
 $(U_BOOT_DIR)/.patched: $(U_BOOT_DIR)/.unpacked
-	toolchain/patch-kernel.sh $(U_BOOT_DIR) target/u-boot/ \
+	toolchain/patch-kernel.sh $(U_BOOT_DIR) target/u-boot/$(U_BOOT_VERSION) \
 		u-boot-$(U_BOOT_VERSION)-\*.patch \
 		u-boot-$(U_BOOT_VERSION)-\*.patch.$(ARCH)
 ifneq ($(strip $(BR2_TARGET_UBOOT_CUSTOM_PATCH)),"")
@@ -67,7 +75,7 @@ $(U_BOOT_DIR)/.configured: $(U_BOOT_DIR)/.header_copied
 		CFLAGS="$(TARGET_CFLAGS)"	\
 		LDFLAGS="$(TARGET_LDFLAGS)"	\
 		$(MAKE) -C $(U_BOOT_DIR)	\
-		$(BR2_TARGET_UBOOT_BOARDNAME)_config
+		$(UBOOT_BOARD_NAME)_config
 	touch $@
 
 $(U_BOOT_DIR)/.header_modified: $(U_BOOT_DIR)/.configured
@@ -120,7 +128,12 @@ $(U_BOOT_DIR)/$(U_BOOT_BIN): $(U_BOOT_DIR)/.header_modified
 		 -C $(U_BOOT_DIR)
 
 $(BINARIES_DIR)/$(U_BOOT_BIN): $(U_BOOT_DIR)/$(U_BOOT_BIN)
-	cp -dpf $(U_BOOT_DIR)/$(U_BOOT_BIN) $(BINARIES_DIR)
+	rm -f $(BINARIES_DIR)/$(U_BOOT_TARGET)
+	rm -f $(BINARIES_DIR)/$(U_BOOT_BIN)
+	cp -dpf $(U_BOOT_DIR)/$(U_BOOT_BIN) $(BINARIES_DIR)/$(U_BOOT_TARGET)
+	(cd $(BINARIES_DIR); ln -s $(U_BOOT_TARGET) $(U_BOOT_BIN)) 
+
+$(U_BOOT_TOOLS):	$(U_BOOT_DIR)/tools/$(U_BOOT_TOOLS_BIN)
 	cp -dpf $(U_BOOT_DIR)/tools/$(U_BOOT_TOOLS_BIN) $(STAGING_DIR)/usr/bin/
 
 $(TARGET_DIR)/usr/bin/mkimage: $(U_BOOT_DIR)/$(U_BOOT_BIN)
@@ -138,11 +151,11 @@ $(TARGET_DIR)/usr/sbin/fw_printenv: $(U_BOOT_DIR)/$(U_BOOT_BIN)
 	$(STRIPCMD) $(STRIP_STRIP_UNNEEDED) $@
 	ln -sf fw_printenv $(TARGET_DIR)/usr/sbin/fw_setenv
 
-u-boot: $(BINARIES_DIR)/$(U_BOOT_BIN) $(U_BOOT_TARGET_TOOLS)
+u-boot: $(BINARIES_DIR)/$(U_BOOT_BIN) $(U_BOOT_TOOLS) $(U_BOOT_TARGET_TOOLS)
 
 u-boot-clean:
 	-$(MAKE) -C $(U_BOOT_DIR) clean
-	rm -f $(STAGING_DIR)/usr/bin/$(U_BOOT_TOOLS_BIN) $(U_BOOT_TARGET_TOOLS)
+	rm -f $(U_BOOT_TOOLS) $(U_BOOT_TARGET_TOOLS)
 
 u-boot-dirclean:
 	rm -rf $(U_BOOT_DIR)
@@ -161,7 +174,7 @@ endif
 u-boot-status:
 	@echo
 	@echo U_BOOT_INC_CONF_FILE = $(U_BOOT_INC_CONF_FILE)
-	@echo
+	@echo BR2_UBOOT_VERSION = $(BR2_UBOOT_VERSION)
 	@echo BR2_TARGET_U_BOOT_CONFIG_HEADER_FILE = $(BR2_TARGET_U_BOOT_CONFIG_HEADER_FILE)
 	@echo BR2_TARGET_U_BOOT_CONFIG_BOARD = $(BR2_TARGET_U_BOOT_CONFIG_BOARD)
 	@echo BR2_TARGET_UBOOT_SERVERIP = $(BR2_TARGET_UBOOT_SERVERIP)
@@ -173,5 +186,14 @@ u-boot-status:
 	@echo BR2_TARGET_UBOOT_BOOTARGS = $(BR2_TARGET_UBOOT_BOOTARGS)
 	@echo BR2_TARGET_UBOOT_BOOTCMD = $(BR2_TARGET_UBOOT_BOOTCMD)
 	@echo BR2_TARGET_UBOOT_SILENT = $(BR2_TARGET_UBOOT_SILENT)
-	@echo
+	@echo BR2_BOOTSOURCE=$(BR2_BOOTSOURCE)
+	@echo BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD=$(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASHCARD)
+	@echo BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH=$(BR2_TARGET_UBOOT_BOOTSOURCE_DATAFLASH)
+	@echo BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH=$(BR2_TARGET_UBOOT_BOOTSOURCE_NANDFLASH)
+	@echo BR2_TARGET_UBOOT_BOOTSOURCE_FLASH=$(BR2_TARGET_UBOOT_BOOTSOURCE_FLASH)
+	@echo BR2_TARGET_UBOOT_BOOTSOURCE_SDCARD=$(BR2_TARGET_UBOOT_BOOTSOURCE_SDCARD)
+	@echo BR2_TARGET_UBOOT_BOOTSOURCE_EEPROM=$(BR2_TARGET_UBOOT_BOOTSOURCE_EEPROM)
+	@echo UBOOT_BOARD_NAME=$(UBOOT_BOARD_NAME)
+	@echo TEST=$(TEST)
 	@exit 0
+