diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2012-11-03 08:27:59 +0000 |
---|---|---|
committer | Peter Korsgaard <jacmet@sunsite.dk> | 2012-11-04 12:51:38 +0100 |
commit | 79ee3c1f847ef472d93c761f0744e3102e707750 (patch) | |
tree | 91805209bc26dcfaf944032be8a695a428e18625 /arch/Config.in.x86 | |
parent | 6c3e3ad4197714ea39fcd49d572a1713f803d835 (diff) | |
download | buildroot-novena-79ee3c1f847ef472d93c761f0744e3102e707750.tar.gz buildroot-novena-79ee3c1f847ef472d93c761f0744e3102e707750.zip |
Split target/Config.in.arch into multiple Config.in.* in arch/
target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:
* An initial Config.in that lists the top-level architecture, and
sources the arch-specific Config.in.<arch> files, as well as
Config.in.common (see below)
* One Config.in.<arch> per architecture, listing the CPU families,
ABI choices, etc.
* One Config.in.common that defines the gcc mtune, march, mcpu values
and other hidden options.
[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Diffstat (limited to 'arch/Config.in.x86')
-rw-r--r-- | arch/Config.in.x86 | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86 new file mode 100644 index 000000000..4f32d7458 --- /dev/null +++ b/arch/Config.in.x86 @@ -0,0 +1,146 @@ +# i386/x86_64 cpu features +config BR2_X86_CPU_HAS_MMX + bool +config BR2_X86_CPU_HAS_SSE + bool +config BR2_X86_CPU_HAS_SSE2 + bool +config BR2_X86_CPU_HAS_SSE3 + bool +config BR2_X86_CPU_HAS_SSSE3 + bool + +choice + prompt "Target Architecture Variant" + depends on BR2_i386 || BR2_x86_64 + default BR2_x86_i586 if BR2_i386 + default BR2_x86_generic if BR2_x86_64 + help + Specific CPU variant to use + +config BR2_x86_generic + bool "generic" +config BR2_x86_i386 + bool "i386" + depends on !BR2_x86_64 +config BR2_x86_i486 + bool "i486" + depends on !BR2_x86_64 +config BR2_x86_i586 + bool "i586" + depends on !BR2_x86_64 +config BR2_x86_i686 + bool "i686" + depends on !BR2_x86_64 +config BR2_x86_pentiumpro + bool "pentium pro" + depends on !BR2_x86_64 +config BR2_x86_pentium_mmx + bool "pentium MMX" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_pentium_m + bool "pentium mobile" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_pentium2 + bool "pentium2" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_pentium3 + bool "pentium3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_pentium4 + bool "pentium4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + depends on !BR2_x86_64 +config BR2_x86_prescott + bool "prescott" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + depends on !BR2_x86_64 +config BR2_x86_nocona + bool "nocona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_core2 + bool "core2" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 +config BR2_x86_atom + bool "atom" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 + select BR2_X86_CPU_HAS_SSSE3 +config BR2_x86_k6 + bool "k6" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_k6_2 + bool "k6-2" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_athlon + bool "athlon" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_athlon_4 + bool "athlon-4" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_opteron + bool "opteron" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 +config BR2_x86_opteron_sse3 + bool "opteron w/ SSE3" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_barcelona + bool "barcelona" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + select BR2_X86_CPU_HAS_SSE2 + select BR2_X86_CPU_HAS_SSE3 +config BR2_x86_geode + bool "geode" + # Don't include MMX support because there several variant of geode + # processor, some with MMX support, some without. + # See: http://en.wikipedia.org/wiki/Geode_%28processor%29 + depends on !BR2_x86_64 +config BR2_x86_c3 + bool "Via/Cyrix C3 (Samuel/Ezra cores)" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_c32 + bool "Via C3-2 (Nehemiah cores)" + select BR2_X86_CPU_HAS_MMX + select BR2_X86_CPU_HAS_SSE + depends on !BR2_x86_64 +config BR2_x86_winchip_c6 + bool "IDT Winchip C6" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +config BR2_x86_winchip2 + bool "IDT Winchip 2" + select BR2_X86_CPU_HAS_MMX + depends on !BR2_x86_64 +endchoice |