Split target/Config.in.arch into multiple Config.in.* in arch/

target/Config.in.arch had become too long, and we want to remove the
target/ directory. So let's move it to arch/ and split it this way:

 * An initial Config.in that lists the top-level architecture, and
   sources the arch-specific Config.in.<arch> files, as well as
   Config.in.common (see below)

 * One Config.in.<arch> per architecture, listing the CPU families,
   ABI choices, etc.

 * One Config.in.common that defines the gcc mtune, march, mcpu values
   and other hidden options.

[Peter: space->tab fix, mipsel64 little endian, mips3 as noted by Arnout]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>

1 files changed, 245 insertions, 0 deletions

diff --git a/arch/Config.in.common b/arch/Config.in.common
new file mode 100644
index 000000000..1ed9929f0
--- /dev/null
+++ b/arch/Config.in.common
@@ -0,0 +1,245 @@
+config BR2_ARCH
+	string
+	default "arm"		if BR2_arm
+	default "armeb"		if BR2_armeb
+	default "aarch64"       if BR2_aarch64
+	default "avr32"		if BR2_avr32
+	default "bfin"		if BR2_bfin
+	default "i386"		if BR2_x86_i386
+	default "i486"		if BR2_x86_i486
+	default "i586"		if BR2_x86_i586
+	default "i586"		if BR2_x86_pentium_mmx
+	default "i586"		if BR2_x86_geode
+	default "i586"		if BR2_x86_c3
+	default "i686"		if BR2_x86_c32
+	default "i586"		if BR2_x86_winchip_c6
+	default "i586"		if BR2_x86_winchip2
+	default "i686"		if BR2_x86_i686
+	default "i686"		if BR2_x86_pentium2
+	default "i686"		if BR2_x86_pentium3
+	default "i686"		if BR2_x86_pentium4
+	default "i686"		if BR2_x86_pentium_m
+	default "i686"		if BR2_x86_pentiumpro
+	default "i686"		if BR2_x86_prescott
+	default "i686"		if BR2_x86_nocona && BR2_i386
+	default "i686"		if BR2_x86_core2 && BR2_i386
+	default "i686"		if BR2_x86_atom && BR2_i386
+	default "i686"		if BR2_x86_opteron && BR2_i386
+	default "i686"		if BR2_x86_opteron_sse3 && BR2_i386
+	default "i686"		if BR2_x86_barcelona && BR2_i386
+	default "i686"		if BR2_x86_k6
+	default "i686"		if BR2_x86_k6_2
+	default "i686"		if BR2_x86_athlon
+	default "i686"		if BR2_x86_athlon_4
+	default "x86_64"	if BR2_x86_64
+	default "m68k"		if BR2_m68k
+	default "microblaze"	if BR2_microblaze
+	default "mips"		if BR2_mips
+	default "mipsel"	if BR2_mipsel
+	default "mips64"	if BR2_mips64
+	default "mips64el"	if BR2_mips64el
+	default "powerpc"	if BR2_powerpc
+	default "sh2"		if BR2_sh2
+	default "sh2a"		if BR2_sh2a
+	default "sh3"		if BR2_sh3
+	default "sh3eb"		if BR2_sh3eb
+	default "sh4"		if BR2_sh4
+	default "sh4eb"		if BR2_sh4eb
+	default "sh4a"		if BR2_sh4a
+	default "sh4aeb"	if BR2_sh4aeb
+	default "sh64"		if BR2_sh64
+	default "sparc"		if BR2_sparc
+
+
+config BR2_ENDIAN
+	string
+	default "LITTLE" if BR2_arm || BR2_bfin || BR2_i386 || BR2_mipsel || BR2_mips64el || \
+			    BR2_sh3 || BR2_sh4 || BR2_sh4a || BR2_x86_64 || BR2_sh64 || \
+			    BR2_microblazeel
+	default "BIG"    if BR2_armeb || BR2_avr32 || BR2_m68k || BR2_mips || BR2_mips64 || \
+			    BR2_powerpc || BR2_sh2 || BR2_sh2a || \
+			    BR2_sh3eb || BR2_sh4eb || BR2_sh4aeb || BR2_sparc || \
+			    BR2_microblazebe
+
+config BR2_GCC_TARGET_TUNE
+	string
+	default i386		if BR2_x86_i386
+	default i486		if BR2_x86_i486
+	default i586		if BR2_x86_i586
+	default pentium-mmx	if BR2_x86_pentium_mmx
+	default i686		if BR2_x86_i686
+	default pentiumpro	if BR2_x86_pentiumpro
+	default pentium-m	if BR2_x86_pentium_m
+	default pentium2	if BR2_x86_pentium2
+	default pentium3	if BR2_x86_pentium3
+	default pentium4	if BR2_x86_pentium4
+	default prescott	if BR2_x86_prescott
+	default nocona		if BR2_x86_nocona
+	default core2		if BR2_x86_core2
+	default atom		if BR2_x86_atom
+	default k8		if BR2_x86_opteron
+	default k8-sse3		if BR2_x86_opteron_sse3
+	default barcelona	if BR2_x86_barcelona
+	default k6		if BR2_x86_k6
+	default k6-2		if BR2_x86_k6_2
+	default athlon		if BR2_x86_athlon
+	default athlon-4	if BR2_x86_athlon_4
+	default winchip-c6	if BR2_x86_winchip_c6
+	default winchip2	if BR2_x86_winchip2
+	default c3		if BR2_x86_c3
+	default c3-2		if BR2_x86_c32
+	default geode		if BR2_x86_geode
+	default generic		if BR2_x86_generic
+	default arm600		if BR2_arm600
+	default arm610		if BR2_arm610
+	default arm620		if BR2_arm620
+	default arm7tdmi	if BR2_arm7tdmi
+	default arm7tdmi	if BR2_arm720t
+	default arm7tdmi	if BR2_arm740t
+	default arm920		if BR2_arm920
+	default arm920t		if BR2_arm920t
+	default arm922t		if BR2_arm922t
+	default arm926ej-s	if BR2_arm926t
+	default arm1136j-s	if BR2_arm1136j_s
+	default arm1136jf-s	if BR2_arm1136jf_s
+	default arm1176jz-s	if BR2_arm1176jz_s
+	default arm1176jzf-s	if BR2_arm1176jzf_s
+	default cortex-a8	if BR2_cortex_a8
+	default cortex-a9	if BR2_cortex_a9
+	default strongarm110	if BR2_sa110
+	default strongarm1100	if BR2_sa1100
+	default xscale		if BR2_xscale
+	default iwmmxt		if BR2_iwmmxt
+	default 68000		if BR2_m68k_68000
+	default 68010		if BR2_m68k_68010
+	default 68020		if BR2_m68k_68020
+	default 68030		if BR2_m68k_68030
+	default 68040		if BR2_m68k_68040
+	default 68060		if BR2_m68k_68060
+	default mips1		if BR2_mips_1
+	default mips2		if BR2_mips_2
+	default mips3		if BR2_mips_3
+	default mips4		if BR2_mips_4
+	default mips32		if BR2_mips_32
+	default mips32r2	if BR2_mips_32r2
+	default mips64		if BR2_mips_64
+	default mips64r2	if BR2_mips_64r2
+	default 401		if BR2_powerpc_401
+	default 403		if BR2_powerpc_403
+	default 405		if BR2_powerpc_405
+	default 405fp		if BR2_powerpc_405fp
+	default 440		if BR2_powerpc_440
+	default 440fp		if BR2_powerpc_440fp
+	default 505		if BR2_powerpc_505
+	default 601		if BR2_powerpc_601
+	default 602		if BR2_powerpc_602
+	default 603		if BR2_powerpc_603
+	default 603e		if BR2_powerpc_603e
+	default 604		if BR2_powerpc_604
+	default 604e		if BR2_powerpc_604e
+	default 620		if BR2_powerpc_620
+	default 630		if BR2_powerpc_630
+	default 740		if BR2_powerpc_740
+	default 7400		if BR2_powerpc_7400
+	default 7450		if BR2_powerpc_7450
+	default 750		if BR2_powerpc_750
+	default 801		if BR2_powerpc_801
+	default 821		if BR2_powerpc_821
+	default 823		if BR2_powerpc_823
+	default 860		if BR2_powerpc_860
+	default 970		if BR2_powerpc_970
+	default 8540		if BR2_powerpc_8540
+	default	8548		if BR2_powerpc_8548
+	default e300c2		if BR2_powerpc_e300c2
+	default e300c3		if BR2_powerpc_e300c3
+	default e500mc		if BR2_powerpc_e500mc
+	default v7		if BR2_sparc_v7
+	default cypress		if BR2_sparc_cypress
+	default v8		if BR2_sparc_v8
+	default supersparc	if BR2_sparc_supersparc
+	default hypersparc	if BR2_sparc_hypersparc
+	default sparclite	if BR2_sparc_sparclite
+	default f930		if BR2_sparc_f930
+	default f934		if BR2_sparc_f934
+	default sparclite86x	if BR2_sparc_sparclite86x
+	default sparclet	if BR2_sparc_sparclet
+	default tsc701		if BR2_sparc_tsc701
+	default v9		if BR2_sparc_v9
+	default v9		if BR2_sparc_v9a
+	default v9		if BR2_sparc_v9b
+	default ultrasparc	if BR2_sparc_ultrasparc
+	default ultrasparc3	if BR2_sparc_ultrasparc3
+	default niagara		if BR2_sparc_niagara
+
+config BR2_GCC_TARGET_ARCH
+	string
+	default i386		if BR2_x86_i386
+	default i486		if BR2_x86_i486
+	default i586		if BR2_x86_i586
+	default pentium-mmx	if BR2_x86_pentium_mmx
+	default i686		if BR2_x86_i686
+	default pentiumpro	if BR2_x86_pentiumpro
+	default pentium-m	if BR2_x86_pentium_m
+	default pentium2	if BR2_x86_pentium2
+	default pentium3	if BR2_x86_pentium3
+	default pentium4	if BR2_x86_pentium4
+	default prescott	if BR2_x86_prescott
+	default nocona		if BR2_x86_nocona
+	default core2		if BR2_x86_core2
+	default atom		if BR2_x86_atom
+	default k8		if BR2_x86_opteron
+	default k8-sse3		if BR2_x86_opteron_sse3
+	default barcelona	if BR2_x86_barcelona
+	default k6		if BR2_x86_k6
+	default k6-2		if BR2_x86_k6_2
+	default athlon		if BR2_x86_athlon
+	default athlon-4	if BR2_x86_athlon_4
+	default winchip-c6	if BR2_x86_winchip_c6
+	default winchip2	if BR2_x86_winchip2
+	default c3		if BR2_x86_c3
+	default c3-2		if BR2_x86_c32
+	default geode		if BR2_x86_geode
+	default armv4t		if BR2_arm7tdmi
+	default armv3		if BR2_arm610
+	default armv3		if BR2_arm710
+	default armv4t		if BR2_arm720t
+	default armv4t		if BR2_arm920t
+	default armv4t		if BR2_arm922t
+	default armv5te		if BR2_arm926t
+	default armv5t		if BR2_arm10t
+	default armv6j		if BR2_arm1136jf_s
+	default armv6zk		if BR2_arm1176jz_s
+	default armv6zk		if BR2_arm1176jzf_s
+	default armv7-a		if BR2_cortex_a8
+	default armv7-a		if BR2_cortex_a9
+	default armv4		if BR2_sa110
+	default armv4		if BR2_sa1100
+	default armv5te		if BR2_xscale
+	default iwmmxt		if BR2_iwmmxt
+	default 68000		if BR2_m68k_68000
+	default 68010		if BR2_m68k_68010
+	default 68020		if BR2_m68k_68020
+	default 68030		if BR2_m68k_68030
+	default 68040		if BR2_m68k_68040
+	default 68060		if BR2_m68k_68060
+
+config BR2_GCC_TARGET_ABI
+	string
+	default apcs-gnu	if BR2_ARM_OABI
+	default aapcs-linux	if BR2_ARM_EABI
+	default 32		if BR2_MIPS_OABI32
+	default n32		if BR2_MIPS_NABI32
+	default 64		if BR2_MIPS_NABI64
+	default altivec		if BR2_powerpc && BR2_PPC_ABI_altivec
+	default no-altivec	if BR2_powerpc && BR2_PPC_ABI_no-altivec
+	default spe		if BR2_powerpc && BR2_PPC_ABI_spe
+	default no-spe		if BR2_powerpc && BR2_PPC_ABI_no-spe
+	default ibmlongdouble	if BR2_powerpc && BR2_PPC_ABI_ibmlongdouble
+	default ieeelongdouble	if BR2_powerpc && BR2_PPC_ABI_ieeelongdouble
+
+config BR2_GCC_TARGET_CPU
+	string
+	default sparchfleon	if BR2_sparc_sparchfleon
+	default sparchfleonv8	if BR2_sparc_sparchfleonv8
+	default sparcsfleon	if BR2_sparc_sparcsfleon
+	default sparcsfleonv8	if BR2_sparc_sparcsfleonv8