From b31c07157b7b8ca7e8823749e140fcab24b787d2 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Tue, 8 Oct 2013 22:05:21 -0400
Subject: working xula2 sim/syn/prog system

---
 hdl/main_xula2.vhd | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 hdl/main_xula2.vhd

(limited to 'hdl/main_xula2.vhd')

diff --git a/hdl/main_xula2.vhd b/hdl/main_xula2.vhd
new file mode 100644
index 0000000..57368f8
--- /dev/null
+++ b/hdl/main_xula2.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity blinker is
+    Port ( clk_i : in  STD_LOGIC;
+           blinker_o : out  STD_LOGIC);
+end blinker;
+
+architecture Behavioral of blinker is
+signal cnt_r : std_logic_vector(22 downto 0) := (others=>'0');
+begin
+
+process(clk_i) is
+begin
+  if rising_edge(clk_i) then
+    cnt_r <= cnt_r + 1;
+  end if;
+end process;
+
+blinker_o <= cnt_r(22);
+
+end Behavioral;
-- 
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