From 7d9fb988443e94507a7d3ca6e0137aaf49af42e1 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Thu, 14 Mar 2013 12:50:17 -0400 Subject: improvements --- README | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'README') diff --git a/README b/README index cda84b1..f7c9069 100644 --- a/README +++ b/README @@ -17,6 +17,8 @@ lives in: ./hdl/project.v +Add other verilog synthesis (not testbench) files to ./hdl/*.v + To edit the project with the ISE GUI, try: make ise @@ -29,9 +31,9 @@ Simulate with isim via: make simulate -View the results using isim with: +View the results using the isim GUI with: - make isim_gui + make isim In isim, you can open the "signals.wcfg" in the file menu to reload a the logic analyzer configuration. This cfg file will not be valid if you delete any -- cgit v1.2.3