From eef34f2975ddb40d0aaedd7a0182111c22db47cf Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Thu, 14 Mar 2013 13:11:23 -0400
Subject: 'main', not 'project' top module by default

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 0fd1347..3b12d98 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 project = project
-top_module = project
+top_module = main
 vendor = xilinx
 
 # This is the chipset from the Xilinx SP605 dev board
-- 
cgit v1.2.3