From 1ad824a33038856ae9a61379b4f78f1f6e888fe8 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Fri, 4 Oct 2013 21:46:17 -0400
Subject: add concept of 'board' for seperate ucfs and top level modules

---
 Makefile | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 20e992a..8bdf2d2 100644
--- a/Makefile
+++ b/Makefile
@@ -5,19 +5,27 @@ top_module := main
 vendor := xilinx
 
 # This is the chipset from the Xilinx SP605 dev board
+board := sp605
 family := spartan6
 device := xc6slx45t
 speedgrade := -3
 device_package := fgg484
-part := $(device)$(speedgrade)-$(device_package)
 
+# This is the chipset for the Xess Xula 2 dev board
+#board := xula2
+#family := spartan6
+#device := XC6SLX25
+#speedgrade := -2
+#device_package := ft256
+
+part := $(device)$(speedgrade)-$(device_package)
 
 # is this build host 64 or 32 bits?
 hostbits := 64
 iseenv := /opt/Xilinx/14.3/ISE_DS/
 
 # list all .v files explicitly with vfiles (no hdl/*.v business)
-vfiles := hdl/project.v
+vfiles := hdl/$(top_module)_$(board).v
 #vfiles += hdl/yours.v
 
 # can only specify a single test bench file here (for now)
-- 
cgit v1.2.3