From 12fb9032819dde0ccd38dfc2645abbffb891cca9 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Tue, 12 Nov 2013 10:37:31 -0500
Subject: initial VHDL support

---
 Makefile | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 2b93161..9541815 100644
--- a/Makefile
+++ b/Makefile
@@ -33,6 +33,9 @@ verilog_files += hdl/rot13.v
 verilog_files += hdl/simple_uart.v
 #verilog_files += hdl/yours.v
 
+# all .vhd files explicitly also
+vhdl_files :=
+
 tbfiles := tb/rot13_tb.v
 tbfiles += tb/xula2_tb.v
 #tbfiles += tb/sp605_tb.v
-- 
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