From 92ed49e97997d769f41f42260e56a41f8391559d Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Tue, 12 Nov 2013 12:54:30 -0500 Subject: Part 1 of refactoring template files into ./contrib BROKEN without later parts (documentation and Makefile updates) This commit moves and deletes a lot of Xula2 and SP605 files around. It also includes a large cleanup of xilinx.mk --- README.tb_test | 12 -- README.xula2 | 16 -- TODO.template | 45 ----- contrib/README.tb_test | 12 ++ contrib/TODO.template | 45 +++++ contrib/default.opt | 42 +++++ contrib/empty.bmm | 1 + contrib/sp605/sp605.bitconf | 3 + contrib/sp605/sp605.mk | 12 ++ contrib/sp605/sp605.ucf | 449 ++++++++++++++++++++++++++++++++++++++++++++ contrib/xilinx.mk | 213 +++++++++++++-------- contrib/xula2.mk | 9 - contrib/xula2/README.xula2 | 16 ++ contrib/xula2/xula2.bitconf | 7 + contrib/xula2/xula2.mk | 24 +++ contrib/xula2/xula2.ucf | 69 +++++++ exampleproj.bmm | 1 - exampleproj.opt | 42 ----- sp605.bitconf | 3 - sp605.bmm | 1 - sp605.ucf | 449 -------------------------------------------- xula2.bitconf | 7 - xula2.bmm | 1 - xula2.ucf | 69 ------- 24 files changed, 817 insertions(+), 731 deletions(-) delete mode 100644 README.tb_test delete mode 100644 README.xula2 delete mode 100644 TODO.template create mode 100644 contrib/README.tb_test create mode 100644 contrib/TODO.template create mode 100644 contrib/default.opt create mode 100644 contrib/empty.bmm create mode 100644 contrib/sp605/sp605.bitconf create mode 100644 contrib/sp605/sp605.mk create mode 100644 contrib/sp605/sp605.ucf delete mode 100644 contrib/xula2.mk create mode 100644 contrib/xula2/README.xula2 create mode 100644 contrib/xula2/xula2.bitconf create mode 100644 contrib/xula2/xula2.mk create mode 100644 contrib/xula2/xula2.ucf delete mode 100644 exampleproj.bmm delete mode 100644 exampleproj.opt delete mode 100644 sp605.bitconf delete mode 100644 sp605.bmm delete mode 100644 sp605.ucf delete mode 100644 xula2.bitconf delete mode 100644 xula2.bmm delete mode 100644 xula2.ucf diff --git a/README.tb_test b/README.tb_test deleted file mode 100644 index 3be00d6..0000000 --- a/README.tb_test +++ /dev/null @@ -1,12 +0,0 @@ - -"testbenches" are helpful wrappers which exersize a piece of code. they should -live in ./tb/, end in "_tb.v" or "_tb.vhd", and have a signal file (ending in -"_tb.wcfg") associated with the same name. update the 'tbfiles' list in -Makefile. invoke the isim GUI with "make isim/name_tb" (for tb/name_tb.v). if -you make a source code change and don't want to reload the whole GUI, you can -do "make resim/name_tb" and then click the "Re-load" button. - -testbenches which can act as headless unit tests (reporting pass/fail by -printing to stdout) should be added to the 'alltests' list in Makefile. run the -test with 'make test/name_tb'; run all tests with 'make tests'. - diff --git a/README.xula2 b/README.xula2 deleted file mode 100644 index 3ca7d50..0000000 --- a/README.xula2 +++ /dev/null @@ -1,16 +0,0 @@ - -To upload bitfiles to the xula2 board, you first need to install the "xstools" -python package: - - https://pypi.python.org/pypi/XsTools/ - -IMPORTANT: if you get the following error when using the xstest.py python tool -with a xula2 board on linux: - - usb.core.USBError: [Errno 5] Input/output error - -and then your board resets (LED turns off), then you probably need to first -upgrade the PIC microcontroller firmware: - - sudo xsusbprg.py - diff --git a/TODO.template b/TODO.template deleted file mode 100644 index cc47521..0000000 --- a/TODO.template +++ /dev/null @@ -1,45 +0,0 @@ - -switch to .EXPORT_ALL_VARIABLES and/or .ONESHELL (as a refactor/cleanup)? - or is that too gmake specific... - -BUG: synth still seems to continue even if first build (verilog compile) - fails - -add .PRECIOUS for intermediate files we don't want to get deleted - -'lint' should use vfiles, not -I./hdl - -for fpga_editor: - DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file> - -effort levels seem high by default: - Overall effort level (-ol): High - Router effort level (-rl): High - -impact: - impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing) - -requests from AJ: - anything related to not rebuilding all the coregen when not necessary. - - e.g. want a make clean equivalent to removing the build dir but not the - cores. This should actually be the default behavior, with different - operator for nixing the cores. - - not auto rebuilding the cores when switching branches/commits if not - strictly necessary. Because git touches all the files, this may be - difficult. - - make isim/simulate will run to completion even if there were errors on - the build. - - In the case of make isim, isim will load and run the previously valid - simulation. Unless you happen to see the error go by in the build log, - you will unknowingly be simulating your previous build, whereas your - current build failed to compile. - - The solution is to have make simulate begin by deleting the previous - simulation executable, so that it must successfully create a new one - before loading isim. - -Add linting to tests (aka, tb/*_tb.v) diff --git a/contrib/README.tb_test b/contrib/README.tb_test new file mode 100644 index 0000000..3be00d6 --- /dev/null +++ b/contrib/README.tb_test @@ -0,0 +1,12 @@ + +"testbenches" are helpful wrappers which exersize a piece of code. they should +live in ./tb/, end in "_tb.v" or "_tb.vhd", and have a signal file (ending in +"_tb.wcfg") associated with the same name. update the 'tbfiles' list in +Makefile. invoke the isim GUI with "make isim/name_tb" (for tb/name_tb.v). if +you make a source code change and don't want to reload the whole GUI, you can +do "make resim/name_tb" and then click the "Re-load" button. + +testbenches which can act as headless unit tests (reporting pass/fail by +printing to stdout) should be added to the 'alltests' list in Makefile. run the +test with 'make test/name_tb'; run all tests with 'make tests'. + diff --git a/contrib/TODO.template b/contrib/TODO.template new file mode 100644 index 0000000..cc47521 --- /dev/null +++ b/contrib/TODO.template @@ -0,0 +1,45 @@ + +switch to .EXPORT_ALL_VARIABLES and/or .ONESHELL (as a refactor/cleanup)? + or is that too gmake specific... + +BUG: synth still seems to continue even if first build (verilog compile) + fails + +add .PRECIOUS for intermediate files we don't want to get deleted + +'lint' should use vfiles, not -I./hdl + +for fpga_editor: + DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file> + +effort levels seem high by default: + Overall effort level (-ol): High + Router effort level (-rl): High + +impact: + impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing) + +requests from AJ: + anything related to not rebuilding all the coregen when not necessary. + + e.g. want a make clean equivalent to removing the build dir but not the + cores. This should actually be the default behavior, with different + operator for nixing the cores. + + not auto rebuilding the cores when switching branches/commits if not + strictly necessary. Because git touches all the files, this may be + difficult. + + make isim/simulate will run to completion even if there were errors on + the build. + + In the case of make isim, isim will load and run the previously valid + simulation. Unless you happen to see the error go by in the build log, + you will unknowingly be simulating your previous build, whereas your + current build failed to compile. + + The solution is to have make simulate begin by deleting the previous + simulation executable, so that it must successfully create a new one + before loading isim. + +Add linting to tests (aka, tb/*_tb.v) diff --git a/contrib/default.opt b/contrib/default.opt new file mode 100644 index 0000000..7fe9d8b --- /dev/null +++ b/contrib/default.opt @@ -0,0 +1,42 @@ +-ifmt mixed +-ofmt NGC +-opt_mode speed +-opt_level 1 +-iuc NO +-keep_hierarchy no +-netlist_hierarchy as_optimized +-rtlview no +-glob_opt AllClockNets +-read_cores yes +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +#-dsp_utilization_ratio 100 +-safe_implementation No +-fsm_extract YES +-fsm_encoding Auto +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-shreg_extract YES +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +#-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/contrib/empty.bmm b/contrib/empty.bmm new file mode 100644 index 0000000..c915ec8 --- /dev/null +++ b/contrib/empty.bmm @@ -0,0 +1 @@ +// Empty file; this is a "Block Ram Memory Map" diff --git a/contrib/sp605/sp605.bitconf b/contrib/sp605/sp605.bitconf new file mode 100644 index 0000000..2a339b6 --- /dev/null +++ b/contrib/sp605/sp605.bitconf @@ -0,0 +1,3 @@ +-g Binary:yes +-g DriveDone:yes +-g StartupClk:Cclk diff --git a/contrib/sp605/sp605.mk b/contrib/sp605/sp605.mk new file mode 100644 index 0000000..857417b --- /dev/null +++ b/contrib/sp605/sp605.mk @@ -0,0 +1,12 @@ +# Configuration variables and build targets for the Xilinx Spartan6 SP605 Dev +# Board + +board := sp605 +family := spartan6 +device := xc6slx45t +speedgrade := -3 +device_package := fgg484 +bitconf_file := ./contrib/sp605/sp605.bitconf +ucf_file := ./contrib/sp605/sp605.ucf +opt_file := ./contrib/default.opt +mcs_datawidth := 16 diff --git a/contrib/sp605/sp605.ucf b/contrib/sp605/sp605.ucf new file mode 100644 index 0000000..9ad7857 --- /dev/null +++ b/contrib/sp605/sp605.ucf @@ -0,0 +1,449 @@ + +################## Clocks and Reset (not GTP) ##################### +# In this application USER_CLOCK is a 25MHz CTS MXO45HS-3C-25M0000 +# 5v, 50ppm, 5ps jitter (?) +NET "user_clock" LOC = "AB13"; ## +NET "user_clock" TNM_NET = "user_clock"; +TIMESPEC "TS_user_clock" = PERIOD "user_clock" 40 ns HIGH 50% INPUT_JITTER 5.0 ps; + +NET "reset_button" LOC = "H8" | CLOCK_DEDICATED_ROUTE = FALSE; ## 2 on SW6 pushbutton (active-high) + +################## GPIO, Switches, LEDs, Headers ##################### +NET "gpio_button<0>" LOC = "F3"; ## 2 on SW4 pushbutton (active-high) +NET "gpio_button<1>" LOC = "G6"; ## 2 on SW7 pushbutton (active-high) +NET "gpio_button<2>" LOC = "F5"; ## 2 on SW5 pushbutton (active-high) +NET "gpio_button<3>" LOC = "C1"; ## 2 on SW8 pushbutton (active-high) +## +# 1 on U52 (level shifter, U52.20 <-> gpio_header<0 <-> series R280 200 ohm <-> 1 on J55 +NET "gpio_header<0>" LOC = "G7" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; +# 3 on U52 (level shifter, U52.18 <-> gpio_header<0 <-> series R281 200 ohm <-> 2 on J55 +NET "gpio_header<1>" LOC = "H6" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; +# 4 on U52 (level shifter, U52.17 <-> gpio_header<0 <-> series R282 200 ohm <-> 3 on J55 +NET "gpio_header<2>" LOC = "D1" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; +# 5 on U52 (level shifter, U52.16 <-> gpio_header<0 <-> series R283 200 ohm <-> 4 on J55 +NET "gpio_header<3>" LOC = "R7" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; +## +NET "gpio_led<0>" LOC = "D17"; ## 2 on DS3 LEDh +NET "gpio_led<1>" LOC = "AB4"; ## 2 on DS4 LED +NET "gpio_led<2>" LOC = "D21"; ## 2 on DS5 LED +NET "gpio_led<3>" LOC = "W15"; ## 2 on DS6 LED +## +NET "gpio_switch<0>" LOC = "C18"; ## 1 on S2 DIP switch (active-high) +NET "gpio_switch<1>" LOC = "Y6"; ## 2 on S2 DIP switch (active-high) +NET "gpio_switch<2>" LOC = "W6"; ## 3 on S2 DIP switch (active-high) +NET "gpio_switch<3>" LOC = "E4"; ## 4 on S2 DIP switch (active-high) + +NET "uart_rx" LOC = "B21"; ## USB_1_RX +NET "uart_tx" LOC = "H17"; ## USB_1_TX + +############################################################################# +################### Entirely Unused Definitions Below ####################### +############################################################################# + +################## GIGE PHY ##################### +#NET "gige_col" LOC = "M16"; ## 114 on U46 "PHY_COL" +#NET "gige_crs" LOC = "N15"; ## 115 on U46 "PHY_CRS" +#NET "gige_int" LOC = "J20"; ## 32 on U46 "PHY_INT" +#NET "gige_mdc" LOC = "R19"; ## 35 on U46 "PHY_MDC" +#NET "gige_mdio" LOC = "V20"; ## 33 on U46 "PHY_MDIO" +#NET "gige_reset" LOC = "J22"; ## 36 on U46 "PHY_RESET" +#NET "gige_rxclk" LOC = "P20"; ## 7 on U46 "PHY_RXCLK" +#NET "gige_rxctl_rxdv" LOC = "T22"; ## 4 on U46 "PHY_RXCTL_RXDV" +#NET "gige_rx_data<0>" LOC = "P19"; ## 3 on U46 "PHY_RXD0" +#NET "gige_rx_data<1>" LOC = "Y22"; ## 128 on U46 "PHY_RXD1" +#NET "gige_rx_data<2>" LOC = "Y21"; ## 126 on U46 "PHY_RXD2" +#NET "gige_rx_data<3>" LOC = "W22"; ## 125 on U46 "PHY_RXD3" +#NET "gige_rx_data<4>" LOC = "W20"; ## 124 on U46 "PHY_RXD4" +#NET "gige_rx_data<5>" LOC = "V22"; ## 123 on U46 "PHY_RXD5" +#NET "gige_rx_data<6>" LOC = "V21"; ## 121 on U46 "PHY_RXD6" +#NET "gige_rx_data<7>" LOC = "U22"; ## 120 on U46 "PHY_RXD7" +#NET "gige_rxer" LOC = "U20"; ## 8 on U46 "PHY_RXER" +#NET "gige_txclk" LOC = "L20"; ## 10 on U46 "PHY_TXCLK" +#NET "gige_txctl_txen" LOC = "T8"; ## 16 on U46 "PHY_TXCTL_TXEN" +#NET "gige_txc_gtxclk" LOC = "AB7"; ## 14 on U46 "PHY_TXC_GTXCLK" +#NET "gige_tx_data<0>" LOC = "U10"; ## 18 on U46 "PHY_TXD0" +#NET "gige_tx_data<1>" LOC = "T10"; ## 19 on U46 "PHY_TXD1" +#NET "gige_tx_data<2>" LOC = "AB8"; ## 20 on U46 "PHY_TXD2" +#NET "gige_tx_data<3>" LOC = "AA8"; ## 24 on U46 "PHY_TXD3" +#NET "gige_tx_data<4>" LOC = "AB9"; ## 25 on U46 "PHY_TXD4" +#NET "gige_tx_data<5>" LOC = "Y9"; ## 26 on U46 "PHY_TXD5" +#NET "gige_tx_data<6>" LOC = "Y12"; ## 28 on U46 "PHY_TXD6" +#NET "gige_tx_data<7>" LOC = "W12"; ## 29 on U46 "PHY_TXD7" +#NET "gige_txer" LOC = "U8"; ## 13 on U46 "PHY_TXER" +## +#NET "CLK_33MHZ_SYSACE" LOC = "N19"; ## 93 on U17 +## +#NET "DVI_D0" LOC = "K16"; ## 63 on U31 (thru series R39 47.5 ohm) +#NET "DVI_D1" LOC = "U19"; ## 62 on U31 (thru series R38 47.5 ohm) +#NET "DVI_D2" LOC = "T20"; ## 61 on U31 (thru series R37 47.5 ohm) +#NET "DVI_D3" LOC = "N16"; ## 60 on U31 (thru series R36 47.5 ohm) +#NET "DVI_D4" LOC = "P16"; ## 59 on U31 (thru series R35 47.5 ohm) +#NET "DVI_D5" LOC = "M17"; ## 58 on U31 (thru series R34 47.5 ohm) +#NET "DVI_D6" LOC = "M18"; ## 55 on U31 (thru series R33 47.5 ohm) +#NET "DVI_D7" LOC = "R15"; ## 54 on U31 (thru series R32 47.5 ohm) +#NET "DVI_D8" LOC = "R16"; ## 53 on U31 (thru series R31 47.5 ohm) +#NET "DVI_D9" LOC = "P17"; ## 52 on U31 (thru series R30 47.5 ohm) +#NET "DVI_D10" LOC = "P18"; ## 51 on U31 (thru series R29 47.5 ohm) +#NET "DVI_D11" LOC = "R17"; ## 50 on U31 (thru series R28 47.5 ohm) +#NET "DVI_DE" LOC = "J17"; ## 2 on U31 (thru series R40 47.5 ohm) +#NET "DVI_GPIO1" LOC = "D22"; ## 18 on U31 +#NET "DVI_H" LOC = "J16"; ## 4 on U31 (thru series R41 47.5 ohm) +#NET "DVI_RESET_B" LOC = "L15"; ## 13 on U31 +#NET "DVI_V" LOC = "B22"; ## 5 on U31 (thru series R42 47.5 ohm) +#NET "DVI_XCLK_N" LOC = "C22"; ## 56 on U31 +#NET "DVI_XCLK_P" LOC = "C20"; ## 57 on U31 +## +#NET "FLASH_A0" LOC = "N22"; ## 29 on U25 +#NET "FLASH_A1" LOC = "N20"; ## 25 on U25 +#NET "FLASH_A2" LOC = "M22"; ## 24 on U25 +#NET "FLASH_A3" LOC = "M21"; ## 23 on U25 +#NET "FLASH_A4" LOC = "L19"; ## 22 on U25 +#NET "FLASH_A5" LOC = "K20"; ## 21 on U25 +#NET "FLASH_A6" LOC = "H22"; ## 20 on U25 +#NET "FLASH_A7" LOC = "H21"; ## 19 on U25 +#NET "FLASH_A8" LOC = "L17"; ## 8 on U25 +#NET "FLASH_A9" LOC = "K17"; ## 7 on U25 +#NET "FLASH_A10" LOC = "G22"; ## 6 on U25 +#NET "FLASH_A11" LOC = "G20"; ## 5 on U25 +#NET "FLASH_A12" LOC = "K18"; ## 4 on U25 +#NET "FLASH_A13" LOC = "K19"; ## 3 on U25 +#NET "FLASH_A14" LOC = "H20"; ## 2 on U25 +#NET "FLASH_A15" LOC = "J19"; ## 1 on U25 +#NET "FLASH_A16" LOC = "E22"; ## 55 on U25 +#NET "FLASH_A17" LOC = "E20"; ## 18 on U25 +#NET "FLASH_A18" LOC = "F22"; ## 17 on U25 +#NET "FLASH_A19" LOC = "F21"; ## 16 on U25 +#NET "FLASH_A20" LOC = "H19"; ## 11 on U25 +#NET "FLASH_A21" LOC = "H18"; ## 10 on U25 +#NET "FLASH_A22" LOC = "F20"; ## 9 on U25 +#NET "FLASH_A23" LOC = "G19"; ## 26 on U25 +#NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## 34 on U25, 8 on U32 (thru series R132 100 ohm), 6 on J17 +#NET "FPGA_D1_MISO2" LOC = "R13"; ## 36 on U25, 3 on J17 +#NET "FPGA_D2_MISO3" LOC = "T14"; ## 39 on U25, 2 on J17 +#NET "FLASH_D3" LOC = "AA6"; ## 41 on U25 +#NET "FLASH_D4" LOC = "AB6"; ## 47 on U25 +#NET "FLASH_D5" LOC = "Y5"; ## 49 on U25 +#NET "FLASH_D6" LOC = "AB5"; ## 51 on U25 +#NET "FLASH_D7" LOC = "W9"; ## 53 on U25 +#NET "FLASH_D8" LOC = "T7"; ## 35 on U25 +#NET "FLASH_D9" LOC = "U6"; ## 37 on U25 +#NET "FLASH_D10" LOC = "AB19"; ## 40 on U25 +#NET "FLASH_D11" LOC = "AA18"; ## 42 on U25 +#NET "FLASH_D12" LOC = "AB18"; ## 48 on U25 +#NET "FLASH_D13" LOC = "Y13"; ## 50 on U25 +#NET "FLASH_D14" LOC = "AA12"; ## 52 on U25 +#NET "FLASH_D15" LOC = "AB12"; ## 54 on U25 +#NET "FLASH_WAIT" LOC = "T18"; ## 56 on U25 +#NET "FLASH_WE_B" LOC = "R20"; ## 14 on U25 +#NET "FLASH_OE_B" LOC = "P22"; ## 32 on U25 +#NET "FLASH_CE_B" LOC = "P21"; ## 30 on U25 +#NET "FLASH_ADV_B" LOC = "T19"; ## 46 on U25 +## NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## 44 on U25 (this signal goes to multiple destinations, see below) +## +#NET "FMC_CLK0_M2C_N" LOC = "G11"; ## H5 on J2 +#NET "FMC_CLK0_M2C_P" LOC = "H12"; ## H4 on J2 +#NET "FMC_CLK1_M2C_N" LOC = "F16"; ## G3 on J2 +#NET "FMC_CLK1_M2C_P" LOC = "E16"; ## G2 on J2 +#NET "FMC_DP0_C2M_N" LOC = "A16"; ## C3 on J2 +#NET "FMC_DP0_C2M_P" LOC = "B16"; ## C2 on J2 +#NET "FMC_DP0_M2C_N" LOC = "C15"; ## C7 on J2 +#NET "FMC_DP0_M2C_P" LOC = "D15"; ## C6 on J2 +## NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 (this signal goes to multiple destinations, see below) +## NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 (this signal goes to multiple destinations, see below) +#NET "FMC_LA00_CC_N" LOC = "F10"; ## G7 on J2 +#NET "FMC_LA00_CC_P" LOC = "G9"; ## G6 on J2 +#NET "FMC_LA01_CC_N" LOC = "F15"; ## D9 on J2 +#NET "FMC_LA01_CC_P" LOC = "F14"; ## D8 on J2 +#NET "FMC_LA02_N" LOC = "F9"; ## H8 on J2 +#NET "FMC_LA02_P" LOC = "G8"; ## H7 on J2 +#NET "FMC_LA03_N" LOC = "A18"; ## G10 on J2 +#NET "FMC_LA03_P" LOC = "B18"; ## G9 on J2 +#NET "FMC_LA04_N" LOC = "A19"; ## H11 on J2 +#NET "FMC_LA04_P" LOC = "C19"; ## H10 on J2 +#NET "FMC_LA05_N" LOC = "A4"; ## D12 on J2 +#NET "FMC_LA05_P" LOC = "C4"; ## D11 on J2 +#NET "FMC_LA06_N" LOC = "D5"; ## C11 on J2 +#NET "FMC_LA06_P" LOC = "D4"; ## C10 on J2 +#NET "FMC_LA07_N" LOC = "A2"; ## H14 on J2 +#NET "FMC_LA07_P" LOC = "B2"; ## H13 on J2 +#NET "FMC_LA08_N" LOC = "A20"; ## G13 on J2 +#NET "FMC_LA08_P" LOC = "B20"; ## G12 on J2 +#NET "FMC_LA09_N" LOC = "F8"; ## D15 on J2 +#NET "FMC_LA09_P" LOC = "F7"; ## D14 on J2 +#NET "FMC_LA10_N" LOC = "H11"; ## C15 on J2 +#NET "FMC_LA10_P" LOC = "H10"; ## C14 on J2 +#NET "FMC_LA11_N" LOC = "G15"; ## H17 on J2 +#NET "FMC_LA11_P" LOC = "H14"; ## H16 on J2 +#NET "FMC_LA12_N" LOC = "G13"; ## G16 on J2 +#NET "FMC_LA12_P" LOC = "H13"; ## G15 on J2 +#NET "FMC_LA13_N" LOC = "F17"; ## D18 on J2 +#NET "FMC_LA13_P" LOC = "G16"; ## D17 on J2 +#NET "FMC_LA14_N" LOC = "A17"; ## C19 on J2 +#NET "FMC_LA14_P" LOC = "C17"; ## C18 on J2 +#NET "FMC_LA15_N" LOC = "D19"; ## H20 on J2 +#NET "FMC_LA15_P" LOC = "D18"; ## H19 on J2 +#NET "FMC_LA16_N" LOC = "A5"; ## G19 on J2 +#NET "FMC_LA16_P" LOC = "C5"; ## G18 on J2 +#NET "FMC_LA17_CC_N" LOC = "AB11"; ## D21 on J2 +#NET "FMC_LA17_CC_P" LOC = "Y11"; ## D20 on J2 +#NET "FMC_LA18_CC_N" LOC = "U12"; ## C23 on J2 +#NET "FMC_LA18_CC_P" LOC = "T12"; ## C22 on J2 +#NET "FMC_LA19_N" LOC = "T11"; ## H23 on J2 +#NET "FMC_LA19_P" LOC = "R11"; ## H22 on J2 +#NET "FMC_LA20_N" LOC = "R8"; ## G22 on J2 +#NET "FMC_LA20_P" LOC = "R9"; ## G21 on J2 +#NET "FMC_LA21_N" LOC = "W11"; ## H26 on J2 +#NET "FMC_LA21_P" LOC = "V11"; ## H25 on J2 +#NET "FMC_LA22_N" LOC = "W8"; ## G25 on J2 +#NET "FMC_LA22_P" LOC = "V7"; ## G24 on J2 +#NET "FMC_LA23_N" LOC = "V9"; ## D24 on J2 +#NET "FMC_LA23_P" LOC = "U9"; ## D23 on J2 +#NET "FMC_LA24_N" LOC = "AB14"; ## H29 on J2 +#NET "FMC_LA24_P" LOC = "AA14"; ## H28 on J2 +#NET "FMC_LA25_N" LOC = "Y14"; ## G28 on J2 +#NET "FMC_LA25_P" LOC = "W14"; ## G27 on J2 +#NET "FMC_LA26_N" LOC = "U13"; ## D27 on J2 +#NET "FMC_LA26_P" LOC = "U14"; ## D26 on J2 +#NET "FMC_LA27_N" LOC = "AB10"; ## C27 on J2 +#NET "FMC_LA27_P" LOC = "AA10"; ## C26 on J2 +#NET "FMC_LA28_N" LOC = "AB16"; ## H32 on J2 +#NET "FMC_LA28_P" LOC = "AA16"; ## H31 on J2 +#NET "FMC_LA29_N" LOC = "U15"; ## G31 on J2 +#NET "FMC_LA29_P" LOC = "T15"; ## G30 on J2 +#NET "FMC_LA30_N" LOC = "AB15"; ## H35 on J2 +#NET "FMC_LA30_P" LOC = "Y15"; ## H34 on J2 +#NET "FMC_LA31_N" LOC = "V15"; ## G34 on J2 +#NET "FMC_LA31_P" LOC = "U16"; ## G33 on J2 +#NET "FMC_LA32_N" LOC = "Y18"; ## H38 on J2 +#NET "FMC_LA32_P" LOC = "W17"; ## H37 on J2 +#NET "FMC_LA33_N" LOC = "AB17"; ## G37 on J2 +#NET "FMC_LA33_P" LOC = "Y17"; ## G36 on J2 +#NET "FMC_PRSNT_M2C_L" LOC = "Y16"; ## H2 on J2 +#NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## D1 on J2, 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (thru series R260 DNP), 44 of U25 +#NET "FLASH_D13" LOC = "Y13"; ## 50 on U25 +#NET "FLASH_D14" LOC = "AA12"; ## 52 on U25 +#NET "FLASH_D15" LOC = "AB12"; ## 54 on U25 +#NET "FLASH_WAIT" LOC = "T18"; ## 56 on U25 +#NET "FLASH_WE_B" LOC = "R20"; ## 14 on U25 +#NET "FLASH_OE_B" LOC = "P22"; ## 32 on U25 +#NET "FLASH_CE_B" LOC = "P21"; ## 30 on U25 +#NET "FLASH_ADV_B" LOC = "T19"; ## 46 on U25 +## NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## 44 on U25 (this signal goes to multiple destinations, see below) +## +#NET "FMC_CLK0_M2C_N" LOC = "G11"; ## H5 on J2 +#NET "FMC_CLK0_M2C_P" LOC = "H12"; ## H4 on J2 +#NET "FMC_CLK1_M2C_N" LOC = "F16"; ## G3 on J2 +#NET "FMC_CLK1_M2C_P" LOC = "E16"; ## G2 on J2 +#NET "FMC_DP0_C2M_N" LOC = "A16"; ## C3 on J2 +#NET "FMC_DP0_C2M_P" LOC = "B16"; ## C2 on J2 +#NET "FMC_DP0_M2C_N" LOC = "C15"; ## C7 on J2 +#NET "FMC_DP0_M2C_P" LOC = "D15"; ## C6 on J2 +#NET "FMC_GBTCLK0_M2C_N" LOC = "F12"; ## D5 on J2 +#NET "FMC_GBTCLK0_M2C_P" LOC = "E12"; ## D4 on J2 +### NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 (this signal goes to multiple destinations, see below) +### NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 (this signal goes to multiple destinations, see below) +#NET "FMC_LA00_CC_N" LOC = "F10"; ## G7 on J2 +#NET "FMC_LA00_CC_P" LOC = "G9"; ## G6 on J2 +#NET "FMC_LA01_CC_N" LOC = "F15"; ## D9 on J2 +#NET "FMC_LA01_CC_P" LOC = "F14"; ## D8 on J2 +#NET "FMC_LA02_N" LOC = "F9"; ## H8 on J2 +#NET "FMC_LA02_P" LOC = "G8"; ## H7 on J2 +#NET "FMC_LA03_N" LOC = "A18"; ## G10 on J2 +#NET "FMC_LA03_P" LOC = "B18"; ## G9 on J2 +#NET "FMC_LA04_N" LOC = "A19"; ## H11 on J2 +#NET "FMC_LA04_P" LOC = "C19"; ## H10 on J2 +#NET "FMC_LA05_N" LOC = "A4"; ## D12 on J2 +#NET "FMC_LA05_P" LOC = "C4"; ## D11 on J2 +#NET "FMC_LA06_N" LOC = "D5"; ## C11 on J2 +#NET "FMC_LA06_P" LOC = "D4"; ## C10 on J2 +#NET "FMC_LA07_N" LOC = "A2"; ## H14 on J2 +#NET "FMC_LA07_P" LOC = "B2"; ## H13 on J2 +#NET "FMC_LA08_N" LOC = "A20"; ## G13 on J2 +#NET "FMC_LA08_P" LOC = "B20"; ## G12 on J2 +#NET "FMC_LA09_N" LOC = "F8"; ## D15 on J2 +#NET "FMC_LA09_P" LOC = "F7"; ## D14 on J2 +#NET "FMC_LA10_N" LOC = "H11"; ## C15 on J2 +#NET "FMC_LA10_P" LOC = "H10"; ## C14 on J2 +#NET "FMC_LA11_N" LOC = "G15"; ## H17 on J2 +#NET "FMC_LA11_P" LOC = "H14"; ## H16 on J2 +#NET "FMC_LA12_N" LOC = "G13"; ## G16 on J2 +#NET "FMC_LA12_P" LOC = "H13"; ## G15 on J2 +#NET "FMC_LA13_N" LOC = "F17"; ## D18 on J2 +#NET "FMC_LA13_P" LOC = "G16"; ## D17 on J2 +#NET "FMC_LA14_N" LOC = "A17"; ## C19 on J2 +#NET "FMC_LA14_P" LOC = "C17"; ## C18 on J2 +#NET "FMC_LA15_N" LOC = "D19"; ## H20 on J2 +#NET "FMC_LA15_P" LOC = "D18"; ## H19 on J2 +#NET "FMC_LA16_N" LOC = "A5"; ## G19 on J2 +#NET "FMC_LA16_P" LOC = "C5"; ## G18 on J2 +#NET "FMC_LA17_CC_N" LOC = "AB11"; ## D21 on J2 +#NET "FMC_LA17_CC_P" LOC = "Y11"; ## D20 on J2 +#NET "FMC_LA18_CC_N" LOC = "U12"; ## C23 on J2 +#NET "FMC_LA18_CC_P" LOC = "T12"; ## C22 on J2 +#NET "FMC_LA19_N" LOC = "T11"; ## H23 on J2 +#NET "FMC_LA19_P" LOC = "R11"; ## H22 on J2 +#NET "FMC_LA20_N" LOC = "R8"; ## G22 on J2 +#NET "FMC_LA20_P" LOC = "R9"; ## G21 on J2 +#NET "FMC_LA21_N" LOC = "W11"; ## H26 on J2 +#NET "FMC_LA21_P" LOC = "V11"; ## H25 on J2 +#NET "FMC_LA22_N" LOC = "W8"; ## G25 on J2 +#NET "FMC_LA22_P" LOC = "V7"; ## G24 on J2 +#NET "FMC_LA23_N" LOC = "V9"; ## D24 on J2 +#NET "FMC_LA23_P" LOC = "U9"; ## D23 on J2 +#NET "FMC_LA24_N" LOC = "AB14"; ## H29 on J2 +#NET "FMC_LA24_P" LOC = "AA14"; ## H28 on J2 +#NET "FMC_LA25_N" LOC = "Y14"; ## G28 on J2 +#NET "FMC_LA25_P" LOC = "W14"; ## G27 on J2 +#NET "FMC_LA26_N" LOC = "U13"; ## D27 on J2 +#NET "FMC_LA26_P" LOC = "U14"; ## D26 on J2 +#NET "FMC_LA27_N" LOC = "AB10"; ## C27 on J2 +#NET "FMC_LA27_P" LOC = "AA10"; ## C26 on J2 +#NET "FMC_LA28_N" LOC = "AB16"; ## H32 on J2 +#NET "FMC_LA28_P" LOC = "AA16"; ## H31 on J2 +#NET "FMC_LA29_N" LOC = "U15"; ## G31 on J2 +#NET "FMC_LA29_P" LOC = "T15"; ## G30 on J2 +#NET "FMC_LA30_N" LOC = "AB15"; ## H35 on J2 +#NET "FMC_LA30_P" LOC = "Y15"; ## H34 on J2 +#NET "FMC_LA31_N" LOC = "V15"; ## G34 on J2 +#NET "FMC_LA31_P" LOC = "U16"; ## G33 on J2 +#NET "FMC_LA32_N" LOC = "Y18"; ## H38 on J2 +#NET "FMC_LA32_P" LOC = "W17"; ## H37 on J2 +#NET "FMC_LA33_N" LOC = "AB17"; ## G37 on J2 +#NET "FMC_LA33_P" LOC = "Y17"; ## G36 on J2 +#NET "FMC_PRSNT_M2C_L" LOC = "Y16"; ## H2 on J2 +#NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## D1 on J2, 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (thru series R260 DNP), 44 of U25 +### +#NET "FPGA_AWAKE" LOC = "V19"; ## 2 on DS7 LED +#NET "FPGA_CCLK" LOC = "Y20"; ## 7 on J17 +#NET "FPGA_CMP_CLK" LOC = "V17"; ## 3 on J3 +#NET "FPGA_CMP_CS_B" LOC = "V18"; ## 4 on J3 +#NET "FPGA_CMP_MOSI" LOC = "W18"; ## 2 on J3 +### NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## this pin is part of the FLASH_nn group +### NET "FPGA_D1_MISO2" LOC = "R13"; ## this pin is part of the FLASH_nn group +### NET "FPGA_D2_MISO3" LOC = "T14"; ## this pin is part of the FLASH_nn group +#NET "FPGA_DONE" LOC = "AB21"; ## 2 on DS2 LED +#NET "FPGA_HSWAPEN" LOC = "C3"; ## 1 on R125 100 ohm to GND +#NET "FPGA_INIT_B" LOC = "Y4"; ## 1 on DS17 (thru sereis R69 75 ohm), 78 on U17 +#NET "FPGA_M0_CMP_MISO" LOC = "AA21"; ## 1 on SW1 DIP switch (active-high), 1 on J3 +#NET "FPGA_M1" LOC = "Y19"; ## 2 on SW1 DIP switch (active-high) +#NET "FPGA_MOSI_CSI_B_MISO0" LOC = "AB20"; ## 15 on U32, 5 on J17 +#NET "FPGA_ONCHIP_TERM1" LOC = "M7"; ## 1 on R124 DNP to GND +#NET "FPGA_ONCHIP_TERM2" LOC = "K7"; ## 1 on R126 100 ohm to GND +#NET "FPGA_PROG_B" LOC = "AB2"; ## 1 on SW3 pushbutton (active-high) 1 on J17, 2 on J48, 2 on R260 DNP connected to NET "FMC_PWR_GOOD_FLASH_RST_B" +#NET "FPGA_SUSPEND" LOC = "AA22"; ## 2 on J47 +#NET "FPGA_TCK" LOC = "A21"; ## 80 on U17 +#NET "FPGA_TDI" LOC = "E18"; ## 82 on U17 +#NET "FPGA_TMS" LOC = "D20"; ## 85 on U17 +#NET "FPGA_VBATT" LOC = "T16"; ## 1 on B2 (battery), 2 on D11 (charging circuit) +#NET "FPGA_VTEMP" LOC = "Y3"; ## 2 on R207 150 ohm to VCC1V5 +### +#NET "IIC_SCL_DVI" LOC = "W13"; ## 15 on U31, 2 on Q7 (level shifter, Q7.3 <-> IIC_CLK_DVI_F <-> series ferrite F9 220 ohm <-> 6 on P3 +#NET "IIC_SDA_DVI" LOC = "AA4"; ## 14 on U31, 2 on Q8 (level shifter, Q7.3 <-> IIC_SDA_DVI_F <-> series ferrite F8 220 ohm <-> 7 on P3 +#NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 +#NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 +#NET "IIC_SCL_SFP" LOC = "E5"; ## 5 on P2 +#NET "IIC_SDA_SFP" LOC = "E6"; ## 4 on P2 +### +#NET "MEM1_A0" LOC = "K2"; ## N3 on U42 +#NET "MEM1_A1" LOC = "K1"; ## P7 on U42 +#NET "MEM1_A2" LOC = "K5"; ## P3 on U42 +#NET "MEM1_A3" LOC = "M6"; ## N2 on U42 +#NET "MEM1_A4" LOC = "H3"; ## P8 on U42 +#NET "MEM1_A5" LOC = "M3"; ## P2 on U42 +#NET "MEM1_A6" LOC = "L4"; ## R8 on U42 +#NET "MEM1_A7" LOC = "K6"; ## R2 on U42 +#NET "MEM1_A8" LOC = "G3"; ## T8 on U42 +#NET "MEM1_A9" LOC = "G1"; ## R3 on U42 +#NET "MEM1_A10" LOC = "J4"; ## L7 on U42 +#NET "MEM1_A11" LOC = "E1"; ## R7 on U42 +#NET "MEM1_A12" LOC = "F1"; ## N7 on U42 +#NET "MEM1_A13" LOC = "J6"; ## T3 on U42 +#NET "MEM1_A14" LOC = "H5"; ## T7 on U42 +#NET "MEM1_BA0" LOC = "J3"; ## M2 on U42 +#NET "MEM1_BA1" LOC = "J1"; ## N8 on U42 +#NET "MEM1_BA2" LOC = "H1"; ## M3 on U42 +#NET "MEM1_CAS_B" LOC = "M4"; ## K3 on U42 +#NET "MEM1_CKE" LOC = "F2"; ## K9 on U42 +#NET "MEM1_CLK_N" LOC = "K3"; ## K7 on U42 +#NET "MEM1_CLK_P" LOC = "K4"; ## J7 on U42 +#NET "MEM1_DQ0" LOC = "R3"; ## G2 on U42 +#NET "MEM1_DQ1" LOC = "R1"; ## H3 on U42 +#NET "MEM1_DQ2" LOC = "P2"; ## E3 on U42 +#NET "MEM1_DQ3" LOC = "P1"; ## F2 on U42 +#NET "MEM1_DQ4" LOC = "L3"; ## H7 on U42 +#NET "MEM1_DQ5" LOC = "L1"; ## H8 on U42 +#NET "MEM1_DQ6" LOC = "M2"; ## F7 on U42 +#NET "MEM1_DQ7" LOC = "M1"; ## F8 on U42 +#NET "MEM1_DQ8" LOC = "T2"; ## C2 on U42 +#NET "MEM1_DQ9" LOC = "T1"; ## C3 on U42 +#NET "MEM1_DQ10" LOC = "U3"; ## A2 on U42 +#NET "MEM1_DQ11" LOC = "U1"; ## D7 on U42 +#NET "MEM1_DQ12" LOC = "W3"; ## A3 on U42 +#NET "MEM1_DQ13" LOC = "W1"; ## C8 on U42 +#NET "MEM1_DQ14" LOC = "Y2"; ## B8 on U42 +#NET "MEM1_DQ15" LOC = "Y1"; ## A7 on U42 +#NET "MEM1_LDM" LOC = "N4"; ## E7 on U42 +#NET "MEM1_LDQS_N" LOC = "N1"; ## G3 on U42 +#NET "MEM1_LDQS_P" LOC = "N3"; ## F3 on U42 +#NET "MEM1_ODT" LOC = "L6"; ## K1 on U42 +#NET "MEM1_RAS_B" LOC = "M5"; ## J3 on U42 +#NET "MEM1_RESET_B" LOC = "E3"; ## T2 on U42 +#NET "MEM1_UDM" LOC = "P3"; ## D3 on U42 +#NET "MEM1_UDQS_N" LOC = "V1"; ## B7 on U42 +#NET "MEM1_UDQS_P" LOC = "V2"; ## C7 on U42 +#NET "MEM1_WE_B" LOC = "H2"; ## L3 on U42 +### +#NET "PCIE_250M_N" LOC = "B10"; ## 1 on series C301 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_N -> 17 on U48 +#NET "PCIE_250M_P" LOC = "A10"; ## 1 on series C300 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_P -> 18 on U48 +#NET "PCIE_PERST_B_LS" LOC = "J7"; ## 6 on U52 (level shifter, U52.20 <-> PCIE_PERST_B <-> series R55 15 ohm <-> A11 on P4 +#NET "PCIE_RX0_N" LOC = "C7"; ## B15 on P4 +#NET "PCIE_RX0_P" LOC = "D7"; ## B14 on P4 +#NET "PCIE_TX0_N" LOC = "A6"; ## 2 on series C26 0.1uF, C26 pin 1 -> PCIE_TX0_C_N -> A17 of P4 +#NET "PCIE_TX0_P" LOC = "B6"; ## 2 on series C27 0.1uF, C26 pin 1 -> PCIE_TX0_C_P -> A16 of P4 +### +#NET "PMBUS_ALERT" LOC = "D3"; ## 35 on U26, 35 on U27 +#NET "PMBUS_CLK" LOC = "W10"; ## 19 on U26, 19 on U27 +#NET "PMBUS_CTRL" LOC = "H16"; ## 36 on U26, 36 on U27 +#NET "PMBUS_DATA" LOC = "Y10"; ## 20 on U26, 20 on U27 +### +#NET "SFPCLK_QO_N" LOC = "B12"; ## 2 on series C298 0.1uF, C298 pin 1 <- SFPCLK_QO_C_N <- 6 of U47 +#NET "SFPCLK_QO_P" LOC = "A12"; ## 2 on series C299 0.1uF, C299 pin 1 <- SFPCLK_QO_C_P <- 7 of U47 +#NET "SFP_LOS" LOC = "T17"; ## 8 on P2, 1 on J14 +#NET "SFP_RX_N" LOC = "C13"; ## 12 on P2 +#NET "SFP_RX_P" LOC = "D13"; ## 13 on P2 +#NET "SFP_TX_DISABLE_FPGA" LOC = "Y8"; ## 3 on P2, 1 on J44 +#NET "SFP_TX_N" LOC = "A14"; ## 19 on P2 +#NET "SFP_TX_P" LOC = "B14"; ## 18 on P2 +### +#NET "SMA_RX_N" LOC = "C9"; ## +#NET "SMA_RX_P" LOC = "D9"; ## +#NET "SMA_TX_N" LOC = "A8"; ## +#NET "SMA_TX_P" LOC = "B8"; ## +### +#NET "SPI_CS_B" LOC = "AA3"; ## +### +#NET "SYSACE_CFGTDI" LOC = "G17"; ## +#NET "SYSACE_D0_LS" LOC = "N6"; ## +#NET "SYSACE_D1_LS" LOC = "N7"; ## +#NET "SYSACE_D2_LS" LOC = "U4"; ## +#NET "SYSACE_D3_LS" LOC = "T4"; ## +#NET "SYSACE_D4_LS" LOC = "P6"; ## +#NET "SYSACE_D5_LS" LOC = "P7"; ## +#NET "SYSACE_D6_LS" LOC = "T3"; ## +#NET "SYSACE_D7_LS" LOC = "R4"; ## +#NET "SYSACE_MPA00_LS" LOC = "V5"; ## +#NET "SYSACE_MPA01_LS" LOC = "V3"; ## +#NET "SYSACE_MPA02_LS" LOC = "P5"; ## +#NET "SYSACE_MPA03_LS" LOC = "P4"; ## +#NET "SYSACE_MPA04_LS" LOC = "H4"; ## +#NET "SYSACE_MPA05_LS" LOC = "G4"; ## +#NET "SYSACE_MPA06_LS" LOC = "D2"; ## +#NET "SYSACE_MPBRDY_LS" LOC = "AA1"; ## +#NET "SYSACE_MPCE_LS" LOC = "W4"; ## +#NET "SYSACE_MPIRQ_LS" LOC = "AA2"; ## +#NET "SYSACE_MPOE_LS" LOC = "T6"; ## +#NET "SYSACE_MPWE_LS" LOC = "T5"; ## +### +#NET "USB_1_CTS" LOC = "F18"; ## +#NET "USB_1_RTS" LOC = "F19"; ## +### diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index ec7af12..3c26ed5 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -2,86 +2,103 @@ # # The top level module should define the variables below then include # this file. The files listed should be in the same directory as the -# Makefile. -# -# TODO: update these listings +# root Makefile. # # variable description # ---------- ------------- # board board target short-name -# project project name (top level module should match this name) +# project project name # top_module top level module of the project # libdir path to library directory # libs library modules used -# verilog_files all local .v files -# vhdl_files all local .vhd files -# end_vhdl_files all local encrypted .vhd files -# xilinx_cores all local .xco files -# vendor vendor of FPGA (xilinx, altera, etc.) +# vendor vendor of FPGA (xilinx, lattice, altera, etc.) # family FPGA device family (spartan3e) # part FPGA part name (xc4vfx12-10-sf363) # flashsize size of flash for mcs file (16384) -# optfile (optional) xst extra opttions file to put in .scr +# vgenerics verilog parameters to be passed into top-level module # map_opts (optional) options to give to map # par_opts (optional) options to give to par # intstyle (optional) intstyle option to all tools # -# files description -# ---------- ------------ -# $(board).ucf ucf file +# files description +# ---------- ------------ +# opt_file xst extra opttions file to put in .scr +# ucf_file .ucf file specifying FPGA constraints +# bitconf_file bitfile generation flags +# bmm_file BRAM default memory +# verilog_files all local non-testbench .v files +# vhdl_files all local .vhd files +# tbfile all local .v testbench files +# end_vhdl_files all local encrypted .vhd files +# xilinx_cores all local .xco files # # Library modules should have a modules.mk in their root directory, # namely $(libdir)//module.mk, that simply adds to the verilog_files # and xilinx_cores variable. # -# all the .xco files listed in xilinx_cores will be generated with core, with +# All the .xco files listed in xilinx_cores will be generated with core, with # the resulting .v and .ngc files placed back in the same directory as # the .xco file. # -# TODO: .xco files are device dependant, should use a template based system -# # NOTE: DO NOT edit this file to change settings; instead edit Makefile +# This file only works with Xilinx stuff +vendor = xilinx + +# Defaults; these should all be overriden though +hostbits ?= 64 +iseenv ?= /opt/Xilinx/14.3/ISE_DS +opt_file ?= ./contrib/default.opt vgenerics ?= +extra_prj ?= +verilog_files ?= +vhdl_files ?= +tbfiles ?= +enc_vhdl_files ?= + +# Low-level Tunables (override in top-level Makefile) +synth_effort ?= high unconst_timing ?= -u 50 const_timing_limit ?= 50 -synth_effort ?= high -coregen_work_dir ?= ./coregen-tmp +flashsize ?= 8192 +mcs_datawidth ?= 8 map_opts ?= -timing -ol $(synth_effort) -detail -pr b -register_duplication -w par_opts ?= -ol $(synth_effort) -hostbits = 64 -iseenv= /opt/Xilinx/14.3/ISE_DS +intstyle ?= -intstyle xflow +multithreading ?= -mt 4 + +# Build Environment iseenvfile?= $(iseenv)/settings$(hostbits).sh xil_env ?= mkdir -p build/; cd ./build; source $(iseenvfile) > /dev/null sim_env ?= cd ./tb; source $(iseenvfile) > /dev/null -flashsize ?= 8192 -mcs_datawidth ?= 16 -extra_prj ?= -end_vhdl_files ?= - +coregen_work_dir ?= ./coregen-tmp PWD := $(shell pwd) -intstyle ?= -intstyle xflow + +# The following are used to color-code console build output colorize ?= 2>&1 | python $(PWD)/contrib/colorize.py red ERROR: yellow WARNING: green \"Number of error messages: 0\" green \"Number of error messages:\t0\" green \"Number of errors: 0\" colorizetest ?= 2>&1 | python $(PWD)/contrib/colorize.py red FAIL green PASS -multithreading ?= -mt 4 - +# Library stuff (TODO: untested) libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) mkfiles = Makefile $(libmks) contrib/xilinx.mk include $(libmks) -# default is a single file -tbfiles ?= ./tb/tb.v -testfiles ?= - +# Setup coregen'd includes corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc)) local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) verilog_files += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) -tbfiles += $(foreach tfile,$(testfiles),$(tfile)) tbmods = $(foreach tbm,$(tbfiles),unenclib.`basename $(tbm) .v`) +define cp_template +$(2): $(1) + cp $(1) $(2) +endef +$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) -.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen impact ldimpact lint planahead partial_fpga_editor final_fpga_editor partial_timing final_timing tests +.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen \ + impact ldimpact lint planahead partial_fpga_editor final_fpga_editor \ + partial_timing final_timing tests +# "PRECIOUS" files will not be deleted by make as casually .PRECIOUS: tb/%.isim default: build/$(project).bit build/$(project).mcs @@ -89,12 +106,6 @@ xilinx_cores: $(corengcs) twr_map: build/$(project)_post_map.twr twr_par: build/$(project)_post_par.twr -define cp_template -$(2): $(1) - cp $(1) $(2) -endef -$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) - $(coregen_work_dir)/$(project).cgp: contrib/template.cgp @if [ -d $(coregen_work_dir) ]; then \ rm -rf $(coregen_work_dir)/*; \ @@ -111,7 +122,9 @@ $(coregen_work_dir)/$(project).cgp: contrib/template.cgp %.ngc %.v: %.xco $(coregen_work_dir)/$(project).cgp @echo "=== rebuilding $@" - @bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -b ../$< -p $(project).cgp;" + @bash -c "$(xil_env); \ + cd ../$(coregen_work_dir); \ + coregen -b ../$< -p $(project).cgp;" @xcodir=`dirname $<`; \ basename=`basename $< .xco`; \ echo $(coregen_work_dir)/$$basename.v; \ @@ -127,15 +140,22 @@ date = $(shell date +%F-%H-%M) programming_files: build/$(project).bit build/$(project).mcs @mkdir -p $@/$(date) @mkdir -p $@/latest - @for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done - @bash -c "$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr" + @for x in .bit .mcs .cfi _bd.bmm; do \ + cp $(project)$$x $@/$(date)/$(project)$$x; \ + cp $(project)$$x $@/latest/$(project)$$x; \ + done + @bash -c "$(xil_env); \ + xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr" build/$(project).mcs: build/$(project).bit - @bash -c "$(xil_env); promgen -w -data_width $(mcs_datawidth) -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit" + @bash -c "$(xil_env); \ + promgen -w -data_width $(mcs_datawidth) -s $(flashsize) -p mcs -o $(project).mcs \ + -u 0 $(project).bit" -build/$(project).bit: build/$(project)_par.ncd build/$(project)_post_par.twr $(board).bitconf +build/$(project).bit: build/$(project)_par.ncd build/$(project)_post_par.twr $(bitconf_file) @bash -c "$(xil_env); \ - bitgen $(intstyle) -f ../$(board).bitconf -w $(project)_par.ncd $(project).bit $(project).pcf" + bitgen $(intstyle) -f ../$(bitconf_file) -w $(project)_par.ncd $(project).bit \ + $(project).pcf" build/$(project)_par.ncd: build/$(project).ncd build/$(project)_post_map.twr @@ -154,16 +174,19 @@ build/$(project).ncd: build/$(project).ngd smartguide=""; \ fi; \ bash -c "$(xil_env); \ - map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)" + map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)" -build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm +build/$(project).ngd: build/$(project).ngc $(ucf_file) $(bmm_file) @bash -c "$(xil_env); \ - ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)" + ngdbuild $(intstyle) $(project).ngc -bm ../$(bmm_file) \ + -sd ../cores -uc ../$(ucf_file) -aul $(colorize)" build/$(project).ngc: $(verilog_files) $(vhdl_files) $(local_corengcs) build/$(project).scr build/$(project).prj + @#TODO: The below line is ugly @bash -c "rm build/$(project).scr; make build/$(project).scr" - @bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr $(colorize)" - @# need to check for success manually; TODO: doesn't work if pre-existed + @bash -c "$(xil_env); \ + xst $(intstyle) -ifn $(project).scr $(colorize)" + @# Need to check for success manually? TODO: doesn't work if pre-existed @if [ ! -f build/$(project).ngc ]; then false; fi build/$(project).prj: $(verilog_files) $(vhdl_files) @@ -173,25 +196,27 @@ build/$(project).prj: $(verilog_files) $(vhdl_files) @sort -u $(project).tmpprj > $@ @rm -f $(project).tmpprj -optfile += $(wildcard $(project).opt) -top_module ?= $(project) -build/$(project).scr: $(optfile) ./$(project).opt - mkdir -p build +build/$(project).scr: $(opt_file) + @mkdir -p build @echo "run" > $@ @echo "-p $(part)" >> $@ @echo "-top $(top_module)" >> $@ @echo "-ifn $(project).prj" >> $@ @echo "-ofn $(project).ngc" >> $@ @echo '-generics {$(vgenerics)}' >> $@ - @cat $(optfile) >> $@ + @cat $(opt_file) >> $@ cp $@ build/$(project).xst build/$(project)_post_map.twr: build/$(project).ncd - @bash -c "$(xil_env); trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) $(project).ncd $(project).pcf -o $(project)_post_map.twr $(colorize)" + @bash -c "$(xil_env); \ + trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) \ + $(project).ncd $(project).pcf -o $(project)_post_map.twr $(colorize)" @echo "Read $@ for timing analysis details" build/$(project)_post_par.twr: build/$(project)_par.ncd - @bash -c "$(xil_env); trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) $(project)_par.ncd $(project).pcf -o $(project)_post_par.twr $(colorize)" + @bash -c "$(xil_env); \ + trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) \ + $(project)_par.ncd $(project).pcf -o $(project)_post_par.twr $(colorize)" @echo "See $@ for timing analysis details" tb/simulate_isim.prj: $(tbfiles) $(verilog_files) $(vhdl_files) $(enc_vhdl_files) @@ -215,7 +240,11 @@ tb/isim.compiled: tb/simulate_isim.prj $(tbfiles) $(verilog_files) $(vhdl_files) @touch tb/isim.compiled tb/simulate_isim: tb/isim.compiled - @bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim $(tbmods) unenclib.glbl $(colorize)" + @bash -c "$(sim_env); \ + cd ../tb/; \ + fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver \ + -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim \ + $(tbmods) unenclib.glbl $(colorize)" simulate: tb/simulate_isim @@ -224,11 +253,17 @@ isim_cli: simulate tb/%.isim: tb/%.v tb/isim.compiled @uut=`basename $< .v`; \ - bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o $$uut.isim unenclib.$$uut unenclib.glbl $(colorize)" + bash -c "$(sim_env); \ + cd ../tb/; \ + fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver \ + -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o $$uut.isim \ + unenclib.$$uut unenclib.glbl $(colorize)" isim/%: tb/%.isim tb/simulate_isim.prj @uut=`basename $@`; \ - bash -c "$(sim_env); cd ../tb; ./$$uut.isim -gui -view $$uut.wcfg &" + bash -c "$(sim_env); \ + cd ../tb; \ + ./$$uut.isim -gui -view $$uut.wcfg &" resim/%: tb/%.isim tb/simulate_isim.prj @true @@ -236,24 +271,36 @@ resim/%: tb/%.isim tb/simulate_isim.prj test/%: tb/%.isim tb/simulate_isim.prj @echo "run all" > ./tb/test.tcl @uut=`basename $@`; \ - bash -c "$(sim_env); cd ../tb/; ./$$uut.isim -tclbatch test.tcl $(colorizetest)" + bash -c "$(sim_env); \ + cd ../tb/; \ + ./$$uut.isim -tclbatch test.tcl $(colorizetest)" tests: $(alltests) isim: simulate - @bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg &" + @bash -c "$(sim_env); \ + cd ../tb/; \ + ./simulate_isim -gui -view signals.wcfg &" coregen: $(coregen_work_dir)/$(project).cgp - @bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -p $(project).cgp &" + @bash -c "$(xil_env); \ + cd ../$(coregen_work_dir); \ + coregen -p $(project).cgp &" impact: - @bash -c "$(xil_env); cd ../build; impact &" + @bash -c "$(xil_env); \ + cd ../build; \ + impact &" ldimpact: - @bash -c "$(xil_env); cd ../build; LD_PRELOAD=/usr/local/lib/libusb-driver.so impact &" + @bash -c "$(xil_env); \ + cd ../build; \ + LD_PRELOAD=/usr/local/lib/libusb-driver.so impact &" autoimpact: - @bash -c "$(xil_env); cd ../build; impact -mode bscan -b build/$(project).bit -port auto -autoassign &" + @bash -c "$(xil_env); \ + cd ../build; \ + impact -mode bscan -b build/$(project).bit -port auto -autoassign &" ise: @echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" @@ -261,29 +308,43 @@ ise: @echo "! (see README) !" @echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" @mkdir -p build - @bash -c "$(xil_env); cd ..; XIL_MAP_LOCWARN=0 ise $(project).xise &" + @bash -c "$(xil_env); \ + cd ..; \ + XIL_MAP_LOCWARN=0 ise $(project).xise &" planahead: - @bash -c "$(xil_env); cd ..; planAhead &" + @bash -c "$(xil_env); \ + cd ..; \ + planAhead &" + +# DISPLAY variable (X Windows) should be inherited from environment +DISPLAY ?= :0 -# TODO: DISPLAY = `echo $DISPLAY |sed s/'\.0'//` partial_fpga_editor: build/$(project).ncd @echo "Starting fpga_editor in the background (can take a minute or two)..." - @bash -c "$(xil_env); DISPLAY=:0 fpga_editor $(project).ncd &" + @echo "IGNORE the RPC errors below." + @echo + @bash -c "$(xil_env); \ + DISPLAY=`echo $(DISPLAY) | sed s/'\.0'//` fpga_editor $(project).ncd &" -# TODO: DISPLAY = `echo $DISPLAY |sed s/'\.0'//` final_fpga_editor: build/$(project)_par.ncd @echo "Starting fpga_editor in the background (can take a minute or two)..." - @bash -c "$(xil_env); DISPLAY=:0 fpga_editor $(project)_par.ncd &" + @echo "IGNORE the RPC errors below." + @echo + @bash -c "$(xil_env); \ + DISPLAY=`echo $(DISPLAY) | sed s/'\.0'//` fpga_editor $(project)_par.ncd &" timingan: - @bash -c "$(xil_env); timingan &" + @bash -c "$(xil_env); \ + timingan &" partial_timing: build/$(project)_post_map.twr - @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &" + @bash -c "$(xil_env); \ + timingan -ucf ../$(ucf_file) $(project).ncd $(project).pcf $(project)_post_map.twx &" final_timing: build/$(project)_post_par.twr - @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" + @bash -c "$(xil_env); \ + timingan -ucf ../$(ucf_file) $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" lint: verilator --lint-only -I./hdl -I./cores -Wall -Wno-DECLFILENAME hdl/$(top_module)_$(board) || true diff --git a/contrib/xula2.mk b/contrib/xula2.mk deleted file mode 100644 index 9c06b3b..0000000 --- a/contrib/xula2.mk +++ /dev/null @@ -1,9 +0,0 @@ -# xula2 device-specific make targets - -.PHONY: prog - -prog: build/$(project).bit - @xsload.py --fpga build/$(project).bit - -prog_flash: build/$(project).bit - @xsload.py --flash build/$(project).bit diff --git a/contrib/xula2/README.xula2 b/contrib/xula2/README.xula2 new file mode 100644 index 0000000..3ca7d50 --- /dev/null +++ b/contrib/xula2/README.xula2 @@ -0,0 +1,16 @@ + +To upload bitfiles to the xula2 board, you first need to install the "xstools" +python package: + + https://pypi.python.org/pypi/XsTools/ + +IMPORTANT: if you get the following error when using the xstest.py python tool +with a xula2 board on linux: + + usb.core.USBError: [Errno 5] Input/output error + +and then your board resets (LED turns off), then you probably need to first +upgrade the PIC microcontroller firmware: + + sudo xsusbprg.py + diff --git a/contrib/xula2/xula2.bitconf b/contrib/xula2/xula2.bitconf new file mode 100644 index 0000000..599289d --- /dev/null +++ b/contrib/xula2/xula2.bitconf @@ -0,0 +1,7 @@ +-g Binary:yes +# below are xula2-specific configurations +-g UnusedPin:Pullnone +-g TckPin:Pullnone +#-g StartupClk:JtagClk # for JTAG upload +-g StartupClk:Cclk # for serial flash +-g ConfigRate:10 # for fast serial flashing diff --git a/contrib/xula2/xula2.mk b/contrib/xula2/xula2.mk new file mode 100644 index 0000000..681fe38 --- /dev/null +++ b/contrib/xula2/xula2.mk @@ -0,0 +1,24 @@ +# xula2 device-specific configuration variables and make targets + +.PHONY: prog prog_flash + +board := xula2 +family := spartan6 +device := XC6SLX25 +speedgrade := -2 +device_package := ftg256 +bitconf_file := ./contrib/xula2/xula2.bitconf +ucf_file := ./contrib/xula2/xula2.ucf +opt_file := ./contrib/default.opt + +# This target uploads directly to the FPGA; volatile +prog: build/$(project).bit + # First ensure that xsload.py is installed + @xsload.py --version + @xsload.py --fpga build/$(project).bit + +# This target uploads to the SPI flash on board; non-volatile +prog_flash: build/$(project).bit + # First ensure that xsload.py is installed + @xsload.py --version + @xsload.py --flash build/$(project).bit diff --git a/contrib/xula2/xula2.ucf b/contrib/xula2/xula2.ucf new file mode 100644 index 0000000..ae04f81 --- /dev/null +++ b/contrib/xula2/xula2.ucf @@ -0,0 +1,69 @@ +# ============================================================================ +# Xess Corp XuLa 2 +# ============================================================================ + +# Originally written October 2013 by LeafLabs, LLC (leaflabs.com). + +# The .ucf supplied by Xess is under GPL. +# https://raw.github.com/xesscorp/XuLA2/master/FPGA/XuLA_lib/XuLA2.ucf + +# This file was written from scratch from the manual. It is intended to be +# reused and copy/pasted from with no copyright or attribution necessary. In +# that an explicit license is necessary for such a file, it is Creative Commons +# Zero. + +# ==== Clocks ==== + +NET "clock_12mhz" LOC = "A9"; +NET "clock_12mhz" IOSTANDARD = LVTTL; +NET "clock_12mhz" TNM_NET = "clock_12mhz"; +TIMESPEC "TS_clock_12mhz" = PERIOD "clock_12mhz" 12 MHz HIGH 50%; + +# ==== Prototyping Header (GPIO) ==== + +NET "chan_clk" LOC = "T7" | IOSTANDARD = LVTTL ; + +NET "chan<0>" LOC = "R7" | IOSTANDARD = LVTTL ; +NET "chan<1>" LOC = "R15" | IOSTANDARD = LVTTL ; +NET "chan<2>" LOC = "R16" | IOSTANDARD = LVTTL ; +NET "chan<3>" LOC = "M15" | IOSTANDARD = LVTTL ; +NET "chan<4>" LOC = "M16" | IOSTANDARD = LVTTL ; +NET "chan<5>" LOC = "K15" | IOSTANDARD = LVTTL ; +NET "chan<6>" LOC = "K16" | IOSTANDARD = LVTTL ; +NET "chan<7>" LOC = "J16" | IOSTANDARD = LVTTL ; +NET "chan<8>" LOC = "J14" | IOSTANDARD = LVTTL ; +NET "chan<9>" LOC = "F15" | IOSTANDARD = LVTTL ; +NET "chan<10>" LOC = "F16" | IOSTANDARD = LVTTL ; +NET "chan<11>" LOC = "C16" | IOSTANDARD = LVTTL ; +NET "chan<12>" LOC = "C15" | IOSTANDARD = LVTTL ; +NET "chan<13>" LOC = "B16" | IOSTANDARD = LVTTL ; +NET "chan<14>" LOC = "B15" | IOSTANDARD = LVTTL ; +NET "chan<15>" LOC = "T4" | IOSTANDARD = LVTTL ; +NET "chan<16>" LOC = "R2" | IOSTANDARD = LVTTL ; +NET "chan<17>" LOC = "R1" | IOSTANDARD = LVTTL ; +NET "chan<18>" LOC = "M2" | IOSTANDARD = LVTTL ; +NET "chan<19>" LOC = "M1" | IOSTANDARD = LVTTL ; +NET "chan<20>" LOC = "K3" | IOSTANDARD = LVTTL ; +NET "chan<21>" LOC = "J4" | IOSTANDARD = LVTTL ; +NET "chan<22>" LOC = "H1" | IOSTANDARD = LVTTL ; +NET "chan<23>" LOC = "H2" | IOSTANDARD = LVTTL ; +NET "chan<24>" LOC = "F1" | IOSTANDARD = LVTTL ; +NET "chan<25>" LOC = "F2" | IOSTANDARD = LVTTL ; +NET "chan<26>" LOC = "E1" | IOSTANDARD = LVTTL ; +NET "chan<27>" LOC = "E2" | IOSTANDARD = LVTTL ; +NET "chan<28>" LOC = "C1" | IOSTANDARD = LVTTL ; +NET "chan<29>" LOC = "B1" | IOSTANDARD = LVTTL ; +NET "chan<30>" LOC = "B2" | IOSTANDARD = LVTTL ; +NET "chan<31>" LOC = "A2" | IOSTANDARD = LVTTL ; + +# ==== SDRAM ==== +# TODO + +# ==== SPI Flash and uSD Card ==== + +NET "microsd_cs" LOC = "T8" | IOSTANDARD = LVTTL ; +NET "flash_cs" LOC = "T3" | IOSTANDARD = LVTTL ; +NET "flash_sclk" LOC = "R11" | IOSTANDARD = LVTTL ; +NET "flash_mosi" LOC = "T10" | IOSTANDARD = LVTTL ; +NET "flash_miso" LOC = "P10" | IOSTANDARD = LVTTL ; + diff --git a/exampleproj.bmm b/exampleproj.bmm deleted file mode 100644 index c915ec8..0000000 --- a/exampleproj.bmm +++ /dev/null @@ -1 +0,0 @@ -// Empty file; this is a "Block Ram Memory Map" diff --git a/exampleproj.opt b/exampleproj.opt deleted file mode 100644 index 7fe9d8b..0000000 --- a/exampleproj.opt +++ /dev/null @@ -1,42 +0,0 @@ --ifmt mixed --ofmt NGC --opt_mode speed --opt_level 1 --iuc NO --keep_hierarchy no --netlist_hierarchy as_optimized --rtlview no --glob_opt AllClockNets --read_cores yes --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 -#-dsp_utilization_ratio 100 --safe_implementation No --fsm_extract YES --fsm_encoding Auto --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --shreg_extract YES --auto_bram_packing NO --resource_sharing YES --async_to_sync NO -#-use_dsp48 auto --iobuf YES --max_fanout 500 --register_duplication YES --register_balancing No --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/sp605.bitconf b/sp605.bitconf deleted file mode 100644 index 2a339b6..0000000 --- a/sp605.bitconf +++ /dev/null @@ -1,3 +0,0 @@ --g Binary:yes --g DriveDone:yes --g StartupClk:Cclk diff --git a/sp605.bmm b/sp605.bmm deleted file mode 100644 index c915ec8..0000000 --- a/sp605.bmm +++ /dev/null @@ -1 +0,0 @@ -// Empty file; this is a "Block Ram Memory Map" diff --git a/sp605.ucf b/sp605.ucf deleted file mode 100644 index 9ad7857..0000000 --- a/sp605.ucf +++ /dev/null @@ -1,449 +0,0 @@ - -################## Clocks and Reset (not GTP) ##################### -# In this application USER_CLOCK is a 25MHz CTS MXO45HS-3C-25M0000 -# 5v, 50ppm, 5ps jitter (?) -NET "user_clock" LOC = "AB13"; ## -NET "user_clock" TNM_NET = "user_clock"; -TIMESPEC "TS_user_clock" = PERIOD "user_clock" 40 ns HIGH 50% INPUT_JITTER 5.0 ps; - -NET "reset_button" LOC = "H8" | CLOCK_DEDICATED_ROUTE = FALSE; ## 2 on SW6 pushbutton (active-high) - -################## GPIO, Switches, LEDs, Headers ##################### -NET "gpio_button<0>" LOC = "F3"; ## 2 on SW4 pushbutton (active-high) -NET "gpio_button<1>" LOC = "G6"; ## 2 on SW7 pushbutton (active-high) -NET "gpio_button<2>" LOC = "F5"; ## 2 on SW5 pushbutton (active-high) -NET "gpio_button<3>" LOC = "C1"; ## 2 on SW8 pushbutton (active-high) -## -# 1 on U52 (level shifter, U52.20 <-> gpio_header<0 <-> series R280 200 ohm <-> 1 on J55 -NET "gpio_header<0>" LOC = "G7" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; -# 3 on U52 (level shifter, U52.18 <-> gpio_header<0 <-> series R281 200 ohm <-> 2 on J55 -NET "gpio_header<1>" LOC = "H6" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; -# 4 on U52 (level shifter, U52.17 <-> gpio_header<0 <-> series R282 200 ohm <-> 3 on J55 -NET "gpio_header<2>" LOC = "D1" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; -# 5 on U52 (level shifter, U52.16 <-> gpio_header<0 <-> series R283 200 ohm <-> 4 on J55 -NET "gpio_header<3>" LOC = "R7" | SLEW = "FAST" | IOSTANDARD = LVCMOS33; -## -NET "gpio_led<0>" LOC = "D17"; ## 2 on DS3 LEDh -NET "gpio_led<1>" LOC = "AB4"; ## 2 on DS4 LED -NET "gpio_led<2>" LOC = "D21"; ## 2 on DS5 LED -NET "gpio_led<3>" LOC = "W15"; ## 2 on DS6 LED -## -NET "gpio_switch<0>" LOC = "C18"; ## 1 on S2 DIP switch (active-high) -NET "gpio_switch<1>" LOC = "Y6"; ## 2 on S2 DIP switch (active-high) -NET "gpio_switch<2>" LOC = "W6"; ## 3 on S2 DIP switch (active-high) -NET "gpio_switch<3>" LOC = "E4"; ## 4 on S2 DIP switch (active-high) - -NET "uart_rx" LOC = "B21"; ## USB_1_RX -NET "uart_tx" LOC = "H17"; ## USB_1_TX - -############################################################################# -################### Entirely Unused Definitions Below ####################### -############################################################################# - -################## GIGE PHY ##################### -#NET "gige_col" LOC = "M16"; ## 114 on U46 "PHY_COL" -#NET "gige_crs" LOC = "N15"; ## 115 on U46 "PHY_CRS" -#NET "gige_int" LOC = "J20"; ## 32 on U46 "PHY_INT" -#NET "gige_mdc" LOC = "R19"; ## 35 on U46 "PHY_MDC" -#NET "gige_mdio" LOC = "V20"; ## 33 on U46 "PHY_MDIO" -#NET "gige_reset" LOC = "J22"; ## 36 on U46 "PHY_RESET" -#NET "gige_rxclk" LOC = "P20"; ## 7 on U46 "PHY_RXCLK" -#NET "gige_rxctl_rxdv" LOC = "T22"; ## 4 on U46 "PHY_RXCTL_RXDV" -#NET "gige_rx_data<0>" LOC = "P19"; ## 3 on U46 "PHY_RXD0" -#NET "gige_rx_data<1>" LOC = "Y22"; ## 128 on U46 "PHY_RXD1" -#NET "gige_rx_data<2>" LOC = "Y21"; ## 126 on U46 "PHY_RXD2" -#NET "gige_rx_data<3>" LOC = "W22"; ## 125 on U46 "PHY_RXD3" -#NET "gige_rx_data<4>" LOC = "W20"; ## 124 on U46 "PHY_RXD4" -#NET "gige_rx_data<5>" LOC = "V22"; ## 123 on U46 "PHY_RXD5" -#NET "gige_rx_data<6>" LOC = "V21"; ## 121 on U46 "PHY_RXD6" -#NET "gige_rx_data<7>" LOC = "U22"; ## 120 on U46 "PHY_RXD7" -#NET "gige_rxer" LOC = "U20"; ## 8 on U46 "PHY_RXER" -#NET "gige_txclk" LOC = "L20"; ## 10 on U46 "PHY_TXCLK" -#NET "gige_txctl_txen" LOC = "T8"; ## 16 on U46 "PHY_TXCTL_TXEN" -#NET "gige_txc_gtxclk" LOC = "AB7"; ## 14 on U46 "PHY_TXC_GTXCLK" -#NET "gige_tx_data<0>" LOC = "U10"; ## 18 on U46 "PHY_TXD0" -#NET "gige_tx_data<1>" LOC = "T10"; ## 19 on U46 "PHY_TXD1" -#NET "gige_tx_data<2>" LOC = "AB8"; ## 20 on U46 "PHY_TXD2" -#NET "gige_tx_data<3>" LOC = "AA8"; ## 24 on U46 "PHY_TXD3" -#NET "gige_tx_data<4>" LOC = "AB9"; ## 25 on U46 "PHY_TXD4" -#NET "gige_tx_data<5>" LOC = "Y9"; ## 26 on U46 "PHY_TXD5" -#NET "gige_tx_data<6>" LOC = "Y12"; ## 28 on U46 "PHY_TXD6" -#NET "gige_tx_data<7>" LOC = "W12"; ## 29 on U46 "PHY_TXD7" -#NET "gige_txer" LOC = "U8"; ## 13 on U46 "PHY_TXER" -## -#NET "CLK_33MHZ_SYSACE" LOC = "N19"; ## 93 on U17 -## -#NET "DVI_D0" LOC = "K16"; ## 63 on U31 (thru series R39 47.5 ohm) -#NET "DVI_D1" LOC = "U19"; ## 62 on U31 (thru series R38 47.5 ohm) -#NET "DVI_D2" LOC = "T20"; ## 61 on U31 (thru series R37 47.5 ohm) -#NET "DVI_D3" LOC = "N16"; ## 60 on U31 (thru series R36 47.5 ohm) -#NET "DVI_D4" LOC = "P16"; ## 59 on U31 (thru series R35 47.5 ohm) -#NET "DVI_D5" LOC = "M17"; ## 58 on U31 (thru series R34 47.5 ohm) -#NET "DVI_D6" LOC = "M18"; ## 55 on U31 (thru series R33 47.5 ohm) -#NET "DVI_D7" LOC = "R15"; ## 54 on U31 (thru series R32 47.5 ohm) -#NET "DVI_D8" LOC = "R16"; ## 53 on U31 (thru series R31 47.5 ohm) -#NET "DVI_D9" LOC = "P17"; ## 52 on U31 (thru series R30 47.5 ohm) -#NET "DVI_D10" LOC = "P18"; ## 51 on U31 (thru series R29 47.5 ohm) -#NET "DVI_D11" LOC = "R17"; ## 50 on U31 (thru series R28 47.5 ohm) -#NET "DVI_DE" LOC = "J17"; ## 2 on U31 (thru series R40 47.5 ohm) -#NET "DVI_GPIO1" LOC = "D22"; ## 18 on U31 -#NET "DVI_H" LOC = "J16"; ## 4 on U31 (thru series R41 47.5 ohm) -#NET "DVI_RESET_B" LOC = "L15"; ## 13 on U31 -#NET "DVI_V" LOC = "B22"; ## 5 on U31 (thru series R42 47.5 ohm) -#NET "DVI_XCLK_N" LOC = "C22"; ## 56 on U31 -#NET "DVI_XCLK_P" LOC = "C20"; ## 57 on U31 -## -#NET "FLASH_A0" LOC = "N22"; ## 29 on U25 -#NET "FLASH_A1" LOC = "N20"; ## 25 on U25 -#NET "FLASH_A2" LOC = "M22"; ## 24 on U25 -#NET "FLASH_A3" LOC = "M21"; ## 23 on U25 -#NET "FLASH_A4" LOC = "L19"; ## 22 on U25 -#NET "FLASH_A5" LOC = "K20"; ## 21 on U25 -#NET "FLASH_A6" LOC = "H22"; ## 20 on U25 -#NET "FLASH_A7" LOC = "H21"; ## 19 on U25 -#NET "FLASH_A8" LOC = "L17"; ## 8 on U25 -#NET "FLASH_A9" LOC = "K17"; ## 7 on U25 -#NET "FLASH_A10" LOC = "G22"; ## 6 on U25 -#NET "FLASH_A11" LOC = "G20"; ## 5 on U25 -#NET "FLASH_A12" LOC = "K18"; ## 4 on U25 -#NET "FLASH_A13" LOC = "K19"; ## 3 on U25 -#NET "FLASH_A14" LOC = "H20"; ## 2 on U25 -#NET "FLASH_A15" LOC = "J19"; ## 1 on U25 -#NET "FLASH_A16" LOC = "E22"; ## 55 on U25 -#NET "FLASH_A17" LOC = "E20"; ## 18 on U25 -#NET "FLASH_A18" LOC = "F22"; ## 17 on U25 -#NET "FLASH_A19" LOC = "F21"; ## 16 on U25 -#NET "FLASH_A20" LOC = "H19"; ## 11 on U25 -#NET "FLASH_A21" LOC = "H18"; ## 10 on U25 -#NET "FLASH_A22" LOC = "F20"; ## 9 on U25 -#NET "FLASH_A23" LOC = "G19"; ## 26 on U25 -#NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## 34 on U25, 8 on U32 (thru series R132 100 ohm), 6 on J17 -#NET "FPGA_D1_MISO2" LOC = "R13"; ## 36 on U25, 3 on J17 -#NET "FPGA_D2_MISO3" LOC = "T14"; ## 39 on U25, 2 on J17 -#NET "FLASH_D3" LOC = "AA6"; ## 41 on U25 -#NET "FLASH_D4" LOC = "AB6"; ## 47 on U25 -#NET "FLASH_D5" LOC = "Y5"; ## 49 on U25 -#NET "FLASH_D6" LOC = "AB5"; ## 51 on U25 -#NET "FLASH_D7" LOC = "W9"; ## 53 on U25 -#NET "FLASH_D8" LOC = "T7"; ## 35 on U25 -#NET "FLASH_D9" LOC = "U6"; ## 37 on U25 -#NET "FLASH_D10" LOC = "AB19"; ## 40 on U25 -#NET "FLASH_D11" LOC = "AA18"; ## 42 on U25 -#NET "FLASH_D12" LOC = "AB18"; ## 48 on U25 -#NET "FLASH_D13" LOC = "Y13"; ## 50 on U25 -#NET "FLASH_D14" LOC = "AA12"; ## 52 on U25 -#NET "FLASH_D15" LOC = "AB12"; ## 54 on U25 -#NET "FLASH_WAIT" LOC = "T18"; ## 56 on U25 -#NET "FLASH_WE_B" LOC = "R20"; ## 14 on U25 -#NET "FLASH_OE_B" LOC = "P22"; ## 32 on U25 -#NET "FLASH_CE_B" LOC = "P21"; ## 30 on U25 -#NET "FLASH_ADV_B" LOC = "T19"; ## 46 on U25 -## NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## 44 on U25 (this signal goes to multiple destinations, see below) -## -#NET "FMC_CLK0_M2C_N" LOC = "G11"; ## H5 on J2 -#NET "FMC_CLK0_M2C_P" LOC = "H12"; ## H4 on J2 -#NET "FMC_CLK1_M2C_N" LOC = "F16"; ## G3 on J2 -#NET "FMC_CLK1_M2C_P" LOC = "E16"; ## G2 on J2 -#NET "FMC_DP0_C2M_N" LOC = "A16"; ## C3 on J2 -#NET "FMC_DP0_C2M_P" LOC = "B16"; ## C2 on J2 -#NET "FMC_DP0_M2C_N" LOC = "C15"; ## C7 on J2 -#NET "FMC_DP0_M2C_P" LOC = "D15"; ## C6 on J2 -## NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 (this signal goes to multiple destinations, see below) -## NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 (this signal goes to multiple destinations, see below) -#NET "FMC_LA00_CC_N" LOC = "F10"; ## G7 on J2 -#NET "FMC_LA00_CC_P" LOC = "G9"; ## G6 on J2 -#NET "FMC_LA01_CC_N" LOC = "F15"; ## D9 on J2 -#NET "FMC_LA01_CC_P" LOC = "F14"; ## D8 on J2 -#NET "FMC_LA02_N" LOC = "F9"; ## H8 on J2 -#NET "FMC_LA02_P" LOC = "G8"; ## H7 on J2 -#NET "FMC_LA03_N" LOC = "A18"; ## G10 on J2 -#NET "FMC_LA03_P" LOC = "B18"; ## G9 on J2 -#NET "FMC_LA04_N" LOC = "A19"; ## H11 on J2 -#NET "FMC_LA04_P" LOC = "C19"; ## H10 on J2 -#NET "FMC_LA05_N" LOC = "A4"; ## D12 on J2 -#NET "FMC_LA05_P" LOC = "C4"; ## D11 on J2 -#NET "FMC_LA06_N" LOC = "D5"; ## C11 on J2 -#NET "FMC_LA06_P" LOC = "D4"; ## C10 on J2 -#NET "FMC_LA07_N" LOC = "A2"; ## H14 on J2 -#NET "FMC_LA07_P" LOC = "B2"; ## H13 on J2 -#NET "FMC_LA08_N" LOC = "A20"; ## G13 on J2 -#NET "FMC_LA08_P" LOC = "B20"; ## G12 on J2 -#NET "FMC_LA09_N" LOC = "F8"; ## D15 on J2 -#NET "FMC_LA09_P" LOC = "F7"; ## D14 on J2 -#NET "FMC_LA10_N" LOC = "H11"; ## C15 on J2 -#NET "FMC_LA10_P" LOC = "H10"; ## C14 on J2 -#NET "FMC_LA11_N" LOC = "G15"; ## H17 on J2 -#NET "FMC_LA11_P" LOC = "H14"; ## H16 on J2 -#NET "FMC_LA12_N" LOC = "G13"; ## G16 on J2 -#NET "FMC_LA12_P" LOC = "H13"; ## G15 on J2 -#NET "FMC_LA13_N" LOC = "F17"; ## D18 on J2 -#NET "FMC_LA13_P" LOC = "G16"; ## D17 on J2 -#NET "FMC_LA14_N" LOC = "A17"; ## C19 on J2 -#NET "FMC_LA14_P" LOC = "C17"; ## C18 on J2 -#NET "FMC_LA15_N" LOC = "D19"; ## H20 on J2 -#NET "FMC_LA15_P" LOC = "D18"; ## H19 on J2 -#NET "FMC_LA16_N" LOC = "A5"; ## G19 on J2 -#NET "FMC_LA16_P" LOC = "C5"; ## G18 on J2 -#NET "FMC_LA17_CC_N" LOC = "AB11"; ## D21 on J2 -#NET "FMC_LA17_CC_P" LOC = "Y11"; ## D20 on J2 -#NET "FMC_LA18_CC_N" LOC = "U12"; ## C23 on J2 -#NET "FMC_LA18_CC_P" LOC = "T12"; ## C22 on J2 -#NET "FMC_LA19_N" LOC = "T11"; ## H23 on J2 -#NET "FMC_LA19_P" LOC = "R11"; ## H22 on J2 -#NET "FMC_LA20_N" LOC = "R8"; ## G22 on J2 -#NET "FMC_LA20_P" LOC = "R9"; ## G21 on J2 -#NET "FMC_LA21_N" LOC = "W11"; ## H26 on J2 -#NET "FMC_LA21_P" LOC = "V11"; ## H25 on J2 -#NET "FMC_LA22_N" LOC = "W8"; ## G25 on J2 -#NET "FMC_LA22_P" LOC = "V7"; ## G24 on J2 -#NET "FMC_LA23_N" LOC = "V9"; ## D24 on J2 -#NET "FMC_LA23_P" LOC = "U9"; ## D23 on J2 -#NET "FMC_LA24_N" LOC = "AB14"; ## H29 on J2 -#NET "FMC_LA24_P" LOC = "AA14"; ## H28 on J2 -#NET "FMC_LA25_N" LOC = "Y14"; ## G28 on J2 -#NET "FMC_LA25_P" LOC = "W14"; ## G27 on J2 -#NET "FMC_LA26_N" LOC = "U13"; ## D27 on J2 -#NET "FMC_LA26_P" LOC = "U14"; ## D26 on J2 -#NET "FMC_LA27_N" LOC = "AB10"; ## C27 on J2 -#NET "FMC_LA27_P" LOC = "AA10"; ## C26 on J2 -#NET "FMC_LA28_N" LOC = "AB16"; ## H32 on J2 -#NET "FMC_LA28_P" LOC = "AA16"; ## H31 on J2 -#NET "FMC_LA29_N" LOC = "U15"; ## G31 on J2 -#NET "FMC_LA29_P" LOC = "T15"; ## G30 on J2 -#NET "FMC_LA30_N" LOC = "AB15"; ## H35 on J2 -#NET "FMC_LA30_P" LOC = "Y15"; ## H34 on J2 -#NET "FMC_LA31_N" LOC = "V15"; ## G34 on J2 -#NET "FMC_LA31_P" LOC = "U16"; ## G33 on J2 -#NET "FMC_LA32_N" LOC = "Y18"; ## H38 on J2 -#NET "FMC_LA32_P" LOC = "W17"; ## H37 on J2 -#NET "FMC_LA33_N" LOC = "AB17"; ## G37 on J2 -#NET "FMC_LA33_P" LOC = "Y17"; ## G36 on J2 -#NET "FMC_PRSNT_M2C_L" LOC = "Y16"; ## H2 on J2 -#NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## D1 on J2, 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (thru series R260 DNP), 44 of U25 -#NET "FLASH_D13" LOC = "Y13"; ## 50 on U25 -#NET "FLASH_D14" LOC = "AA12"; ## 52 on U25 -#NET "FLASH_D15" LOC = "AB12"; ## 54 on U25 -#NET "FLASH_WAIT" LOC = "T18"; ## 56 on U25 -#NET "FLASH_WE_B" LOC = "R20"; ## 14 on U25 -#NET "FLASH_OE_B" LOC = "P22"; ## 32 on U25 -#NET "FLASH_CE_B" LOC = "P21"; ## 30 on U25 -#NET "FLASH_ADV_B" LOC = "T19"; ## 46 on U25 -## NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## 44 on U25 (this signal goes to multiple destinations, see below) -## -#NET "FMC_CLK0_M2C_N" LOC = "G11"; ## H5 on J2 -#NET "FMC_CLK0_M2C_P" LOC = "H12"; ## H4 on J2 -#NET "FMC_CLK1_M2C_N" LOC = "F16"; ## G3 on J2 -#NET "FMC_CLK1_M2C_P" LOC = "E16"; ## G2 on J2 -#NET "FMC_DP0_C2M_N" LOC = "A16"; ## C3 on J2 -#NET "FMC_DP0_C2M_P" LOC = "B16"; ## C2 on J2 -#NET "FMC_DP0_M2C_N" LOC = "C15"; ## C7 on J2 -#NET "FMC_DP0_M2C_P" LOC = "D15"; ## C6 on J2 -#NET "FMC_GBTCLK0_M2C_N" LOC = "F12"; ## D5 on J2 -#NET "FMC_GBTCLK0_M2C_P" LOC = "E12"; ## D4 on J2 -### NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 (this signal goes to multiple destinations, see below) -### NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 (this signal goes to multiple destinations, see below) -#NET "FMC_LA00_CC_N" LOC = "F10"; ## G7 on J2 -#NET "FMC_LA00_CC_P" LOC = "G9"; ## G6 on J2 -#NET "FMC_LA01_CC_N" LOC = "F15"; ## D9 on J2 -#NET "FMC_LA01_CC_P" LOC = "F14"; ## D8 on J2 -#NET "FMC_LA02_N" LOC = "F9"; ## H8 on J2 -#NET "FMC_LA02_P" LOC = "G8"; ## H7 on J2 -#NET "FMC_LA03_N" LOC = "A18"; ## G10 on J2 -#NET "FMC_LA03_P" LOC = "B18"; ## G9 on J2 -#NET "FMC_LA04_N" LOC = "A19"; ## H11 on J2 -#NET "FMC_LA04_P" LOC = "C19"; ## H10 on J2 -#NET "FMC_LA05_N" LOC = "A4"; ## D12 on J2 -#NET "FMC_LA05_P" LOC = "C4"; ## D11 on J2 -#NET "FMC_LA06_N" LOC = "D5"; ## C11 on J2 -#NET "FMC_LA06_P" LOC = "D4"; ## C10 on J2 -#NET "FMC_LA07_N" LOC = "A2"; ## H14 on J2 -#NET "FMC_LA07_P" LOC = "B2"; ## H13 on J2 -#NET "FMC_LA08_N" LOC = "A20"; ## G13 on J2 -#NET "FMC_LA08_P" LOC = "B20"; ## G12 on J2 -#NET "FMC_LA09_N" LOC = "F8"; ## D15 on J2 -#NET "FMC_LA09_P" LOC = "F7"; ## D14 on J2 -#NET "FMC_LA10_N" LOC = "H11"; ## C15 on J2 -#NET "FMC_LA10_P" LOC = "H10"; ## C14 on J2 -#NET "FMC_LA11_N" LOC = "G15"; ## H17 on J2 -#NET "FMC_LA11_P" LOC = "H14"; ## H16 on J2 -#NET "FMC_LA12_N" LOC = "G13"; ## G16 on J2 -#NET "FMC_LA12_P" LOC = "H13"; ## G15 on J2 -#NET "FMC_LA13_N" LOC = "F17"; ## D18 on J2 -#NET "FMC_LA13_P" LOC = "G16"; ## D17 on J2 -#NET "FMC_LA14_N" LOC = "A17"; ## C19 on J2 -#NET "FMC_LA14_P" LOC = "C17"; ## C18 on J2 -#NET "FMC_LA15_N" LOC = "D19"; ## H20 on J2 -#NET "FMC_LA15_P" LOC = "D18"; ## H19 on J2 -#NET "FMC_LA16_N" LOC = "A5"; ## G19 on J2 -#NET "FMC_LA16_P" LOC = "C5"; ## G18 on J2 -#NET "FMC_LA17_CC_N" LOC = "AB11"; ## D21 on J2 -#NET "FMC_LA17_CC_P" LOC = "Y11"; ## D20 on J2 -#NET "FMC_LA18_CC_N" LOC = "U12"; ## C23 on J2 -#NET "FMC_LA18_CC_P" LOC = "T12"; ## C22 on J2 -#NET "FMC_LA19_N" LOC = "T11"; ## H23 on J2 -#NET "FMC_LA19_P" LOC = "R11"; ## H22 on J2 -#NET "FMC_LA20_N" LOC = "R8"; ## G22 on J2 -#NET "FMC_LA20_P" LOC = "R9"; ## G21 on J2 -#NET "FMC_LA21_N" LOC = "W11"; ## H26 on J2 -#NET "FMC_LA21_P" LOC = "V11"; ## H25 on J2 -#NET "FMC_LA22_N" LOC = "W8"; ## G25 on J2 -#NET "FMC_LA22_P" LOC = "V7"; ## G24 on J2 -#NET "FMC_LA23_N" LOC = "V9"; ## D24 on J2 -#NET "FMC_LA23_P" LOC = "U9"; ## D23 on J2 -#NET "FMC_LA24_N" LOC = "AB14"; ## H29 on J2 -#NET "FMC_LA24_P" LOC = "AA14"; ## H28 on J2 -#NET "FMC_LA25_N" LOC = "Y14"; ## G28 on J2 -#NET "FMC_LA25_P" LOC = "W14"; ## G27 on J2 -#NET "FMC_LA26_N" LOC = "U13"; ## D27 on J2 -#NET "FMC_LA26_P" LOC = "U14"; ## D26 on J2 -#NET "FMC_LA27_N" LOC = "AB10"; ## C27 on J2 -#NET "FMC_LA27_P" LOC = "AA10"; ## C26 on J2 -#NET "FMC_LA28_N" LOC = "AB16"; ## H32 on J2 -#NET "FMC_LA28_P" LOC = "AA16"; ## H31 on J2 -#NET "FMC_LA29_N" LOC = "U15"; ## G31 on J2 -#NET "FMC_LA29_P" LOC = "T15"; ## G30 on J2 -#NET "FMC_LA30_N" LOC = "AB15"; ## H35 on J2 -#NET "FMC_LA30_P" LOC = "Y15"; ## H34 on J2 -#NET "FMC_LA31_N" LOC = "V15"; ## G34 on J2 -#NET "FMC_LA31_P" LOC = "U16"; ## G33 on J2 -#NET "FMC_LA32_N" LOC = "Y18"; ## H38 on J2 -#NET "FMC_LA32_P" LOC = "W17"; ## H37 on J2 -#NET "FMC_LA33_N" LOC = "AB17"; ## G37 on J2 -#NET "FMC_LA33_P" LOC = "Y17"; ## G36 on J2 -#NET "FMC_PRSNT_M2C_L" LOC = "Y16"; ## H2 on J2 -#NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "V13"; ## D1 on J2, 1 of Q2 (LED DS1 driver), U1 AB2 FPGA_PROG (thru series R260 DNP), 44 of U25 -### -#NET "FPGA_AWAKE" LOC = "V19"; ## 2 on DS7 LED -#NET "FPGA_CCLK" LOC = "Y20"; ## 7 on J17 -#NET "FPGA_CMP_CLK" LOC = "V17"; ## 3 on J3 -#NET "FPGA_CMP_CS_B" LOC = "V18"; ## 4 on J3 -#NET "FPGA_CMP_MOSI" LOC = "W18"; ## 2 on J3 -### NET "FPGA_D0_DIN_MISO_MISO1" LOC = "AA20"; ## this pin is part of the FLASH_nn group -### NET "FPGA_D1_MISO2" LOC = "R13"; ## this pin is part of the FLASH_nn group -### NET "FPGA_D2_MISO3" LOC = "T14"; ## this pin is part of the FLASH_nn group -#NET "FPGA_DONE" LOC = "AB21"; ## 2 on DS2 LED -#NET "FPGA_HSWAPEN" LOC = "C3"; ## 1 on R125 100 ohm to GND -#NET "FPGA_INIT_B" LOC = "Y4"; ## 1 on DS17 (thru sereis R69 75 ohm), 78 on U17 -#NET "FPGA_M0_CMP_MISO" LOC = "AA21"; ## 1 on SW1 DIP switch (active-high), 1 on J3 -#NET "FPGA_M1" LOC = "Y19"; ## 2 on SW1 DIP switch (active-high) -#NET "FPGA_MOSI_CSI_B_MISO0" LOC = "AB20"; ## 15 on U32, 5 on J17 -#NET "FPGA_ONCHIP_TERM1" LOC = "M7"; ## 1 on R124 DNP to GND -#NET "FPGA_ONCHIP_TERM2" LOC = "K7"; ## 1 on R126 100 ohm to GND -#NET "FPGA_PROG_B" LOC = "AB2"; ## 1 on SW3 pushbutton (active-high) 1 on J17, 2 on J48, 2 on R260 DNP connected to NET "FMC_PWR_GOOD_FLASH_RST_B" -#NET "FPGA_SUSPEND" LOC = "AA22"; ## 2 on J47 -#NET "FPGA_TCK" LOC = "A21"; ## 80 on U17 -#NET "FPGA_TDI" LOC = "E18"; ## 82 on U17 -#NET "FPGA_TMS" LOC = "D20"; ## 85 on U17 -#NET "FPGA_VBATT" LOC = "T16"; ## 1 on B2 (battery), 2 on D11 (charging circuit) -#NET "FPGA_VTEMP" LOC = "Y3"; ## 2 on R207 150 ohm to VCC1V5 -### -#NET "IIC_SCL_DVI" LOC = "W13"; ## 15 on U31, 2 on Q7 (level shifter, Q7.3 <-> IIC_CLK_DVI_F <-> series ferrite F9 220 ohm <-> 6 on P3 -#NET "IIC_SDA_DVI" LOC = "AA4"; ## 14 on U31, 2 on Q8 (level shifter, Q7.3 <-> IIC_SDA_DVI_F <-> series ferrite F8 220 ohm <-> 7 on P3 -#NET "IIC_SCL_MAIN" LOC = "T21"; ## C30 on J2 -#NET "IIC_SDA_MAIN" LOC = "R22"; ## C31 on J2 -#NET "IIC_SCL_SFP" LOC = "E5"; ## 5 on P2 -#NET "IIC_SDA_SFP" LOC = "E6"; ## 4 on P2 -### -#NET "MEM1_A0" LOC = "K2"; ## N3 on U42 -#NET "MEM1_A1" LOC = "K1"; ## P7 on U42 -#NET "MEM1_A2" LOC = "K5"; ## P3 on U42 -#NET "MEM1_A3" LOC = "M6"; ## N2 on U42 -#NET "MEM1_A4" LOC = "H3"; ## P8 on U42 -#NET "MEM1_A5" LOC = "M3"; ## P2 on U42 -#NET "MEM1_A6" LOC = "L4"; ## R8 on U42 -#NET "MEM1_A7" LOC = "K6"; ## R2 on U42 -#NET "MEM1_A8" LOC = "G3"; ## T8 on U42 -#NET "MEM1_A9" LOC = "G1"; ## R3 on U42 -#NET "MEM1_A10" LOC = "J4"; ## L7 on U42 -#NET "MEM1_A11" LOC = "E1"; ## R7 on U42 -#NET "MEM1_A12" LOC = "F1"; ## N7 on U42 -#NET "MEM1_A13" LOC = "J6"; ## T3 on U42 -#NET "MEM1_A14" LOC = "H5"; ## T7 on U42 -#NET "MEM1_BA0" LOC = "J3"; ## M2 on U42 -#NET "MEM1_BA1" LOC = "J1"; ## N8 on U42 -#NET "MEM1_BA2" LOC = "H1"; ## M3 on U42 -#NET "MEM1_CAS_B" LOC = "M4"; ## K3 on U42 -#NET "MEM1_CKE" LOC = "F2"; ## K9 on U42 -#NET "MEM1_CLK_N" LOC = "K3"; ## K7 on U42 -#NET "MEM1_CLK_P" LOC = "K4"; ## J7 on U42 -#NET "MEM1_DQ0" LOC = "R3"; ## G2 on U42 -#NET "MEM1_DQ1" LOC = "R1"; ## H3 on U42 -#NET "MEM1_DQ2" LOC = "P2"; ## E3 on U42 -#NET "MEM1_DQ3" LOC = "P1"; ## F2 on U42 -#NET "MEM1_DQ4" LOC = "L3"; ## H7 on U42 -#NET "MEM1_DQ5" LOC = "L1"; ## H8 on U42 -#NET "MEM1_DQ6" LOC = "M2"; ## F7 on U42 -#NET "MEM1_DQ7" LOC = "M1"; ## F8 on U42 -#NET "MEM1_DQ8" LOC = "T2"; ## C2 on U42 -#NET "MEM1_DQ9" LOC = "T1"; ## C3 on U42 -#NET "MEM1_DQ10" LOC = "U3"; ## A2 on U42 -#NET "MEM1_DQ11" LOC = "U1"; ## D7 on U42 -#NET "MEM1_DQ12" LOC = "W3"; ## A3 on U42 -#NET "MEM1_DQ13" LOC = "W1"; ## C8 on U42 -#NET "MEM1_DQ14" LOC = "Y2"; ## B8 on U42 -#NET "MEM1_DQ15" LOC = "Y1"; ## A7 on U42 -#NET "MEM1_LDM" LOC = "N4"; ## E7 on U42 -#NET "MEM1_LDQS_N" LOC = "N1"; ## G3 on U42 -#NET "MEM1_LDQS_P" LOC = "N3"; ## F3 on U42 -#NET "MEM1_ODT" LOC = "L6"; ## K1 on U42 -#NET "MEM1_RAS_B" LOC = "M5"; ## J3 on U42 -#NET "MEM1_RESET_B" LOC = "E3"; ## T2 on U42 -#NET "MEM1_UDM" LOC = "P3"; ## D3 on U42 -#NET "MEM1_UDQS_N" LOC = "V1"; ## B7 on U42 -#NET "MEM1_UDQS_P" LOC = "V2"; ## C7 on U42 -#NET "MEM1_WE_B" LOC = "H2"; ## L3 on U42 -### -#NET "PCIE_250M_N" LOC = "B10"; ## 1 on series C301 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_N -> 17 on U48 -#NET "PCIE_250M_P" LOC = "A10"; ## 1 on series C300 0.1uF, C300 pin 2 -> PCIE_250M_MGT1_C_P -> 18 on U48 -#NET "PCIE_PERST_B_LS" LOC = "J7"; ## 6 on U52 (level shifter, U52.20 <-> PCIE_PERST_B <-> series R55 15 ohm <-> A11 on P4 -#NET "PCIE_RX0_N" LOC = "C7"; ## B15 on P4 -#NET "PCIE_RX0_P" LOC = "D7"; ## B14 on P4 -#NET "PCIE_TX0_N" LOC = "A6"; ## 2 on series C26 0.1uF, C26 pin 1 -> PCIE_TX0_C_N -> A17 of P4 -#NET "PCIE_TX0_P" LOC = "B6"; ## 2 on series C27 0.1uF, C26 pin 1 -> PCIE_TX0_C_P -> A16 of P4 -### -#NET "PMBUS_ALERT" LOC = "D3"; ## 35 on U26, 35 on U27 -#NET "PMBUS_CLK" LOC = "W10"; ## 19 on U26, 19 on U27 -#NET "PMBUS_CTRL" LOC = "H16"; ## 36 on U26, 36 on U27 -#NET "PMBUS_DATA" LOC = "Y10"; ## 20 on U26, 20 on U27 -### -#NET "SFPCLK_QO_N" LOC = "B12"; ## 2 on series C298 0.1uF, C298 pin 1 <- SFPCLK_QO_C_N <- 6 of U47 -#NET "SFPCLK_QO_P" LOC = "A12"; ## 2 on series C299 0.1uF, C299 pin 1 <- SFPCLK_QO_C_P <- 7 of U47 -#NET "SFP_LOS" LOC = "T17"; ## 8 on P2, 1 on J14 -#NET "SFP_RX_N" LOC = "C13"; ## 12 on P2 -#NET "SFP_RX_P" LOC = "D13"; ## 13 on P2 -#NET "SFP_TX_DISABLE_FPGA" LOC = "Y8"; ## 3 on P2, 1 on J44 -#NET "SFP_TX_N" LOC = "A14"; ## 19 on P2 -#NET "SFP_TX_P" LOC = "B14"; ## 18 on P2 -### -#NET "SMA_RX_N" LOC = "C9"; ## -#NET "SMA_RX_P" LOC = "D9"; ## -#NET "SMA_TX_N" LOC = "A8"; ## -#NET "SMA_TX_P" LOC = "B8"; ## -### -#NET "SPI_CS_B" LOC = "AA3"; ## -### -#NET "SYSACE_CFGTDI" LOC = "G17"; ## -#NET "SYSACE_D0_LS" LOC = "N6"; ## -#NET "SYSACE_D1_LS" LOC = "N7"; ## -#NET "SYSACE_D2_LS" LOC = "U4"; ## -#NET "SYSACE_D3_LS" LOC = "T4"; ## -#NET "SYSACE_D4_LS" LOC = "P6"; ## -#NET "SYSACE_D5_LS" LOC = "P7"; ## -#NET "SYSACE_D6_LS" LOC = "T3"; ## -#NET "SYSACE_D7_LS" LOC = "R4"; ## -#NET "SYSACE_MPA00_LS" LOC = "V5"; ## -#NET "SYSACE_MPA01_LS" LOC = "V3"; ## -#NET "SYSACE_MPA02_LS" LOC = "P5"; ## -#NET "SYSACE_MPA03_LS" LOC = "P4"; ## -#NET "SYSACE_MPA04_LS" LOC = "H4"; ## -#NET "SYSACE_MPA05_LS" LOC = "G4"; ## -#NET "SYSACE_MPA06_LS" LOC = "D2"; ## -#NET "SYSACE_MPBRDY_LS" LOC = "AA1"; ## -#NET "SYSACE_MPCE_LS" LOC = "W4"; ## -#NET "SYSACE_MPIRQ_LS" LOC = "AA2"; ## -#NET "SYSACE_MPOE_LS" LOC = "T6"; ## -#NET "SYSACE_MPWE_LS" LOC = "T5"; ## -### -#NET "USB_1_CTS" LOC = "F18"; ## -#NET "USB_1_RTS" LOC = "F19"; ## -### diff --git a/xula2.bitconf b/xula2.bitconf deleted file mode 100644 index 599289d..0000000 --- a/xula2.bitconf +++ /dev/null @@ -1,7 +0,0 @@ --g Binary:yes -# below are xula2-specific configurations --g UnusedPin:Pullnone --g TckPin:Pullnone -#-g StartupClk:JtagClk # for JTAG upload --g StartupClk:Cclk # for serial flash --g ConfigRate:10 # for fast serial flashing diff --git a/xula2.bmm b/xula2.bmm deleted file mode 100644 index c915ec8..0000000 --- a/xula2.bmm +++ /dev/null @@ -1 +0,0 @@ -// Empty file; this is a "Block Ram Memory Map" diff --git a/xula2.ucf b/xula2.ucf deleted file mode 100644 index ae04f81..0000000 --- a/xula2.ucf +++ /dev/null @@ -1,69 +0,0 @@ -# ============================================================================ -# Xess Corp XuLa 2 -# ============================================================================ - -# Originally written October 2013 by LeafLabs, LLC (leaflabs.com). - -# The .ucf supplied by Xess is under GPL. -# https://raw.github.com/xesscorp/XuLA2/master/FPGA/XuLA_lib/XuLA2.ucf - -# This file was written from scratch from the manual. It is intended to be -# reused and copy/pasted from with no copyright or attribution necessary. In -# that an explicit license is necessary for such a file, it is Creative Commons -# Zero. - -# ==== Clocks ==== - -NET "clock_12mhz" LOC = "A9"; -NET "clock_12mhz" IOSTANDARD = LVTTL; -NET "clock_12mhz" TNM_NET = "clock_12mhz"; -TIMESPEC "TS_clock_12mhz" = PERIOD "clock_12mhz" 12 MHz HIGH 50%; - -# ==== Prototyping Header (GPIO) ==== - -NET "chan_clk" LOC = "T7" | IOSTANDARD = LVTTL ; - -NET "chan<0>" LOC = "R7" | IOSTANDARD = LVTTL ; -NET "chan<1>" LOC = "R15" | IOSTANDARD = LVTTL ; -NET "chan<2>" LOC = "R16" | IOSTANDARD = LVTTL ; -NET "chan<3>" LOC = "M15" | IOSTANDARD = LVTTL ; -NET "chan<4>" LOC = "M16" | IOSTANDARD = LVTTL ; -NET "chan<5>" LOC = "K15" | IOSTANDARD = LVTTL ; -NET "chan<6>" LOC = "K16" | IOSTANDARD = LVTTL ; -NET "chan<7>" LOC = "J16" | IOSTANDARD = LVTTL ; -NET "chan<8>" LOC = "J14" | IOSTANDARD = LVTTL ; -NET "chan<9>" LOC = "F15" | IOSTANDARD = LVTTL ; -NET "chan<10>" LOC = "F16" | IOSTANDARD = LVTTL ; -NET "chan<11>" LOC = "C16" | IOSTANDARD = LVTTL ; -NET "chan<12>" LOC = "C15" | IOSTANDARD = LVTTL ; -NET "chan<13>" LOC = "B16" | IOSTANDARD = LVTTL ; -NET "chan<14>" LOC = "B15" | IOSTANDARD = LVTTL ; -NET "chan<15>" LOC = "T4" | IOSTANDARD = LVTTL ; -NET "chan<16>" LOC = "R2" | IOSTANDARD = LVTTL ; -NET "chan<17>" LOC = "R1" | IOSTANDARD = LVTTL ; -NET "chan<18>" LOC = "M2" | IOSTANDARD = LVTTL ; -NET "chan<19>" LOC = "M1" | IOSTANDARD = LVTTL ; -NET "chan<20>" LOC = "K3" | IOSTANDARD = LVTTL ; -NET "chan<21>" LOC = "J4" | IOSTANDARD = LVTTL ; -NET "chan<22>" LOC = "H1" | IOSTANDARD = LVTTL ; -NET "chan<23>" LOC = "H2" | IOSTANDARD = LVTTL ; -NET "chan<24>" LOC = "F1" | IOSTANDARD = LVTTL ; -NET "chan<25>" LOC = "F2" | IOSTANDARD = LVTTL ; -NET "chan<26>" LOC = "E1" | IOSTANDARD = LVTTL ; -NET "chan<27>" LOC = "E2" | IOSTANDARD = LVTTL ; -NET "chan<28>" LOC = "C1" | IOSTANDARD = LVTTL ; -NET "chan<29>" LOC = "B1" | IOSTANDARD = LVTTL ; -NET "chan<30>" LOC = "B2" | IOSTANDARD = LVTTL ; -NET "chan<31>" LOC = "A2" | IOSTANDARD = LVTTL ; - -# ==== SDRAM ==== -# TODO - -# ==== SPI Flash and uSD Card ==== - -NET "microsd_cs" LOC = "T8" | IOSTANDARD = LVTTL ; -NET "flash_cs" LOC = "T3" | IOSTANDARD = LVTTL ; -NET "flash_sclk" LOC = "R11" | IOSTANDARD = LVTTL ; -NET "flash_mosi" LOC = "T10" | IOSTANDARD = LVTTL ; -NET "flash_miso" LOC = "P10" | IOSTANDARD = LVTTL ; - -- cgit v1.2.3