From 7d9fb988443e94507a7d3ca6e0137aaf49af42e1 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Thu, 14 Mar 2013 12:50:17 -0400
Subject: improvements

---
 Makefile             | 11 ++++++++---
 README               |  6 ++++--
 contrib/template.cgp | 12 ++++++++++++
 contrib/xilinx.mk    | 32 ++++++++++++++++++++------------
 project.xise         | 30 ++++++++++--------------------
 5 files changed, 54 insertions(+), 37 deletions(-)
 create mode 100644 contrib/template.cgp

diff --git a/Makefile b/Makefile
index fb70c09..0fd1347 100644
--- a/Makefile
+++ b/Makefile
@@ -4,13 +4,18 @@ vendor = xilinx
 
 # This is the chipset from the Xilinx SP605 dev board
 family = spartan6
-part = xc6slx45t-3-fgg484
+device = xc6slx45t
+speedgrade = -3
+device_package = fgg484
+part = $(device)$(speedgrade)-$(device_package)
+
 
 # is this build host 64 or 32 bits?
 hostbits = 64
 iseenv= /opt/Xilinx/14.3/ISE_DS/
 
-vfiles = ./hdl/project.v
-tbfiles = ./tb/tb.v
+vfiles = ./hdl/*.v
+tbfiles = ./tb/*.v
+xilinx_cores = 
 
 include ./contrib/xilinx.mk
diff --git a/README b/README
index cda84b1..f7c9069 100644
--- a/README
+++ b/README
@@ -17,6 +17,8 @@ lives in:
 
     ./hdl/project.v
 
+Add other verilog synthesis (not testbench) files to ./hdl/*.v
+
 To edit the project with the ISE GUI, try:
 
     make ise
@@ -29,9 +31,9 @@ Simulate with isim via:
 
     make simulate
 
-View the results using isim with:
+View the results using the isim GUI with:
 
-    make isim_gui
+    make isim
 
 In isim, you can open the "signals.wcfg" in the file menu to reload a the logic
 analyzer configuration. This cfg file will not be valid if you delete any
diff --git a/contrib/template.cgp b/contrib/template.cgp
new file mode 100644
index 0000000..d5ac466
--- /dev/null
+++ b/contrib/template.cgp
@@ -0,0 +1,12 @@
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET verilogsim = true
+SET vhdlsim = false
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index f8773ac..7060c99 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -45,7 +45,7 @@ par_opts ?= -ol high
 hostbits = 64
 iseenv= /opt/Xilinx/14.3/ISE_DS
 iseenvfile?= $(iseenv)/settings$(hostbits).sh
-xil_env ?= cd ./build; source $(iseenvfile) > /dev/null
+xil_env ?= mkdir -p build/; cd ./build; source $(iseenvfile) > /dev/null
 sim_env ?= cd ./tb; source $(iseenvfile) > /dev/null
 flashsize ?= 8192
 
@@ -70,25 +70,32 @@ $(2): $(1)
 endef
 $(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
 
-%.ngc %.v: %.xco
-	@echo "=== rebuilding $@"
+$(coregen_work_dir)/$(project).cgp: contrib/template.cgp Makefile
 	if [ -d $(coregen_work_dir) ]; then \
 		rm -rf $(coregen_work_dir)/*; \
 	else \
 		mkdir -p $(coregen_work_dir); \
 	fi
-	cd $(coregen_work_dir); \
-	bash -c "$(xil_env); \
-	coregen -b $$OLDPWD/$<; \
-	cd -
+	cp contrib/template.cgp $@
+	echo "SET designentry = Verilog " >> $@
+	echo "SET device = $(device)" >> $@
+	echo "SET devicefamily = $(family)" >> $@
+	echo "SET package = $(device_package)" >> $@
+	echo "SET speedgrade = $(speedgrade)" >> $@
+	echo "SET workingdirectory = ./tmp/" >> $@
+
+%.ngc %.v: %.xco $(coregen_work_dir)/$(project).cgp
+	@echo "=== rebuilding $@"
+	bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -b $$OLDPWD/../$< -p $(project).cgp;"
 	xcodir=`dirname $<`; \
 	basename=`basename $< .xco`; \
-	if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
+	echo $(coregen_work_dir)/$$basename.v; \
+	if [ ! -r $(coregen_work_dir)/$$basename.ngc ]; then \
 		echo "'$@' wasn't created."; \
 		exit 1; \
 	else \
 		cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
-	fi"
+	fi
 junk += $(coregen_work_dir)
 
 date = $(shell date +%F-%H-%M)
@@ -140,7 +147,7 @@ junk += $(project)_summary.xml $(project)_usage.xml
 
 build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm
 	bash -c "$(xil_env); \
-	ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm"
+	ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm -sd ../cores"
 junk += $(project).ngd $(project).bld
 
 build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj
@@ -202,10 +209,10 @@ tb/simulate_isim: tb/isim
 
 simulate: tb/simulate_isim
 
-isim_gui: simulate
+isim_cli: simulate
 	bash -c "$(sim_env); cd ../tb/; ./simulate_isim"
 
-isim_gui: simulate
+isim: simulate
 	bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg"
 
 ise:
@@ -224,5 +231,6 @@ clean_sim::
 
 clean_synth::
 	rm -rf build
+	rm -rf coregen-tmp
 #rm -rf $(junk)
 
diff --git a/project.xise b/project.xise
index cff885d..42b5b99 100644
--- a/project.xise
+++ b/project.xise
@@ -14,18 +14,7 @@
 
   <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
 
-  <files>
-    <file xil_pn:name="hdl/project.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="project.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="project.bmm" xil_pn:type="FILE_BMM">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-  </files>
+  <files/>
 
   <properties>
     <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
@@ -88,6 +77,7 @@
     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -140,9 +130,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Module|project" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="../hdl/project.v" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/project" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -205,11 +195,11 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="project" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -219,10 +209,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="project_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="project_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="project_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="project_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
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