From 58a4d81047891bf2bcfaa141f81b4ea34f0c3594 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Wed, 9 Oct 2013 00:30:58 -0400
Subject: fix up minor xula2 typos

---
 Makefile         | 1 -
 hdl/main_xula2.v | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index b0de5d6..2b93161 100644
--- a/Makefile
+++ b/Makefile
@@ -19,7 +19,6 @@ device := XC6SLX25
 speedgrade := -2
 device_package := ftg256
 extra_includes = ./contrib/xula2.mk
-include ./contrib/xula2.mk
 
 part := $(device)$(speedgrade)-$(device_package)
 
diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v
index 49581e1..4436665 100644
--- a/hdl/main_xula2.v
+++ b/hdl/main_xula2.v
@@ -36,7 +36,7 @@ module main (
     wire [7:0] rx_byte;
     wire [7:0] tx_byte;
     wire uart_flag;
-    simple_uart (
+    simple_uart #(
         .CLOCK_DIVIDE(313) // for 12MHz clock
     ) simple_uart_inst (
         .clk(clock_12mhz),
-- 
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