From 48d0e230c56be8a2722851556b2b1e039c4847c4 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Wed, 13 Mar 2013 16:31:09 -0400 Subject: move stuff around; backup --- .gitignore | 2 +- Makefile | 8 +- contrib/xilinx.mk | 23 ++- contrib/xilinx.opt | 42 ----- project.opt | 42 +++++ project.xise | 366 ++++++++++++++++++++++++++++++++++++++++++++ tb/signals.wcfg | 42 +++++ tb/tb.v | 45 ++++++ testbench/fuse.sh | 2 - testbench/signals.wcfg | 42 ----- testbench/simulate_isim.exe | Bin 21792 -> 0 bytes testbench/simulate_isim.prj | 3 - testbench/tb.v | 45 ------ 13 files changed, 518 insertions(+), 144 deletions(-) delete mode 100644 contrib/xilinx.opt create mode 100644 project.opt create mode 100644 project.xise create mode 100644 tb/signals.wcfg create mode 100755 tb/tb.v delete mode 100755 testbench/fuse.sh delete mode 100644 testbench/signals.wcfg delete mode 100755 testbench/simulate_isim.exe delete mode 100644 testbench/simulate_isim.prj delete mode 100755 testbench/tb.v diff --git a/.gitignore b/.gitignore index f1906a2..4f84d26 100644 --- a/.gitignore +++ b/.gitignore @@ -42,7 +42,7 @@ isim.wdb *.xmsgs fuseRelaunch.cmd isim.wdb -isim/ +tb/isim/ dump.vcd simulation/ *_envsettings.html diff --git a/Makefile b/Makefile index e595d9c..d434552 100644 --- a/Makefile +++ b/Makefile @@ -1,8 +1,10 @@ project = project -vendor = xilinx -family = spartan3s -part = xc3s1000-4ft256 top_module = project +vendor = xilinx + +# This is the chipset from the Xilinx SP605 dev board +family = spartan6 +part = xc6slx45t-3-fgg484 iseenvfile = /opt/Xilinx/14.3/ISE_DS/settings64.sh diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index c03f4c3..8533121 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -1,9 +1,11 @@ -# This file came from excamera's build example. +# This file oritinally came from excamera's build example. # # The top level module should define the variables below then include # this file. The files listed should be in the same directory as the # Makefile. # +# TODO: update these listings +# # variable description # ---------- ------------- # project project name (top level module should match this name) @@ -53,7 +55,7 @@ local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) junk += $(local_corengcs) -.PHONY: default xilinx_cores clean twr etwr ise isim +.PHONY: default xilinx_cores clean twr etwr ise default: build/$(project).bit build/$(project).mcs xilinx_cores: $(corengcs) twr: $(project).twr @@ -151,14 +153,15 @@ junk += $(project).prj optfile += $(wildcard $(project).opt) top_module ?= $(project) -build/$(project).scr: $(optfile) $(mkfiles) ./contrib/xilinx.opt +build/$(project).scr: $(optfile) $(mkfiles) ./$(project).opt mkdir -p build echo "run" > $@ echo "-p $(part)" >> $@ echo "-top $(top_module)" >> $@ echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ - cat ./contrib/xilinx.opt $(optfile) >> $@ + cat $(optfile) >> $@ + cp $@ build/$(project).xst junk += $(project).scr build/$(project).post_map.twr: build/$(project).ncd @@ -176,6 +179,14 @@ junk += $(project)_err.twr $(project)_err.twx .gitignore: $(mkfiles) echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore +ise: + @echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + @echo "! WARNING: you might need to update ISE's project settings !" + @echo "! (see README) !" + @echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + @mkdir -p build + bash -c "$(xil_env); ise .. &" + clean:: - rm -rf $(junk) - cd build; rm -rf $(junk) + rm -rf build +#rm -rf $(junk) diff --git a/contrib/xilinx.opt b/contrib/xilinx.opt deleted file mode 100644 index 7fe9d8b..0000000 --- a/contrib/xilinx.opt +++ /dev/null @@ -1,42 +0,0 @@ --ifmt mixed --ofmt NGC --opt_mode speed --opt_level 1 --iuc NO --keep_hierarchy no --netlist_hierarchy as_optimized --rtlview no --glob_opt AllClockNets --read_cores yes --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 -#-dsp_utilization_ratio 100 --safe_implementation No --fsm_extract YES --fsm_encoding Auto --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --shreg_extract YES --auto_bram_packing NO --resource_sharing YES --async_to_sync NO -#-use_dsp48 auto --iobuf YES --max_fanout 500 --register_duplication YES --register_balancing No --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/project.opt b/project.opt new file mode 100644 index 0000000..7fe9d8b --- /dev/null +++ b/project.opt @@ -0,0 +1,42 @@ +-ifmt mixed +-ofmt NGC +-opt_mode speed +-opt_level 1 +-iuc NO +-keep_hierarchy no +-netlist_hierarchy as_optimized +-rtlview no +-glob_opt AllClockNets +-read_cores yes +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +#-dsp_utilization_ratio 100 +-safe_implementation No +-fsm_extract YES +-fsm_encoding Auto +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-shreg_extract YES +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +#-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/project.xise b/project.xise new file mode 100644 index 0000000..cff885d --- /dev/null +++ b/project.xise @@ -0,0 +1,366 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tb/signals.wcfg b/tb/signals.wcfg new file mode 100644 index 0000000..dbb5e1a --- /dev/null +++ b/tb/signals.wcfg @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + LED_output_2 + LED_output_2 + + + Switch_input_0 + Switch_input_0 + + + Switch_input_1 + Switch_input_1 + + + Switch_input_2 + Switch_input_2 + + + Switch_input_3 + Switch_input_3 + + + SYSTEMCLOCK + SYSTEMCLOCK + + + PUSH_BUTTON_RESET_RAW + PUSH_BUTTON_RESET_RAW + + diff --git a/tb/tb.v b/tb/tb.v new file mode 100755 index 0000000..19e07bf --- /dev/null +++ b/tb/tb.v @@ -0,0 +1,45 @@ +`timescale 1ps/1ps +module tb; + + reg CLK100; +always @(CLK100) begin + #4980.00 CLK100 <= ~CLK100; +end + +initial begin + #0 CLK100 <= 1'b0; // the first event that sets the clock in motion +end + + +reg [7:0] Switch_input; +wire [7:0] LED_output; +wire FPGA_RESET; + +project project_i ( + .PUSH_BUTTON_RESET_RAW(FPGA_RESET), + .LED_output_0(LED_output[0]), + .LED_output_1(LED_output[1]), + .LED_output_2(LED_output[2]), + .LED_output_3(LED_output[3]), + .LED_output_4(LED_output[4]), + .LED_output_5(LED_output[5]), + .LED_output_6(LED_output[6]), + .SYSTEMCLOCK(CLK100), + .Switch_input_0(Switch_input[0]), + .Switch_input_1(Switch_input[1]), + .Switch_input_2(Switch_input[2]), + .Switch_input_3(Switch_input[3]) + ); + + +initial begin + #0 Switch_input <= 8'h00; + $display("Switch set to zero"); + #1000000 Switch_input <= 8'h01; + $display("Switch set to one"); + #2000000 + $display("TEST COMPLETE"); + $finish(); +end + +endmodule diff --git a/testbench/fuse.sh b/testbench/fuse.sh deleted file mode 100755 index ad08c93..0000000 --- a/testbench/fuse.sh +++ /dev/null @@ -1,2 +0,0 @@ -vlogcomp -prj simulate_isim.prj -fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim.exe unenclib.tb unenclib.glbl diff --git a/testbench/signals.wcfg b/testbench/signals.wcfg deleted file mode 100644 index dbb5e1a..0000000 --- a/testbench/signals.wcfg +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - LED_output_2 - LED_output_2 - - - Switch_input_0 - Switch_input_0 - - - Switch_input_1 - Switch_input_1 - - - Switch_input_2 - Switch_input_2 - - - Switch_input_3 - Switch_input_3 - - - SYSTEMCLOCK - SYSTEMCLOCK - - - PUSH_BUTTON_RESET_RAW - PUSH_BUTTON_RESET_RAW - - diff --git a/testbench/simulate_isim.exe b/testbench/simulate_isim.exe deleted file mode 100755 index 5e50691..0000000 Binary files a/testbench/simulate_isim.exe and /dev/null differ diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj deleted file mode 100644 index e610cc5..0000000 --- a/testbench/simulate_isim.prj +++ /dev/null @@ -1,3 +0,0 @@ -verilog unenclib ../hdl/project.v -verilog unenclib tb.v -verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v diff --git a/testbench/tb.v b/testbench/tb.v deleted file mode 100755 index 19e07bf..0000000 --- a/testbench/tb.v +++ /dev/null @@ -1,45 +0,0 @@ -`timescale 1ps/1ps -module tb; - - reg CLK100; -always @(CLK100) begin - #4980.00 CLK100 <= ~CLK100; -end - -initial begin - #0 CLK100 <= 1'b0; // the first event that sets the clock in motion -end - - -reg [7:0] Switch_input; -wire [7:0] LED_output; -wire FPGA_RESET; - -project project_i ( - .PUSH_BUTTON_RESET_RAW(FPGA_RESET), - .LED_output_0(LED_output[0]), - .LED_output_1(LED_output[1]), - .LED_output_2(LED_output[2]), - .LED_output_3(LED_output[3]), - .LED_output_4(LED_output[4]), - .LED_output_5(LED_output[5]), - .LED_output_6(LED_output[6]), - .SYSTEMCLOCK(CLK100), - .Switch_input_0(Switch_input[0]), - .Switch_input_1(Switch_input[1]), - .Switch_input_2(Switch_input[2]), - .Switch_input_3(Switch_input[3]) - ); - - -initial begin - #0 Switch_input <= 8'h00; - $display("Switch set to zero"); - #1000000 Switch_input <= 8'h01; - $display("Switch set to one"); - #2000000 - $display("TEST COMPLETE"); - $finish(); -end - -endmodule -- cgit v1.2.3