From 12fb9032819dde0ccd38dfc2645abbffb891cca9 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Tue, 12 Nov 2013 10:37:31 -0500
Subject: initial VHDL support

---
 Makefile          |  3 +++
 contrib/xilinx.mk | 20 ++++++++++++++++----
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 2b93161..9541815 100644
--- a/Makefile
+++ b/Makefile
@@ -33,6 +33,9 @@ verilog_files += hdl/rot13.v
 verilog_files += hdl/simple_uart.v
 #verilog_files += hdl/yours.v
 
+# all .vhd files explicitly also
+vhdl_files :=
+
 tbfiles := tb/rot13_tb.v
 tbfiles += tb/xula2_tb.v
 #tbfiles += tb/sp605_tb.v
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index 7f65ca8..4fde6c9 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -14,6 +14,8 @@
 #   libdir        path to library directory
 #   libs          library modules used
 #   verilog_files all local .v files
+#   vhdl_files    all local .vhd files
+#   end_vhdl_files all local encrypted .vhd files
 #   xilinx_cores  all local .xco files
 #   vendor        vendor of FPGA (xilinx, altera, etc.)
 #   family        FPGA device family (spartan3e) 
@@ -54,6 +56,8 @@ xil_env ?= mkdir -p build/; cd ./build; source $(iseenvfile) > /dev/null
 sim_env ?= cd ./tb; source $(iseenvfile) > /dev/null
 flashsize ?= 8192
 mcs_datawidth ?= 16
+extra_prj ?=
+end_vhdl_files ?=
 
 PWD := $(shell pwd)
 intstyle ?= -intstyle xflow
@@ -156,14 +160,16 @@ build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm
 	@bash -c "$(xil_env); \
 	ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)"
 
-build/$(project).ngc: $(verilog_files) $(local_corengcs) build/$(project).scr build/$(project).prj
+build/$(project).ngc: $(verilog_files) $(vhdl_files) $(local_corengcs) build/$(project).scr build/$(project).prj
 	@bash -c "rm build/$(project).scr; make build/$(project).scr"
 	@bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr $(colorize)"
 	@# need to check for success manually; TODO: doesn't work if pre-existed
 	@if [ ! -f build/$(project).ngc ]; then false; fi
 
-build/$(project).prj: $(verilog_files)
+build/$(project).prj: $(verilog_files) $(vhdl_files)
 	@for src in $(verilog_files); do echo "verilog work ../$$src" >> $(project).tmpprj; done
+	@for src in $(vhdl_files); do echo "vhdl work ../$$src" >> $(project).tmpprj; done
+	@for stub in $(extra_prj); do cat $$stub >> $(project).tmpprj; done
 	@sort -u $(project).tmpprj > $@
 	@rm -f $(project).tmpprj
 
@@ -188,17 +194,23 @@ build/$(project)_post_par.twr: build/$(project)_par.ncd
 	@bash -c "$(xil_env); trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) $(project)_par.ncd $(project).pcf -o $(project)_post_par.twr $(colorize)"
 	@echo "See $@ for timing analysis details"
 
-tb/simulate_isim.prj: $(tbfiles) $(verilog_files)
+tb/simulate_isim.prj: $(tbfiles) $(verilog_files) $(vhdl_files) $(enc_vhdl_files)
 	@rm -f $@
 	@for f in $(verilog_files); do \
 		echo "verilog unenclib ../$$f" >> $@; \
 	done
+	@for f in $(vhdl_files); do \
+		echo "vhdl unenclib ../$$f" >> $@; \
+	done
+	@for f in $(enc_vhdl_files); do \
+		echo "vhdl enclib ../$$f" >> $@; \
+	done
 	@for f in $(tbfiles); do \
 		echo "verilog unenclib ../$$f" >> $@; \
 	done
 	@echo "verilog unenclib $(iseenv)/ISE/verilog/src/glbl.v" >> $@
 
-tb/isim.compiled: tb/simulate_isim.prj $(tbfiles) $(verilog_files)
+tb/isim.compiled: tb/simulate_isim.prj $(tbfiles) $(verilog_files) $(vhdl_files)
 	@bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj $(colorize)"
 	@touch tb/isim.compiled
 
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