From 05339331c99cf830abae0985237437e06b9bcc3a Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Thu, 27 Jun 2013 18:44:54 -0400
Subject: a better minimalist project, including a timing constraint

---
 hdl/project.v | 49 +++++++++++++++++++++++++++----------------------
 project.ucf   | 21 ++++++++++++---------
 2 files changed, 39 insertions(+), 31 deletions(-)

diff --git a/hdl/project.v b/hdl/project.v
index 9e382a5..1b4f9f2 100644
--- a/hdl/project.v
+++ b/hdl/project.v
@@ -1,26 +1,31 @@
-module main
-   (
-    output wire LED_output_0,
-    output wire LED_output_1,
-    output wire LED_output_2,
-    output wire LED_output_3,
-    output wire LED_output_4,
-    output wire LED_output_5,
-    output wire LED_output_6,
-    input wire 	Switch_input_0,
-    input wire 	Switch_input_1,
-    input wire 	Switch_input_2,
-    input wire 	Switch_input_3,
-    input wire 	SYSTEMCLOCK,
-    input wire 	PUSH_BUTTON_RESET_RAW //Xilinx GTP - this is active low-
+// very minimal example top-level module
+
+module main (
+    output reg [3:0] gpio_led,
+    input wire [3:0] gpio_switch,
+    input wire SYSTEMCLOCK,
+    input wire PUSH_BUTTON_RESET_RAW // this is active low
     );
 
-   assign LED_output_0 = 1'b0;
-   assign LED_output_1 = 1'b0;
-   assign LED_output_2 = 1'b0;
-   assign LED_output_3 = 1'b0;
-   assign LED_output_4 = 1'b0;
-   assign LED_output_5 = 1'b0;
-   assign LED_output_6 = 1'b0;
+    wire reset;
+    assign reset = !PUSH_BUTTON_RESET_RAW;
+
+    reg [25:0] throb_counter = 0;
+
+    always @(posedge SYSTEMCLOCK) begin
+        if (reset) begin
+            gpio_led <= 7'b1111;
+            throb_counter <= 26'd0;
+        end else begin
+            gpio_led[1:0] <= gpio_switch[1:0];
+            gpio_led[2] <= gpio_switch[2] || gpio_switch[3];
+            if (throb_counter >= 26'd50_000_000) begin
+                gpio_led[3] <= !gpio_led[3]; 
+                throb_counter <= 26'd0;
+            end else begin
+                throb_counter <= throb_counter + 26'd1;
+            end
+        end
+    end
 
 endmodule
diff --git a/project.ucf b/project.ucf
index 1581eb6..2dba99f 100755
--- a/project.ucf
+++ b/project.ucf
@@ -1,15 +1,18 @@
-NET "PUSH_BUTTON_RESET_RAW" LOC = F3;
 
 #200MHz clock
 NET "SYSTEMCLOCK" LOC = K21;
+NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK";
+TIMESPEC "TS_SYSTEMCLOCK" = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50%;
+
+NET "PUSH_BUTTON_RESET_RAW" LOC = F3;
 
-NET "Switch_input_0" LOC = C18;
-NET "Switch_input_1" LOC = Y6;
-NET "Switch_input_2" LOC = W6;
-NET "Switch_input_3" LOC = E4;
+NET "gpio_switch<0>" LOC = C18;
+NET "gpio_switch<1>" LOC = Y6;
+NET "gpio_switch<2>" LOC = W6;
+NET "gpio_switch<3>" LOC = E4;
 
-NET "LED_output_1" LOC = D17;
-NET "LED_output_2" LOC = AB4;
-NET "LED_output_4" LOC = D21;
-NET "LED_output_5" LOC = W15;
+NET "gpio_led<0>" LOC = D17;
+NET "gpio_led<1>" LOC = AB4;
+NET "gpio_led<2>" LOC = D21;
+NET "gpio_led<3>" LOC = W15;
 
-- 
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