From 0451d1c0df95884d39b85f26a736df1f3086e642 Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Wed, 13 Nov 2013 10:35:52 -0500
Subject: TODO updates

---
 contrib/TODO | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/contrib/TODO b/contrib/TODO
index bb97bce..9c10050 100644
--- a/contrib/TODO
+++ b/contrib/TODO
@@ -1,7 +1,11 @@
 
-BUG: synth still seems to continue even if first build (verilog compile) fails
+rename repo...
+    hdl-build
+    basic-hdl-project
+
+cleanup simple_uart.v
 
-For bitfile/mcs targets, add an echo that they are being created (slow).
+BUG: synth still seems to continue even if first build (verilog compile) fails
 
 requests from AJ:
     anything related to not rebuilding all the coregen when not necessary.
-- 
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