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This folder contains a template Verilog/VHDL HDL project with a basic build
system for using the Xilinx ISE toolchain to target FPGAs.                  
                                                                            
When using this as a project template, edit this file and then delete this
section. See ./contrib/QUICK_START.txt for help setting up a new project. At a
minimum you will need to copy ./contrib/Makefile.example to ./Makefile.     
                                                                            
Hint: search this file for "<board>"                                        

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== About =====================================================================



  <<<<fill this part in>>>>



See COPYING for copyright and licensing information.

This folder contains Verilog/VHDL source code and a build system based on the
no-cost Xilinx ISE WebPack toolchain for simulating and synthesizing targeting
FPGAs.

== Repository Contents =======================================================

  hdl/
    Synthesizable Verilog and VHDL source code

  tb/
    Testbench simulation source code, unit tests, related data and scripts

  docs/
    Documentation might live here

  contrib/
    Project-independent build scripts are set here

  bitfiles/
    A handful of old "known-good" bitfiles might get archived here.

  Makefile
    Project-specific build variables are set here

== Synthesis =================================================================

The Xilinx ISE development must be installed and licensed on the local machine.
A set of command-line build scripts are usually used to build the project
instead of the ISE IDE, but the later could be configured and used as well.

Python and GNU make must be on the $PATH.

Synthesize a bitfile with:

    make

To upload the bitfile over JTAG using the Xilinx Impact utility, run the
command below. There may be other upload board-specific upload mechanisms; look
elsewhere in this file or for a README in ./contrib/<board>.

The toplevel ucf (constraints mapping netlist objects from the verilog
compilation to hardware resources, and place and routing and timing
constraints) will either be a .ucf file in this top directory, or, if a board
template was used, might live in ./contrib/<board>/<board>.ucf.

The toplevel verilog module, which probably does nothing (just sets some pins
to zero) lives in:

    ./hdl/main_<board>.v

To load a synthesized bitfile, 

== Simulation ================================================================

To simulate the testbench in ./tb/<testbench>_tb with the isim GUI:

    make isim/<testbench>_tb

A "tb/<testbench>_tb.wcfg" may be missing for new testbenches, which isim will
complain about. After you set up your waveform configuration in isim for the
first time, be sure to save and rename the configuration appropriately.

After editing any HDL files (either the testbench itself or files in ./hdl/),
instead of restarting isim you can simply run the following command and then
hit the "Re-launch" button in the isim GUI:

    make resim/<testbench>_tb

Some testbenches may be written in a particular style and can be run as
automated tests. To run a particular test, or to run all unit tests:

    make test/<testname>_tb
    make tests

== Development ===============================================================

This project uses a template HDL build system. You can read more about
developing with this system in the HOWTO and README files in the ./contrib/
directory. In particular, there are directions on:

 - using Xilinx Coregen to instantiate HDL cores
 - creating unittest-style testbenches