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@@ -0,0 +1,104 @@ + +Central circuit: +http://www.cryogenius.com/hardware/rng/ + +Using 17v (or +8.5v?) from a MAX232 as a voltage source. + +### BOM + +Breadboard prototype will be maple mini plus through-hole and DIP components. + +Version for fab should try to use surface mount components for everything, with +SOT-sized-ish components for reasonable hand assembly. + +Central circuit: + +Q1,Q2,Q3 2N3904 transistors + 74LS14 schmitt trigger (only one needed) +C1 0.1uF cap, ceramic ok +R1,R3,R4 4.7K resistors +R2 1M resistor + +Alternatively, use a series of 3 74ALS04 inverters (single chip) instead of the +schmitt trigger and Q3 for amplification. This increases requires an extra +0.1uF capacitor and two 2.7K resistors; see jfet.org diagram. + +Voltage source: + + MAX232 level shifter (as a cheap voltage source) +3x 1uF capacitor, ceramic SMD ok (1206?) + +mchck: +2x 0603 10ohm resistors +2x 0603 1k resistors +5x 0603 100n 6.3v+ capacitor +1x 0603 1uF 20v+ capacitor +1x 0603 1uF 6.3v+ capacitor +1x 0603 LED (any?) +1x button +1x 8MHz 3-pin resonator +1x MIC5202 3.3v regulator +1x MCU: STM32L151C8T6 + +### Circuit + +Power to all transistors comes from the MAX232; this higher-voltage segment is +isolated from the rest of the circuit by a capacitor. Both trigger and MAX232 +Vcc are straight to USB +5v/GND (which already has seperate stabilizing cap). + +When using MCHCK, grab Vext and GND off headers and route to circuit. PB5 (on +the end header) looks like a decent input pin to pipe in to: it is 5v tolerant +and connected to both timer3 and comparator2. + +Optionally, according to jfet.org, the floating collector could be tied to the +base of the first transistor. + +### Software + +Raw bits should be sampled at a regular rate, possibly using DMA to increase +speed and reduce interrupts. + +Raw bits should be analysed for their bias (some acceptable ratio; 20-80% over +512 bits?) and potentially quickly for randomness. If they pass, they should go +through von neumann de-biasing, then a quick randomness test. Every 1024 bits +or so coming out of that phase should get hashed down to 256 bits or so, then +that output again checked for randomness (really?). Finally bundle up packets +and put them in a USB read buffer. Packet could include some extra data (eg, +bias), or not. + +Failures due to poor bias should be skipped, at least for a long time. Any +other failures due to non-randomness should cause the device to lock up and +possibly report tampering. + +Optionally, randomness could get pushed out over i2c, SPI, UART, pin, or port. + +Raw read should be very fast and have highest interrupt, followed by USB +interrupt. + +Alternatively, a timer can be used to measure the timing between digital value +transitions. + +### 'scoping Notes + +Used cyrogenius circuit. Capacitor may be + +"minimum viable voltage" seems to be 10v: first state flips to 2.8v around +9.45v, first trigger scope at 5v at 11v input, reliably triggering at 12v. At +20v in, peaks around 9.5v. At 17v in, peaks around 8.4v. + +Seems like sampling should be at least 1usec apart to reduce correlations +between bits. This would make for about 125 kilobytes (not bits) per second +best case, which seems very reasonable for rooter. + +Tying collector to base of first transistor doesn't seem to have a detrimental +effect. + +Really can't discern any strong bias just by looking at the scope. + +### TODO + +- both 1uF really required for MAX232? +- MAX202D vs. MAX232D? smaller caps +- smaller schmitt trigger +- 3-in-one 2N309 transistors? + |