From 9a486c19a6ef6499bfddb76c3557e5e337c25f1a Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Mon, 13 May 2013 12:54:31 -0400 Subject: xilinx data: extensions, corrections --- xilinx_data/spartan6.csv | 2 ++ xilinx_data/spartan6_notes.csv | 9 +++++++++ xilinx_data/spartan6_shared.csv | 9 ++++++--- xilinx_data/zynq7000_shared.csv | 15 ++++++++++++--- 4 files changed, 29 insertions(+), 6 deletions(-) create mode 100644 xilinx_data/spartan6_notes.csv diff --git a/xilinx_data/spartan6.csv b/xilinx_data/spartan6.csv index bddbd43..16f0518 100644 --- a/xilinx_data/spartan6.csv +++ b/xilinx_data/spartan6.csv @@ -12,6 +12,8 @@ DSP48A Slices,8,16,32,38,58,132,180,180,38,58,132,180,180 Endpoint Block for PCI Express,n/a,n/a,n/a,n/a,n/a,n/a,n/a,n/a,1,1,1,1,1 Memory Controller Blocks,0,2,2,2,2,4,4,4,2,2,4,4,4 GTP Low Power Transceivers,n/a,n/a,n/a,n/a,n/a,n/a,n/a,n/a,2,4,8,8,8 +Speed Grades,"-1L, -2, -3","-1L, -2, -3, -3N","-1L, -2, -3, -3N","-1L, -2, -3, -3N","-1L, -2, -3, -3N","-1L, -2, -3, -3N","-1L, -2, -3, -3N","-1L, -2, -3, -3N","-2, -3, -3N","-2, -3, -3N","-2, -3, -3N","-2, -3, -3N","-2, -3, -3N" +Temperature Ratings,"C, I","C, I","C, I","C, I","C, I","C, I","C, I","C, I","C, I","C, I","C, I","C, I","C, I" Configuration Memory (Mb),2.7,2.7,3.7,6.4,11.9,19.6,26.5,33.8,6.4,11.9,19.6,26.5,33.8 ###,,,,,,,,,,,,, CPG196,106,106,106,,,,,,,,,, diff --git a/xilinx_data/spartan6_notes.csv b/xilinx_data/spartan6_notes.csv new file mode 100644 index 0000000..7359caa --- /dev/null +++ b/xilinx_data/spartan6_notes.csv @@ -0,0 +1,9 @@ +1,"Each slice contains four LUTs and eight flip-flops" +2,"Spartan-6 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6-input LUT architecture" +3,"Each CMT contains two DCMs and one PLL" +4,"Each DSP48A1 slice contains an 18x18 multiplier, an adder, and an accumulator" +5,"The LX device pinouts are not compatible with the LXT device pinouts" +7,"CPG196 and TQG144 do not have memory controller support. -3N is not available for these packages" +8,"CSG225 has X8 memory controller support in the LX9 and LX16 devices. There is no memory controller int he LX4 devices" +9,"Devices in the FG(G)484 and GS484 packages have support for two memory controllers" +10,"Devices with -3N speed grade do not support MCB functionality" diff --git a/xilinx_data/spartan6_shared.csv b/xilinx_data/spartan6_shared.csv index 7a6cacc..6236227 100644 --- a/xilinx_data/spartan6_shared.csv +++ b/xilinx_data/spartan6_shared.csv @@ -1,3 +1,6 @@ -Widgets,123 -Whatchamecallems,Gazmo -Yub Yubs,3840 +Clock Networks, 16 +Silicon Process, 45nm +I/O Pin Logic Levels, 3.3v and 1.2v +I/O Pin drive current, 24mA per pin +Differential I/O Speed, 1,080 Mb/s +Configuration Interfaces,"SPI, NOR flash, JTAG" diff --git a/xilinx_data/zynq7000_shared.csv b/xilinx_data/zynq7000_shared.csv index 7a6cacc..888e2fd 100644 --- a/xilinx_data/zynq7000_shared.csv +++ b/xilinx_data/zynq7000_shared.csv @@ -1,3 +1,12 @@ -Widgets,123 -Whatchamecallems,Gazmo -Yub Yubs,3840 +Processor Core, Dual-Core ARM Cortex-A9 MPCore +Processor Extensions, NEON & Single / Double Precision Floating Point for each processor +L1 Cache, 32 KB Instruction, 32 KB Data per processor +L2 Cache, 512 KB +On-Chip Memory, 256 KB +External Memory,"16bit or 32bit DDR3, DDR3L, DDR2, LPDDR3 (1GB of address space)" +External Static Memory Support,"2x Quad-SPI, NAND, NOR" +DMA Channels, 8 (4 dedicated to Programmable Logic) +Peripherals,"2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO" +Peripherals w/ built-in DMA,"2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO" +Security,"RSA Authentication, and AES and SHA 256b Decryption and Authentication for Secure Boot" +PS-PL Primary Interfaces,"2x AXI 32b Master 2x AXI 32b Slave; 4x AXI 64b/32b Memory; AXI 64b ACP; 16 Interrupts" -- cgit v1.2.3